[llvm] Fixed a number of typos

[GabrielRavier]

Summary

I went over the output of the following mess of a command:

(ulimit -m 2000000; ulimit -v 2000000; git ls-files -z | parallel --xargs -0 cat | aspell list --mode=none --ignore-case | grep -E '^[A-Za-z][a-z]*$' | sort | uniq -c | sort -n | grep -vE '.{25}' | aspell pipe -W3 | grep : | cut -d' ' -f2 | less)

and proceeded to spend a few days looking at it to find probable typos
and fixed a few hundred of them in all of the llvm project (note, the
ones I found are not anywhere near all of them, but it seems like a
good start).

[asbirlea]

Thank you for the elaborate cleanup!

Drive-by comments, didn't get to all.

llvm/docs/GlobalISel/GMIR.rst

198 ↗

(On Diff #449818)

One word, not a typo.

llvm/lib/IR/BuiltinGCs.cpp

62

addressspace

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

1552 ↗

(On Diff #449818)

addressspaces.

llvm/test/Analysis/LoopAccessAnalysis/forward-loop-independent.ll

7

s/dependencies/dependences (consistent with above)

llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll

111

dependences

[GabrielRavier]

Fixed problems pointed out by asbirlea

[jhenderson]

The changes to tools, test/tools, and utils/lit all look good to me. I haven't checked anywhere else.

llvm/cmake/config.guess

 #! /bin/sh
 # Attempt to guess a canonical system name.
 #   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
 #   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
 #   2011 Free Software Foundation, Inc.
 
-timestamp='2011-08-20'
+timestamp='2022-08-04'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 2 of the License, or
 # (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful, but
 # WITHOUT ANY WARRANTY; without even the implied warranty of
else
     echo ${UNAME_MACHINE}-pc-sysv32
   fi
   exit ;;
     pc:*:*:*)
   # Left here for compatibility:
   # uname -m prints for DJGPP always 'pc', but it prints nothing about
   # the processor, so we play safe by assuming i586.
   # Note: whatever this is, it MUST be the same as what config.sub
-  # prints for the "djgpp" host, or else GDB configury will decide that
+  # prints for the "djgpp" host, or else GDB configure will decide that
   # this is a cross-build.
   echo i586-pc-msdosdjgpp
   exit ;;
     Intel:Mach:3*:*)
   echo i386-pc-mach3
   exit ;;
     paragon:*:*:*)
   echo i860-intel-osf1

llvm/cmake/modules/AddLLVM.cmake

if((ARG_SHARED AND ARG_STATIC) OR ARG_OBJECT)
     # Bring in the target include directories from our original target.
     target_include_directories(${obj_name} PRIVATE $<TARGET_PROPERTY:${name},INCLUDE_DIRECTORIES>)
 
     set_target_properties(${obj_name} PROPERTIES FOLDER "Object Libraries")
     if(ARG_DEPENDS)
       add_dependencies(${obj_name} ${ARG_DEPENDS})
     endif()
     # Treat link libraries like PUBLIC dependencies.  LINK_LIBS might
-    # result in generating header files.  Add a dependendency so that
+    # result in generating header files.  Add a dependency so that
     # the generated header is created before this object library.
     if(ARG_LINK_LIBS)
       cmake_parse_arguments(LINK_LIBS_ARG
         ""
         ""
         "PUBLIC;PRIVATE"
         ${ARG_LINK_LIBS})
       foreach(link_lib ${LINK_LIBS_ARG_PUBLIC})

 
 # An LLVM component is a cmake target with the following cmake properties
 # eventually set:
 #   - LLVM_COMPONENT_NAME: the name of the component, which can be the name of
 #     the associated library or the one specified through COMPONENT_NAME
 #   - LLVM_LINK_COMPONENTS: a list of component this component depends on
 #   - COMPONENT_HAS_JIT: (only for group component) whether this target group
 #     supports JIT compilation
-# Additionnaly, the ADD_TO_COMPONENT <component> option make it possible to add this
+# Additionally, the ADD_TO_COMPONENT <component> option make it possible to add this
 # component to the LLVM_LINK_COMPONENTS of <component>.
 function(add_llvm_component_library name)
   cmake_parse_arguments(ARG
     ""
     "COMPONENT_NAME;ADD_TO_COMPONENT"
     ""
     ${ARGN})
   add_llvm_library(${name} COMPONENT_LIB ${ARG_UNPARSED_ARGUMENTS})

llvm/cmake/modules/CoverageReport.cmake

 # This isn't connected to any dependencies because it is a bit finacky to get
 # working exactly how a user might want.
 add_custom_target(clear-profile-data
                   COMMAND ${CMAKE_COMMAND} -E
                           remove_directory ${LLVM_PROFILE_DATA_DIR})
 
 # This currently only works for LLVM, but could be expanded to work for all
 # sub-projects. The current limitation is based on not having a good way to
-# automaticall plumb through the targets that we want to run coverage against.
+# automatically plumb through the targets that we want to run coverage against.
 add_custom_target(generate-coverage-report
                   COMMAND ${Python3_EXECUTABLE} ${PREPARE_CODE_COV_ARTIFACT}
                           ${LLVM_PROFDATA} ${LLVM_COV} ${LLVM_PROFILE_DATA_DIR}
                           ${REPORT_DIR} ${coverage_binaries}
                           --unified-report ${restrict_flags}
                   WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
                   DEPENDS check-llvm) # Run tests

llvm/docs/LangRef.rst

 
 The string '``undef``' can be used anywhere a constant is expected, and
 indicates that the user of the value may receive an unspecified
 bit-pattern. Undefined values may be of any type (other than '``label``'
 or '``void``') and be used anywhere a constant is permitted.
 
 .. note::
 
-  A '``poison``' value (decribed in the next section) should be used instead of
+  A '``poison``' value (described in the next section) should be used instead of
   '``undef``' whenever possible. Poison values are stronger than undef, and
   enable more optimizations. Just the existence of '``undef``' blocks certain
   optimizations (see the examples below).
 
 Undefined values are useful because they indicate to the compiler that
 the program is well defined no matter what value is used. This gives the
 compiler more freedom to optimize. Here are some examples of
 (potentially surprising) transformations that are valid (in pseudo IR):

llvm/docs/MemorySSA.rst

 
 Precision in practice
 ^^^^^^^^^^^^^^^^^^^^^
 
 In practice, there are implementation details in LLVM that also affect the
 results' precision provided by ``MemorySSA``. For example, AliasAnalysis has various
 caps, or restrictions on looking through phis which can affect what ``MemorySSA``
 can infer. Changes made by different passes may make MemorySSA either "overly
-optimized" (it can provide a more acccurate result than if it were recomputed
+optimized" (it can provide a more accurate result than if it were recomputed
 from scratch), or "under optimized" (it could infer more if it were recomputed).
 This can lead to challenges to reproduced results in isolation with a single pass
-when the result relies on the state aquired by ``MemorySSA`` due to being updated by
+when the result relies on the state acquired by ``MemorySSA`` due to being updated by
 multiple subsequent passes.
 Passes that use and update ``MemorySSA`` should do so through the APIs provided by the
 ``MemorySSAUpdater``, or through calls on the Walker.
 Direct optimizations to ``MemorySSA`` are not permitted.
 There is currently a single, narrowly scoped exception where DSE (DeadStoreElimination)
 updates an optimized access of a store, after a traversal that guarantees the
 optimization is correct. This is solely allowed due to the traversals and inferences
 being beyond what ``MemorySSA`` does and them being "free" (i.e. DSE does them anyway).

llvm/include/llvm-c/Object.h

 
 /**
  * Create a binary file from the given memory buffer.
  *
  * The exact type of the binary file will be inferred automatically, and the
  * appropriate implementation selected.  The context may be NULL except if
  * the resulting file is an LLVM IR file.
  *
- * The memory buffer is not consumed by this function.  It is the responsibilty
+ * The memory buffer is not consumed by this function.  It is the responsibility
  * of the caller to free it with \c LLVMDisposeMemoryBuffer.
  *
  * If NULL is returned, the \p ErrorMessage parameter is populated with the
  * error's description.  It is then the caller's responsibility to free this
  * message by calling \c LLVMDisposeMessage.
  *
  * @see llvm::object::createBinary
  */
 LLVMBinaryRef LLVMCreateBinary(LLVMMemoryBufferRef MemBuf,
                                LLVMContextRef Context,
                                char **ErrorMessage);
 
 /**
  * Dispose of a binary file.
  *
- * The binary file does not own its backing buffer.  It is the responsibilty
+ * The binary file does not own its backing buffer.  It is the responsibility
  * of the caller to free it with \c LLVMDisposeMemoryBuffer.
  */
 void LLVMDisposeBinary(LLVMBinaryRef BR);
 
 /**
  * Retrieves a copy of the memory buffer associated with this object file.
  *
  * The returned buffer is merely a shallow copy and does not own the actual

llvm/include/llvm-c/Orc.h

  */
 LLVMErrorRef LLVMOrcMaterializationResponsibilityDefineMaterializing(
     LLVMOrcMaterializationResponsibilityRef MR,
     LLVMOrcCSymbolFlagsMapPairs Pairs, size_t NumPairs);
 
 /**
  * Notify all not-yet-emitted covered by this MaterializationResponsibility
  * instance that an error has occurred.
- * This will remove all symbols covered by this MaterializationResponsibilty
+ * This will remove all symbols covered by this MaterializationResponsibility
  * from the target JITDylib, and send an error to any queries waiting on
  * these symbols.
  */
 void LLVMOrcMaterializationResponsibilityFailMaterialization(
     LLVMOrcMaterializationResponsibilityRef MR);
 
 /**
  * Transfers responsibility to the given MaterializationUnit for all

llvm/include/llvm/Analysis/BranchProbabilityInfo.h

 //===- BranchProbabilityInfo.h - Branch Probability Analysis ----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This pass is used to evaluate branch probabilties.
+// This pass is used to evaluate branch probabilities.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H
 #define LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseMapInfo.h"

llvm/include/llvm/Analysis/LoopAccessAnalysis.h

enum class VectorizationSafetyStatus {
     // safe.
     Safe,
     // Can possibly vectorize with RT checks to overcome unknown dependencies.
     PossiblySafeWithRtChecks,
     // Cannot vectorize due to known unsafe dependencies.
     Unsafe,
   };
 
-  /// Dependece between memory access instructions.
+  /// Dependence between memory access instructions.
   struct Dependence {
     /// The type of the dependence.
     enum DepType {
       // No dependence.
       NoDep,
       // We couldn't determine the direction or the distance.
       Unknown,
       // Lexically forward.
const PointerInfo &getPointerInfo(unsigned PtrIdx) const {
     return Pointers[PtrIdx];
   }
 
   ScalarEvolution *getSE() const { return SE; }
 
 private:
   /// Groups pointers such that a single memcheck is required
   /// between two different groups. This will clear the CheckingGroups vector
-  /// and re-compute it. We will only group dependecies if \p UseDependencies
+  /// and re-compute it. We will only group dependencies if \p UseDependencies
   /// is true, otherwise we will create a separate group for each pointer.
   void groupChecks(MemoryDepChecker::DepCandidates &DepCands,
                    bool UseDependencies);
 
   /// Generate the checks and return them.
   SmallVector<RuntimePointerCheck, 4> generateChecks();
 
   /// Try to create add a new (pointer-difference, access size) pair to

llvm/include/llvm/Analysis/LoopAnalysisManager.h

 /// cached in the \c LoopAnalysisManager.
 template <> class LoopAnalysisManagerFunctionProxy::Result {
 public:
   explicit Result(LoopAnalysisManager &InnerAM, LoopInfo &LI)
       : InnerAM(&InnerAM), LI(&LI) {}
   Result(Result &&Arg)
       : InnerAM(std::move(Arg.InnerAM)), LI(Arg.LI), MSSAUsed(Arg.MSSAUsed) {
     // We have to null out the analysis manager in the moved-from state
-    // because we are taking ownership of the responsibilty to clear the
+    // because we are taking ownership of the responsibility to clear the
     // analysis state.
     Arg.InnerAM = nullptr;
   }
   Result &operator=(Result &&RHS) {
     InnerAM = RHS.InnerAM;
     LI = RHS.LI;
     MSSAUsed = RHS.MSSAUsed;
     // We have to null out the analysis manager in the moved-from state
-    // because we are taking ownership of the responsibilty to clear the
+    // because we are taking ownership of the responsibility to clear the
     // analysis state.
     RHS.InnerAM = nullptr;
     return *this;
   }
   ~Result() {
     // InnerAM is cleared in a moved from state where there is nothing to do.
     if (!InnerAM)
       return;

llvm/include/llvm/Analysis/LoopCacheAnalysis.h

 /// 2. they have a loop carried dependence with a small dependence distance
 ///    (e.g. less than 2) carried by the inner loop, or
 /// 3. they refer to the same array, and the subscript in their innermost
 ///    dimension is less than or equal to 'd' (where 'd' is less than the cache
 ///    line size)
 ///
 /// Intuitively a reference group represents memory references that access
 /// the same cache line. Conditions 1,2 above account for temporal reuse, while
-/// contition 3 accounts for spacial reuse.
+/// condition 3 accounts for spacial reuse.
 using ReferenceGroupTy = SmallVector<std::unique_ptr<IndexedReference>, 8>;
 using ReferenceGroupsTy = SmallVector<ReferenceGroupTy, 8>;
 
 /// \c CacheCost represents the estimated cost of a inner loop as the number of
 /// cache lines used by the memory references it contains.
 /// The 'cache cost' of a loop 'L' in a loop nest 'LN' is computed as the sum of
 /// the cache costs of all of its reference groups when the loop is considered
 /// to be in the innermost position in the nest.

llvm/include/llvm/Analysis/MLModelRunner.h

 #include "llvm/Analysis/TensorSpec.h"
 #include "llvm/IR/PassManager.h"
 
 namespace llvm {
 class LLVMContext;
 
 /// MLModelRunner interface: abstraction of a mechanism for evaluating a
 /// tensorflow "saved model".
-/// NOTE: feature indices are expected to be consistent all accross
+/// NOTE: feature indices are expected to be consistent all across
 /// MLModelRunners (pertaining to the same model), and also Loggers (see
 /// TFUtils.h)
 class MLModelRunner {
 public:
   // Disallows copy and assign.
   MLModelRunner(const MLModelRunner &) = delete;
   MLModelRunner &operator=(const MLModelRunner &) = delete;
   virtual ~MLModelRunner() = default;

llvm/include/llvm/Analysis/RegionInfo.h

#endif
   /// Check if this is a correctly build Region. This is an expensive check, as
   /// the complete CFG of the Region will be walked.
   void verifyRegion() const;
 
   /// Clear the cache for BB RegionNodes.
   ///
   /// After calling this function the BasicBlock RegionNodes will be stored at
   /// different memory locations. RegionNodes obtained before this function is
-  /// called are therefore not comparable to RegionNodes abtained afterwords.
+  /// called are therefore not comparable to RegionNodes obtained afterwords.
   void clearNodeCache();
 
   /// @name Subregion Iterators
   ///
   /// These iterators iterator over all subregions of this Region.
   //@{
   using iterator = typename RegionSet::iterator;
   using const_iterator = typename RegionSet::const_iterator;

llvm/include/llvm/CodeGen/BasicTTIImpl.h

public:
   bool shouldBuildRelLookupTables() const {
     const TargetMachine &TM = getTLI()->getTargetMachine();
     // If non-PIC mode, do not generate a relative lookup table.
     if (!TM.isPositionIndependent())
       return false;
 
     /// Relative lookup table entries consist of 32-bit offsets.
     /// Do not generate relative lookup tables for large code models
-    /// in 64-bit achitectures where 32-bit offsets might not be enough.
+    /// in 64-bit architectures where 32-bit offsets might not be enough.
     if (TM.getCodeModel() == CodeModel::Medium ||
         TM.getCodeModel() == CodeModel::Large)
       return false;
 
     Triple TargetTriple = TM.getTargetTriple();
     if (!TargetTriple.isArch64Bit())
       return false;
 

llvm/include/llvm/CodeGen/DFAPacketizer.h

public:
   // and the instruction will be added to the next packet.
   virtual bool shouldAddToPacket(const MachineInstr &MI) { return true; }
 
   // Check if it is legal to packetize SUI and SUJ together.
   virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
     return false;
   }
 
-  // Check if it is legal to prune dependece between SUI and SUJ.
+  // Check if it is legal to prune dependence between SUI and SUJ.
   virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
     return false;
   }
 
   // Add a DAG mutation to be done before the packetization begins.
   void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation);
 
   bool alias(const MachineInstr &MI1, const MachineInstr &MI2,

llvm/include/llvm/CodeGen/LiveRangeCalc.h

class LiveRangeCalc {
   ///
   /// For every basic block, MBB, one of these conditions shall be true:
   ///
   ///  1. !Seen.count(MBB->getNumber())
   ///     Blocks without a Seen bit are ignored.
   ///  2. LiveOut[MBB].second.getNode() == MBB
   ///     The live-out value is defined in MBB.
   ///  3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB]
-  ///     The live-out value passses through MBB. All predecessors must carry
+  ///     The live-out value passes through MBB. All predecessors must carry
   ///     the same value.
   ///
   /// The domtree node may be null, it can be computed.
   ///
   /// The map can be shared by multiple live ranges as long as no two are
   /// live-out of the same block.
   LiveOutMap Map;
 

llvm/include/llvm/CodeGen/MIRPrinter.h

 /// output stream.
 void printMIR(raw_ostream &OS, const MachineFunction &MF);
 
 /// Determine a possible list of successors of a basic block based on the
 /// basic block machine operand being used inside the block. This should give
 /// you the correct list of successor blocks in most cases except for things
 /// like jump tables where the basic block references can't easily be found.
 /// The MIRPRinter will skip printing successors if they match the result of
-/// this funciton and the parser will use this function to construct a list if
+/// this function and the parser will use this function to construct a list if
 /// it is missing.
 void guessSuccessors(const MachineBasicBlock &MBB,
                      SmallVectorImpl<MachineBasicBlock*> &Result,
                      bool &IsFallthrough);
 
 } // end namespace llvm
 
 #endif

llvm/include/llvm/CodeGen/MachineBranchProbabilityInfo.h

 //=- MachineBranchProbabilityInfo.h - Branch Probability Analysis -*- C++ -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This pass is used to evaluate branch probabilties on machine basic blocks.
+// This pass is used to evaluate branch probabilities on machine basic blocks.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H
 #define LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H
 
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Pass.h"

llvm/include/llvm/CodeGen/RegisterBankInfo.h

struct PartialMapping {
 
     /// Print this partial mapping on dbgs() stream.
     void dump() const;
 
     /// Print this partial mapping on \p OS;
     void print(raw_ostream &OS) const;
 
     /// Check that the Mask is compatible with the RegBank.
-    /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
+    /// Indeed, if the RegBank cannot accomodate the "active bits" of the mask,
     /// there is no way this mapping is valid.
     ///
     /// \note This method does not check anything when assertions are disabled.
     ///
     /// \return True is the check was successful.
     bool verify() const;
   };
 

llvm/include/llvm/CodeGen/RegisterPressure.h

class RegPressureTracker {
   const LiveIntervals *LIS = nullptr;
 
   /// We currently only allow pressure tracking within a block.
   const MachineBasicBlock *MBB = nullptr;
 
   /// Track the max pressure within the region traversed so far.
   RegisterPressure &P;
 
-  /// Run in two modes dependending on whether constructed with IntervalPressure
+  /// Run in two modes depending on whether constructed with IntervalPressure
   /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
   bool RequireIntervals;
 
   /// True if UntiedDefs will be populated.
   bool TrackUntiedDefs = false;
 
   /// True if lanemasks should be tracked.
   bool TrackLaneMasks = false;

llvm/include/llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h

 private:
   void clear();
 
   /// A helper structure that can quickly determine the size in bytes of an
   /// abbreviation declaration.
   struct FixedSizeInfo {
     /// The fixed byte size for fixed size forms.
     uint16_t NumBytes = 0;
-    /// Number of DW_FORM_address forms in this abbrevation declaration.
+    /// Number of DW_FORM_address forms in this abbreviation declaration.
     uint8_t NumAddrs = 0;
-    /// Number of DW_FORM_ref_addr forms in this abbrevation declaration.
+    /// Number of DW_FORM_ref_addr forms in this abbreviation declaration.
     uint8_t NumRefAddrs = 0;
     /// Number of 4 byte in DWARF32 and 8 byte in DWARF64 forms.
     uint8_t NumDwarfOffsets = 0;
 
     FixedSizeInfo() = default;
 
     /// Calculate the fixed size in bytes given a DWARFUnit.
     ///

llvm/include/llvm/ExecutionEngine/Orc/Core.h

public:
   /// initializer symbols: Queries using
   /// SymbolLookupFlags::WeaklyReferencedSymbol can be used to trigger their
   /// emission, and this method can be used to remove them from the JITDylib
   /// once materialization is complete.
   void defineNonExistent(ArrayRef<SymbolStringPtr> Symbols);
 
   /// Notify all not-yet-emitted covered by this MaterializationResponsibility
   /// instance that an error has occurred.
-  /// This will remove all symbols covered by this MaterializationResponsibilty
+  /// This will remove all symbols covered by this MaterializationResponsibility
   /// from the target JITDylib, and send an error to any queries waiting on
   /// these symbols.
   void failMaterialization();
 
   /// Transfers responsibility to the given MaterializationUnit for all
   /// symbols defined by that MaterializationUnit. This allows
   /// materializers to break up work based on run-time information (e.g.
   /// by introspecting which symbols have actually been looked up and

llvm/include/llvm/ExecutionEngine/Orc/DebugUtils.h

 
 /// Render a SymbolMap.
 raw_ostream &operator<<(raw_ostream &OS, const SymbolMap &Symbols);
 
 /// Render a SymbolDependenceMap entry.
 raw_ostream &operator<<(raw_ostream &OS,
                         const SymbolDependenceMap::value_type &KV);
 
-/// Render a SymbolDependendeMap.
+/// Render a SymbolDependenceMap.
 raw_ostream &operator<<(raw_ostream &OS, const SymbolDependenceMap &Deps);
 
 /// Render a MaterializationUnit.
 raw_ostream &operator<<(raw_ostream &OS, const MaterializationUnit &MU);
 
 //// Render a JITDylibLookupFlags instance.
 raw_ostream &operator<<(raw_ostream &OS,
                         const JITDylibLookupFlags &JDLookupFlags);

llvm/include/llvm/ExecutionEngine/Orc/EPCEHFrameRegistrar.h

 class ExecutionSession;
 
 /// Register/Deregisters EH frames in a remote process via a
 /// ExecutorProcessControl instance.
 class EPCEHFrameRegistrar : public jitlink::EHFrameRegistrar {
 public:
   /// Create from a ExecutorProcessControl instance alone. This will use
   /// the EPC's lookupSymbols method to find the registration/deregistration
-  /// funciton addresses by name.
+  /// function addresses by name.
   static Expected<std::unique_ptr<EPCEHFrameRegistrar>>
   Create(ExecutionSession &ES);
 
   /// Create a EPCEHFrameRegistrar with the given ExecutorProcessControl
   /// object and registration/deregistration function addresses.
   EPCEHFrameRegistrar(ExecutionSession &ES,
                       ExecutorAddr RegisterEHFrameWrapperFnAddr,
                       ExecutorAddr DeregisterEHFRameWrapperFnAddr)

llvm/include/llvm/ExecutionEngine/RuntimeDyld.h

virtual void reserveAllocationSpace(uintptr_t CodeSize, uint32_t CodeAlign,
                                         uint32_t RODataAlign,
                                         uintptr_t RWDataSize,
                                         uint32_t RWDataAlign) {}
 
     /// Override to return true to enable the reserveAllocationSpace callback.
     virtual bool needsToReserveAllocationSpace() { return false; }
 
     /// Override to return false to tell LLVM no stub space will be needed.
-    /// This requires some guarantees depending on architecuture, but when
+    /// This requires some guarantees depending on architecture, but when
     /// you know what you are doing it saves allocated space.
     virtual bool allowStubAllocation() const { return true; }
 
     /// Register the EH frames with the runtime so that c++ exceptions work.
     ///
     /// \p Addr parameter provides the local address of the EH frame section
     /// data, while \p LoadAddr provides the address of the data in the target
     /// address space.  If the section has not been remapped (which will usually

llvm/include/llvm/Frontend/OpenMP/OMPConstants.h

 #include "llvm/Frontend/OpenMP/OMPKinds.def"
 };
 
 #define OMP_DEFAULT_KIND(Enum, ...)                                            \
   constexpr auto Enum = omp::DefaultKind::Enum;
 #include "llvm/Frontend/OpenMP/OMPKinds.def"
 
 /// IDs for all omp runtime library ident_t flag encodings (see
-/// their defintion in openmp/runtime/src/kmp.h).
+/// their definition in openmp/runtime/src/kmp.h).
 enum class IdentFlag {
 #define OMP_IDENT_FLAG(Enum, Str, Value) Enum = Value,
 #include "llvm/Frontend/OpenMP/OMPKinds.def"
   LLVM_MARK_AS_BITMASK_ENUM(0x7FFFFFFF)
 };
 
 #define OMP_IDENT_FLAG(Enum, ...) constexpr auto Enum = omp::IdentFlag::Enum;
 #include "llvm/Frontend/OpenMP/OMPKinds.def"

llvm/include/llvm/Frontend/OpenMP/OMPContext.h

 
 /// Return true if \p Property can be nested in \p Selector and \p Set.
 bool isValidTraitPropertyForTraitSetAndSelector(TraitProperty Property,
                                                 TraitSelector Selector,
                                                 TraitSet Set);
 
 /// Variant match information describes the required traits and how they are
 /// scored (via the ScoresMap). In addition, the required consturct nesting is
-/// decribed as well.
+/// described as well.
 struct VariantMatchInfo {
   /// Add the trait \p Property to the required trait set. \p RawString is the
   /// string we parsed and derived \p Property from. If \p Score is not null, it
   /// recorded as well. If \p Property is in the `construct` set it is recorded
   /// in-order in the ConstructTraits as well.
   void addTrait(TraitProperty Property, StringRef RawString,
                 APInt *Score = nullptr) {
     addTrait(getOpenMPContextTraitSetForProperty(Property), Property, RawString,

llvm/include/llvm/IR/GlobalValue.h

public:
   /// Inlining is okay across non-exact linkage types as long as they're not
   /// interposable (see \c isInterposable), since in such cases the currently
   /// visible variant is *a* correct implementation of the original source
   /// function; it just isn't the *only* correct implementation.
   bool isDefinitionExact() const {
     return !mayBeDerefined();
   }
 
-  /// Return true if this global has an exact defintion.
+  /// Return true if this global has an exact definition.
   bool hasExactDefinition() const {
     // While this computes exactly the same thing as
     // isStrongDefinitionForLinker, the intended uses are different.  This
     // function is intended to help decide if specific inter-procedural
     // transforms are correct, while isStrongDefinitionForLinker's intended use
     // is in low level code generation.
     return !isDeclaration() && isDefinitionExact();
   }

llvm/include/llvm/IR/IntrinsicsAMDGPU.td

 //                         scheduled across SCHED_BARRIER, i.e. allow ALU instructions to pass.
 //     MASK = 0x0000 0002: VALU instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0004: SALU instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0008: MFMA instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0010: ALL VMEM instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0020: VMEM read instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0040: VMEM write instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0080: ALL DS instructions may be scheduled across SCHED_BARRIER.
-//     MASK = 0x0000 0100: ALL DS read instructions may be scheduled accoss SCHED_BARRIER.
+//     MASK = 0x0000 0100: ALL DS read instructions may be scheduled across SCHED_BARRIER.
 //     MASK = 0x0000 0200: ALL DS write instructions may be scheduled across SCHED_BARRIER.
 def int_amdgcn_sched_barrier : ClangBuiltin<"__builtin_amdgcn_sched_barrier">,
   Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent,
                                 IntrWillReturn]>;
 
 // The first parameter is a mask that determines the types of instructions that
 // you would like to synchronize around and add to a scheduling group. The
 // values of the mask are defined above for sched_barrier. These instructions

llvm/include/llvm/IR/PassManager.h

public:
     /// invalidate method should in turn be provided to this routine.
     ///
     /// The first time this is called for a given analysis pass, it will call
     /// the corresponding result's \c invalidate method.  Subsequent calls will
     /// use a cache of the results of that initial call.  It is an error to form
     /// cyclic dependencies between analysis results.
     ///
     /// This returns true if the given analysis's result is invalid. Any
-    /// dependecies on it will become invalid as a result.
+    /// dependencies on it will become invalid as a result.
     template <typename PassT>
     bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA) {
       using ResultModelT =
           detail::AnalysisResultModel<IRUnitT, PassT, typename PassT::Result,
                                       PreservedAnalyses, Invalidator>;
 
       return invalidateImpl<ResultModelT>(PassT::ID(), IR, PA);
     }
: public AnalysisInfoMixin<
           InnerAnalysisManagerProxy<AnalysisManagerT, IRUnitT>> {
 public:
   class Result {
   public:
     explicit Result(AnalysisManagerT &InnerAM) : InnerAM(&InnerAM) {}
 
     Result(Result &&Arg) : InnerAM(std::move(Arg.InnerAM)) {
       // We have to null out the analysis manager in the moved-from state
-      // because we are taking ownership of the responsibilty to clear the
+      // because we are taking ownership of the responsibility to clear the
       // analysis state.
       Arg.InnerAM = nullptr;
     }
 
     ~Result() {
       // InnerAM is cleared in a moved from state where there is nothing to do.
       if (!InnerAM)
         return;
 
       // Clear out the analysis manager if we're being destroyed -- it means we
       // didn't even see an invalidate call when we got invalidated.
       InnerAM->clear();
     }
 
     Result &operator=(Result &&RHS) {
       InnerAM = RHS.InnerAM;
       // We have to null out the analysis manager in the moved-from state
-      // because we are taking ownership of the responsibilty to clear the
+      // because we are taking ownership of the responsibility to clear the
       // analysis state.
       RHS.InnerAM = nullptr;
       return *this;
     }
 
     /// Accessor for the analysis manager.
     AnalysisManagerT &getManager() { return *InnerAM; }
 

llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h

public:
    * \defgroup Options setters
    * @{
    */
 
   /**
    * \defgroup Cache controlling options
    *
    * These entry points control the ThinLTO cache. The cache is intended to
-   * support incremental build, and thus needs to be persistent accross build.
+   * support incremental build, and thus needs to be persistent across build.
    * The client enabled the cache by supplying a path to an existing directory.
    * The code generator will use this to store objects files that may be reused
    * during a subsequent build.
    * To avoid filling the disk space, a few knobs are provided:
    *  - The pruning interval limit the frequency at which the garbage collector
    *    will try to scan the cache directory to prune it from expired entries.
    *    Setting to -1 disable the pruning (default). Setting to 0 will force
    *    pruning to occur.

llvm/include/llvm/MC/MCStreamer.h

virtual void emitValueToOffset(const MCExpr *Offset, unsigned char Value,
                                  SMLoc Loc);
 
   /// @}
 
   /// Switch to a new logical file.  This is used to implement the '.file
   /// "foo.c"' assembler directive.
   virtual void emitFileDirective(StringRef Filename);
 
-  /// Emit ".file assembler diretive with additioal info.
+  /// Emit ".file assembler diretive with additional info.
   virtual void emitFileDirective(StringRef Filename, StringRef CompilerVerion,
                                  StringRef TimeStamp, StringRef Description);
 
   /// Emit the "identifiers" directive.  This implements the
   /// '.ident "version foo"' assembler directive.
   virtual void emitIdent(StringRef IdentString) {}
 
   /// Associate a filename with a specified logical file number.  This

llvm/include/llvm/Support/BranchProbability.h

public:
   static BranchProbability getUnknown() { return BranchProbability(UnknownN); }
   // Create a BranchProbability object with the given numerator and 1<<31
   // as denominator.
   static BranchProbability getRaw(uint32_t N) { return BranchProbability(N); }
   // Create a BranchProbability object from 64-bit integers.
   static BranchProbability getBranchProbability(uint64_t Numerator,
                                                 uint64_t Denominator);
 
-  // Normalize given probabilties so that the sum of them becomes approximate
+  // Normalize given probabilities so that the sum of them becomes approximate
   // one.
   template <class ProbabilityIter>
   static void normalizeProbabilities(ProbabilityIter Begin,
                                      ProbabilityIter End);
 
   uint32_t getNumerator() const { return N; }
   static uint32_t getDenominator() { return D; }
 

llvm/include/llvm/Support/RWMutex.h

 #define LLVM_SUPPORT_RWMUTEX_H
 
 #include "llvm/Config/llvm-config.h"
 #include "llvm/Support/Threading.h"
 #include <cassert>
 #include <mutex>
 #include <shared_mutex>
 
-// std::shared_timed_mutex is only availble on macOS 10.12 and later.
+// std::shared_timed_mutex is only available on macOS 10.12 and later.
 #if defined(__APPLE__) && defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__)
 #if __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 101200
 #define LLVM_USE_RW_MUTEX_IMPL
 #endif
 #endif
 
 namespace llvm {
 namespace sys {

llvm/include/llvm/Support/TypeName.h

 
 namespace llvm {
 
 /// We provide a function which tries to compute the (demangled) name of a type
 /// statically.
 ///
 /// This routine may fail on some platforms or for particularly unusual types.
 /// Do not use it for anything other than logging and debugging aids. It isn't
-/// portable or dependendable in any real sense.
+/// portable or dependable in any real sense.
 ///
 /// The returned StringRef will point into a static storage duration string.
 /// However, it may not be null terminated and may be some strangely aligned
 /// inner substring of a larger string.
 template <typename DesiredTypeName>
 inline StringRef getTypeName() {
 #if defined(__clang__) || defined(__GNUC__)
   StringRef Name = __PRETTY_FUNCTION__;

llvm/include/llvm/Transforms/IPO/Attributor.h

struct AbstractState {
   virtual ChangeStatus indicatePessimisticFixpoint() = 0;
 };
 
 /// Simple state with integers encoding.
 ///
 /// The interface ensures that the assumed bits are always a subset of the known
 /// bits. Users can only add known bits and, except through adding known bits,
 /// they can only remove assumed bits. This should guarantee monotoniticy and
-/// thereby the existence of a fixpoint (if used corretly). The fixpoint is
+/// thereby the existence of a fixpoint (if used correctly). The fixpoint is
 /// reached when the assumed and known state/bits are equal. Users can
 /// force/inidicate a fixpoint. If an optimistic one is indicated, the known
 /// state will catch up with the assumed one, for a pessimistic fixpoint it is
 /// the other way around.
 template <typename base_ty, base_ty BestState, base_ty WorstState>
 struct IntegerStateBase : public AbstractState {
   using base_t = base_ty;
 
struct BooleanState : public IntegerStateBase<bool, true, false> {
   using base_t = IntegerStateBase::base_t;
 
   BooleanState() = default;
   BooleanState(base_t Assumed) : super(Assumed) {}
 
   /// Set the assumed value to \p Value but never below the known one.
   void setAssumed(bool Value) { Assumed &= (Known | Value); }
 
-  /// Set the known and asssumed value to \p Value.
+  /// Set the known and assumed value to \p Value.
   void setKnown(bool Value) {
     Known |= Value;
     Assumed |= Value;
   }
 
   /// Return true if the state is assumed to hold.
   bool isAssumed() const { return getAssumed(); }
 
struct DerefState : AbstractState {
   /// int f(int *A){
   ///    *A = 0;
   ///    *(A+2) = 2;
   ///    *(A+1) = 1;
   ///    *(A+10) = 10;
   /// }
   /// ```
   /// In that case, AccessedBytesMap is `{0:4, 4:4, 8:4, 40:4}`.
-  /// AccessedBytesMap is std::map so it is iterated in accending order on
+  /// AccessedBytesMap is std::map so it is iterated in ascending order on
   /// key(Offset). So KnownBytes will be updated like this:
   ///
   /// |Access | KnownBytes
   /// |(0, 4)| 0 -> 4
   /// |(4, 4)| 4 -> 8
   /// |(8, 4)| 8 -> 12
   /// |(40, 4) | 12 (break)
   void computeKnownDerefBytesFromAccessedMap() {

llvm/include/llvm/Transforms/IPO/FunctionAttrs.h

 bool thinLTOPropagateFunctionAttrs(
     ModuleSummaryIndex &Index,
     function_ref<bool(GlobalValue::GUID, const GlobalValueSummary *)>
         isPrevailing);
 
 /// Computes function attributes in post-order over the call graph.
 ///
 /// By operating in post-order, this pass computes precise attributes for
-/// called functions prior to processsing their callers. This "bottom-up"
+/// called functions prior to processing their callers. This "bottom-up"
 /// approach allows powerful interprocedural inference of function attributes
 /// like memory access patterns, etc. It can discover functions that do not
 /// access memory, or only read memory, and give them the readnone/readonly
 /// attribute. It also discovers function arguments that are not captured by
 /// the function and marks them with the nocapture attribute.
 struct PostOrderFunctionAttrsPass : PassInfoMixin<PostOrderFunctionAttrsPass> {
   PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &AM,
                         LazyCallGraph &CG, CGSCCUpdateResult &UR);

llvm/include/llvm/Transforms/Scalar/LoopPassManager.h

 /// FunctionPassManager. Note that if this pass is constructed with a \c
 /// FunctionAnalysisManager it will run the \c LoopAnalysisManagerFunctionProxy
 /// analysis prior to running the loop passes over the function to enable a \c
 /// LoopAnalysisManager to be used within this run safely.
 ///
 /// The adaptor comes with two modes: the loop mode and the loop-nest mode, and
 /// the worklist updater lived inside will be in the same mode as the adaptor
 /// (refer to the documentation of \c LPMUpdater for more detailed explanation).
-/// Specifically, in loop mode, all loops in the funciton will be pushed into
+/// Specifically, in loop mode, all loops in the function will be pushed into
 /// the worklist and processed by \p Pass, while only top-level loops are
 /// processed in loop-nest mode. Please refer to the various specializations of
 /// \fn createLoopFunctionToLoopPassAdaptor to see when loop mode and loop-nest
 /// mode are used.
 class FunctionToLoopPassAdaptor
     : public PassInfoMixin<FunctionToLoopPassAdaptor> {
 public:
   using PassConceptT =

llvm/lib/Analysis/BasicAliasAnalysis.cpp

AliasResult BasicAAResult::aliasGEP(
   APInt ModOffset = DecompGEP1.Offset.srem(GCD);
   if (ModOffset.isNegative())
     ModOffset += GCD; // We want mod, not rem.
   if (ModOffset.uge(V2Size.getValue()) &&
       (GCD - ModOffset).uge(V1Size.getValue()))
     return AliasResult::NoAlias;
 
   // Compute ranges of potentially accessed bytes for both accesses. If the
-  // interseciton is empty, there can be no overlap.
+  // intersection is empty, there can be no overlap.
   unsigned BW = OffsetRange.getBitWidth();
   ConstantRange Range1 = OffsetRange.add(
       ConstantRange(APInt(BW, 0), APInt(BW, V1Size.getValue())));
   ConstantRange Range2 =
       ConstantRange(APInt(BW, 0), APInt(BW, V2Size.getValue()));
   if (Range1.intersectWith(Range2).isEmptySet())
     return AliasResult::NoAlias;
 

llvm/lib/Analysis/DependenceAnalysis.cpp

else {
     if (Splitable)
       OS << " splitable";
   }
   OS << "!\n";
 }
 
 // Returns NoAlias/MayAliass/MustAlias for two memory locations based upon their
 // underlaying objects. If LocA and LocB are known to not alias (for any reason:
-// tbaa, non-overlapping regions etc), then it is known there is no dependecy.
+// tbaa, non-overlapping regions etc), then it is known there is no dependency.
 // Otherwise the underlying objects are checked to see if they point to
 // different identifiable objects.
 static AliasResult underlyingObjectsAlias(AAResults *AA,
                                           const DataLayout &DL,
                                           const MemoryLocation &LocA,
                                           const MemoryLocation &LocB) {
   // Check the original locations (minus size) for noalias, which can happen for
   // tbaa, incompatible underlying object locations, etc.

llvm/lib/Analysis/InstructionSimplify.cpp

if (isa<ConstantPointerNull>(RHS) && ICmpInst::isEquality(Pred) &&
                            IIQ.UseInstrInfo))
     return ConstantInt::get(getCompareTy(LHS), !CmpInst::isTrueWhenEqual(Pred));
 
   // We can only fold certain predicates on pointer comparisons.
   switch (Pred) {
   default:
     return nullptr;
 
-    // Equality comaprisons are easy to fold.
+    // Equality comparisons are easy to fold.
   case CmpInst::ICMP_EQ:
   case CmpInst::ICMP_NE:
     break;
 
     // We can only handle unsigned relational comparisons because 'inbounds' on
     // a GEP only protects against unsigned wrapping.
   case CmpInst::ICMP_UGT:
   case CmpInst::ICMP_UGE:

llvm/lib/Analysis/LazyCallGraph.cpp

for (int i = SourceIdx, e = TargetIdx + 1; i < e; ++i)
     SCCIndices.find(SCCs[i])->second = i;
 
   // If the target doesn't connect to the source, then we've corrected the
   // post-order and there are no cycles formed.
   if (!ConnectedSet.count(&TargetSCC)) {
     assert(SourceI > (SCCs.begin() + SourceIdx) &&
            "Must have moved the source to fix the post-order.");
     assert(*std::prev(SourceI) == &TargetSCC &&
-           "Last SCC to move should have bene the target.");
+           "Last SCC to move should have been the target.");
 
     // Return an empty range at the target SCC indicating there is nothing to
     // merge.
     return make_range(std::prev(SourceI), std::prev(SourceI));
   }
 
   assert(SCCs[TargetIdx] == &TargetSCC &&
          "Should not have moved target if connected!");

llvm/lib/Analysis/TFUtils.cpp

public:
   void initInput(size_t Index, TF_DataType Type,
                  const std::vector<int64_t> &Dimensions);
   const std::vector<TF_Tensor *> &getInput() const { return Input; }
 
   ~TFModelEvaluatorImpl();
 
 private:
   /// The objects necessary for carrying out an evaluation of the SavedModel.
-  /// They are expensive to set up, and we maintain them accross all the
+  /// They are expensive to set up, and we maintain them across all the
   /// evaluations of the model.
   TF_Session *Session = nullptr;
   TFGraphPtr Graph;
   TFSessionOptionsPtr Options;
 
   /// The specification of the input nodes.
   std::vector<TF_Output> InputFeed;
 

llvm/lib/Analysis/VectorUtils.cpp

for (auto *Group : LoadGroups) {
     // nullptr even without the transformation.
     if (Group->getNumMembers() == Group->getFactor())
       continue;
 
     // Case 2: If first and last members of the group don't wrap this implies
     // that all the pointers in the group don't wrap.
     // So we check only group member 0 (which is always guaranteed to exist),
     // and group member Factor - 1; If the latter doesn't exist we rely on
-    // peeling (if it is a non-reversed accsess -- see Case 3).
+    // peeling (if it is a non-reversed access -- see Case 3).
     if (InvalidateGroupIfMemberMayWrap(Group, 0, std::string("first")))
       continue;
     if (Group->getMember(Group->getFactor() - 1))
       InvalidateGroupIfMemberMayWrap(Group, Group->getFactor() - 1,
                                      std::string("last"));
     else {
       // Case 3: A non-reversed interleaved load group with gaps: We need
       // to execute at least one scalar epilogue iteration. This will ensure

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::emitBBAddrMapSection(const MachineFunction &MF) {
   OutStreamer->emitInt8(OutStreamer->getContext().getBBAddrMapVersion());
   OutStreamer->AddComment("feature");
   OutStreamer->emitInt8(0);
   OutStreamer->AddComment("function address");
   OutStreamer->emitSymbolValue(FunctionSymbol, getPointerSize());
   OutStreamer->AddComment("number of basic blocks");
   OutStreamer->emitULEB128IntValue(MF.size());
   const MCSymbol *PrevMBBEndSymbol = FunctionSymbol;
-  // Emit BB Information for each basic block in the funciton.
+  // Emit BB Information for each basic block in the function.
   for (const MachineBasicBlock &MBB : MF) {
     const MCSymbol *MBBSymbol =
         MBB.isEntryBlock() ? FunctionSymbol : MBB.getSymbol();
     // Emit the basic block offset relative to the end of the previous block.
     // This is zero unless the block is padded due to alignment.
     emitLabelDifferenceAsULEB128(MBBSymbol, PrevMBBEndSymbol);
     // Emit the basic block size. When BBs have alignments, their size cannot
     // always be computed from their offsets.

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

static TypeRecordKind getRecordKind(const DICompositeType *Ty) {
   case dwarf::DW_TAG_structure_type:
     return TypeRecordKind::Struct;
   default:
     llvm_unreachable("unexpected tag");
   }
 }
 
 /// Return ClassOptions that should be present on both the forward declaration
-/// and the defintion of a tag type.
+/// and the definition of a tag type.
 static ClassOptions getCommonClassOptions(const DICompositeType *Ty) {
   ClassOptions CO = ClassOptions::None;
 
   // MSVC always sets this flag, even for local types. Clang doesn't always
   // appear to give every type a linkage name, which may be problematic for us.
   // FIXME: Investigate the consequences of not following them here.
   if (!Ty->getIdentifier().empty())
     CO |= ClassOptions::HasUniqueName;

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

void DwarfDebug::beginModule(Module *M) {
 
   if (!Asm || !MMI->hasDebugInfo())
     return;
 
   unsigned NumDebugCUs = std::distance(M->debug_compile_units_begin(),
                                        M->debug_compile_units_end());
   assert(NumDebugCUs > 0 && "Asm unexpectedly initialized");
   assert(MMI->hasDebugInfo() &&
-         "DebugInfoAvailabilty unexpectedly not initialized");
+         "DebugInfoAvailability unexpectedly not initialized");
   SingleCU = NumDebugCUs == 1;
   DenseMap<DIGlobalVariable *, SmallVector<DwarfCompileUnit::GlobalExpr, 1>>
       GVMap;
   for (const GlobalVariable &Global : M->globals()) {
     SmallVector<DIGlobalVariableExpression *, 1> GVs;
     Global.getDebugInfo(GVs);
     for (auto *GVE : GVs)
       GVMap[GVE->getVariable()].push_back({&Global, GVE->getExpression()});
if (StartLabel == EndLabel) {
       LLVM_DEBUG(dbgs() << "Omitting location list entry with empty range.\n");
       continue;
     }
 
     SmallVector<DbgValueLoc, 4> Values;
     for (auto &R : OpenRanges)
       Values.push_back(R.second);
 
-    // With Basic block sections, it is posssible that the StartLabel and the
+    // With Basic block sections, it is possible that the StartLabel and the
     // Instr are not in the same section.  This happens when the StartLabel is
     // the function begin label and the dbg value appears in a basic block
     // that is not the entry.  In this case, the range needs to be split to
     // span each individual section in the range from StartLabel to EndLabel.
     if (Asm->MF->hasBBSections() && StartLabel == Asm->getFunctionBegin() &&
         !Instr->getParent()->sameSection(&Asm->MF->front())) {
       const MCSymbol *BeginSectionLabel = StartLabel;
 

llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp

MCSymbol *EHStreamer::emitExceptionTable() {
 
   // Compute the actions table and gather the first action index for each
   // landing pad site.
   SmallVector<ActionEntry, 32> Actions;
   SmallVector<unsigned, 64> FirstActions;
   computeActionsTable(LandingPads, Actions, FirstActions);
 
   // Compute the call-site table and call-site ranges. Normally, there is only
-  // one call-site-range which covers the whole funciton. With
+  // one call-site-range which covers the whole function. With
   // -basic-block-sections, there is one call-site-range per basic block
   // section.
   SmallVector<CallSiteEntry, 64> CallSites;
   SmallVector<CallSiteRange, 4> CallSiteRanges;
   computeCallSiteTable(CallSites, CallSiteRanges, LandingPads, FirstActions);
 
   bool IsSJLJ = Asm->MAI->getExceptionHandlingType() == ExceptionHandling::SjLj;
   bool IsWasm = Asm->MAI->getExceptionHandlingType() == ExceptionHandling::Wasm;

llvm/lib/CodeGen/BasicBlockSections.cpp

 //===-- BasicBlockSections.cpp ---=========--------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // BasicBlockSections implementation.
 //
 // The purpose of this pass is to assign sections to basic blocks when
 // -fbasic-block-sections= option is used. Further, with profile information
 // only the subset of basic blocks with profiles are placed in separate sections
 // and the rest are grouped in a cold section. The exception handling blocks are
-// treated specially to ensure they are all in one seciton.
+// treated specially to ensure they are all in one section.
 //
 // Basic Block Sections
 // ====================
 //
 // With option, -fbasic-block-sections=list, every function may be split into
 // clusters of basic blocks. Every cluster will be emitted into a separate
 // section with its basic blocks sequenced in the given order. To get the
 // optimized performance, the clusters must form an optimal BB layout for the

llvm/lib/CodeGen/BreakFalseDeps.cpp

for (MCRegUnitRootIterator Root(*Unit, TRI); Root.isValid(); ++Root) {
         return false;
     }
   }
 
   // Get the undef operand's register class
   const TargetRegisterClass *OpRC =
     TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
 
-  // If the instruction has a true dependency, we can hide the false depdency
+  // If the instruction has a true dependency, we can hide the false dependency
   // behind it.
   for (MachineOperand &CurrMO : MI->operands()) {
     if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
       !OpRC->contains(CurrMO.getReg()))
       continue;
     // We found a true dependency - replace the undef register with the true
     // dependency.
     MO.setReg(CurrMO.getReg());

llvm/lib/CodeGen/CodeGenPrepare.cpp

 //   ...
 //   %UGEPI = gep %GEPI, (UIdx-Idx)
 //   ...
 // ---------------------------
 //
 // The register pressure on the IndirectBr edges is reduced because %GEPIOp is
 // no longer alive on them.
 //
-// We try to unmerge GEPs here in CodGenPrepare, as opposed to limiting merging
+// We try to unmerge GEPs here in CodeGenPrepare, as opposed to limiting merging
 // of GEPs in the first place in InstCombiner::visitGetElementPtrInst() so as
 // not to disable further simplications and optimizations as a result of GEP
 // merging.
 //
 // Note this unmerging may increase the length of the data flow critical path
 // (the path from %GEPIOp to %UGEPI would go through %GEPI), which is a tradeoff
 // between the register pressure and the length of data-flow critical
 // path. Restricting this to the uncommon IndirectBr case would minimize the

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) {
     // Widen SrcTy to WideTy. This does not affect the result, but since the
     // user requested this size, it is probably better handled than SrcTy and
     // should reduce the total number of legalization artifacts.
     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
       SrcTy = WideTy;
       SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0);
     }
 
-    // Theres no unmerge type to target. Directly extract the bits from the
+    // There's no unmerge type to target. Directly extract the bits from the
     // source type
     unsigned DstSize = DstTy.getSizeInBits();
 
     MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
     for (int I = 1; I != NumDst; ++I) {
       auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
       auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
       MIRBuilder.buildTrunc(MI.getOperand(I), Shr);

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

if (MI.isTerminator()) {
       // therefore there is no need to split.
       if (ValMapping.NumBreakDowns == 1)
         // This is a already a copy, there is nothing to do.
         RepairPt.switchTo(RepairingPlacement::RepairingKind::Reassign);
     }
     return;
   }
 
-  // At this point, we need to repair a defintion of a terminator.
+  // At this point, we need to repair a definition of a terminator.
 
   // Technically we need to fix the def of MI on all outgoing
   // edges of MI to keep the repairing local. In other words, we
   // will create several definitions of the same register. This
   // does not work for SSA unless that definition is a physical
   // register.
   // However, there are other cases where we can get away with
   // that while still keeping the repairing local.

llvm/lib/CodeGen/LiveVariables.cpp

for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
     // Or is it live because there is a use in a successor that kills it?
     if (Kills.count(SuccMBB))
       return true;
   }
 
   return false;
 }
 
-/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
+/// addNewBlock - Add a new basic block BB as an empty successor to DomBB. All
 /// variables that are live out of DomBB will be marked as passing live through
 /// BB.
 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
                                 MachineBasicBlock *DomBB,
                                 MachineBasicBlock *SuccBB) {
   const unsigned NumNew = BB->getNumber();
 
   DenseSet<unsigned> Defs, Kills;
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     // If the register is either killed in or live through SuccBB it's also live
     // through BB.
     VarInfo &VI = getVarInfo(Reg);
     if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
       VI.AliveBlocks.set(NumNew);
   }
 }
 
-/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
+/// addNewBlock - Add a new basic block BB as an empty successor to DomBB. All
 /// variables that are live out of DomBB will be marked as passing live through
 /// BB. LiveInSets[BB] is *not* updated (because it is not needed during
 /// PHIElimination).
 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
                                 MachineBasicBlock *DomBB,
                                 MachineBasicBlock *SuccBB,
                                 std::vector<SparseBitVector<>> &LiveInSets) {
   const unsigned NumNew = BB->getNumber();

llvm/lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::visitMachineFunctionAfter() {
 
   if (LiveVars)
     verifyLiveVariables();
   if (LiveInts)
     verifyLiveIntervals();
 
   // Check live-in list of each MBB. If a register is live into MBB, check
   // that the register is in regsLiveOut of each predecessor block. Since
-  // this must come from a definition in the predecesssor or its live-in
+  // this must come from a definition in the predecessor or its live-in
   // list, this will catch a live-through case where the predecessor does not
   // have the register in its live-in list.  This currently only checks
   // registers that have no aliases, are not allocatable and are not
   // reserved, which could mean a condition code register for instance.
   if (MRI->tracksLiveness())
     for (const auto &MBB : *MF)
       for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
         MCPhysReg LiveInReg = P.PhysReg;

llvm/lib/CodeGen/ModuloSchedule.cpp

if (MO.isDef()) {
       if (LastDef)
         replaceRegUsesAfterLoop(reg, NewReg, BB, MRI, LIS);
     } else if (MO.isUse()) {
       MachineInstr *Def = MRI.getVRegDef(reg);
       // Compute the stage that contains the last definition for instruction.
       int DefStageNum = Schedule.getStage(Def);
       unsigned StageNum = CurStageNum;
       if (DefStageNum != -1 && (int)InstrStageNum > DefStageNum) {
-        // Compute the difference in stages between the defintion and the use.
+        // Compute the difference in stages between the definition and the use.
         unsigned StageDiff = (InstrStageNum - DefStageNum);
         // Make an adjustment to get the last definition.
         StageNum -= StageDiff;
       }
       if (VRMap[StageNum].count(reg))
         MO.setReg(VRMap[StageNum][reg]);
     }
   }

llvm/lib/CodeGen/PrologEpilogInserter.cpp

else
       StackAlign = TFI.getTransientStackAlign();
 
     // If the frame pointer is eliminated, all frame offsets will be relative to
     // SP not FP. Align to MaxAlign so this works.
     StackAlign = std::max(StackAlign, MaxAlign);
     int64_t OffsetBeforeAlignment = Offset;
     Offset = alignTo(Offset, StackAlign, Skew);
 
-    // If we have increased the offset to fulfill the alignment constrants,
+    // If we have increased the offset to fulfill the alignment constraints,
     // then the scavenging spill slots may become harder to reach from the
     // stack pointer, float them so they stay close.
     if (StackGrowsDown && OffsetBeforeAlignment != Offset && RS &&
         !EarlyScavengingSlots) {
       SmallVector<int, 2> SFIs;
       RS->getScavengingFrameIndices(SFIs);
       LLVM_DEBUG(if (!SFIs.empty()) llvm::dbgs()
                      << "Adjusting emergency spill slots!\n";);

llvm/lib/CodeGen/RegisterCoalescer.cpp

 static cl::opt<unsigned> LargeIntervalSizeThreshold(
     "large-interval-size-threshold", cl::Hidden,
     cl::desc("If the valnos size of an interval is larger than the threshold, "
              "it is regarded as a large interval. "),
     cl::init(100));
 
 static cl::opt<unsigned> LargeIntervalFreqThreshold(
     "large-interval-freq-threshold", cl::Hidden,
-    cl::desc("For a large interval, if it is coalesed with other live "
+    cl::desc("For a large interval, if it is coalesced with other live "
              "intervals many times more than the threshold, stop its "
              "coalescing to control the compile time. "),
     cl::init(100));
 
 namespace {
 
   class JoinVals;
 

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

if (MI.mayRaiseFPException()) {
       }
     }
 
     // If it's not a store or a variant load, we're done.
     if (!MI.mayStore() &&
         !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad()))
       continue;
 
-    // Always add dependecy edge to BarrierChain if present.
+    // Always add dependency edge to BarrierChain if present.
     if (BarrierChain)
       BarrierChain->addPredBarrier(SU);
 
     // Find the underlying objects for MI. The Objs vector is either
     // empty, or filled with the Values of memory locations which this
     // SU depends on.
     UnderlyingObjectsVector Objs;
     bool ObjsFound = getUnderlyingObjectsForInstr(&MI, MFI, Objs,

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
                getCurSDLoc(), LeftProb, RightProb);
 
   if (W.MBB == SwitchMBB)
     visitSwitchCase(CB, SwitchMBB);
   else
     SL->SwitchCases.push_back(CB);
 }
 
-// Scale CaseProb after peeling a case with the probablity of PeeledCaseProb
+// Scale CaseProb after peeling a case with the probability of PeeledCaseProb
 // from the swith statement.
 static BranchProbability scaleCaseProbality(BranchProbability CaseProb,
                                             BranchProbability PeeledCaseProb) {
   if (PeeledCaseProb == BranchProbability::getOne())
     return BranchProbability::getZero();
   BranchProbability SwitchProb = PeeledCaseProb.getCompl();
 
   uint32_t Numerator = CaseProb.getNumerator();
MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
   auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
   SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt,
                           nullptr,   nullptr,      TopCaseProb.getCompl()};
   lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
 
   Clusters.erase(PeeledCaseIt);
   for (CaseCluster &CC : Clusters) {
     LLVM_DEBUG(
-        dbgs() << "Scale the probablity for one cluster, before scaling: "
+        dbgs() << "Scale the probability for one cluster, before scaling: "
                << CC.Prob << "\n");
     CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb);
     LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n");
   }
   PeeledCaseProb = TopCaseProb;
   return PeeledSwitchMBB;
 }
 
void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
 
   MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
 
   // Cluster adjacent cases with the same destination. We do this at all
   // optimization levels because it's cheap to do and will make codegen faster
   // if there are many clusters.
   sortAndRangeify(Clusters);
 
-  // The branch probablity of the peeled case.
+  // The branch probability of the peeled case.
   BranchProbability PeeledCaseProb = BranchProbability::getZero();
   MachineBasicBlock *PeeledSwitchMBB =
       peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
 
   // If there is only the default destination, jump there directly.
   MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
   if (Clusters.empty()) {
     assert(PeeledSwitchMBB == SwitchMBB);

llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp

 namespace {
 /// This pass calculates the liveness information for each basic block in
 /// a function and attaches the register live-out information to a patchpoint
 /// intrinsic if present.
 ///
 /// This pass can be disabled via the -enable-patchpoint-liveness=false flag.
 /// The pass skips functions that don't have any patchpoint intrinsics. The
 /// information provided by this pass is optional and not required by the
-/// aformentioned intrinsic to function.
+/// aforementioned intrinsic to function.
 class StackMapLiveness : public MachineFunctionPass {
   const TargetRegisterInfo *TRI;
   LivePhysRegs LiveRegs;
 
 public:
   static char ID;
 
   /// Default construct and initialize the pass.

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

if (Kind.isText()) {
     return TextSection;
   }
 
   // TODO: We may put Kind.isReadOnlyWithRel() under option control, because
   // user may want to have read-only data with relocations placed into a
   // read-only section by the compiler.
   // For BSS kind, zero initialized data must be emitted to the .data section
   // because external linkage control sections that get mapped to the .bss
-  // section will be linked as tentative defintions, which is only appropriate
+  // section will be linked as tentative definitions, which is only appropriate
   // for SectionKind::Common.
   if (Kind.isData() || Kind.isReadOnlyWithRel() || Kind.isBSS()) {
     if (TM.getDataSections()) {
       SmallString<128> Name;
       getNameWithPrefix(Name, GO, TM);
       return getContext().getXCOFFSection(
           Name, SectionKind::getData(),
           XCOFF::CsectProperties(XCOFF::XMC_RW, XCOFF::XTY_SD));

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

if (MO.isUse()) {
         Kills.push_back(MOReg);
     } else if (MOReg.isPhysical()) {
       Defs.push_back(MOReg);
       if (!MO.isDead())
         LiveDefs.push_back(MOReg);
     }
   }
 
-  // Check if the reschedule will not break depedencies.
+  // Check if the reschedule will not break dependencies.
   unsigned NumVisited = 0;
   for (MachineInstr &OtherMI :
        make_range(mi, MachineBasicBlock::iterator(KillMI))) {
     // Debug or pseudo instructions cannot be counted against the limit.
     if (OtherMI.isDebugOrPseudoInstr())
       continue;
     if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
       return false;

llvm/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp

while (true) {
     if (A && F) {
       bool IsImplicitConst = (F == DW_FORM_implicit_const);
       if (IsImplicitConst) {
         int64_t V = Data.getSLEB128(OffsetPtr);
         AttributeSpecs.push_back(AttributeSpec(A, F, V));
         continue;
       }
       Optional<uint8_t> ByteSize;
-      // If this abbrevation still has a fixed byte size, then update the
+      // If this abbreviation still has a fixed byte size, then update the
       // FixedAttributeSize as needed.
       switch (F) {
       case DW_FORM_addr:
         if (FixedAttributeSize)
           ++FixedAttributeSize->NumAddrs;
         break;
 
       case DW_FORM_ref_addr:
if (A && F) {
       AttributeSpecs.push_back(AttributeSpec(A, F, ByteSize));
     } else if (A == 0 && F == 0) {
       // We successfully reached the end of this abbreviation declaration
       // since both attribute and form are zero.
       break;
     } else {
       // Attribute and form pairs must either both be non-zero, in which case
       // they are added to the abbreviation declaration, or both be zero to
-      // terminate the abbrevation declaration. In this case only one was
+      // terminate the abbreviation declaration. In this case only one was
       // zero which is an error.
       clear();
       return false;
     }
   }
   return true;
 }
 

llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp

llvm::Expected<LookupResult> FunctionInfo::lookup(DataExtractor &Data,
                                                   uint64_t FuncAddr,
                                                   uint64_t Addr) {
   LookupResult LR;
   LR.LookupAddr = Addr;
   uint64_t Offset = 0;
   LR.FuncRange = {FuncAddr, FuncAddr + Data.getU32(&Offset)};
   uint32_t NameOffset = Data.getU32(&Offset);
   // The "lookup" functions doesn't report errors as accurately as the "decode"
-  // function as it is meant to be fast. For more accurage errors we could call
+  // function as it is meant to be fast. For more accurate errors we could call
   // "decode".
   if (!Data.isValidOffset(Offset))
     return createStringError(std::errc::io_error,
                               "FunctionInfo data is truncated");
   // This function will be called with the result of a binary search of the
   // address table, we must still make sure the address does not fall into a
   // gap between functions are after the last function.
   if (LR.FuncRange.size() > 0 && !LR.FuncRange.contains(Addr))

llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp

extern "C" {
   extern "C" void __jit_debug_register_code();
 }
 
 namespace {
 
 // FIXME: lli aims to provide both, RuntimeDyld and JITLink, as the dynamic
 // loaders for it's JIT implementations. And they both offer debugging via the
 // GDB JIT interface, which builds on the two well-known symbol names below.
-// As these symbols must be unique accross the linked executable, we can only
+// As these symbols must be unique across the linked executable, we can only
 // define them in one of the libraries and make the other depend on it.
 // OrcTargetProcess is a minimal stub for embedding a JIT client in remote
 // executors. For the moment it seems reasonable to have the definition there
 // and let ExecutionEngine depend on it, until we find a better solution.
 //
 LLVM_ATTRIBUTE_USED void requiredSymbolDefinitionsFromOrcTargetProcess() {
   errs() << (void *)&__jit_debug_register_code
          << (void *)&__jit_debug_descriptor;

llvm/lib/ExecutionEngine/JITLink/COFFLinkGraphBuilder.cpp

 //=--------- COFFLinkGraphBuilder.cpp - COFF LinkGraph builder ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// Generic COFF LinkGraph buliding code.
+// Generic COFF LinkGraph building code.
 //
 //===----------------------------------------------------------------------===//
 #include "COFFLinkGraphBuilder.h"
 
 #define DEBUG_TYPE "jitlink"
 
 static const char *CommonSectionName = "__common";
 

llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.cpp

 //=----------- ELFLinkGraphBuilder.cpp - ELF LinkGraph builder ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// Generic ELF LinkGraph buliding code.
+// Generic ELF LinkGraph building code.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ELFLinkGraphBuilder.h"
 
 #define DEBUG_TYPE "jitlink"
 
 static const char *DWSecNames[] = {

llvm/lib/ExecutionEngine/JITLink/ELF_aarch64.cpp

return ELFLinkGraphBuilder_aarch64<object::ELF64LE>((*ELFObj)->getFileName(),
       .buildGraph();
 }
 
 void link_ELF_aarch64(std::unique_ptr<LinkGraph> G,
                       std::unique_ptr<JITLinkContext> Ctx) {
   PassConfiguration Config;
   const Triple &TT = G->getTargetTriple();
   if (Ctx->shouldAddDefaultTargetPasses(TT)) {
-    // Add eh-frame passses.
+    // Add eh-frame passes.
     Config.PrePrunePasses.push_back(DWARFRecordSectionSplitter(".eh_frame"));
     Config.PrePrunePasses.push_back(EHFrameEdgeFixer(
         ".eh_frame", 8, aarch64::Pointer32, aarch64::Pointer64,
         aarch64::Delta32, aarch64::Delta64, aarch64::NegDelta32));
 
     // Add a mark-live pass.
     if (auto MarkLive = Ctx->getMarkLivePass(TT))
       Config.PrePrunePasses.push_back(std::move(MarkLive));

llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp

 //=--------- MachOLinkGraphBuilder.cpp - MachO LinkGraph builder ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// Generic MachO LinkGraph buliding code.
+// Generic MachO LinkGraph building code.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MachOLinkGraphBuilder.h"
 
 #define DEBUG_TYPE "jitlink"
 
 static const char *CommonSectionName = "__common";

llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp

if (auto MarkLive = Ctx->getMarkLivePass(G->getTargetTriple()))
       Config.PrePrunePasses.push_back(std::move(MarkLive));
     else
       Config.PrePrunePasses.push_back(markAllSymbolsLive);
 
     // Add compact unwind splitter pass.
     Config.PrePrunePasses.push_back(
         CompactUnwindSplitter("__LD,__compact_unwind"));
 
-    // Add eh-frame passses.
+    // Add eh-frame passes.
     // FIXME: Prune eh-frames for which compact-unwind is available once
     // we support compact-unwind registration with libunwind.
     Config.PrePrunePasses.push_back(
         DWARFRecordSectionSplitter("__TEXT,__eh_frame"));
     Config.PrePrunePasses.push_back(EHFrameEdgeFixer(
         "__TEXT,__eh_frame", 8, aarch64::Pointer32, aarch64::Pointer64,
         aarch64::Delta32, aarch64::Delta64, aarch64::NegDelta32));
 

llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp

 }
 
 void link_MachO_x86_64(std::unique_ptr<LinkGraph> G,
                        std::unique_ptr<JITLinkContext> Ctx) {
 
   PassConfiguration Config;
 
   if (Ctx->shouldAddDefaultTargetPasses(G->getTargetTriple())) {
-    // Add eh-frame passses.
+    // Add eh-frame passes.
     Config.PrePrunePasses.push_back(createEHFrameSplitterPass_MachO_x86_64());
     Config.PrePrunePasses.push_back(createEHFrameEdgeFixerPass_MachO_x86_64());
 
     // Add compact unwind splitter pass.
     Config.PrePrunePasses.push_back(
         CompactUnwindSplitter("__LD,__compact_unwind"));
 
     // Add a mark-live pass.

llvm/lib/ExecutionEngine/Orc/Core.cpp

if (Err) {
       // FIXME: Should this be reported / treated as failure to materialize?
       // Or should this be treated as a sanctioned bailing-out?
       ES.reportError(std::move(Err));
       R->failMaterialization();
       return;
     }
   }
 
-  // The OnResolveInfo struct will hold the aliases and responsibilty for each
+  // The OnResolveInfo struct will hold the aliases and responsibility for each
   // query in the list.
   struct OnResolveInfo {
     OnResolveInfo(std::unique_ptr<MaterializationResponsibility> R,
                   SymbolAliasMap Aliases)
         : R(std::move(R)), Aliases(std::move(Aliases)) {}
 
     std::unique_ptr<MaterializationResponsibility> R;
     SymbolAliasMap Aliases;
for (auto &KV : Dependencies) {
           DepsOnOtherJITDylib.insert(OtherSymbol);
         }
       }
 
       if (DepsOnOtherJITDylib.empty())
         MI.UnemittedDependencies.erase(&OtherJITDylib);
     }
 
-    // If this symbol dependended on any symbols in the error state then move
+    // If this symbol depended on any symbols in the error state then move
     // this symbol to the error state too.
     if (DependsOnSymbolInErrorState)
       Symbols[Name].setFlags(Symbols[Name].getFlags() |
                              JITSymbolFlags::HasError);
   });
 }
 
 Error JITDylib::resolve(MaterializationResponsibility &MR,

llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp

Error RTDyldObjectLinkingLayer::onObjLoad(
   SymbolFlagsMap ExtraSymbolsToClaim;
   SymbolMap Symbols;
 
   // Hack to support COFF constant pool comdats introduced during compilation:
   // (See http://llvm.org/PR40074)
   if (auto *COFFObj = dyn_cast<object::COFFObjectFile>(&Obj)) {
     auto &ES = getExecutionSession();
 
-    // For all resolved symbols that are not already in the responsibilty set:
+    // For all resolved symbols that are not already in the responsibility set:
     // check whether the symbol is in a comdat section and if so mark it as
     // weak.
     for (auto &Sym : COFFObj->symbols()) {
       // getFlags() on COFF symbols can't fail.
       uint32_t SymFlags = cantFail(Sym.getFlags());
       if (SymFlags & object::BasicSymbolRef::SF_Undefined)
         continue;
       auto Name = Sym.getName();

llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp

Error SimpleRemoteEPC::handleSetup(uint64_t SeqNo, ExecutorAddr TagAddr,
   if (TagAddr)
     return make_error<StringError>("Setup packet TagAddr not zero",
                                    inconvertibleErrorCode());
 
   std::lock_guard<std::mutex> Lock(SimpleRemoteEPCMutex);
   auto I = PendingCallWrapperResults.find(0);
   assert(PendingCallWrapperResults.size() == 1 &&
          I != PendingCallWrapperResults.end() &&
-         "Setup message handler not connectly set up");
+         "Setup message handler not correctly set up");
   auto SetupMsgHandler = std::move(I->second);
   PendingCallWrapperResults.erase(I);
 
   auto WFR =
       shared::WrapperFunctionResult::copyFrom(ArgBytes.data(), ArgBytes.size());
   SetupMsgHandler(std::move(WFR));
   return Error::success();
 }

llvm/lib/IR/Attributes.cpp

bool AttrBuilder::hasAlignmentAttr() const {
   return getRawIntAttr(Attribute::Alignment) != 0;
 }
 
 bool AttrBuilder::operator==(const AttrBuilder &B) const {
   return Attrs == B.Attrs;
 }
 
 //===----------------------------------------------------------------------===//
-// AttributeFuncs Function Defintions
+// AttributeFuncs Function Definitions
 //===----------------------------------------------------------------------===//
 
 /// Which attributes cannot be applied to a type.
 AttributeMask AttributeFuncs::typeIncompatible(Type *Ty,
                                                AttributeSafetyKind ASK) {
   AttributeMask Incompatible;
 
   if (!Ty->isIntegerTy()) {

llvm/lib/IR/BuiltinGCs.cpp

 class ShadowStackGC : public GCStrategy {
 public:
   ShadowStackGC() = default;
 };
 
 /// A GCStrategy which serves as an example for the usage of a statepoint based
 /// lowering strategy.  This GCStrategy is intended to suitable as a default
 /// implementation usable with any collector which can consume the standard
-/// stackmap format generated by statepoints, uses the default addrespace to
+/// stackmap format generated by statepoints, uses the default addressspace to
 /// distinguish between gc managed and non-gc managed pointers, and has
 /// reasonable relocation semantics.
 class StatepointGC : public GCStrategy {
 public:
   StatepointGC() {
     UseStatepoints = true;
     // These options are all gc.root specific, we specify them so that the
     // gc.root lowering code doesn't run.

llvm/lib/IR/PassManager.cpp

 //===- PassManager.cpp - Infrastructure for managing & running IR passes --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/IR/PassManager.h"
 #include "llvm/ADT/DenseMapInfo.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/IR/PassManagerImpl.h"
 
 using namespace llvm;
 
 namespace llvm {
-// Explicit template instantiations and specialization defininitions for core
+// Explicit template instantiations and specialization definitions for core
 // template typedefs.
 template class AllAnalysesOn<Module>;
 template class AllAnalysesOn<Function>;
 template class PassManager<Module>;
 template class PassManager<Function>;
 template class AnalysisManager<Module>;
 template class AnalysisManager<Function>;
 template class InnerAnalysisManagerProxy<FunctionAnalysisManager, Module>;

llvm/lib/IR/ReplaceConstant.cpp

for (auto &Path : Paths) {
 
           // Mark CE as visited by mapping CE to NI.
           Visited[CE] = NI;
 
           // If required collect NI.
           if (Insts)
             Insts->insert(NI);
         } else {
-          // We had already encountered CE, the correponding instruction already
-          // exist, use it to replace CE.
+          // We had already encountered CE, the corresponding instruction
+          // already exists, use it to replace CE.
           NI = Visited[CE];
         }
 
         assert(NI && "Expected an instruction corresponding to constant "
                      "expression.");
 
         // Replace all uses of constant expression CE by the corresponding
         // instruction NI within the current parent instruction.

llvm/lib/MC/ELFObjectWriter.cpp

bool ELFWriter::isInSymtab(const MCAsmLayout &Layout, const MCSymbolELF &Symbol,
 
   if (Used)
     return true;
 
   if (Renamed)
     return false;
 
   if (Symbol.isVariable() && Symbol.isUndefined()) {
-    // FIXME: this is here just to diagnose the case of a var = commmon_sym.
+    // FIXME: this is here just to diagnose the case of a var = common_sym.
     Layout.getBaseSymbol(Symbol);
     return false;
   }
 
   if (Symbol.isTemporary())
     return false;
 
   if (Symbol.getType() == ELF::STT_SECTION)

llvm/lib/MC/MCParser/AsmLexer.cpp

bool AsmLexer::isAtStartOfComment(const char *Ptr) {
   if (MAI.getRestrictCommentStringToStartOfStatement() && !IsAtStartOfStatement)
     return false;
 
   StringRef CommentString = MAI.getCommentString();
 
   if (CommentString.size() == 1)
     return CommentString[0] == Ptr[0];
 
-  // Allow # preprocessor commments also be counted as comments for "##" cases
+  // Allow # preprocessor comments also be counted as comments for "##" cases
   if (CommentString[1] == '#')
     return CommentString[0] == Ptr[0];
 
   return strncmp(Ptr, CommentString.data(), CommentString.size()) == 0;
 }
 
 bool AsmLexer::isAtStatementSeparator(const char *Ptr) {
   return strncmp(Ptr, MAI.getSeparatorString(),

llvm/lib/MC/MCParser/AsmParser.cpp

 //    ::= .ascii [ "string"+ ( , "string"+ )* ]
 ///   ::= ( .asciz | .string ) [ "string" ( , "string" )* ]
 bool AsmParser::parseDirectiveAscii(StringRef IDVal, bool ZeroTerminated) {
   auto parseOp = [&]() -> bool {
     std::string Data;
     if (checkForValidSection())
       return true;
     // Only support spaces as separators for .ascii directive for now. See the
-    // discusssion at https://reviews.llvm.org/D91460 for more details.
+    // discussion at https://reviews.llvm.org/D91460 for more details.
     do {
       if (parseEscapedString(Data))
         return true;
       getStreamer().emitBytes(Data);
     } while (!ZeroTerminated && getTok().is(AsmToken::String));
     if (ZeroTerminated)
       getStreamer().emitBytes(StringRef("\0", 1));
     return false;

llvm/lib/MC/MCParser/ELFAsmParser.cpp

if (L.isNot(AsmToken::Comma))
     return false;
   Lex();
   StringRef UniqueStr;
   if (getParser().parseIdentifier(UniqueStr))
     return TokError("expected identifier in directive");
   if (UniqueStr != "unique")
     return TokError("expected 'unique'");
   if (L.isNot(AsmToken::Comma))
-    return TokError("expected commma");
+    return TokError("expected comma");
   Lex();
   if (getParser().parseAbsoluteExpression(UniqueID))
     return true;
   if (UniqueID < 0)
     return TokError("unique id must be positive");
   if (!isUInt<32>(UniqueID) || UniqueID == ~0U)
     return TokError("unique id is too large");
   return false;

llvm/lib/MC/WasmObjectWriter.cpp

if (Section.isWasmData()) {
       }
       if (Name == "target_features") {
         TargetFeaturesSection =
             std::make_unique<WasmCustomSection>(Name, &Section);
         continue;
       }
 
       // Custom sections can also belong to COMDAT groups. In this case the
-      // decriptor's "index" field is the section index (in the final object
+      // descriptor's "index" field is the section index (in the final object
       // file), but that is not known until after layout, so it must be fixed up
       // later
       if (const MCSymbolWasm *C = Section.getGroup()) {
         Comdats[C->getName()].emplace_back(
             WasmComdatEntry{wasm::WASM_COMDAT_SECTION,
                             static_cast<uint32_t>(CustomSections.size())});
       }
 

llvm/lib/Option/OptTable.cpp

InputArgList OptTable::ParseArgs(ArrayRef<const char *> ArgArr,
   return Args;
 }
 
 InputArgList OptTable::parseArgs(int Argc, char *const *Argv,
                                  OptSpecifier Unknown, StringSaver &Saver,
                                  function_ref<void(StringRef)> ErrorFn) const {
   SmallVector<const char *, 0> NewArgv;
   // The environment variable specifies initial options which can be overridden
-  // by commnad line options.
+  // by command line options.
   cl::expandResponseFiles(Argc, Argv, EnvVar, Saver, NewArgv);
 
   unsigned MAI, MAC;
   opt::InputArgList Args = ParseArgs(makeArrayRef(NewArgv), MAI, MAC);
   if (MAC)
     ErrorFn((Twine(Args.getArgString(MAI)) + ": missing argument").str());
 
   // For each unknwon option, call ErrorFn with a formatted error message. The

llvm/lib/ProfileData/MemProf.cpp

Expected<MemProfSchema> readMemProfSchema(const unsigned char *&Buffer) {
   for (size_t I = 0; I < NumSchemaIds; I++) {
     const uint64_t Tag = endian::readNext<uint64_t, little, unaligned>(Ptr);
     if (Tag >= static_cast<uint64_t>(Meta::Size)) {
       return make_error<InstrProfError>(instrprof_error::malformed,
                                         "memprof schema invalid");
     }
     Result.push_back(static_cast<Meta>(Tag));
   }
-  // Advace the buffer to one past the schema if we succeeded.
+  // Advance the buffer to one past the schema if we succeeded.
   Buffer = Ptr;
   return Result;
 }
 
 } // namespace memprof
 } // namespace llvm

llvm/lib/Support/FileUtilities.cpp

static bool CompareNumbers(const char *&F1P, const char *&F2P,
 
   // Otherwise, advance our read pointers to the end of the numbers.
   F1P = F1NumEnd;  F2P = F2NumEnd;
   return false;
 }
 
 /// DiffFilesWithTolerance - Compare the two files specified, returning 0 if the
 /// files match, 1 if they are different, and 2 if there is a file error.  This
-/// function differs from DiffFiles in that you can specify an absolete and
+/// function differs from DiffFiles in that you can specify an absolute and
 /// relative FP error that is allowed to exist.  If you specify a string to fill
 /// in for the error option, it will set the string to an error message if an
 /// error occurs, allowing the caller to distinguish between a failed diff and a
 /// file system error.
 ///
 int llvm::DiffFilesWithTolerance(StringRef NameA,
                                  StringRef NameB,
                                  double AbsTol, double RelTol,

llvm/lib/Support/Triple.cpp

return StringSwitch<Triple::EnvironmentType>(EnvironmentName)
       .StartsWith("callable", Triple::Callable)
       .StartsWith("mesh", Triple::Mesh)
       .StartsWith("amplification", Triple::Amplification)
       .Default(Triple::UnknownEnvironment);
 }
 
 static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
   return StringSwitch<Triple::ObjectFormatType>(EnvironmentName)
-      // "xcoff" must come before "coff" because of the order-dependendent
+      // "xcoff" must come before "coff" because of the order-dependent
       // pattern matching.
       .EndsWith("xcoff", Triple::XCOFF)
       .EndsWith("coff", Triple::COFF)
       .EndsWith("elf", Triple::ELF)
       .EndsWith("goff", Triple::GOFF)
       .EndsWith("macho", Triple::MachO)
       .EndsWith("wasm", Triple::Wasm)
       .EndsWith("spirv", Triple::SPIRV)

llvm/lib/Support/Unix/Path.inc

std::error_code openFileForRead(const Twine &Name, int &ResultFD,
   if (EC)
     return EC;
 
   // Attempt to get the real name of the file, if the user asked
   if(!RealPath)
     return std::error_code();
   RealPath->clear();
 #if defined(F_GETPATH)
-  // When F_GETPATH is availble, it is the quickest way to get
+  // When F_GETPATH is available, it is the quickest way to get
   // the real path name.
   char Buffer[PATH_MAX];
   if (::fcntl(ResultFD, F_GETPATH, Buffer) != -1)
     RealPath->append(Buffer, Buffer + strlen(Buffer));
 #else
   char Buffer[PATH_MAX];
 #if defined(TRY_PROC_SELF_FD)
   if (hasProcSelfFD()) {

llvm/lib/TableGen/Record.cpp

if (StringInit *Name = dyn_cast<StringInit>(Expr)) {
     // the final resolve to ensure that we get the correct type for them.
     auto *Anonymous = dyn_cast<AnonymousNameInit>(CurRec->getNameInit());
     if (Name == CurRec->getNameInit() ||
         (Anonymous && Name == Anonymous->getNameInit())) {
       if (!IsFinal)
         return const_cast<ExistsOpInit *>(this);
 
       // No doubt that there exists a record, so we should check if types are
-      // compatiable.
+      // compatible.
       return IntInit::get(getRecordKeeper(),
                           CurRec->getType()->typeIsA(CheckType));
     }
 
     // Look up all defined records to see if we can find one.
     Record *D = CheckType->getRecordKeeper().getDef(Name->getValue());
     if (!D) {
       if (IsFinal)
         return IntInit::get(getRecordKeeper(), 0);
       return const_cast<ExistsOpInit *>(this);
     }
 
-    // Check if types are compatiable.
+    // Check if types are compatible.
     return IntInit::get(getRecordKeeper(),
                         DefInit::get(D)->getType()->typeIsA(CheckType));
   }
   return const_cast<ExistsOpInit *>(this);
 }
 
 Init *ExistsOpInit::resolveReferences(Resolver &R) const {
   Init *NewExpr = Expr->resolveReferences(R);

llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp

void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
   LLVM_DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into "
                     << printMBBReference(*Head) << ":\n"
                     << *CmpBB);
 
   // All CmpBB instructions are moved into Head, and CmpBB is deleted.
   // Update the CFG first.
   updateTailPHIs();
 
-  // Save successor probabilties before removing CmpBB and Tail from their
+  // Save successor probabilities before removing CmpBB and Tail from their
   // parents.
   BranchProbability Head2CmpBB = MBPI->getEdgeProbability(Head, CmpBB);
   BranchProbability CmpBB2Tail = MBPI->getEdgeProbability(CmpBB, Tail);
 
   Head->removeSuccessor(CmpBB);
   CmpBB->removeSuccessor(Tail);
 
-  // If Head and CmpBB had successor probabilties, udpate the probabilities to
+  // If Head and CmpBB had successor probabilities, udpate the probabilities to
   // reflect the ccmp-conversion.
   if (Head->hasSuccessorProbabilities() && CmpBB->hasSuccessorProbabilities()) {
 
     // Head is allowed two successors. We've removed CmpBB, so the remaining
     // successor is Tail. We need to increase the successor probability for
     // Tail to account for the CmpBB path we removed.
     //
     // Pr(Tail|Head) += Pr(CmpBB|Head) * Pr(Tail|CmpBB).

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerDUPQLane(SDValue Op,
   EVT VT = Op.getValueType();
   if (!isTypeLegal(VT) || !VT.isScalableVector())
     return SDValue();
 
   // Current lowering only supports the SVE-ACLE types.
   if (VT.getSizeInBits().getKnownMinSize() != AArch64::SVEBitsPerBlock)
     return SDValue();
 
-  // The DUPQ operation is indepedent of element type so normalise to i64s.
+  // The DUPQ operation is independent of element type so normalise to i64s.
   SDValue Idx128 = Op.getOperand(2);
 
   // DUPQ can be used when idx is in range.
   auto *CIdx = dyn_cast<ConstantSDNode>(Idx128);
   if (CIdx && (CIdx->getZExtValue() <= 3)) {
     SDValue CI = DAG.getTargetConstant(CIdx->getZExtValue(), DL, MVT::i64);
     return DAG.getNode(AArch64ISD::DUPLANE128, DL, VT, Op.getOperand(1), CI);
   }

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   /// condition codes as if it's results had been fed to a PTEST instruction
   /// along with the same general predicate.
   bool isPTestLikeOpcode(unsigned Opc) const;
   /// Returns true if the opcode is for an SVE WHILE## instruction.
   bool isWhileOpcode(unsigned Opc) const;
   /// Returns true if the instruction has a shift by immediate that can be
   /// executed in one cycle less.
   static bool isFalkorShiftExtFast(const MachineInstr &MI);
-  /// Return true if the instructions is a SEH instruciton used for unwinding
+  /// Return true if the instructions is a SEH instruction used for unwinding
   /// on Windows.
   static bool isSEHInstruction(const MachineInstr &MI);
 
   Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                       Register Reg) const override;
 
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
   }
   // So we increment a zero register and test for bits other
   // than bit 0? Conservatively bail out in case the verifier
   // missed this case.
   if (IsTestAndBranch && MI.getOperand(1).getImm())
     return false;
 
   // Find Definition.
-  assert(MI.getParent() && "Incomplete machine instruciton\n");
+  assert(MI.getParent() && "Incomplete machine instruction\n");
   MachineBasicBlock *MBB = MI.getParent();
   MachineFunction *MF = MBB->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   Register VReg = MI.getOperand(0).getReg();
   if (!Register::isVirtualRegister(VReg))
     return false;
 
   MachineInstr *DefMI = MRI->getVRegDef(VReg);

llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp

if (!llvm::is_contained(Regs, AArch64::LR))
     return false;
 
   switch (Type) {
   case FrameHelperType::Prolog:
     // Prolog helper cannot save FP/LR.
     InstCount--;
     break;
   case FrameHelperType::PrologFrame: {
-    // Effecitvely no change in InstCount since FpAdjusment is included.
+    // Effecitvely no change in InstCount since FpAdjustment is included.
     break;
   }
   case FrameHelperType::Epilog:
     // Bail-out if X16 is live across the epilog helper because it is used in
     // the helper to handle X30.
     for (auto NextMI = NextMBBI; NextMI != MBB.end(); NextMI++) {
       if (NextMI->readsRegister(AArch64::W16, TRI))
         return false;

llvm/lib/Target/AArch64/AArch64SLSHardening.cpp

-//===- AArch64SLSHardening.cpp - Harden Straight Line Missspeculation -----===//
+//===- AArch64SLSHardening.cpp - Harden Straight Line Misspeculation -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass to insert code to mitigate against side channel

llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp

-//===- AArch64SpeculationHardening.cpp - Harden Against Missspeculation  --===//
+//===- AArch64SpeculationHardening.cpp - Harden Against Misspeculation  --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass to insert code to mitigate against side channel

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

private:
   // Used to track instructions that are already to added to a different
   // SchedGroup with the same SyncID.
   DenseMap<int, DenseSet<SUnit *>> SyncedInstrsMap;
 
   // Add DAG edges that enforce SCHED_BARRIER ordering.
   void addSchedBarrierEdges(SUnit &SU);
 
   // Use a SCHED_BARRIER's mask to identify instruction SchedGroups that should
-  // not be reordered accross the SCHED_BARRIER. This is used for the base
+  // not be reordered across the SCHED_BARRIER. This is used for the base
   // SCHED_BARRIER, and not SCHED_GROUP_BARRIER. The difference is that
   // SCHED_BARRIER will always block all instructions that can be classified
   // into a particular SchedClass, whereas SCHED_GROUP_BARRIER has a fixed size
   // and may only synchronize with some SchedGroups. Returns the inverse of
   // Mask. SCHED_BARRIER's mask describes which instruction types should be
   // allowed to be scheduled across it. Invert the mask to get the
   // SchedGroupMask of instructions that should be barred.
   SchedGroupMask invertSchedBarrierMask(SchedGroupMask Mask) const;

llvm/lib/Target/ARM/ARMFrameLowering.cpp

bool ARMFrameLowering::assignCalleeSavedSpillSlots(
 
   // For functions, which sign their return address, upon function entry, the
   // return address PAC is computed in R12. Treat R12 as a callee-saved register
   // in this case.
   const auto &AFI = *MF.getInfo<ARMFunctionInfo>();
   if (AFI.shouldSignReturnAddress()) {
     // The order of register must match the order we push them, because the
     // PEI assigns frame indices in that order. When compiling for return
-    // address sign and authenication, we use split push, therefore the orders
+    // address sign and authentication, we use split push, therefore the orders
     // we want are:
     // LR, R7, R6, R5, R4, <R12>, R11, R10,  R9,  R8, D15-D8
     CSI.insert(find_if(CSI,
                        [=](const auto &CS) {
                          Register Reg = CS.getReg();
                          return Reg == ARM::R10 || Reg == ARM::R11 ||
                                 Reg == ARM::R8 || Reg == ARM::R9 ||
                                 ARM::DPRRegClass.contains(Reg);

llvm/lib/Target/ARM/ARMSLSHardening.cpp

-//===- ARMSLSHardening.cpp - Harden Straight Line Missspeculation ---------===//
+//===- ARMSLSHardening.cpp - Harden Straight Line Misspeculation ---------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass to insert code to mitigate against side channel

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

ARMTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   }
   case Intrinsic::fptosi_sat:
   case Intrinsic::fptoui_sat: {
     if (ICA.getArgTypes().empty())
       break;
     bool IsSigned = ICA.getID() == Intrinsic::fptosi_sat;
     auto LT = TLI->getTypeLegalizationCost(DL, ICA.getArgTypes()[0]);
     EVT MTy = TLI->getValueType(DL, ICA.getReturnType());
-    // Check for the legal types, with the corect subtarget features.
+    // Check for the legal types, with the correct subtarget features.
     if ((ST->hasVFP2Base() && LT.second == MVT::f32 && MTy == MVT::i32) ||
         (ST->hasFP64() && LT.second == MVT::f64 && MTy == MVT::i32) ||
         (ST->hasFullFP16() && LT.second == MVT::f16 && MTy == MVT::i32))
       return LT.first;
 
     // Equally for MVE vector types
     if (ST->hasMVEFloatOps() &&
         (LT.second == MVT::v4f32 || LT.second == MVT::v8f16) &&

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

case MCCFIInstruction::OpOffset: // DW_CFA_offset
       break;
     case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
       // Ignore
       break;
     default:
       // Directive not convertable to compact unwind, bail out.
       DEBUG_WITH_TYPE("compact-unwind",
                       llvm::dbgs()
-                          << "CFI directive not compatiable with comact "
-                             "unwind encoding, opcode=" << Inst.getOperation()
-                          << "\n");
+                          << "CFI directive not compatible with compact "
+                             "unwind encoding, opcode="
+                          << Inst.getOperation() << "\n");
       return CU::UNWIND_ARM_MODE_DWARF;
       break;
     }
   }
 
   // If no frame set up, return no unwind info.
   if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
     return 0;

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

 
 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
 /// instructions, and rewrite them to their Thumb2 form if we are currently in
 /// Thumb2 mode.
 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
                                                  unsigned EncodedValue,
                                                  const MCSubtargetInfo &STI) const {
   if (isThumb2(STI)) {
-    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
+    // NEON Thumb2 data-processing encodings are very simple: bit 24 is moved
     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
     // set to 1111.
     unsigned Bit24 = EncodedValue & 0x01000000;
     unsigned Bit28 = Bit24 << 4;
     EncodedValue &= 0xEFFFFFFF;
     EncodedValue |= Bit28;
     EncodedValue |= 0x0F000000;
   }

llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp

bool MVETPAndVPTOptimisations::ReplaceVCMPsByVPNOTs(MachineBasicBlock &MBB) {
   // operand here to remove the kill flag in case we need to use PrevVCMP's
   // result.
   MachineOperand *PrevVCMPResultKiller = nullptr;
 
   for (MachineInstr &Instr : MBB.instrs()) {
     if (PrevVCMP) {
       if (MachineOperand *MO = Instr.findRegisterUseOperand(
               PrevVCMP->getOperand(0).getReg(), /*isKill*/ true)) {
-        // If we come accross the instr that kills PrevVCMP's result, record it
+        // If we come across the instr that kills PrevVCMP's result, record it
         // so we can remove the kill flag later if we need to.
         PrevVCMPResultKiller = MO;
       }
     }
 
     // Ignore predicated instructions.
     if (getVPTInstrPredicate(Instr) != ARMVCC::None)
       continue;

llvm/lib/Target/AVR/AVRInstrInfo.cpp

if (I->getOpcode() == AVR::RJMPk) {
       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
         TBB = nullptr;
         I->eraseFromParent();
         I = MBB.end();
         UnCondBrIter = MBB.end();
         continue;
       }
 
-      // TBB is used to indicate the unconditinal destination.
+      // TBB is used to indicate the unconditional destination.
       TBB = I->getOperand(0).getMBB();
       continue;
     }
 
     // Handle conditional branches.
     AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
     if (BranchCode == AVRCC::COND_INVALID) {
       return true; // Can't handle indirect branch.

llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp

 // This feature relies on the following three intrinsic calls:
 //   addr = preserve_array_access_index(base, dimension, index)
 //   addr = preserve_union_access_index(base, di_index)
 //          !llvm.preserve.access.index <union_ditype>
 //   addr = preserve_struct_access_index(base, gep_index, di_index)
 //          !llvm.preserve.access.index <struct_ditype>
 //
 // Bitfield member access needs special attention. User cannot take the
-// address of a bitfield acceess. To facilitate kernel verifier
+// address of a bitfield access. To facilitate kernel verifier
 // for easy bitfield code optimization, a new clang intrinsic is introduced:
 //   uint32_t __builtin_preserve_field_info(member_access, info_kind)
 // In IR, a chain with two (or more) intrinsic calls will be generated:
 //   ...
 //   addr = preserve_struct_access_index(base, 1, 1) !struct s
 //   uint32_t result = bpf_preserve_field_info(addr, info_kind)
 //
 // Suppose the info_kind is FIELD_SIGNEDNESS,

llvm/lib/Target/BPF/BPFInstrInfo.cpp

if (I->getOpcode() == BPF::JMP) {
       // Delete the J if it's equivalent to a fall-through.
       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
         TBB = nullptr;
         I->eraseFromParent();
         I = MBB.end();
         continue;
       }
 
-      // TBB is used to indicate the unconditinal destination.
+      // TBB is used to indicate the unconditional destination.
       TBB = I->getOperand(0).getMBB();
       continue;
     }
     // Cannot handle conditional branches
     return true;
   }
 
   return false;

llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp

 //===----- BPFMISimplifyPatchable.cpp - MI Simplify Patchable Insts -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass targets a subset of instructions like below
 //    ld_imm64 r1, @global
 //    ldd r2, r1, 0
 //    add r3, struct_base_reg, r2
 //
-// Here @global should represent an AMA (abstruct member access).
+// Here @global should represent an AMA (abstract member access).
 // Such an access is subject to bpf load time patching. After this pass, the
 // code becomes
 //    ld_imm64 r1, @global
 //    add r3, struct_base_reg, r1
 //
 // Eventually, at BTF output stage, a relocation record will be generated
 // for ld_imm64 which should be replaced later by bpf loader:
 //    r1 = <calculated field_info>

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     break;
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
 
-  // Used with vargs to acumulate store chains.
+  // Used with vargs to accumulate store chains.
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
   CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
 

llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp

 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This implements NewValueJump pass in Hexagon.
 // Ideally, we should merge this as a Peephole pass prior to register
 // allocation, but because we have a spill in between the feeder and new value
 // jump instructions, we are forced to write after register allocation.
 // Having said that, we should re-attempt to pull this earlier at some point
 // in future.
 
-// The basic approach looks for sequence of predicated jump, compare instruciton
+// The basic approach looks for sequence of predicated jump, compare instruction
 // that genereates the predicate and, the feeder to the predicate. Once it finds
 // all, it collapses compare and jump instruction into a new value jump
 // intstructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/InitializePasses.h"
 #include "Hexagon.h"

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h

public:
   // isSoloInstruction - return true if instruction MI can not be packetized
   // with any other instruction, which means that MI itself is a packet.
   bool isSoloInstruction(const MachineInstr &MI) override;
 
   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
   // together.
   bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
 
-  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
+  // isLegalToPruneDependencies - Is it legal to prune dependence between SUI
   // and SUJ.
   bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
 
   bool foundLSInPacket();
   MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
   void endPacket(MachineBasicBlock *MBB,
                  MachineBasicBlock::iterator MI) override;
   bool shouldAddToPacket(const MachineInstr &MI) override;

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
   //   c) %p0 = C2_cmpeqi %r26, 1
   // }
   //
   // On general check a) and b) are complements, but presence of c) will
   // convert a) to .new form, and then it is not a complement.
   // We attempt to detect it by analyzing existing dependencies in the packet.
 
   // Analyze relationships between all existing members of the packet.
-  // Look for Anti dependecy on the same predicate reg as used in the
+  // Look for Anti dependency on the same predicate reg as used in the
   // candidate.
   for (auto I : CurrentPacketMIs) {
     // Scheduling Unit for current insn in the packet.
     SUnit *PacketSU = MIToSUnit.find(I)->second;
 
     // If this instruction in the packet is succeeded by the candidate...
     if (PacketSU->isSucc(SU)) {
       for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {

llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp

 }
 
 bool HexagonVectorLoopCarriedReuse::isEquivalentOperation(Instruction *I1,
                                                           Instruction *I2) {
   if (!I1->isSameOperationAs(I2))
     return false;
   // This check is in place specifically for intrinsics. isSameOperationAs will
   // return two for any two hexagon intrinsics because they are essentially the
-  // same instruciton (CallInst). We need to scratch the surface to see if they
+  // same instruction (CallInst). We need to scratch the surface to see if they
   // are calls to the same function.
   if (CallInst *C1 = dyn_cast<CallInst>(I1)) {
     if (CallInst *C2 = dyn_cast<CallInst>(I2)) {
       if (C1->getCalledFunction() != C2->getCalledFunction())
         return false;
     }
   }
 

llvm/lib/Target/M68k/M68kInstrInfo.td

 def MxCONDgt  : PatLeaf<(i8 14)>; // Greater Than
 def MxCONDle  : PatLeaf<(i8 15)>; // Less or Equal
 
 
 //===----------------------------------------------------------------------===//
 // Complex Patterns
 //===----------------------------------------------------------------------===//
 
-// NOTE Though this CP is not strictly necessarily it will simplify instruciton
+// NOTE Though this CP is not strictly necessarily it will simplify instruction
 // definitions
 def MxCP_ARI   : ComplexPattern<iPTR, 1, "SelectARI",
                                 [], [SDNPWantParent]>;
 
 def MxCP_ARIPI : ComplexPattern<iPTR, 1, "SelectARIPI",
                                 [], [SDNPWantParent]>;
 
 def MxCP_ARIPD : ComplexPattern<iPTR, 1, "SelectARIPD",

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

 //===-- M68kMCCodeEmitter.cpp - Convert M68k code emitter -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// This file contains defintions for M68k code emitter.
+/// This file contains definitions for M68k code emitter.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/M68kMCCodeEmitter.h"
 #include "MCTargetDesc/M68kBaseInfo.h"
 #include "MCTargetDesc/M68kFixupKinds.h"
 #include "MCTargetDesc/M68kMCTargetDesc.h"
 

llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {
       // Delete the JMP if it's equivalent to a fall-through.
       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
         TBB = nullptr;
         I->eraseFromParent();
         I = MBB.end();
         continue;
       }
 
-      // TBB is used to indicate the unconditinal destination.
+      // TBB is used to indicate the unconditional destination.
       TBB = I->getOperand(0).getMBB();
       continue;
     }
 
     // Handle conditional branches.
     assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
     MSP430CC::CondCodes BranchCode =
       static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (Tok.isNot(AsmToken::LParen)) {
         auto Base = MipsOperand::createGPRReg(
             0, "0", getContext().getRegisterInfo(), S, E, *this);
         Operands.push_back(
             MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
         return MatchOperand_Success;
       }
       MCBinaryExpr::Opcode Opcode;
       // GAS and LLVM treat comparison operators different. GAS will generate -1
-      // or 0, while LLVM will generate 0 or 1. Since a comparsion operator is
+      // or 0, while LLVM will generate 0 or 1. Since a comparison operator is
       // highly unlikely to be found in a memory offset expression, we don't
       // handle them.
       switch (Tok.getKind()) {
       case AsmToken::Plus:
         Opcode = MCBinaryExpr::Add;
         Parser.Lex();
         break;
       case AsmToken::Minus:

llvm/lib/Target/Mips/MipsISelLowering.cpp

SDValue MipsTargetLowering::LowerFormalArguments(
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   MipsFI->setVarArgsFrameIndex(0);
 
-  // Used with vargs to acumulate store chains.
+  // Used with vargs to accumulate store chains.
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
                      *DAG.getContext());
   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1));
   const Function &Func = DAG.getMachineFunction().getFunction();

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
   if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
     return tryLDGLDU(N);
   }
 
   unsigned int PointerSize =
       CurDAG->getDataLayout().getPointerSizeInBits(MemSD->getAddressSpace());
 
   // Volatile Setting
-  // - .volatile is only availalble for .global and .shared
+  // - .volatile is only available for .global and .shared
   bool IsVolatile = MemSD->isVolatile();
   if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
       CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
       CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
     IsVolatile = false;
 
   // Vector Setting
   MVT SimpleVT = LoadedVT.getSimpleVT();

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp

void PPCELFStreamer::emitGOTToPCRelLabel(const MCInst &Inst) {
   const MCSymbolRefExpr *SymExpr = static_cast<const MCSymbolRefExpr *>(Expr);
   assert(SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT &&
          "Expecting a symbol of type VK_PPC_PCREL_OPT");
   MCSymbol *LabelSym =
       getContext().getOrCreateSymbol(SymExpr->getSymbol().getName());
   emitLabel(LabelSym, Inst.getLoc());
 }
 
-// This funciton checks if the parameter Inst is part of the setup for a link
+// This function checks if the parameter Inst is part of the setup for a link
 // time GOT PC Relative optimization. For example in this situation:
 // <MCInst PLDpc <MCOperand Reg:282> <MCOperand Expr:(glob_double@got@pcrel)>
 //   <MCOperand Imm:0> <MCOperand Expr:(.Lpcrel@<<invalid>>)>>
 // <MCInst SOME_LOAD <MCOperand Reg:22> <MCOperand Imm:0> <MCOperand Reg:282>
 //   <MCOperand Expr:(.Lpcrel@<<invalid>>)>>
 // The above is a pair of such instructions and this function will not return
 // None for either one of them. In both cases we are looking for the last
 // operand <MCOperand Expr:(.Lpcrel@<<invalid>>)> which needs to be an MCExpr
 // and has the flag MCSymbolRefExpr::VK_PPC_PCREL_OPT. After that we just look
 // at the opcode and in the case of PLDpc we will return true. For the load
 // (or store) this function will return false indicating it has found the second
-// instruciton in the pair.
+// instruction in the pair.
 Optional<bool> llvm::isPartOfGOTToPCRelPair(const MCInst &Inst,
                                             const MCSubtargetInfo &STI) {
   // Need at least two operands.
   if (Inst.getNumOperands() < 2)
     return None;
 
   unsigned LastOp = Inst.getNumOperands() - 1;
   // The last operand needs to be an MCExpr and it needs to have a variant kind

llvm/lib/Target/PowerPC/PPCGenScalarMASSEntries.cpp

 
 // Returns true if 'nnan', 'ninf' and 'nsz' flags exist on the call instruction
 // with the math function
 bool PPCGenScalarMASSEntries::isFiniteCallSafe(const CallInst &CI) const {
   // skip functions with no scalar or vector FP type (like cosisin)
   if (!isa<FPMathOperator>(CI))
     return false;
 
-  // FIXME: no-errno and trapping-math need to be set for MASS converstion
+  // FIXME: no-errno and trapping-math need to be set for MASS conversion
   // but they don't have IR representation.
   return CI.hasNoNaNs() && CI.hasNoInfs() && CI.hasNoSignedZeros();
 }
 
 /// Lowers scalar math functions to scalar MASS functions.
 ///     e.g.: tanh         --> __xl_tanh_finite or __xl_tanh
 /// Both function prototype and its callsite is updated during lowering.
 bool PPCGenScalarMASSEntries::createScalarMASSCall(StringRef MASSEntry,

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

bool SelectForceXForm(SDNode *Parent, SDValue N, SDValue &Disp,
                           SDValue &Base) {
       return PPCLowering->SelectForceXFormMode(N, Disp, Base, *CurDAG) ==
              PPC::AM_XForm;
     }
 
     /// SelectAddrIdx - Given the specified address, check to see if it can be
     /// represented as an indexed [r+r] operation.
     /// This is for xform instructions whose associated displacement form is D.
-    /// The last parameter \p 0 means associated D form has no requirment for 16
-    /// bit signed displacement.
+    /// The last parameter \p 0 means associated D form has no requirement for
+    /// 16 bit signed displacement.
     /// Returns false if it can be represented by [r+imm], which are preferred.
     bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
       return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG, None);
     }
 
     /// SelectAddrIdx4 - Given the specified address, check to see if it can be
     /// represented as an indexed [r+r] operation.
     /// This is for xform instructions whose associated displacement form is DS.
public:
     /// SelectAddrIdxOnly - Given the specified address, force it to be
     /// represented as an indexed [r+r] operation.
     bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
       return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
     }
 
     /// SelectAddrImm - Returns true if the address N can be represented by
     /// a base register plus a signed 16-bit displacement [r+imm].
-    /// The last parameter \p 0 means D form has no requirment for 16 bit signed
-    /// displacement.
+    /// The last parameter \p 0 means D form has no requirement for 16 bit
+    /// signed displacement.
     bool SelectAddrImm(SDValue N, SDValue &Disp,
                        SDValue &Base) {
       return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, None);
     }
 
     /// SelectAddrImmX4 - Returns true if the address N can be represented by
     /// a base register plus a signed 16-bit displacement that is a multiple of
     /// 4 (last parameter). Suitable for use by STD and friends.

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     CR6SET,
     CR6UNSET,
 
     /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
     /// for non-position independent code on PPC32.
     PPC32_GOT,
 
     /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
-    /// local dynamic TLS and position indendepent code on PPC32.
+    /// local dynamic TLS and position independent code on PPC32.
     PPC32_PICGOT,
 
     /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
     /// TLS model, produces an ADDIS8 instruction that adds the GOT
     /// base to sym\@got\@tprel\@ha.
     ADDIS_GOT_TPREL_HA,
 
     /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
                               const TargetMachine &TM,
                               bool IsStrictFPCall = false) {
   if (CFlags.IsTailCall)
     return PPCISD::TC_RETURN;
 
   unsigned RetOpc = 0;
   // This is a call through a function pointer.
   if (CFlags.IsIndirect) {
-    // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
+    // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer across
     // indirect calls. The save of the caller's TOC pointer to the stack will be
     // inserted into the DAG as part of call lowering. The restore of the TOC
     // pointer is modeled by using a pseudo instruction for the call opcode that
     // represents the 2 instruction sequence of an indirect branch and link,
     // immediately followed by a load of the TOC pointer from the the stack save
     // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
     // as it is not saved or used.
     RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
                                                  : PPCISD::BCTRL;
   } else if (Subtarget.isUsingPCRelativeCalls()) {
     assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.");
     RetOpc = PPCISD::CALL_NOTOC;
   } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
-    // The ABIs that maintain a TOC pointer accross calls need to have a nop
+    // The ABIs that maintain a TOC pointer across calls need to have a nop
     // immediately following the call instruction if the caller and callee may
     // have different TOC bases. At link time if the linker determines the calls
     // may not share a TOC base, the call is redirected to a trampoline inserted
     // by the linker. The trampoline will (among other things) save the callers
     // TOC pointer at an ABI designated offset in the linkage area and the
     // linker will rewrite the nop to be a load of the TOC pointer from the
     // linkage area into gpr2.
     RetOpc = callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
if (DAG.isSplatValue(Op, true) &&
       unsigned NumUsesOfInputLD = 128 / ElementSize;
       for (SDValue BVInOp : Op->ops())
         if (BVInOp.isUndef())
           NumUsesOfInputLD--;
 
       // Exclude somes case where LD_SPLAT is worse than scalar_to_vector:
       // Below cases should also happen for "lfiwzx/lfiwax + LE target + index
       // 1" and "lxvrhx + BE target + index 7" and "lxvrbx + BE target + index
-      // 15", but funciton IsValidSplatLoad() now will only return true when
+      // 15", but function IsValidSplatLoad() now will only return true when
       // the data at index 0 is not nullptr. So we will not get into trouble for
       // these cases.
       //
       // case 1 - lfiwzx/lfiwax
       // 1.1: load result is i32 and is sign/zero extend to i64;
       // 1.2: build a v2i64 vector type with above loaded value;
       // 1.3: the vector has only one value at index 0, others are all undef;
       // 1.4: on BE target, so that lfiwzx/lfiwax does not need any permute.

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

 // Rewrite the new base according to BasePtrSCEV.
 // bb.loop.preheader:
 //   %newstart = ...
 // bb.loop.body:
 //   %phinode = phi [ %newstart, %bb.loop.preheader ], [ %add, %bb.loop.body ]
 //   ...
 //   %add = getelementptr %phinode, %inc
 //
-// First returned instruciton is %phinode (or a type cast to %phinode), caller
+// First returned instruction is %phinode (or a type cast to %phinode), caller
 // needs this value to rewrite other load/stores in the same chain.
 // Second returned instruction is %add, caller needs this value to rewrite other
 // load/stores in the same chain.
 std::pair<Instruction *, Instruction *>
 PPCLoopInstrFormPrep::rewriteForBase(Loop *L, const SCEVAddRecExpr *BasePtrSCEV,
                                      Instruction *BaseMemI, bool CanPreInc,
                                      PrepForm Form, SCEVExpander &SCEVE,
                                      SmallPtrSet<Value *, 16> &DeletedPtrs) {

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineBasicBlock &MBB2 : *MF) {
     MachineInstr *BI1   = &*MBB1->getFirstInstrTerminator();
     MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
 
     MachineInstr *BI2   = &*MBB2.getFirstInstrTerminator();
     MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
     bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr);
 
     // We cannot optimize an unsupported compare opcode or
-    // a mix of 32-bit and 64-bit comaprisons
+    // a mix of 32-bit and 64-bit comparisons
     if (!isSupportedCmpOp(CMPI1->getOpcode()) ||
         !isSupportedCmpOp(CMPI2->getOpcode()) ||
         is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode()))
       continue;
 
     unsigned NewOpCode = 0;
     unsigned NewPredicate1 = 0, NewPredicate2 = 0;
     int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;

llvm/lib/Target/PowerPC/PPCRegisterInfoMMA.td

let SubRegIndices = [sub_pair0, sub_pair1] in {
   def ACC6 : ACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>;
   def ACC7 : ACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>;
 }
 def ACCRC : RegisterClass<"PPC", [v512i1], 128, (add ACC0, ACC1, ACC2, ACC3,
                                                       ACC4, ACC5, ACC6, ACC7)> {
   // The AllocationPriority is in the range [0, 63]. Assigned the ACC registers
   // the highest possible priority in this range to force the register allocator
   // to assign these registers first. This is done because the ACC registers
-  // must represent 4 advacent vector registers. For example ACC1 must be
+  // must represent 4 adjacent vector registers. For example ACC1 must be
   // VS4 - VS7. The value here must be at least 32 as we want to allocate
   // these registers even before we allocate global ranges.
   let AllocationPriority = 63;
   let Size = 512;
 }
 
 let SubRegIndices = [sub_pair0, sub_pair1] in {
   def UACC0 : UACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;

llvm/lib/Target/PowerPC/README_ALTIVEC.txt

...
         vcmpeqfp. v2, v3, v2
         bne cr6, LBB1_2 ; cond_next
 
 The vcmpeqfp/vcmpeqfp. instructions currently cannot be merged when the
 vcmpeqfp. result is used by a branch.  This can be improved.
 
 //===----------------------------------------------------------------------===//
 
-The code generated for this is truly aweful:
+The code generated for this is truly awful:
 
 vector float test(float a, float b) {
  return (vector float){ 0.0, a, 0.0, 0.0}; 
 }
 
 LCPI1_0:                                        ;  float
         .space  4
         .text

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Func.hasFnAttribute("interrupt")) {
     if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
       report_fatal_error(
         "Function interrupt attribute argument not supported!");
   }
 
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
-  // Used with vargs to acumulate store chains.
+  // Used with vargs to accumulate store chains.
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
   if (CallConv == CallingConv::GHC)
     CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC);

llvm/lib/Target/Sparc/SparcInstrInfo.td

def V9FCMPED  : F3_3c<2, 0b110101, 0b001010110,
                    (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
                    "fcmped $rd, $rs1, $rs2", []>;
   def V9FCMPEQ  : F3_3c<2, 0b110101, 0b001010111,
                    (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                    "fcmpeq $rd, $rs1, $rs2", []>,
                    Requires<[HasHardQuad]>;
 }
 
-// Floating point conditional move instrucitons with %fcc0-%fcc3.
+// Floating point conditional move instructions with %fcc0-%fcc3.
 let Predicates = [HasV9] in {
   let Constraints = "$f = $rd", intcc = 0 in {
     def V9MOVFCCrr
       : F4_1<0b101100, (outs IntRegs:$rd),
              (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
              "mov$cond $cc, $rs2, $rd", []>;
     def V9MOVFCCri
       : F4_2<0b101100, (outs IntRegs:$rd),

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

if (Branch.CCMask == SystemZ::CCMASK_ANY) {
       // Delete the JMP if it's equivalent to a fall-through.
       if (MBB.isLayoutSuccessor(Branch.getMBBTarget())) {
         TBB = nullptr;
         I->eraseFromParent();
         I = MBB.end();
         continue;
       }
 
-      // TBB is used to indicate the unconditinal destination.
+      // TBB is used to indicate the unconditional destination.
       TBB = Branch.getMBBTarget();
       continue;
     }
 
     // Working from the bottom, handle the first conditional branch.
     if (Cond.empty()) {
       // FIXME: add X86-style branch swap
       FBB = TBB;

llvm/lib/Target/WebAssembly/README.txt

For more information on WebAssembly itself, see the home page:
 
   * https://webassembly.github.io/
 
 Emscripten provides a C/C++ compilation environment based on clang which
 includes standard libraries, tools, and packaging for producing WebAssembly
 applications that can run in browsers and other environments.
 
 wasi-sdk provides a more minimal C/C++ SDK based on clang, llvm and a libc based
-on musl, for producing WebAssemmbly applictions that use the WASI ABI.
+on musl, for producing WebAssemmbly applications that use the WASI ABI.
 
 Rust provides WebAssembly support integrated into Cargo. There are two
 main options:
  - wasm32-unknown-unknown, which provides a relatively minimal environment
    that has an emphasis on being "native"
  - wasm32-unknown-emscripten, which uses Emscripten internally and
    provides standard C/C++ libraries, filesystem emulation, GL and SDL
    bindings

llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp

for (auto &P : UnwindWEVec) {
                           << SrcWE->getEHPad()->getNumber() << "."
                           << SrcWE->getEHPad()->getName() << "'s exception\n");
         WE->setParentException(SrcWE->getParentException());
       }
     }
   }
 
   // Add BBs to exceptions' block set. This is a preparation to take out
-  // remaining incorect BBs from exceptions, because we need to iterate over BBs
-  // for each exception.
+  // remaining incorrect BBs from exceptions, because we need to iterate over
+  // BBs for each exception.
   for (auto *DomNode : post_order(&MDT)) {
     MachineBasicBlock *MBB = DomNode->getBlock();
     WebAssemblyException *WE = getExceptionFor(MBB);
     for (; WE; WE = WE->getParentException())
       WE->addToBlocksSet(MBB);
   }
 
   // 2. We take out remaining individual BBs out. Now we have added BBs to each

llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp

 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyFixBrTableDefaults() : MachineFunctionPass(ID) {}
 };
 
 char WebAssemblyFixBrTableDefaults::ID = 0;
 
-// Target indepedent selection dag assumes that it is ok to use PointerTy
+// Target independent selection dag assumes that it is ok to use PointerTy
 // as the index for a "switch", whereas Wasm so far only has a 32-bit br_table.
 // See e.g. SelectionDAGBuilder::visitJumpTableHeader
 // We have a 64-bit br_table in the tablegen defs as a result, which does get
 // selected, and thus we get incorrect truncates/extensions happening on
 // wasm64. Here we fix that.
 void fixBrTableIndex(MachineInstr &MI, MachineBasicBlock *MBB,
                      MachineFunction &MF) {
   // Only happens on wasm64.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
       setCondCodeAction(CC, MVT::v2i64, Custom);
 
     // 64x2 conversions are not in the spec
     for (auto Op :
          {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
       for (auto T : {MVT::v2i64, MVT::v2f64})
         setOperationAction(Op, T, Expand);
 
-    // But saturating fp_to_int converstions are
+    // But saturating fp_to_int conversions are
     for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT})
       setOperationAction(Op, MVT::v4i32, Custom);
   }
 
   // As a special case, these operators use the type to mean the type to
   // sign-extend from.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   if (!Subtarget->hasSignExt()) {

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

 bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
     const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case WebAssembly::CONST_I32:
   case WebAssembly::CONST_I64:
   case WebAssembly::CONST_F32:
   case WebAssembly::CONST_F64:
     // isReallyTriviallyReMaterializableGeneric misses these because of the
-    // ARGUMENTS implicit def, so we manualy override it here.
+    // ARGUMENTS implicit def, so we manually override it here.
     return true;
   default:
     return false;
   }
 }
 
 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
 
   if (!CanPadInst)
     return;
 
   if (PendingBA && OS.getCurrentFragment()->getPrevNode() == PendingBA) {
     // Macro fusion actually happens and there is no other fragment inserted
     // after the previous instruction.
     //
-    // Do nothing here since we already inserted a BoudaryAlign fragment when
+    // Do nothing here since we already inserted a BoundaryAlign fragment when
     // we met the first instruction in the fused pair and we'll tie them
     // together in emitInstructionEnd.
     //
     // Note: When there is at least one fragment, such as MCAlignFragment,
     // inserted after the previous instruction, e.g.
     //
     // \code
     //   cmp %rax %rcx

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

case MVT::i64:
              IsSigned ? X86::IMUL64m : X86::MUL64m;
       LoReg = UseMULX ? X86::RDX : X86::RAX;
       HiReg = X86::RDX;
       break;
     }
 
     SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
     bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
-    // Multiply is commmutative.
+    // Multiply is commutative.
     if (!foldedLoad) {
       foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
       if (foldedLoad)
         std::swap(N0, N1);
     }
 
     SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
                                           N0, SDValue()).getValue(1);

llvm/lib/Target/X86/X86InstrFMA3Info.h

struct X86InstrFMA3Group {
   enum : uint16_t {
     /// This bit must be set in the 'Attributes' field of FMA group if such
     /// group of FMA opcodes consists of FMA intrinsic opcodes.
     Intrinsic = 0x1,
 
     /// This bit must be set in the 'Attributes' field of FMA group if such
     /// group of FMA opcodes consists of AVX512 opcodes accepting a k-mask and
     /// passing the elements from the 1st operand to the result of the operation
-    /// when the correpondings bits in the k-mask are unset.
+    /// when the corresponding bits in the k-mask are unset.
     KMergeMasked = 0x2,
 
     /// This bit must be set in the 'Attributes' field of FMA group if such
     /// group of FMA opcodes consists of AVX512 opcodes accepting a k-zeromask.
     KZeroMasked = 0x4,
   };
 
   /// Returns the 132 form of FMA opcode.

llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

 def X86SubVBroadcastld256 : PatFrag<(ops node:$src),
                                     (X86SubVBroadcastld node:$src), [{
   return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 32;
 }]>;
 
 // Scalar SSE intrinsic fragments to match several different types of loads.
 // Used by scalar SSE intrinsic instructions which have 128 bit types, but
 // only load a single element.
-// FIXME: We should add more canolicalizing in DAGCombine. Particulary removing
+// FIXME: We should add more canonicalizing in DAGCombine. Particulary removing
 // the simple_load case.
 def sse_load_f16 : PatFrags<(ops node:$ptr),
                             [(v8f16 (simple_load node:$ptr)),
                              (v8f16 (X86vzload16 node:$ptr)),
                              (v8f16 (scalar_to_vector (loadf16 node:$ptr)))]>;
 def sse_load_f32 : PatFrags<(ops node:$ptr),
                             [(v4f32 (simple_load node:$ptr)),
                              (v4f32 (X86vzload32 node:$ptr)),

llvm/lib/Target/X86/X86MCInstLower.cpp

void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
   SmallVector<MCFixup, 4> Fixups;
   raw_svector_ostream VecOS(Code);
   CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
 
   if (Code.size() < MinSize) {
     if (MinSize == 2 && Subtarget->is32Bit() &&
         Subtarget->isTargetWindowsMSVC() &&
         (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) {
-      // For compatibilty reasons, when targetting MSVC, is is important to
+      // For compatibility reasons, when targetting MSVC, is is important to
       // generate a 'legacy' NOP in the form of a 8B FF MOV EDI, EDI. Some tools
       // rely specifically on this pattern to be able to patch a function.
       // This is only for 32-bit targets, when using /arch:IA32 or /arch:SSE.
       OutStreamer->emitInstruction(
           MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
           *Subtarget);
     } else if (MinSize == 2 && Opcode == X86::PUSH64r) {
       // This is an optimization that lets us get away without emitting a nop in

llvm/lib/Target/X86/X86PreAMXConfig.cpp

 bool X86PreAMXConfig::getKeyAMXShapes(IntrinsicInst *KeyAMX,
                                       SmallVector<Value *, 8> &Shapes) {
   for (unsigned I = 0; I < KeyAMX->getNumOperands(); I++) {
     Value *Op = KeyAMX->getOperand(I);
     if (!Op->getType()->isX86_AMXTy())
       continue;
     IntrinsicInst *TileDef = dyn_cast<IntrinsicInst>(Op);
     assert((TileDef && isTileLoad(TileDef)) &&
-           "All KeyAMX's tile definiation should comes from TileLoad!");
+           "All KeyAMX's tile definition should comes from TileLoad!");
     Shapes.push_back(TileDef->getOperand(0));
     Shapes.push_back(TileDef->getOperand(1));
   }
   if (!isTileStore(KeyAMX)) {
     Shapes.push_back(KeyAMX->getOperand(0));
     Shapes.push_back(KeyAMX->getOperand(1));
   }
   return Shapes.size() != 0;

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

if (MBB.succ_size() <= 1)
       continue;
 
     // Skip blocks unless their terminators start with a branch. Other
     // terminators don't seem interesting for guarding against misspeculation.
     auto TermIt = MBB.getFirstTerminator();
     if (TermIt == MBB.end() || !TermIt->isBranch())
       continue;
 
-    // Add all the non-EH-pad succossors to the blocks we want to harden. We
+    // Add all the non-EH-pad successors to the blocks we want to harden. We
     // skip EH pads because there isn't really a condition of interest on
     // entering.
     for (MachineBasicBlock *SuccMBB : MBB.successors())
       if (!SuccMBB->isEHPad())
         Blocks.insert(SuccMBB);
   }
 
   for (MachineBasicBlock *MBB : Blocks) {

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

auto *CoalescedVecTy =
         CurrNumEltPerOp == 1
             ? CurrVecTy
             : FixedVectorType::get(
                   IntegerType::get(Src->getContext(),
                                    EltTyBits * CurrNumEltPerOp),
                   CurrVecTy->getNumElements() / CurrNumEltPerOp);
     assert(DL.getTypeSizeInBits(CoalescedVecTy) ==
                DL.getTypeSizeInBits(CurrVecTy) &&
-           "coalesciing elements doesn't change vector width.");
+           "coalescing elements doesn't change vector width.");
 
     while (NumEltRemaining > 0) {
       assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?");
 
       // Can we use this vector size, as per the remaining element count?
       // Iff the vector is naturally aligned, we can do a wide load regardless.
       if (NumEltRemaining < CurrNumEltPerOp &&
           (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) &&

llvm/lib/Transforms/Coroutines/CoroFrame.cpp

Shape.AsyncLowering.FrameOffset =
         alignTo(Shape.AsyncLowering.ContextHeaderSize, Shape.FrameAlign);
     // Also make the final context size a multiple of the context alignment to
     // make allocation easier for allocators.
     Shape.AsyncLowering.ContextSize =
         alignTo(Shape.AsyncLowering.FrameOffset + Shape.FrameSize,
                 Shape.AsyncLowering.getContextAlignment());
     if (Shape.AsyncLowering.getContextAlignment() < Shape.FrameAlign) {
       report_fatal_error(
-          "The alignment requirment of frame variables cannot be higher than "
+          "The alignment requirement of frame variables cannot be higher than "
           "the alignment of the async function context");
     }
     break;
   }
   }
 
   return FrameTy;
 }
if (auto *AsyncEnd = dyn_cast<CoroAsyncEndInst>(CE)) {
       auto Arguments = ArrayRef<Value *>(Args).drop_front(3);
       auto *Call = createMustTailCall(AsyncEnd->getDebugLoc(), MustTailCallFn,
                                       Arguments, Builder);
       splitAround(Call, "MustTailCall.Before.CoroEnd");
     }
   }
 
   // Later code makes structural assumptions about single predecessors phis e.g
-  // that they are not live accross a suspend point.
+  // that they are not live across a suspend point.
   cleanupSinglePredPHIs(F);
 
   // Transforms multi-edge PHI Nodes, so that any value feeding into a PHI will
   // never has its definition separated from the PHI by the suspend point.
   rewritePHIs(F);
 
   // Build suspend crossing info.
   SuspendCrossingInfo Checker(F, Shape);

llvm/lib/Transforms/Coroutines/CoroSplit.cpp

while (I->isTerminator() || isa<CmpInst>(I)) {
     } else if (auto *CondCmp = dyn_cast<CmpInst>(I)) {
       // If the case number of suspended switch instruction is reduced to
       // 1, then it is simplified to CmpInst in llvm::ConstantFoldTerminator.
       auto *BR = dyn_cast<BranchInst>(
           GetFirstValidInstruction(CondCmp->getNextNode()));
       if (!BR || !BR->isConditional() || CondCmp != BR->getCondition())
         return false;
 
-      // And the comparsion looks like : %cond = icmp eq i8 %V, constant.
+      // And the comparison looks like : %cond = icmp eq i8 %V, constant.
       // So we try to resolve constant for the first operand only since the
       // second operand should be literal constant by design.
       ConstantInt *Cond0 = TryResolveConstant(CondCmp->getOperand(0));
       auto *Cond1 = dyn_cast<ConstantInt>(CondCmp->getOperand(1));
       if (!Cond0 || !Cond1)
         return false;
 
       // Both operands of the CmpInst are Constant. So that we could evaluate

llvm/lib/Transforms/IPO/AttributorAttributes.cpp

 namespace AA {
 namespace PointerInfo {
 
 struct State;
 
 } // namespace PointerInfo
 } // namespace AA
 
-/// Helper for AA::PointerInfo::Acccess DenseMap/Set usage.
+/// Helper for AA::PointerInfo::Access DenseMap/Set usage.
 template <>
 struct DenseMapInfo<AAPointerInfo::Access> : DenseMapInfo<Instruction *> {
   using Access = AAPointerInfo::Access;
   static inline Access getEmptyKey();
   static inline Access getTombstoneKey();
   static unsigned getHashValue(const Access &A);
   static bool isEqual(const Access &LHS, const Access &RHS);
 };
 
 /// Helper that allows OffsetAndSize as a key in a DenseMap.
 template <>
 struct DenseMapInfo<AAPointerInfo ::OffsetAndSize>
     : DenseMapInfo<std::pair<int64_t, int64_t>> {};
 
-/// Helper for AA::PointerInfo::Acccess DenseMap/Set usage ignoring everythign
+/// Helper for AA::PointerInfo::Access DenseMap/Set usage ignoring everythign
 /// but the instruction
 struct AccessAsInstructionInfo : DenseMapInfo<Instruction *> {
   using Base = DenseMapInfo<Instruction *>;
   using Access = AAPointerInfo::Access;
   static inline Access getEmptyKey();
   static inline Access getTombstoneKey();
   static unsigned getHashValue(const Access &A);
   static bool isEqual(const Access &LHS, const Access &RHS);

llvm/lib/Transforms/IPO/OpenMPOpt.cpp

 
 static cl::opt<bool> PrintModuleBeforeOptimizations(
     "openmp-opt-print-module-before",
     cl::desc("Print the current module before OpenMP optimizations."),
     cl::Hidden, cl::init(false));
 
 static cl::opt<bool> AlwaysInlineDeviceFunctions(
     "openmp-opt-inline-device",
-    cl::desc("Inline all applicible functions on the device."), cl::Hidden,
+    cl::desc("Inline all applicable functions on the device."), cl::Hidden,
     cl::init(false));
 
 static cl::opt<bool>
     EnableVerboseRemarks("openmp-opt-verbose-remarks",
                          cl::desc("Enables more verbose remarks."), cl::Hidden,
                          cl::init(false));
 
 static cl::opt<unsigned>

llvm/lib/Transforms/IPO/PartialInlining.cpp

BranchProbability PartialInlinerImpl::getOutliningCallBBRelativeFreq(
 
   // When profile data is not available, we need to be conservative in
   // estimating the overall savings. Static branch prediction can usually
   // guess the branch direction right (taken/non-taken), but the guessed
   // branch probability is usually not biased enough. In case when the
   // outlined region is predicted to be likely, its probability needs
   // to be made higher (more biased) to not under-estimate the cost of
   // function outlining. On the other hand, if the outlined region
-  // is predicted to be less likely, the predicted probablity is usually
+  // is predicted to be less likely, the predicted probability is usually
   // higher than the actual. For instance, the actual probability of the
-  // less likely target is only 5%, but the guessed probablity can be
+  // less likely target is only 5%, but the guessed probability can be
   // 40%. In the latter case, there is no need for further adjustement.
   // FIXME: add an option for this.
   if (OutlineRegionRelFreq < BranchProbability(45, 100))
     return OutlineRegionRelFreq;
 
   OutlineRegionRelFreq = std::max(
       OutlineRegionRelFreq, BranchProbability(OutlineRegionFreqPercent, 100));
 

llvm/lib/Transforms/IPO/SampleProfile.cpp

SampleProfileLoader::shouldInlineCandidate(InlineCandidate &Candidate) {
   InlineParams Params = getInlineParams();
   // We will ignore the threshold from inline cost, so always get full cost.
   Params.ComputeFullInlineCost = true;
   Params.AllowRecursiveCall = AllowRecursiveInline;
   // Checks if there is anything in the reachable portion of the callee at
   // this callsite that makes this inlining potentially illegal. Need to
   // set ComputeFullInlineCost, otherwise getInlineCost may return early
   // when cost exceeds threshold without checking all IRs in the callee.
-  // The acutal cost does not matter because we only checks isNever() to
+  // The actual cost does not matter because we only checks isNever() to
   // see if it is legal to inline the callsite.
   InlineCost Cost = getInlineCost(*Candidate.CallInstr, Callee, Params,
                                   GetTTI(*Callee), GetAC, GetTLI);
 
   // Honor always inline and never inline from call analyzer
   if (Cost.isNever() || Cost.isAlways())
     return Cost;
 

llvm/lib/Transforms/IPO/SampleProfileProbe.cpp

static uint64_t computeCallStackHash(const Instruction &Inst) {
   return getCallStackHash(Inst.getDebugLoc());
 }
 
 bool PseudoProbeVerifier::shouldVerifyFunction(const Function *F) {
   // Skip function declaration.
   if (F->isDeclaration())
     return false;
   // Skip function that will not be emitted into object file. The prevailing
-  // defintion will be verified instead.
+  // definition will be verified instead.
   if (F->hasAvailableExternallyLinkage())
     return false;
   // Do a name matching.
   static std::unordered_set<std::string> VerifyFuncNames(
       VerifyPseudoProbeFuncList.begin(), VerifyPseudoProbeFuncList.end());
   return VerifyFuncNames.empty() || VerifyFuncNames.count(F->getName().str());
 }
 

llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp

if (!F.isDeclaration() || F.getFunctionType() == EmptyFT ||
         // Changing the type of an intrinsic may invalidate the IR.
         F.getName().startswith("llvm."))
       continue;
 
     Function *NewF =
         Function::Create(EmptyFT, GlobalValue::ExternalLinkage,
                          F.getAddressSpace(), "", &M);
     NewF->copyAttributesFrom(&F);
-    // Only copy function attribtues.
+    // Only copy function attributes.
     NewF->setAttributes(AttributeList::get(M.getContext(),
                                            AttributeList::FunctionIndex,
                                            F.getAttributes().getFnAttrs()));
     NewF->takeName(&F);
     F.replaceAllUsesWith(ConstantExpr::getBitCast(NewF, F.getType()));
     F.eraseFromParent();
   }
 

llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

private:
 
     APFloat *getFpValPtr() { return reinterpret_cast<APFloat *>(&FpValBuf); }
 
     const APFloat *getFpValPtr() const {
       return reinterpret_cast<const APFloat *>(&FpValBuf);
     }
 
     const APFloat &getFpVal() const {
-      assert(IsFp && BufHasFpVal && "Incorret state");
+      assert(IsFp && BufHasFpVal && "Incorrect state");
       return *getFpValPtr();
     }
 
     APFloat &getFpVal() {
-      assert(IsFp && BufHasFpVal && "Incorret state");
+      assert(IsFp && BufHasFpVal && "Incorrect state");
       return *getFpValPtr();
     }
 
     bool isInt() const { return !IsFp; }
 
     // If the coefficient is represented by an integer, promote it to a
     // floating point.
     void convertToFpType(const fltSemantics &Sem);

llvm/lib/Transforms/Scalar/IndVarSimplify.cpp

bool IndVarSimplify::predicateLoopExits(Loop *L, SCEVExpander &Rewriter) {
 
   // Finally, see if we can rewrite our exit conditions into a loop invariant
   // form. If we have a read-only loop, and we can tell that we must exit down
   // a path which does not need any of the values computed within the loop, we
   // can rewrite the loop to exit on the first iteration.  Note that this
   // doesn't either a) tell us the loop exits on the first iteration (unless
   // *all* exits are predicateable) or b) tell us *which* exit might be taken.
   // This transformation looks a lot like a restricted form of dead loop
-  // elimination, but restricted to read-only loops and without neccesssarily
+  // elimination, but restricted to read-only loops and without neccessarily
   // needing to kill the loop entirely.
   if (!LoopPredication)
     return false;
 
   // Note: ExactBTC is the exact backedge taken count *iff* the loop exits
   // through *explicit* control flow.  We have to eliminate the possibility of
   // implicit exits (see below) before we know it's truly exact.
   const SCEV *ExactBTC = SE->getBackedgeTakenCount(L);

llvm/lib/Transforms/Scalar/LoopFuse.cpp

 };
 
 using LoopVector = SmallVector<Loop *, 4>;
 
 // Set of Control Flow Equivalent (CFE) Fusion Candidates, sorted in dominance
 // order. Thus, if FC0 comes *before* FC1 in a FusionCandidateSet, then FC0
 // dominates FC1 and FC1 post-dominates FC0.
 // std::set was chosen because we want a sorted data structure with stable
-// iterators. A subsequent patch to loop fusion will enable fusing non-ajdacent
+// iterators. A subsequent patch to loop fusion will enable fusing non-adjacent
 // loops by moving intervening code around. When this intervening code contains
 // loops, those loops will be moved also. The corresponding FusionCandidates
 // will also need to be moved accordingly. As this is done, having stable
 // iterators will simplify the logic. Similarly, having an efficient insert that
 // keeps the FusionCandidateSet sorted will also simplify the implementation.
 using FusionCandidateSet = std::set<FusionCandidate, FusionCandidateCompare>;
 using FusionCandidateCollection = SmallVector<FusionCandidateSet, 4>;
 
haveIdenticalTripCounts(const FusionCandidate &FC0,
     const unsigned TC0 = SE.getSmallConstantTripCount(FC0.L);
     const unsigned TC1 = SE.getSmallConstantTripCount(FC1.L);
 
     // If any of the tripcounts are zero that means that loop(s) do not have
     // a single exit or a constant tripcount.
     if (TC0 == 0 || TC1 == 0) {
       LLVM_DEBUG(dbgs() << "Loop(s) do not have a single exit point or do not "
                            "have a constant number of iterations. Peeling "
-                           "is not benefical\n");
+                           "is not beneficial\n");
       return {false, None};
     }
 
     Optional<unsigned> Difference = None;
     int Diff = TC0 - TC1;
 
     if (Diff > 0)
       Difference = Diff;

llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp

findStoreToLoadDependences(const LoopAccessInfo &LAI) {
     const auto *Deps = LAI.getDepChecker().getDependences();
     if (!Deps)
       return Candidates;
 
     // Find store->load dependences (consequently true dep).  Both lexically
     // forward and backward dependences qualify.  Disqualify loads that have
     // other unknown dependences.
 
-    SmallPtrSet<Instruction *, 4> LoadsWithUnknownDepedence;
+    SmallPtrSet<Instruction *, 4> LoadsWithUnknownDependence;
 
     for (const auto &Dep : *Deps) {
       Instruction *Source = Dep.getSource(LAI);
       Instruction *Destination = Dep.getDestination(LAI);
 
       if (Dep.Type == MemoryDepChecker::Dependence::Unknown) {
         if (isa<LoadInst>(Source))
-          LoadsWithUnknownDepedence.insert(Source);
+          LoadsWithUnknownDependence.insert(Source);
         if (isa<LoadInst>(Destination))
-          LoadsWithUnknownDepedence.insert(Destination);
+          LoadsWithUnknownDependence.insert(Destination);
         continue;
       }
 
       if (Dep.isBackward())
         // Note that the designations source and destination follow the program
         // order, i.e. source is always first.  (The direction is given by the
         // DepType.)
         std::swap(Source, Destination);
for (const auto &Dep : *Deps) {
       // Only progagate the value if they are of the same type.
       if (Store->getPointerOperandType() != Load->getPointerOperandType() ||
           getLoadStoreType(Store) != getLoadStoreType(Load))
         continue;
 
       Candidates.emplace_front(Load, Store);
     }
 
-    if (!LoadsWithUnknownDepedence.empty())
+    if (!LoadsWithUnknownDependence.empty())
       Candidates.remove_if([&](const StoreToLoadForwardingCandidate &C) {
-        return LoadsWithUnknownDepedence.count(C.Load);
+        return LoadsWithUnknownDependence.count(C.Load);
       });
 
     return Candidates;
   }
 
   /// Return the index of the instruction according to program order.
   unsigned getInstrIndex(Instruction *Inst) {
     auto I = InstOrder.find(Inst);
     assert(I != InstOrder.end() && "No index for instruction");
     return I->second;
   }
 
   /// If a load has multiple candidates associated (i.e. different
   /// stores), it means that it could be forwarding from multiple stores
   /// depending on control flow.  Remove these candidates.
   ///
   /// Here, we rely on LAA to include the relevant loop-independent dependences.
   /// LAA is known to omit these in the very simple case when the read and the
   /// write within an alias set always takes place using the *same* pointer.
   ///
   /// However, we know that this is not the case here, i.e. we can rely on LAA
   /// to provide us with loop-independent dependences for the cases we're
   /// interested.  Consider the case for example where a loop-independent
-  /// dependece S1->S2 invalidates the forwarding S3->S2.
+  /// dependence S1->S2 invalidates the forwarding S3->S2.
   ///
   ///         A[i]   = ...   (S1)
   ///         ...    = A[i]  (S2)
   ///         A[i+1] = ...   (S3)
   ///
   /// LAA will perform dependence analysis here because there are two
   /// *different* pointers involved in the same alias set (&A[i] and &A[i+1]).
   void removeDependencesFromMultipleStores(

llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp

void deleteDeadLoopBlocks() {
     DTU.applyUpdates(DTUpdates);
     DTUpdates.clear();
     for (auto *BB : DeadLoopBlocks)
       DTU.deleteBB(BB);
 
     NumLoopBlocksDeleted += DeadLoopBlocks.size();
   }
 
-  /// Constant-fold terminators of blocks acculumated in FoldCandidates into the
+  /// Constant-fold terminators of blocks accumulated in FoldCandidates into the
   /// unconditional branches.
   void foldTerminators() {
     for (BasicBlock *BB : FoldCandidates) {
       assert(LI.getLoopFor(BB) == &L && "Should be a loop block!");
       BasicBlock *TheOnlySucc = getOnlyLiveSuccessor(BB);
       assert(TheOnlySucc && "Should have one live successor!");
 
       LLVM_DEBUG(dbgs() << "Replacing terminator of " << BB->getName()

llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp

 /// reg({-1,+,1})  (2/3) * (2/3) *   1
 /// reg({a,+,1})   (2/3) *   1   *   1
 /// reg({b,+,1})     1   * (2/3) * (2/3)
 /// reg(c)           1   *   1   *   0
 ///
 /// Now count registers number mathematical expectation for each formula:
 /// Note that for each use we exclude probability if not selecting for the use.
 /// For example for Use1 probability for reg(a) would be just 1 * 1 (excluding
-/// probabilty 1/3 of not selecting for Use1).
+/// probability 1/3 of not selecting for Use1).
 /// Use1:
 ///  reg(a) + reg({0,+,1})          1 + 1/3       -- to be deleted
 ///  reg(a) + reg({-1,+,1}) + 1     1 + 4/9       -- to be deleted
 ///  reg({a,+,1})                   1
 /// Use2:
 ///  reg(b) + reg({0,+,1})          1/2 + 1/3     -- to be deleted
 ///  reg(b) + reg({-1,+,1}) + 1     1/2 + 2/3     -- to be deleted
 ///  reg({b,+,1})                   2/3

llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp

bool PlaceSafepoints::runOnFunction(Function &F) {
 
   const TargetLibraryInfo &TLI =
       getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
 
   bool Modified = false;
 
   // In various bits below, we rely on the fact that uses are reachable from
   // defs.  When there are basic blocks unreachable from the entry, dominance
-  // and reachablity queries return non-sensical results.  Thus, we preprocess
+  // and reachability queries return non-sensical results.  Thus, we preprocess
   // the function to ensure these properties hold.
   Modified |= removeUnreachableBlocks(F);
 
   // STEP 1 - Insert the safepoint polling locations.  We do not need to
   // actually insert parse points yet.  That will be done for all polls and
   // calls in a single pass.
 
   DominatorTree DT;

llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp

 #include "llvm/Support/DebugCounter.h"
 #include "llvm/Transforms/Utils/Local.h"
 
 using namespace llvm;
 
 namespace llvm {
 cl::opt<bool> ShouldPreserveAllAttributes(
     "assume-preserve-all", cl::init(false), cl::Hidden,
-    cl::desc("enable preservation of all attrbitues. even those that are "
+    cl::desc("enable preservation of all attributes. even those that are "
              "unlikely to be usefull"));
 
 cl::opt<bool> EnableKnowledgeRetention(
     "enable-knowledge-retention", cl::init(false), cl::Hidden,
     cl::desc(
         "enable preservation of attributes throughout code transformation"));
 } // namespace llvm
 

llvm/lib/Transforms/Utils/CodeExtractor.cpp

if (doesNotReturn)
     newFunction->setDoesNotReturn();
 
   LLVM_DEBUG(if (verifyFunction(*newFunction, &errs())) {
     newFunction->dump();
     report_fatal_error("verification of newFunction failed!");
   });
   LLVM_DEBUG(if (verifyFunction(*oldFunction))
              report_fatal_error("verification of oldFunction failed!"));
-  LLVM_DEBUG(if (AC && verifyAssumptionCache(*oldFunction, *newFunction, AC))
-                 report_fatal_error("Stale Asumption cache for old Function!"));
+  LLVM_DEBUG(
+      if (AC && verifyAssumptionCache(*oldFunction, *newFunction, AC))
+          report_fatal_error("Stale Assumption cache for old Function!"));
   return newFunction;
 }
 
 bool CodeExtractor::verifyAssumptionCache(const Function &OldFunc,
                                           const Function &NewFunc,
                                           AssumptionCache *AC) {
   for (auto AssumeVH : AC->assumptions()) {
     auto *I = dyn_cast_or_null<CallInst>(AssumeVH);

llvm/lib/Transforms/Utils/LoopPeel.cpp

for (auto *BB : L.blocks()) {
 
     // With *that* peel count, does the predicate !Pred become known in the
     // first iteration of the loop body after peeling?
     if (!SE.isKnownPredicate(ICmpInst::getInversePredicate(Pred), IterVal,
                              RightSCEV))
       continue; // If not, give up.
 
     // However, for equality comparisons, that isn't always sufficient to
-    // eliminate the comparsion in loop body, we may need to peel one more
+    // eliminate the comparison in loop body, we may need to peel one more
     // iteration. See if that makes !Pred become unknown again.
     if (ICmpInst::isEquality(Pred) &&
         !SE.isKnownPredicate(ICmpInst::getInversePredicate(Pred), NextIterVal,
                              RightSCEV) &&
         !SE.isKnownPredicate(Pred, IterVal, RightSCEV) &&
         SE.isKnownPredicate(Pred, NextIterVal, RightSCEV)) {
       if (!CanPeelOneMoreIteration())
         continue; // Need to peel one more iteration, but can't. Give up.
       PeelOneMoreIteration(); // Great!
     }
 
     DesiredPeelCount = std::max(DesiredPeelCount, NewPeelCount);
   }
 
   return DesiredPeelCount;
 }
 
 /// This "heuristic" exactly matches implicit behavior which used to exist
 /// inside getLoopEstimatedTripCount.  It was added here to keep an
-/// improvement inside that API from causing peeling to become more agressive.
+/// improvement inside that API from causing peeling to become more aggressive.
 /// This should probably be removed.
 static bool violatesLegacyMultiExitLoopCheck(Loop *L) {
   BasicBlock *Latch = L->getLoopLatch();
   if (!Latch)
     return true;
 
   BranchInst *LatchBR = dyn_cast<BranchInst>(Latch->getTerminator());
   if (!LatchBR || LatchBR->getNumSuccessors() != 2 || !L->isLoopExiting(Latch))

llvm/lib/Transforms/Utils/SymbolRewriter.cpp

 //      + Transform     (pattern transformation)
 // - global alias:      (global alias rewriting)
 //      + Source        (original name of the aliased name)
 //      + Target        (explicit transformation)
 //      + Transform     (pattern transformation)
 //
 // Note that source and exactly one of [Target, Transform] must be provided
 //
-// New rewrite descriptors can be created.  Addding a new rewrite descriptor
+// New rewrite descriptors can be created.  Adding a new rewrite descriptor
 // involves:
 //
 //  a) extended the rewrite descriptor kind enumeration
 //     (<anonymous>::RewriteDescriptor::RewriteDescriptorType)
 //  b) implementing the new descriptor
 //     (c.f. <anonymous>::ExplicitRewriteFunctionDescriptor)
 //  c) extending the rewrite map parser
 //     (<anonymous>::RewriteMapParser::parseEntry)

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

protected:
   Value *TripCount = nullptr;
 
   /// Trip count of the widened loop (TripCount - TripCount % (VF*UF))
   Value *VectorTripCount = nullptr;
 
   /// The legality analysis.
   LoopVectorizationLegality *Legal;
 
-  /// The profitablity analysis.
+  /// The profitability analysis.
   LoopVectorizationCostModel *Cost;
 
   // Record whether runtime checks are added.
   bool AddedSafetyChecks = false;
 
   // Holds the end values for each induction variable. We save the end values
   // so we can later fix-up the external users of the induction variables.
   DenseMap<PHINode *, Value *> IVEndValues;

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

for (ScheduleData *BundleMember = SD; BundleMember;
         ScheduleData *DestBundle = DepDest->FirstInBundle;
         if (!DestBundle->IsScheduled)
           BundleMember->incrementUnscheduledDeps(1);
         if (!DestBundle->hasValidDependencies())
           WorkList.push_back(DestBundle);
       };
 
       // Any instruction which isn't safe to speculate at the begining of the
-      // block is control dependend on any early exit or non-willreturn call
+      // block is control dependent on any early exit or non-willreturn call
       // which proceeds it.
       if (!isGuaranteedToTransferExecutionToSuccessor(BundleMember->Inst)) {
         for (Instruction *I = BundleMember->Inst->getNextNode();
              I != ScheduleEnd; I = I->getNextNode()) {
           if (isSafeToSpeculativelyExecute(I, &*BB->begin()))
             continue;
 
           // Add the dependency
for (ScheduleData *BundleMember = SD; BundleMember;
         // from reordering above a preceeding stackrestore.
         if (match(BundleMember->Inst, m_Intrinsic<Intrinsic::stacksave>()) ||
             match(BundleMember->Inst, m_Intrinsic<Intrinsic::stackrestore>())) {
           for (Instruction *I = BundleMember->Inst->getNextNode();
                I != ScheduleEnd; I = I->getNextNode()) {
             if (match(I, m_Intrinsic<Intrinsic::stacksave>()) ||
                 match(I, m_Intrinsic<Intrinsic::stackrestore>()))
               // Any allocas past here must be control dependent on I, and I
-              // must be memory dependend on BundleMember->Inst.
+              // must be memory dependent on BundleMember->Inst.
               break;
 
             if (!isa<AllocaInst>(I))
               continue;
 
             // Add the dependency
             makeControlDependent(I);
           }

llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h

class VPRecipeBuilder {
   Loop *OrigLoop;
 
   /// Target Library Info.
   const TargetLibraryInfo *TLI;
 
   /// The legality analysis.
   LoopVectorizationLegality *Legal;
 
-  /// The profitablity analysis.
+  /// The profitability analysis.
   LoopVectorizationCostModel &CM;
 
   PredicatedScalarEvolution &PSE;
 
   VPBuilder &Builder;
 
   /// When we if-convert we need to create edge masks. We have to cache values
   /// so that we don't end up with exponential recursion/IR. Note that

llvm/lib/Transforms/Vectorize/VPlan.h

return Op == getAddr() && all_of(getStoredValues(), [Op](VPValue *StoredV) {
            });
   }
 };
 
 /// A recipe to represent inloop reduction operations, performing a reduction on
 /// a vector operand into a scalar value, and adding the result to a chain.
 /// The Operands are {ChainOp, VecOp, [Condition]}.
 class VPReductionRecipe : public VPRecipeBase, public VPValue {
-  /// The recurrence decriptor for the reduction in question.
+  /// The recurrence descriptor for the reduction in question.
   const RecurrenceDescriptor *RdxDesc;
   /// Pointer to the TTI, needed to create the target reduction
   const TargetTransformInfo *TTI;
 
 public:
   VPReductionRecipe(const RecurrenceDescriptor *R, Instruction *I,
                     VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp,
                     const TargetTransformInfo *TTI)

llvm/test/Analysis/BasicAA/modref.ll

 ;
   %V1 = load i32, i32* %P
   call i32 @func_argmemonly(i32* %P2)
   %V2 = load i32, i32* %P
   %Diff = sub i32 %V1, %V2
   ret i32 %Diff
 }
 
-;; In this case load can *not* be removed. Function clobers only %P2 but it may
+;; In this case load can *not* be removed. Function clobbers only %P2 but it may
 ;; alias with %P.
 define i32 @test10(i32* %P, i32* %P2) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:    [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @func_argmemonly(i32* [[P2:%.*]])
 ; CHECK-NEXT:    [[V2:%.*]] = load i32, i32* [[P]], align 4
 ; CHECK-NEXT:    [[DIFF:%.*]] = sub i32 [[V1]], [[V2]]
 ; CHECK-NEXT:    ret i32 [[DIFF]]

llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheckFixedSize.ll

 ; RUN: opt < %s -disable-output -passes="print<da>" 2>&1 | FileCheck %s
 
-; Note: exact results can be achived even if
+; Note: exact results can be achieved even if
 ; "-da-disable-delinearization-checks" is not used
 
 ; CHECK-LABEL: t1
 ; CHECK: da analyze - none!
 ; CHECK: da analyze - consistent anti [1 -2]!
 ; CHECK: da analyze - none!
 
 ;; #define N 1024

llvm/test/Analysis/LoopAccessAnalysis/forward-loop-independent.ll

 ; RUN: opt -passes='print-access-info' -disable-output  < %s 2>&1 | FileCheck %s
 
-; Check that loop-indepedent forward dependences are discovered properly.
+; Check that loop-independent forward dependences are discovered properly.
 ;
 ; FIXME: This does not actually always work which is pretty confusing.  Right
-; now there is hack in LAA that tries to figure out loop-indepedent forward
-; dependeces *outside* of the MemoryDepChecker logic (i.e. proper dependence
+; now there is hack in LAA that tries to figure out loop-independent forward
+; dependences *outside* of the MemoryDepChecker logic (i.e. proper dependence
 ; analysis).
 ;
 ; Therefore if there is only loop-independent dependences for an array
 ; (i.e. the same index is used), we don't discover the forward dependence.
 ; So, at ***, we add another non-I-based access of A to trigger
 ; MemoryDepChecker analysis for accesses of A.
 ;
 ;   for (unsigned i = 0; i < 100; i++) {

llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll

for.body:                                         ; preds = %entry, %for.body
   %arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %1
   %2 = trunc i64 %1 to i32
   store i32 %2, i32* %arrayidx3, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2
   %cmp = icmp ult i64 %indvars.iv.next, 1024
   br i1 %cmp, label %for.body, label %for.cond.cleanup
 }
 
-; Following cases are unsafe depdences and are not vectorizable.
+; Following cases are unsafe dependences and are not vectorizable.
 
 ; void unsafe_Read_Write(int *A) {
 ;   for (unsigned i = 0; i < 1024; i+=3)
 ;     A[i+3] = A[i] + 1;
 ; }
 
 ; CHECK: function 'unsafe_Read_Write':
 ; CHECK-NEXT:   for.body:

llvm/test/BugPoint/metadata.ll

 ; REQUIRES: plugins
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%pluginext %s -output-prefix %t -bugpoint-crashcalls -silence-passes -disable-namedmd-remove -disable-strip-debuginfo -disable-strip-debug-types > /dev/null
 ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s
 ;
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%pluginext %s -output-prefix %t-nodebug -bugpoint-crashcalls -silence-passes -disable-namedmd-remove > /dev/null
 ; RUN: llvm-dis %t-nodebug-reduced-simplified.bc -o - | FileCheck %s --check-prefix=NODEBUG
 ;
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%pluginext %s -output-prefix %t-notype -bugpoint-crashcalls -silence-passes -disable-namedmd-remove -disable-strip-debuginfo > /dev/null
 ; RUN: llvm-dis %t-notype-reduced-simplified.bc -o - | FileCheck %s --check-prefix=NOTYPE
 ;
-; Bugpoint can drop the metadata on the call, as it does not contrinute to the crash.
+; Bugpoint can drop the metadata on the call, as it does not contribute to the crash.
 
 ; CHECK: call void @foo()
 ; NODEBUG: call void @foo()
 ; NOTYPE: call void @foo()
 ; NODEBUG-NOT: call void @foo()
 ; NOTYPE-NOT: !DIBasicType
 ; NOTYPE: !DICompileUnit
 ; NOTYPE-NOT: !DIBasicType

llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll

 ; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    movi d2, #0000000000000000
 ; CHECK-NEXT:    movi d3, #0000000000000000
 ; CHECK-NEXT:    ret
   ret [ 2 x %T_STRUCT_ARRAYM ] zeroinitializer
 }
 
 ;; All non-aggregate fields must have the same type, all through the
-;; overall aggreagate. This is false here because of the i32.
+;; overall aggregate. This is false here because of the i32.
 %T_NESTED_STRUCT_DIFFM = type {
   [ 1 x { { double, double } } ],
   [ 1 x { { double, i32 } } ]
 };
 
 define %T_NESTED_STRUCT_DIFFM @struct_nested_different_field_types() {
 ; CHECK-LABEL: struct_nested_different_field_types:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll

 ; REQUIRES: asserts
 ;
-; The Cortext-A57 machine model will avoid scheduling load instructions in
+; The Cortex-A57 machine model will avoid scheduling load instructions in
 ; succession because loads on the A57 have a latency of 4 cycles and they all
 ; issue to the same pipeline. Instead, it will move other instructions between
 ; the loads to avoid unnecessary stalls. The generic machine model schedules 4
 ; loads consecutively for this case and will cause stalls.
 ;
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: main:%bb.2

llvm/test/CodeGen/AArch64/ccmp-successor-probs.mir

 # RUN: llc -o - %s -mtriple=aarch64--linux-gnu -mcpu=falkor -run-pass=aarch64-ccmp | FileCheck %s
 ---
-# This test checks that successor probabilties are properly updated after a
+# This test checks that successor probabilities are properly updated after a
 # ccmp-conversion.
 #
 # CHECK-LABEL: name: aarch64-ccmp-successor-probs
 # CHECK:       bb.0:
 # CHECK-NEXT:    successors: %bb.2(0x04000000), %bb.3(0x7c000000)
 # CHECK:         CCMPXr %5, %4, 0, 10, implicit-def $nzcv, implicit $nzcv
 #
 name: aarch64-ccmp-successor-probs

llvm/test/CodeGen/AArch64/ifcvt-select.ll

 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
-; Do not generate redundant select in early if-converstion pass. 
+; Do not generate redundant select in early if-conversion pass. 
 
 define i32 @foo(i32 %a, i32 %b)  {
 entry:
 ;CHECK-LABEL: foo:
 ;CHECK: csinc
 ;CHECK-NOT: csel
   %sub = sub nsw i32 %b, %a
   %cmp10 = icmp sgt i32 %a, 0

llvm/test/CodeGen/AArch64/swift-async-win.ll

entryresume.0:
   %7 = bitcast i8* %6 to void (%swift.context*)**
   %8 = load void (%swift.context*)*, void (%swift.context*)** %7, align 8
   %9 = bitcast i8* %5 to %swift.context*
   musttail call swifttailcc void %8(%swift.context* %9) #4
   ret void
 }
 
 ; NOTE: we do not see the canonical windows frame setup due to the `nounwind`
-; attribtue on the function.
+; attribute on the function.
 
 ; CHECK: sub sp, sp, #64
 ; CHECK: stp x30, x29, [sp, #16]
 ; CHECK: add x29, sp, #16
 ; CHECK: stp x22, x21, [sp, #32]
 ; CHECK: sub x8, x29, #8
 ; CHECK: stp x20, x19, [sp, #48]
 ; CHECK: ldr x9, [x0]

llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll

 ; COMMON:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
 ; COMMON:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
 ; SDAG:  STRXui %{{.*}}, %fixed-stack.0
 ; SDAG:  STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
 ; GISEL:  STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
 ; GISEL:  STRXui %{{.*}}, %fixed-stack.0
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
-; Without this edge the scheduler would be free to move the store accross the load.
+; Without this edge the scheduler would be free to move the store across the load.
 
 ; COMMON: {{^SU(.*)}}:   [[VRB]]:gpr64 = LDRXui %fixed-stack.2
 ; COMMON-NOT: {{^SU(.*)}}:
 ; COMMON:  Successors:
 ; COMMON:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; COMMON:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
 ; GlobalISel outputs DEPSTOREB before DEPSTOREA, but the dependency relationship
 ; still holds.
 ; SDAG: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.0
 ; SDAG: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.1
 
 ; GISEL: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.0
 ; GISEL: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.1

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll

 ; CHECK-LABEL: name: fma_fast
 ; CHECK: nnan ninf nsz arcp contract afn reassoc G_FMA
 define amdgpu_kernel void @fma_fast(float %arg0, float %arg1, float %arg2) {
   %res = call fast float @llvm.fma.f32(float %arg0, float %arg1, float %arg2)
   store float %res, float addrspace(1)* undef
   ret void
 }
 
-; Check flags are preserved for an arbitrarry target intrinsic
+; Check flags are preserved for an arbitrary target intrinsic
 ; CHECK-LABEL: name: rcp_nsz
 ; CHECK: = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %{{[0-9]+}}(s32)
 define amdgpu_kernel void @rcp_nsz(float %arg0) {
   %res = call nsz float @llvm.amdgcn.rcp.f32 (float %arg0)
   store float %res, float addrspace(1)* undef
   ret void
 }
 
 declare float @llvm.fma.f32(float, float, float)
 declare float @llvm.amdgcn.rcp.f32(float)

llvm/test/CodeGen/AMDGPU/collapse-endcf.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s
 
-# Make sure dbg_value doesn't change codeegn when collapsing end_cf
+# Make sure dbg_value doesn't change codegen when collapsing end_cf
 ---
 name: simple_nested_if_dbg_value
 tracksRegLiveness: true
 machineFunctionInfo:
   isEntryFunction: true
 body:             |
   ; GCN-LABEL: name: simple_nested_if_dbg_value
   ; GCN: bb.0:

llvm/test/CodeGen/AMDGPU/idot4u.ll

entry:
   %mad2 = add i8 %mul2, %mad1
   %mad3 = add i8 %mul3, %mad2
   %mad4 = add i8 %mul4, %mad3
 
   store i8 %mad4, i8 addrspace(1)* %dst, align 2
   ret void
 }
 
-; TODO: Support commutation accross the adds.
+; TODO: Support commutation across the adds.
 define amdgpu_kernel void @udot4_CommutationAccrossMADs(<4 x i8> addrspace(1)* %src1,
 ; GFX7-LABEL: udot4_CommutationAccrossMADs:
 ; GFX7:       ; %bb.0: ; %entry
 ; GFX7-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX7-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s10, 0
 ; GFX7-NEXT:    s_mov_b32 s11, s3

llvm/test/CodeGen/AMDGPU/idot8u.ll

entry:
   %add6 = add i8 %add5, %mul5
   %add7 = add i8 %add6, %mul6
   %add8 = add i8 %add7, %mul7
 
   store i8 %add8, i8 addrspace(1)* %dst, align 4
   ret void
 }
 
-; TODO: Once the adictional "and+add" are removed, the pattern will be recognized.
+; TODO: Once the additional "and+add" are removed, the pattern will be recognized.
 define amdgpu_kernel void @udot8_acc4_vecMul(<8 x i4> addrspace(1)* %src1,
 ; GFX7-LABEL: udot8_acc4_vecMul:
 ; GFX7:       ; %bb.0: ; %entry
 ; GFX7-NEXT:    s_mov_b32 s12, SCRATCH_RSRC_DWORD0
 ; GFX7-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1
 ; GFX7-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX7-NEXT:    s_mov_b32 s14, -1

llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll

bb:
   %tmp6 = extractelement <9 x i32> %tmp5, i32 1
   %tmp7 = bitcast <9 x float> %tmp4 to <9 x i32>
   %tmp8 = extractelement <9 x i32> %tmp7, i32 5
   store volatile i32 %tmp6, i32 addrspace(3)* undef, align 4
   store volatile i32 %tmp8, i32 addrspace(3)* undef, align 4
   ret void
 }
 
-; offset puts outside of superegister bounaries, so clamp to 1st element.
+; offset puts outside of superegister boundaries, so clamp to 1st element.
 ; GCN-LABEL: {{^}}extract_largest_inbounds_offset:
 ; GCN-DAG: buffer_load_dwordx4 v[[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]
 ; GCN-DAG: s_load_dword [[IDX0:s[0-9]+]]
 ; GCN-DAG: s_add_i32 [[IDX:s[0-9]+]], [[IDX0]], 15
 
 ; MOVREL: s_mov_b32 m0, [[IDX]]
 ; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
 

llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir

bb.0:
     ; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v1
     ; CHECK-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
     ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v1
     $vgpr0 = V_EXP_F32_e32 $vgpr0, implicit $exec, implicit $mode
     $vgpr1 = V_ADD_U32_e32 $vgpr1, $vgpr1, implicit $exec
     $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr1, implicit $exec
 ...
 
-# There's no need to encode the VALU depdendency because it will complete before
+# There's no need to encode the VALU dependency because it will complete before
 # the TRANS.
 ---
 name: trans32_dep_1_only
 body: |
   bb.0:
     ; CHECK-LABEL: {{^}}trans32_dep_1_only:
     ; CHECK: %bb.0:
     ; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v0

llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll

 ; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs < %s 2>&1 | FileCheck %s
 
 ; This testcase fails register allocation at the same time it performs
 ; virtual register splitting (by introducing VGPR to AGPR copies). We
 ; still need to enqueue and allocate the newly split vregs after the
 ; failure.
 
 ; The machine verifier complains about usage of register
 ; which is marked as killed in previous instruction.
 ; This happens due to when register allocator is out of registers
-; it takes the first avialable register.
+; it takes the first available register.
 
 ; CHECK: error: ran out of registers during register allocation
 ; CHECK: Bad machine code: Using an undefined physical register
 define amdgpu_kernel void @alloc_failure_with_split_vregs(float %v0, float %v1) #0 {
   %agpr0 = call float asm sideeffect "; def $0", "=${a0}"()
   %agpr.vec = insertelement <16 x float> undef, float %agpr0, i32 0
   %mfma0 = call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float %v0, float %v1, <16 x float> %agpr.vec, i32 0, i32 0, i32 0)
   %mfma0.3 = extractelement <16 x float> %mfma0, i32 3

llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll

define amdgpu_kernel void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 {
   %load0 = load i32, i32 addrspace(1)* %ptr, align 4
   %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 2
   %load1 = load i32, i32 addrspace(1)* %gep, align 4
   store i32 %load0, i32 addrspace(1)* %out0, align 4
   store i32 %load1, i32 addrspace(1)* %out1, align 4
   ret void
 }
 
-; Test for a crach in SIInstrInfo::areLoadsFromSameBasePtr() when checking
+; Test for a crash in SIInstrInfo::areLoadsFromSameBasePtr() when checking
 ; an MUBUF load which does not have a vaddr operand.
 ; FUNC-LABEL: {{^}}same_base_ptr_crash:
 ; SI: buffer_load_dword
 ; SI: buffer_load_dword
 define amdgpu_kernel void @same_base_ptr_crash(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) {
 entry:
   %out1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
   %tmp0 = load i32, i32 addrspace(1)* %out
   %tmp1 = load i32, i32 addrspace(1)* %out1
   %tmp2 = add i32 %tmp0, %tmp1
   store i32 %tmp2, i32 addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/scratch-buffer.ll

 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
 
 ; When a frame index offset is more than 12-bits, make sure we don't store
 ; it in mubuf's offset field.
 
-; Also, make sure we use the same register for storing the scratch buffer addresss
+; Also, make sure we use the same register for storing the scratch buffer address
 ; for both stores. This register is allocated by the register scavenger, so we
 ; should be able to reuse the same regiser for each scratch buffer access.
 
 ; GCN-LABEL: {{^}}legal_offset_fi:
 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:4{{$}}
 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x8004
 ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
 

llvm/test/CodeGen/AMDGPU/structurize1.ll

 ; RUN: llc -march=r600 -mcpu=redwood -r600-if-convert=0 < %s | FileCheck %s
 
-; This tests for abug where the AMDILCFGStructurizer was crashing on loops
+; This tests for a bug where the AMDILCFGStructurizer was crashing on loops
 ; like this:
 ;
 ; for (i = 0; i < x; i++) {
 ;   if (cond0) {
 ;     if (cond1) {
 ;
 ;     } else {
 ;

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

main_body:
   call void asm sideeffect "", "~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() #0
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
   call void @extern_func()
   ret <4 x float> %v
 }
 
 define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) {
 ; The vgpr tuple8 operand in image_gather4_c_b_cl instruction needs to be preserved
-; across the call and should get allcoated to 8 CSRs.
+; across the call and should get allocated to 8 CSRs.
 ; Only the lower 5 sub-registers of the tuple are preserved.
 ; The upper 3 sub-registers are unused.
 ; GFX9-LABEL: call_preserved_vgpr_tuple8:
 ; GFX9:       ; %bb.0: ; %main_body
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
 ; GFX9-NEXT:    s_mov_b64 exec, s[4:5]

llvm/test/CodeGen/AMDGPU/vtx-schedule.ll

 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ; This test is for a scheduler bug where VTX_READ instructions that used
 ; the result of another VTX_READ instruction were being grouped in the
-; same fetch clasue.
+; same fetch clause.
 
 ; CHECK: {{^}}test:
 ; CHECK: Fetch clause
 ; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
 ; CHECK: Fetch clause
 ; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
 define amdgpu_kernel void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
 entry:
   %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %in0
   %1 = load i32, i32 addrspace(1)* %0
   store i32 %1, i32 addrspace(1)* %out
   ret void
 }

llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir

 # RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # TODO: Write this test.
-# This instruction isn't expanded by the pseudo expansion passs, but
+# This instruction isn't expanded by the pseudo expansion pass, but
 # rather AVRRegisterInfo::eliminateFrameIndex.
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }

llvm/test/CodeGen/Hexagon/fp16.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; This test validates the following facts for half-precision floating point
 ; conversions.
 ; Generate correct libcall names for conversion from fp16 to fp32.
 ; (__extendhfsf2).
 ;  The extension from fp16 to fp64 is implicitly handled by __extendhfsf2 and convert_sf2d.
 ; (fp16->fp32->fp64).
-; Generate correcct libcall names for conversion from fp32/fp64 to fp16
+; Generate correct libcall names for conversion from fp32/fp64 to fp16
 ; (__truncsfhf2 and __truncdfhf2)
 ; Verify that we generate loads and stores of halfword.
 
 ; Validate that we generate correct lib calls to convert fp16
 
 ;CHECK-LABEL: @test1
 ;CHECK: call __extendhfsf2
 ;CHECK: r0 = memuh

llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll

 ; RUN: llc -march=hexagon -O2 -enable-pipeliner -disable-block-placement=0 < %s  | FileCheck %s
 
 ; For the Phis generated in the epilog, test that we generate the correct
-; names for the values coming from the prolog stages. The test belows
+; names for the values coming from the prolog stages. The test below
 ; checks that the value loaded in the first prolog block gets propagated
 ; through the first epilog to the use after the loop.
 
 ; CHECK: if ({{.*}}) jump
 ; CHECK: [[VREG:v([0-9]+)]]{{.*}} = {{.*}}vmem(r{{[0-9]+}}++#1)
 ; CHECK: if ({{.*}}) {{jump|jump:nt|jump:t}} [[EPLOG1:(.*)]]
 ; CHECK: if ({{.*}}) {{jump|jump:nt|jump:t}} [[EPLOG:(.*)]]
 ; CHECK: [[EPLOG]]:

llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll

 ; RUN: llc -march=hexagon -pipeliner-ignore-recmii -pipeliner-max-stages=2 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s
 
-; This is a loop we pipeline to three packets, though we could do bettter.
+; This is a loop we pipeline to three packets, though we could do better.
 
 ; CHECK: loop0(.LBB0_[[LOOP:.]],
 ; CHECK: .LBB0_[[LOOP]]:
 ; CHECK: {
 ; CHECK: }
 ; CHECK: {
 ; CHECK: }
 ; CHECK: {

llvm/test/CodeGen/M68k/Arith/mul64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
 
-; Currenlty making the libcall is ok, x20 supports i32 mul/div which
+; Currently making the libcall is ok, x20 supports i32 mul/div which
 ; yields saner expansion for i64 mul
 define i64 @foo(i64 %t, i64 %u) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l (36,%sp), (12,%sp)
 ; CHECK-NEXT:    move.l (32,%sp), (8,%sp)
 ; CHECK-NEXT:    move.l (28,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (%sp)
 ; CHECK-NEXT:    jsr __muldi3@PLT
 ; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
   %k = mul i64 %t, %u
   ret i64 %k
 }

llvm/test/CodeGen/M68k/CollapseMOVEM.mir

 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 # RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=asm -o - \
 # RUN:   | FileCheck %s
 
 #------------------------------------------------------------------------------
 # CollapseMOVEM pass finds sequences of MOVEM instructions and collapse them
-# into a single instruciton with merged masks. This only works with stack data
+# into a single instruction with merged masks. This only works with stack data
 #------------------------------------------------------------------------------
 
 --- # CollapseMOVEM_RM
 #
 # CHECK-LABEL: CollapseMOVEM_RM
 # CHECK:       movem.l (0,%sp), %d0-%d2/%d7/%a1-%a3/%a5
 name: CollapseMOVEM_RM
 body: |

llvm/test/CodeGen/PowerPC/ppc-vaarg-agg.ll

 
 sw.bb326:                                         ; preds = %repeat
   unreachable
 
 maxlen_reached:                                   ; preds = %entry
   ret void
 }
 
-; If the SD nodes are not cleaup up correctly, then this can fail to compile
+; If the SD nodes are not cleaned up correctly, then this can fail to compile
 ; with an error like:  Cannot select: ch = setlt [ID=6]
 ; CHECK: @test1
 

llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll

 ; CHECK-SCO-LABEL: caller_64_64_copy:
 ; CHECK-SCO: b callee_64_64_copy
 }
 
 define internal fastcc void @callee_64_64_copy_fastcc([8 x i64] %a, [8 x i64] %b) #0 { ret void }
 define dso_local void @caller_64_64_copy_ccc([8 x i64] %a, [8 x i64] %b) #1 {
   tail call fastcc void @callee_64_64_copy_fastcc([8 x i64] %a, [8 x i64] %b)
   ret void
-; If caller and callee use different calling convensions, we cannot apply TCO.
+; If caller and callee use different calling conventions, we cannot apply TCO.
 ; CHECK-SCO-LABEL: caller_64_64_copy_ccc:
 ; CHECK-SCO: bl callee_64_64_copy_fastcc
 }
 
 define dso_local void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
   tail call void @callee_64_64_copy([8 x i64] %b, [8 x i64] %a)
   ret void
 

llvm/test/CodeGen/PowerPC/store_fptoi.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-PWR8 %s
 
 ; ==========================================
-; Tests for store of fp_to_sint converstions
+; Tests for store of fp_to_sint conversions
 ; ==========================================
 
 ; Function Attrs: norecurse nounwind
 define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) {
 ; CHECK-LABEL: qpConv2sdw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv 2, 0(3)
 ; CHECK-NEXT:    xscvqpsdz 2, 2
entry:
   %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1
   ret void
 
 
 }
 
 ; ==========================================
-; Tests for store of fp_to_uint converstions
+; Tests for store of fp_to_uint conversions
 ; ==========================================
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2udw(double* nocapture readonly %a, i64* nocapture %b) {
 ; CHECK-LABEL: dpConv2udw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd 0, 0(3)
 ; CHECK-NEXT:    xscvdpuxds 2, 0

llvm/test/CodeGen/PowerPC/test-vector-insert.ll

 ; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
 ; xscvdpsxws and xscvdpsxws is only available on Power7 and above
-; Codgen is different for Power7, Power8, and Power9.
+; Codegen is different for Power7, Power8, and Power9.
 
 define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
 ; CHECK-LE-P7-LABEL: test:
 ; CHECK-LE-P7:       # %bb.0: # %entry
 ; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -4
 ; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI0_0@toc@l

llvm/test/CodeGen/RISCV/frm-dependency.ll

define float @fmadd_s(float %a, float %b, float %c) nounwind {
   ; RV64IF-NEXT:   [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f
   ; RV64IF-NEXT:   %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm
   ; RV64IF-NEXT:   $f10_f = COPY %3
   ; RV64IF-NEXT:   PseudoRET implicit $f10_f
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
-; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependncy.
+; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependency.
 define i32 @fcvt_w_s(float %a) nounwind {
   ; RV32IF-LABEL: name: fcvt_w_s
   ; RV32IF: bb.0 (%ir-block.0):
   ; RV32IF-NEXT:   liveins: $f10_f
   ; RV32IF-NEXT: {{  $}}
   ; RV32IF-NEXT:   [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
   ; RV32IF-NEXT:   %1:gpr = nofpexcept FCVT_W_S [[COPY]], 1
   ; RV32IF-NEXT:   $x10 = COPY %1

llvm/test/CodeGen/SystemZ/fp-const-10.ll

 ; Test loads of SNaN.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Test that we don't do an FP extending load, as this would result in a
-; converstion to QNaN.
+; conversion to QNaN.
 define double @f1() {
 ; CHECK-LABEL: .LCPI0_0
 ; CHECK:      .quad   0x7ff4000000000000
 ; CHECK-LABEL: f1:
 ; CHECK:      larl    %r1, .LCPI0_0
 ; CHECK-NOT:  ldeb    %f0, 0(%r1)
 ; CHECK:      ld      %f0, 0(%r1)
   ret double 0x7FF4000000000000
 }

llvm/test/CodeGen/Thumb2/2010-02-24-BigStack.ll

 ; RUN: llc < %s -O0 -relocation-model=pic -frame-pointer=all -mcpu=cortex-a8 -mattr=+vfp2
 ; This test creates a big stack frame without spilling any callee-saved registers.
-; Make sure the whole stack frame is addrerssable wiothout scavenger crashes.
+; Make sure the whole stack frame is addressable wiothout scavenger crashes.
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin3.0.0-iphoneos"
 
 define void @FindMin(double* %panelTDEL, i8* %dclOfRow, i32 %numRows, i32 %numCols, double* %retMin_RES_TDEL) {
 entry:
   %panelTDEL.addr = alloca double*, align 4       ; <double**> [#uses=1]
   %panelResTDEL = alloca [2560 x double], align 4 ; <[2560 x double]*> [#uses=0]
   store double* %panelTDEL, double** %panelTDEL.addr
   store double* %retMin_RES_TDEL, double** undef
   store i32 0, i32* undef
   unreachable
 }

llvm/test/CodeGen/Thumb2/thumb2-sub5.ll

 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2,+32bit %s -o - \
 ; RUN:  | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: subs.w r0, r0, r2
-; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
+; To test dead_carry, +32bit prevents sbc converting to 16-bit sbcs
 ; CHECK: sbc.w  r1, r1, r3
     %tmp = sub i64 %a, %b
     ret i64 %tmp
 }

llvm/test/CodeGen/WebAssembly/exception.ll

catch.start:                                      ; preds = %catch.dispatch
   %2 = call i8* @llvm.wasm.get.exception(token %1)
   %3 = call i32 @llvm.wasm.get.ehselector(token %1)
   catchret from %1 to label %try.cont
 
 try.cont:                                         ; preds = %catch.start, %entry
   ret void
 }
 
-; Tests a case when a cleanup region (cleanuppad ~ clanupret) contains another
+; Tests a case when a cleanup region (cleanuppad ~ cleanupret) contains another
 ; catchpad
 define void @test_complex_cleanup_region() personality i8* bitcast (i32 (...)* @__gxx_wasm_personality_v0 to i8*) {
 entry:
   invoke void @foo()
           to label %invoke.cont unwind label %ehcleanup
 
 invoke.cont:                                      ; preds = %entry
   ret void

llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=i686-unknown-linux -relocation-model=static -stats 2>&1 | \
 ; RUN:   grep asm-printer | grep 14
 ;
 ; It's possible to schedule this in 14 instructions by avoiding
 ; callee-save registers, but the scheduler isn't currently that
-; conervative with registers.
+; conservative with registers.
 @size20 = external dso_local global i32   ; <ptr> [#uses=1]
 @in5 = external dso_local global ptr    ; <ptr> [#uses=1]
 
 define i32 @compare(ptr %a, ptr %b) nounwind {
   %tmp.upgrd.1 = load i32, ptr @size20    ; <i32> [#uses=1]
   %tmp.upgrd.2 = load ptr, ptr @in5   ; <ptr> [#uses=2]
   %tmp3 = load i32, ptr %b    ; <i32> [#uses=1]
   %gep.upgrd.3 = zext i32 %tmp3 to i64    ; <i64> [#uses=1]

llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll

 ; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt -enable-misched=false < %s | FileCheck %s
 ; Check that lowered arguments do not overwrite the return address before it is moved.
 ; Bug 6225
 ;
 ; If a call is a fastcc tail call and tail call optimization is enabled, the
 ; caller frame is replaced by the callee frame. This can require that arguments are
 ; placed on the former return address stack slot. Special care needs to be taken
 ; taken that the return address is moved / or stored in a register before
 ; lowering of arguments potentially overwrites the value.
 ;
 ; Move return address (76(%esp)) to a temporary register (%ebp)
 ; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]]
-; Overwrite return addresss
+; Overwrite return address
 ; CHECK: movl [[EBX:%[a-z]+]], 76(%esp)
 ; Move return address from temporary register (%ebp) to new stack location (60(%esp))
 ; CHECK: movl [[REGISTER]], 60(%esp)
 
 %tupl = type [9 x i32]
 
 declare fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) nounwind
 declare fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) nounwind

llvm/test/CodeGen/X86/avx2-vbroadcast.ll

; X64-AVX512VL-NEXT:    retq
   %2 = insertelement <8 x i32> undef, i32 %1, i32 0
   %3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> zeroinitializer
   %4 = shufflevector <8 x i32> undef, <8 x i32> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   store <16 x i32> %4, ptr %b, align 4
   ret void
 }
 
 ; Test cases for <rdar://problem/16074331>.
-; Instruction selection for broacast instruction fails if
+; Instruction selection for broadcast instruction fails if
 ; the load cannot be folded into the broadcast.
 ; This happens if the load has initial one use but other uses are
 ; created later, or if selection DAG cannot prove that folding the
 ; load will not create a cycle in the DAG.
 ; Those test cases exerce the latter.
 
 define void @isel_crash_16b(ptr %cV_R.addr) {
 ; X32-LABEL: isel_crash_16b:

llvm/test/CodeGen/X86/bitcnt-false-dep.ll

loop:
   br i1 %exitcond, label %ret, label %loop
 ret:
   ret i32 %s2
 
 ;HSW-LABEL:@loopdep_tzct32
 ;HSW: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
 ;HSW-NEXT: tzcntl {{.*}}, [[GPR0]]
 
-; This false dependecy issue was fixed in Skylake
+; This false dependency issue was fixed in Skylake
 ;SKL-LABEL:@loopdep_tzct32
 ;SKL-NOT: xor
 ;SKL: tzcntl
 }
 
 define i64 @loopdep_tzct64(ptr nocapture %x, ptr nocapture %y) nounwind {
 entry:
   %vx = load i64, ptr %x
loop:
   br i1 %exitcond, label %ret, label %loop
 ret:
   ret i64 %s2
 
 ;HSW-LABEL:@loopdep_tzct64
 ;HSW: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
 ;HSW-NEXT: tzcntq {{.*}}, %r[[GPR0]]
 
-; This false dependecy issue was fixed in Skylake
+; This false dependency issue was fixed in Skylake
 ;SKL-LABEL:@loopdep_tzct64
 ;SKL-NOT: xor
 ;SKL: tzcntq
 }
 
 define i32 @loopdep_lzct32(ptr nocapture %x, ptr nocapture %y) nounwind {
 entry:
   %vx = load i32, ptr %x
loop:
   br i1 %exitcond, label %ret, label %loop
 ret:
   ret i32 %s2
 
 ;HSW-LABEL:@loopdep_lzct32
 ;HSW: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
 ;HSW-NEXT: lzcntl {{.*}}, [[GPR0]]
 
-; This false dependecy issue was fixed in Skylake
+; This false dependency issue was fixed in Skylake
 ;SKL-LABEL:@loopdep_lzct32
 ;SKL-NOT: xor
 ;SKL: lzcntl
 }
 
 define i64 @loopdep_lzct64(ptr nocapture %x, ptr nocapture %y) nounwind {
 entry:
   %vx = load i64, ptr %x
loop:
   br i1 %exitcond, label %ret, label %loop
 ret:
   ret i64 %s2
 
 ;HSW-LABEL:@loopdep_lzct64
 ;HSW: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
 ;HSW-NEXT: lzcntq {{.*}}, %r[[GPR0]]
 
-; This false dependecy issue was fixed in Skylake
+; This false dependency issue was fixed in Skylake
 ;SKL-LABEL:@loopdep_lzct64
 ;SKL-NOT: xor
 ;SKL: lzcntq
 }

llvm/test/CodeGen/X86/block-placement.ll

ret:                                              ; preds = %endif, %then
   ret void
 }
 
 define i32 @not_rotate_if_extra_branch(i32 %count) {
 ; Test checks that there is no loop rotation
 ; if it introduces extra branch.
 ; Specifically in this case because best exit is .header
 ; but it has fallthrough to .middle block and last block in
-; loop chain .slow does not have afallthrough to .header.
+; loop chain .slow does not have a fallthrough to .header.
 ; CHECK-LABEL: not_rotate_if_extra_branch
 ; CHECK: %.entry
 ; CHECK: %.header
 ; CHECK: %.middle
 ; CHECK: %.backedge
 ; CHECK: %.slow
 ; CHECK: %.bailout
 ; CHECK: %.stop

 
 .stop:
   %sum.phi = phi i32 [ %sum.1, %.backedge ], [ %sum.2, %.bailout ]
   ret i32 %sum.phi
 }
 
 define i32 @not_rotate_if_extra_branch_regression(i32 %count, i32 %init) {
 ; This is a regression test against patch avoid loop rotation if
-; it introduce an extra btanch.
+; it introduce an extra branch.
 ; CHECK-LABEL: not_rotate_if_extra_branch_regression
 ; CHECK: %.entry
 ; CHECK: %.first_backedge
 ; CHECK: %.second_header
 ; CHECK: %.slow
 .entry:
   %sum.0 = shl nsw i32 %count, 1
   br label %.first_header

llvm/test/CodeGen/X86/crash-lre-eliminate-dead-def.ll

 ; ...
 ; v2 = loadimm cst 
 ; ...
 ; = use v2
 ;
 ; v1 is now dead so we remove its live-range.
 ; Actually, we shrink it to empty to keep the
 ; instruction around for futher remat opportunities
-; (accessbile via the origin pointer.)
+; (accessible via the origin pointer.)
 ;
 ; Later v2 gets remove as well (e.g., because we
 ; remat it closer to its use) and the live-range
 ; gets eliminated. We used to crash at this point
 ; because we were looking for a VNI of origin (v1)
 ; at the slot index of the definition of v2. However,
 ; we do not have a VNI for v1 at this point, since the
 ; live-range is now empty... crash!

llvm/test/CodeGen/X86/dagcombine-shifts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
 
 ; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
 
-; Canolicalize the sequence shl/zext/lshr performing the zeroextend
+; Canonicalize the sequence shl/zext/lshr performing the zeroextend
 ; as the last instruction of the sequence.
 ; This will help DAGCombiner to identify and then fold the sequence
 ; of shifts into a single AND.
 ; This transformation is profitable if the shift amounts are the same
 ; and if there is only one use of the zext.
 
 define i16 @fun1(i8 zeroext %v) {
 ; CHECK-LABEL: fun1:

llvm/test/CodeGen/X86/fptoui-may-overflow.ll

 ; CHECK-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %f = fptoui <4 x float> %arg to <4 x i8>
   %z = zext <4 x i8> %f to <4 x i32>
   %b = bitcast <4 x i32> %z to <16 x i8>
   ret <16 x i8> %b
 }
 
-; In @fptoui_shuffle, we must preserve the vpand for correctnesss. Only the
+; In @fptoui_shuffle, we must preserve the vpand for correctness. Only the
 ; i8 values extracted from %s are poison.  The values from the zeroinitializer
 ; are not.
 
 define <16 x i8> @fptoui_shuffle(<4 x float> %arg) {
 ; CHECK-LABEL: fptoui_shuffle:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
 ; CHECK-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %f = fptoui <4 x float> %arg to <4 x i8>
   %s = shufflevector <4 x i8> %f, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %ss = shufflevector <16 x i8> %s, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 1, i32 21, i32 22, i32 23, i32 2, i32 25, i32 26, i32 27, i32 3, i32 29, i32 30, i32 31>
   ret <16 x i8> %ss
 }

llvm/test/CodeGen/X86/i386-tlscall-fastregalloc.ll

 ; Get c.
 ; C is spilled because of the scheduling of the instructions,
 ; but a smarter regalloc wouldn't have spilled it.
 ; CHECK: movl L_c{{[^,]*}}, [[C_ADDR:%[a-z]+]]
 ; CHECK-NEXT: movl [[C_ADDR]], [[C_SPILLED:[0-8]+\(%esp\)]]
 ; Get p.
 ; CHECK-NEXT: movl _p@{{[0-9a-zA-Z]+}}, [[P_ADDR:%[a-z]+]]
 ; CHECK-NEXT: calll *([[P_ADDR]])
-; At this point eax contiains the address of p.
+; At this point eax contains the address of p.
 ; Load c address.
 ; Make sure we do not clobber eax.
 ; CHECK-NEXT: movl [[C_SPILLED]], [[C_ADDR_RELOADED:%e[b-z]x+]]
 ; Store c address into p.
 ; CHECK-NEXT: movl [[C_ADDR_RELOADED]], (%eax)
 define void @f() #0 {
 entry:
   store ptr @c, ptr @p, align 4
   ret void
 }

llvm/test/CodeGen/X86/win64-funclet-preisel-intrinsics.ll

 ; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s
 
 ; WinEH requires funclet tokens on nounwind intrinsics if they can lower to
 ; regular function calls in the course of IR transformations.
 ;
 ; Test that the code generator will emit the function call and not consider it
-; an "implausible instruciton". In the past this silently truncated code on
+; an "implausible instruction". In the past this silently truncated code on
 ; exception paths and caused crashes at runtime.
 ;
 ; Reduced IR generated from ObjC++ source:
 ;
 ;     @class Ety;
 ;     void opaque(void);
 ;     void test_catch_with_objc_intrinsic(void) {
 ;       @try {

llvm/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 
 ;; In functions with 'no_caller_saved_registers' attribute, all registers should
 ;; be preserved except for registers used for passing/returning arguments.
 ;; In the following function registers %rdi, %rsi and %xmm0 are used to store
-;; arguments %a0, %a1 and %b0 accordingally. The value is returned in %rax.
+;; arguments %a0, %a1 and %b0 accordingly. The value is returned in %rax.
 ;; The above registers should not be preserved, however other registers
 ;; (that are modified by the function) should be preserved (%rdx and %xmm1).
 define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pushq %rdx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill

llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll

landing:
   ret void
 
 return:
   ret void
 }
 
 ; Check landing pad again.
 ; This time checks that we can shrink-wrap when the epilogue does not
-; span accross several blocks.
+; span across several blocks.
 ;
 ; CHECK-LABEL: with_nounwind_same_succ:
 ;
 ; Jump to throw_exception:
 ; CHECK: testb $1, %dil
 ; CHECK-NEXT: je [[RET_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue

llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

end:
   ret i32 %tmp.0
 }
 
 @b = internal unnamed_addr global i1 false
 @c = internal unnamed_addr global i8 0, align 1
 @a = common global i32 0, align 4
 
 ; Make sure the prologue does not clobber the EFLAGS when
-; it is live accross.
+; it is live across.
 ; PR25629.
 ; Note: The registers may change in the following patterns, but
 ; because they imply register hierarchy (e.g., eax, al) this is
 ; tricky to write robust patterns.
 define i32 @useLEAForPrologue(i32 %d, i32 %a, i8 %c) #3 {
 ; ENABLE-LABEL: useLEAForPrologue:
 ; ENABLE:       ## %bb.0: ## %entry
 ; ENABLE-NEXT:    pushq %rbx

llvm/test/DebugInfo/Generic/debug-info-enum.ll

 ; CHECK:         DW_TAG_enumeration_type
 ; CHECK-DW2-NOT:   DW_AT_type
 ; CHECK-DW4:       DW_AT_type{{.*}}"int"
 ; CHECK-NOT:       DW_AT_enum_class
 ; CHECK:           DW_AT_name      ("E8")
 
 ; Test enumeration without a fixed underlying type, but with the DIFlagEnumClass
 ; set. The DW_AT_enum_class attribute should be absent. This behaviour is
-; intented to keep compatibilty with existing DWARF consumers, which may imply
+; intented to keep compatibility with existing DWARF consumers, which may imply
 ; the type is present whenever DW_AT_enum_class is set.
 !63 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "E9", file: !3, line: 63, size: 32, flags: DIFlagEnumClass,  elements: !64, identifier: "_ZTS2E9")
 !64 = !{!65, !66}
 !65 = !DIEnumerator(name: "A9", value: -128)
 !66 = !DIEnumerator(name: "B9", value: 127)
 ; CHECK:     DW_TAG_enumeration_type
 ; CHECK-NOT:   DW_AT_type
 ; CHECK-NOT:   DW_AT_enum_class

llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir

 --- | 
   ; RUN: llc -run-pass=machinelicm -o - %s | FileCheck %s
   ; Line numbers should not be retained when loop invariant instructions are hoisted.
-  ; Doing so causes poor stepping bevavior.
+  ; Doing so causes poor stepping behavior.
   ;
   ; Created from:
   ; int x;
   ; void Process(const unsigned int *p)
   ; {
   ;    while (1)
   ;      x = *p++;
   ; }

llvm/test/DebugInfo/X86/dbg-value-funcarg3.ll

 ; CHECK-LABEL: name:            fn1
 ; CHECK: DBG_VALUE $rdi, $noreg, ![[T1]], !DIExpression(),
 ; CHECK-NEXT: %0:gr64 = COPY $rdi
 ; CHECK-NEXT: DBG_VALUE %0, $noreg, ![[T1]], !DIExpression(),
 ; CHECK-NEXT: %1:gr32 = COPY %0.sub_32bit
 ; CHECK-NEXT: COPY
 ; CHECK-NEXT: RET
 ;
-;; For instr-ref, no copies should be considered. Because argumenst are
+;; For instr-ref, no copies should be considered. Because arguments are
 ;; Special, we don't label them in the same way, and currently emit a
 ;; DBG_VALUE for the physreg.
 ; INSTRREF-LABEL: name:            fn1
 ; INSTRREF: DBG_VALUE $rdi, $noreg, ![[T1]], !DIExpression(),
 ; INSTRREF-NEXT: %0:gr64 = COPY $rdi
 ; INSTRREF-NEXT: %1:gr32 = COPY %0.sub_32bit
 ; INSTRREF-NEXT: COPY
 ; INSTRREF-NEXT: RET

llvm/test/DebugInfo/X86/dimodule-external-fortran.ll

 ; This test verifies that the debug info for an external Fortran module
 ; is correctly generated.
 ;
 ; To generate the test source, compile the following two files in order in
 ; the same directory (as the second compilation uses the .mod from the first):
 ; external_module.f90 (to compile: <fortran compiler> -g -c external_module.f90)
 ;   module external_module
 ;     real :: dummy
 ;   end module external_module
 ;
-; em.f90 (to compile: <fortran compierl> -g -llvm-emit -c -S em.f90)
+; em.f90 (to compile: <fortran compiler> -g -llvm-emit -c -S em.f90)
 ;   program use_external_module
 ;   use external_module
 ;   implicit none
 ;
 ;     real :: x
 ;     x = 2.0 + dummy
 ;
 ;   end program use_external_module

llvm/test/DebugInfo/macro_link.ll

 ; RUN: llvm-link %s %s -S -o -| FileCheck %s
 
-; This test checks that DIMacro and DIMacroFile comaprison works correctly.
+; This test checks that DIMacro and DIMacroFile comparison works correctly.
 
 ; CHECK: !llvm.dbg.cu = !{[[CU1:![0-9]*]], [[CU2:![0-9]*]]}
 
 ; CHECK: [[CU1]] = distinct !DICompileUnit
 ; CHECK-SAME: macros: [[MS1:![0-9]*]]
 ; CHECK: [[F1:![0-9]*]] = !DIFile(filename: "t.c"
 ; CHECK: [[MS1]] = !{[[MF1:![0-9]*]]}
 ; CHECK: [[MF1]] = !DIMacroFile(

llvm/test/Instrumentation/SanitizerCoverage/gep-tracing.ll

entry:
   ret void
 }
 
 ; CHECK-LABEL: define void @gep_2([1000 x i32]* nocapture %a, i32 %i, i32 %j)
 ; CHECK: call void @__sanitizer_cov_trace_gep(i64 %idxprom1)
 ; CHECK: call void @__sanitizer_cov_trace_gep(i64 %idxprom)
 ; CHECK: ret void
 
-; Just make sure we don't insturment this one and don't crash
+; Just make sure we don't instrument this one and don't crash
 define void @gep_3(<2 x i8*> %a, i32 %i, i32 %j) {
 entry:
   %0 = getelementptr i8, <2 x i8*> %a, <2 x i64> <i64 8, i64 8>
   ret void
 }
 

llvm/test/MC/AArch64/arm64-branch-encoding.s

 ; CHECK: encoding: [0xa0,0x00,0x1f,0xd6]
   blr x9
 ; CHECK: encoding: [0x20,0x01,0x3f,0xd6]
   bl  L1
 ; CHECK: bl L1   ; encoding: [A,A,A,0b100101AA]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_call26
 
 ;-----------------------------------------------------------------------------
-; Contitional branch instructions.
+; Conditional branch instructions.
 ;-----------------------------------------------------------------------------
 
   b     L1
 ; CHECK: b L1      ; encoding: [A,A,A,0b000101AA]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch26
   b.eq  L1
 ; CHECK: b.eq L1   ; encoding: [0bAAA00000,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19

llvm/test/MC/ARM/mul-v4.s

-@ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
+@ PR17647: MUL/MLA/SMLAL/UMLAL should be available to IAS for ARMv4 and higher
 
 @ RUN: llvm-mc < %s -triple armv4-unknown-unknown -show-encoding | FileCheck %s --check-prefix=ARMV4
 
 @ ARMV4: mul  r0, r1, r2              @ encoding: [0x91,0x02,0x00,0xe0]
 @ ARMV4: muls  r0, r1, r2              @ encoding: [0x91,0x02,0x10,0xe0]
 @ ARMV4: mulne  r0, r1, r2              @ encoding: [0x91,0x02,0x00,0x10]
 @ ARMV4: mulseq  r0, r1, r2              @ encoding: [0x91,0x02,0x10,0x00]
 mul r0, r1, r2

llvm/test/MC/AsmParser/directive_abort.s

 # RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t
 # RUN: FileCheck -input-file %t %s
 
-# CHECK: error: .abort 'please stop assembing'
+# CHECK: error: .abort 'please stop assembling'
 TEST0:
-  .abort       please stop assembing
+  .abort       please stop assembling

llvm/test/MC/ELF/section-sym.s

 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -S --symbols -r --expand-relocs - | FileCheck %s
 
 .section foo, "aG", @progbits, f1, comdat
 .section foo, "G", @progbits, f2, comdat
 .section bar
 .long foo
 
 // Test that the relocation points to the first section foo.
 
-// The first seciton foo has index 6
+// The first section foo has index 6
 // CHECK:      Section {
 // CHECK:        Index:   4
 // CHECK-NEXT:   Name:    foo
 // CHECK-NEXT:   Type:    SHT_PROGBITS (0x1)
 // CHECK-NEXT:   Flags [ (0x202)
 // CHECK-NEXT:     SHF_ALLOC (0x2)
 // CHECK-NEXT:     SHF_GROUP (0x200)
 // CHECK-NEXT:   ]

llvm/test/MC/ELF/section-unique-err4.s

 // RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
-// CHECK:  error: expected commma
+// CHECK:  error: expected comma
 
         .section  .text,"ax",@progbits,unique 1

llvm/test/MC/Hexagon/capitalizedEndloop.s

 # RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
 #
 
-# Verify that capitaizled endloops work
+# Verify that capitalized endloops work
 
   { R0 = mpyi(R0,R0) } : endloop0
   { R0 = mpyi(R0,R0) } : ENDLOOP0
   { R0 = mpyi(R0,R0) }:endloop0
 
   { R0 = mpyi(R0,R0) } : endloop1
   { R0 = mpyi(R0,R0) } : ENDLOOP1
   { R0 = mpyi(R0,R0) }:endloop1

llvm/test/MC/Mips/mt/module-directive.s

 # RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
 # RUN:   llvm-readobj -A - | FileCheck --check-prefix=CHECK-OBJ %s
 # RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=asm -o - | \
 # RUN:   FileCheck --check-prefix=CHECK-ASM %s
 
 # Test that the .module directive sets the MT flag in .MIPS.abiflags when
-# assembling to boject files.
+# assembling to object files.
 
 # Test that the .moodule directive is re-emitted when expanding assembly.
 
 # CHECK-OBJ: ASEs
 # CHECK-OBJ-NEXT: MT (0x40)
 
 # CHECK-ASM:  .module mt
 .module mt
 nop

llvm/test/MC/X86/align-via-relaxation.s

# NOPAD-NEXT:    20: cc              int3
   jmp foo
   jmp foo
   jmp foo
   .p2align 5
   int3
 foo:
   ret
 
-  # Check that we're not shifting aroudn the offsets of labels - doing
+  # Check that we're not shifting around the offsets of labels - doing
   # that would require a further round of relaxation
   # CHECK: <bar>:
   # CHECK: 22: eb fe                          jmp 0x22 <bar>
   # CHECK: 24: 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:(%rax,%rax)
   # CHECK: 30: 0f 0b                          ud2
 
 bar:  
   jmp bar

llvm/test/Object/archive-update.test

 Either the shell supports the 'touch' command with a flag to manually set the
 mtime or we sleep for over two seconds so that the mtime is definitely
 observable.
 RUN: touch -m -t 200001010000 %t/tmp.older/evenlen || sleep 2.1
 
 RUN: echo newer > %t/tmp.newer/evenlen
 RUN: touch %t/tmp.newer/evenlen
 
-Create an achive with the newest file
+Create an archive with the newest file
 RUN: llvm-ar rU %t/tmp.a %t/tmp.newer/evenlen
 RUN: llvm-ar p %t/tmp.a | FileCheck --check-prefix=NEWER %s
 
 Check that without the 'u' option the member is replaced with an older file.
 RUN: llvm-ar rU %t/tmp.a %t/tmp.older/evenlen
 RUN: llvm-ar p %t/tmp.a | FileCheck --check-prefix=OLDER %s
 
 Check that with the 'u' option the member is replaced with a newer file.

llvm/test/ThinLTO/X86/guid_collision.ll

 ; Make sure LTO succeeds even if %t.bc contains a GlobalVariable F and
-; %t2.bc cointains a Function F with the same GUID.
+; %t2.bc contains a Function F with the same GUID.
 ;
 ; RUN: opt -module-summary %s -o %t.bc
 ; RUN: opt -module-summary %p/Inputs/guid_collision.ll -o %t2.bc
 ; RUN: llvm-lto2 run %t.bc %t2.bc -o %t.out -save-temps \
 ; RUN: -r=%t.bc,H,px -r=%t.bc,G, -r=%t2.bc,G,px
 ; RUN: llvm-dis -o - %t.out.1.3.import.bc | FileCheck %s
 
 ; RUN: llvm-lto2 run %t.bc %t2.bc -o %t.out -thinlto-distributed-indexes \

llvm/test/Transforms/ArgumentPromotion/profile.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes
 ; RUN: opt -passes=argpromotion,mem2reg -S < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
-; Checks if !prof metadata is corret in deadargelim.
+; Checks if !prof metadata is correct in deadargelim.
 
 define void @caller() #0 {
 ; CHECK-LABEL: define {{[^@]+}}@caller() {
 ; CHECK-NEXT:    call void @promote_i32_ptr(i32 42), !prof [[PROF0:![0-9]+]]
 ; CHECK-NEXT:    ret void
 ;
   %x = alloca i32
   store i32 42, i32* %x

llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals
 ; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM
 ; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM
 ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM
 ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
-; Checks if !prof metadata is corret in deadargelim.
+; Checks if !prof metadata is correct in deadargelim.
 
 define void @caller() #0 {
 ; IS________OPM-LABEL: define {{[^@]+}}@caller() {
 ; IS________OPM-NEXT:    [[X:%.*]] = alloca i32, align 4
 ; IS________OPM-NEXT:    store i32 42, i32* [[X]], align 4
 ; IS________OPM-NEXT:    call void @promote_i32_ptr(i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[X]]), !prof [[PROF0:![0-9]+]]
 ; IS________OPM-NEXT:    ret void
 ;

llvm/test/Transforms/Attributor/dereferenceable-1.ll

 ; CHECK-NEXT:    store i32 1, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    ret void
 ;
   store i32 1, i32* %0
   ret void
 }
 
 ; TEST 8
-; Use Constant range in deereferenceable
+; Use Constant range in dereferenceable
 ; void g(int *p, long long int *range){
 ;   int r = *range ; // [10, 99]
 ;   fill_range(p, *range);
 ; }
 
 ; FIXME: %ptr should be dereferenceable(31)
 define void @test8(i8* %ptr) #0 {
 ; IS________OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind writeonly

llvm/test/Transforms/Attributor/liveness.ll

continue:
   %p = phi i32 [ %call, %cond.true ], [ %call1, %cond.false ]
   ret i32 %p
 
 cleanup:
   %res = landingpad { i8*, i32 } catch i8* null
   ret i32 0
 }
 
-; TEST 6: Undefined behvior, taken from LangRef.
+; TEST 6: Undefined behavior, taken from LangRef.
 ; FIXME: Should be able to detect undefined behavior.
 
 define void @ub(i32* %0) {
 ; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@ub
 ; NOT_CGSCC_NPM-SAME: (i32* nocapture nofree writeonly [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] {
 ; NOT_CGSCC_NPM-NEXT:    [[POISON:%.*]] = sub nuw i32 0, 1
 ; NOT_CGSCC_NPM-NEXT:    [[STILL_POISON:%.*]] = and i32 [[POISON]], 0

llvm/test/Transforms/CodeGenPrepare/AArch64/widen_switch.ll

-;; AArch64 is arbitralily chosen as a 32/64-bit RISC representative to show the transform in all tests.
+;; AArch64 is arbitrarily chosen as a 32/64-bit RISC representative to show the transform in all tests.
 
 ; RUN: opt < %s -codegenprepare -S -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=ARM64
 
 ; AArch64 widens to 32-bit.
 
 define i32 @widen_switch_i16(i32 %a)  {
 entry:
   %trunc = trunc i32 %a to i16

llvm/test/Transforms/DeadArgElim/aggregates.ll

 }
 
 define i32 @test_ret_applies_to_all() {
   %val = call {i32, i32} @ret_applies_to_all({i32, i32} {i32 42, i32 43})
   %ret = extractvalue {i32, i32} %val, 1
   ret i32 %ret
 }
 
-; Case 6: When considering @mid, the return instruciton has sub-value 0
+; Case 6: When considering @mid, the return instruction has sub-value 0
 ; unconditionally live, but 1 only conditionally live. Since at that level we're
 ; applying the results to the whole of %res, this means %res is live and cannot
 ; be reduced. There is scope for further optimisation here (though not visible
 ; in this test-case).
 
 ; CHECK-LABEL: define internal { i8*, i32 } @inner()
 
 define internal {i8*, i32} @mid() {

llvm/test/Transforms/DeadArgElim/call_profile.ll

 ; RUN: opt -passes=deadargelim -S < %s | FileCheck %s
 
-; Checks if !prof metadata is corret in deadargelim.
+; Checks if !prof metadata is correct in deadargelim.
 
 define void @caller() #0 {
 ; CHECK: call void @test_vararg(), !prof ![[PROF:[0-9]]]
 ; CHECK: call void @test(), !prof ![[PROF]]
   call void (i32, ...) @test_vararg(i32 1), !prof !0
   call void @test(i32 1), !prof !0
   ret void
 }

llvm/test/Transforms/EarlyCSE/fence.ll

 ; CHECK: ret
   %a = load i32, ptr %addr.i, align 4
   fence acquire
   %a2 = load i32, ptr %addr.i, align 4
   %res = sub i32 %a, %a2
   ret i32 %res
 }
 
-; We can not dead store eliminate accross the fence.  We could in 
+; We can not dead store eliminate across the fence.  We could in 
 ; principal reorder the second store above the fence and then DSE either
 ; store, but this is beyond the simple last-store DSE which EarlyCSE
 ; implements.
 define void @test4(ptr %addr.i) {
 ; CHECK-LABEL: @test4
 ; CHECK: store
 ; CHECK: fence
 ; CHECK: store

llvm/test/Transforms/EarlyCSE/invariant.start.ll

;
   %v1 = load i32, ptr %p
   call void @clobber()
   %v2 = load i32, ptr %p
   call void @llvm.invariant.end.p0(ptr %scope, i64 4, ptr %p)
   %sub = sub i32 %v1, %v2
   ret i32 %sub
 }
 
-; Invariant load defact starts an invariant.start scope of the appropriate size
+; Invariant load defacto starts an invariant.start scope of the appropriate size
 define i32 @test_invariant_load_scope(ptr %p) {
 ; NO_ASSUME-LABEL: define {{[^@]+}}@test_invariant_load_scope
 ; NO_ASSUME-SAME: (ptr [[P:%.*]])
 ; NO_ASSUME-NEXT:    [[V1:%.*]] = load i32, ptr [[P]], align 4, !invariant.load !4
 ; NO_ASSUME-NEXT:    call void @clobber()
 ; NO_ASSUME-NEXT:    ret i32 0
 ;
 ; USE_ASSUME-LABEL: define {{[^@]+}}@test_invariant_load_scope

llvm/test/Transforms/GlobalOpt/invariant.group.ll

enter:
   ret void
 }
 
 ; We can't step through launder.invariant.group here, because that would change
 ; this load in @usage_of_globals()
 ; %val = load i32, i32* %ptrVal, !invariant.group !0
 ; into
 ; %val = load i32, i32* @tmp3, !invariant.group !0
-; and then we could assume that %val and %val2 to be the same, which coud be
+; and then we could assume that %val and %val2 to be the same, which could be
 ; false, because @changeTmp3ValAndCallBarrierInside() may change the value
 ; of @tmp3.
 define void @_not_optimizable() {
 enter:
   store i32 13, i32* @tmp3, !invariant.group !0
 
   %0 = bitcast i32* @tmp3 to i8*
   %barr = call i8* @llvm.launder.invariant.group(i8* %0)

llvm/test/Transforms/GuardWidening/posion.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -guard-widening -dce < %s | FileCheck %s
 
 ; FIXME: All the tests below must be fixed.
 
 declare void @llvm.experimental.guard(i1,...)
 
 ; This tests shows the incorrect behavior of guard widening in terms of
 ; interaction with poison values.
 
 ; Let x incoming parameter is used for rane checks.
-; Test generates 5 checks. One of them (c2) is used to get the corretness
+; Test generates 5 checks. One of them (c2) is used to get the correctness
 ; of nuw/nsw flags for x3 and x5. Others are used in guards and represent
 ; the checks x + 10 u< L, x + 15 u< L, x + 20 u< L and x + 3 u< L.
 ; The first two checks are in the first basic block and guard widening
 ; considers them as profitable to combine.
 ; When c4 and c3 are considered, number of check becomes more than two
 ; and combineRangeCheck consider them as profitable even if they are in
 ; different basic blocks.
-; Accoding to algorithm of combineRangeCheck it detects that c3 and c4
+; According to algorithm of combineRangeCheck it detects that c3 and c4
 ; are enough to cover c1 and c5, so it ends up with guard of c3 && c4
 ; while both of them are poison at entry. This is a bug.
 
 define void @combine_range_checks(i32 %x) {
 ; CHECK-LABEL: @combine_range_checks(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X2:%.*]] = add i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[C2:%.*]] = icmp ult i32 [[X2]], 200

llvm/test/Transforms/IndVarSimplify/lftr-dead-ivs.ll

 ; Provide legal integer types.
 target datalayout = "n8:16:32:64"
 
 @data = common global [240 x i8] zeroinitializer, align 16
 
 ;; In this example, the pointer IV is dynamicaly dead.  As such, the fact that
 ;; inbounds produces poison *does not* trigger UB in the original loop.  As
 ;; such, the pointer IV can be poison and adding a new use of the pointer
-;; IV which dependends on that poison computation in a manner which might
+;; IV which depends on that poison computation in a manner which might
 ;; trigger UB would be incorrect.
 ;; FIXME: This currently shows a miscompile!
 define void @neg_dynamically_dead_inbounds(i1 %always_false) #0 {
 ; CHECK-LABEL: @neg_dynamically_dead_inbounds(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[I_0:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[CONT:%.*]] ]

llvm/test/Transforms/Inline/inline_call.ll

entry:
   ; CHECK: {{.*}} = {{.*}} call {{.*}} @ext
   ; CHECK-NOT: {{.*}} = {{.*}} call {{.*}} @third
   ; CHECK-NOT: {{.*}} = {{.*}} call {{.*}} @second
   ; CHECK-NOT: {{.*}} = {{.*}} call {{.*}} @wrapper
   %q = alloca i8*, align 8
   store i8* bitcast (void ()* @third to i8*), i8** %q, align 8
   %tmp = call void (...)* @second(i8** %q)
   ; The call to 'wrapper' here is to ensure that its function attributes
-  ; i.e., returning its parameter and having no side effect, will be decuded
+  ; i.e., returning its parameter and having no side effect, will be deduced
   ; before the next round of inlining happens to 'top' to expose the bug.
   %call =  call void (...)* @wrapper(void (...)* %tmp) 
   ; The indirect call here is to confuse the alias analyzer so that
   ; an incomplete graph will be built during the first round of inlining.
   ; This allows the current function to be processed before the actual 
   ; callee, i.e., the function 'run', is processed. Once it's simplified to 
   ; a direct call, it also enables an additional round of inlining with all
   ; function attributes deduced. 

 entry:
   %f = alloca void (...)*, align 8
   %call = call void (...)* @gen()
   store void (...)* %call, void (...)** %f, align 8
   %tmp = load void (...)*, void (...)** %f, align 8
   call void @run(void (...)* %tmp)
   ret void
 }
 No newline at end of file

llvm/test/Transforms/InstCombine/memchr-10.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 ;
 ; Verify that the result of memchr calls with past-the-end pointers used
 ; in equality expressions don't cause trouble and either are folded when
 ; they might be valid or not when they're provably undefined.
 
 declare i8* @memchr(i8*, i32, i64)
 
 
 @a5 = constant [5 x i8] c"12345"
 
 
-; Fold memchr(a5 + 5, c, 1) == a5 + 5 to an arbitrary constrant.
+; Fold memchr(a5 + 5, c, 1) == a5 + 5 to an arbitrary constraint.
 ; The call is transformed to a5[5] == c by the memchr simplifier, with
 ; a5[5] being indeterminate.  The equality then is the folded with
 ; an undefined/arbitrary result.
 
 define i1 @call_memchr_ap5_c_1_eq_a(i32 %c, i64 %n) {
 ; CHECK-LABEL: @call_memchr_ap5_c_1_eq_a(
 ; CHECK-NEXT:    ret i1
 ;

llvm/test/Transforms/InstCombine/zext.ll

;
   %1 = icmp sgt i64 %a, %b
   %2 = zext i1 %1 to i8
   %3 = icmp slt i64 %a, %c
   %4 = zext i1 %3 to i8
   %5 = xor i8 %2, %4
   ret i8 %5
 }
 
-; Assert that zexts in logic(zext(icmp), zext(icmp)) are also folded accross
+; Assert that zexts in logic(zext(icmp), zext(icmp)) are also folded across
 ; nested logical operators.
 
 define i8 @fold_nested_logic_zext_icmp(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: @fold_nested_logic_zext_icmp(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i64 [[A]], [[C:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i64 [[A]], [[D:%.*]]

llvm/test/Transforms/LICM/hoist-phi.ll

 cond2.end:
   br label %end
 
 end:
   %phi2 = phi i32 [ 1, %cond1 ], [ 2, %cond1.else ], [ 3, %cond1.end ], [ 4, %cond2 ], [ 5, %cond2.else ], [ 6, %cond2.end ]
   br label %loop
 }
 
-; Check that we correctly handle the hoisting of %gep when theres a critical
+; Check that we correctly handle the hoisting of %gep when there's a critical
 ; edge that branches to the preheader.
 ; CHECK-LABEL: @crit_edge
 define void @crit_edge(i32* %ptr, i32 %idx, i1 %cond1, i1 %cond2) {
 ; CHECK-LABEL: entry:
 ; CHECK: %gep = getelementptr inbounds i32, i32* %ptr, i32 %idx
 ; CHECK: br label %preheader
 entry:
   br label %preheader

llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll

define amdgpu_kernel void @no_crash(i32 %arg) {
   store i32 0, i32 addrspace(3)* %tmp3, align 4
   store i32 0, i32 addrspace(3)* %tmp5, align 4
   store i32 0, i32 addrspace(3)* %tmp5, align 4
   store i32 0, i32 addrspace(3)* %tmp5, align 4
 
   ret void
 }
 
-; Check adjiacent memory locations are properly matched and the
+; Check adjacent memory locations are properly matched and the
 ; longest chain vectorized
 
 ; GCN-LABEL: @interleave_get_longest
 
 ; GFX7: load <2 x i32>
 ; GFX7: load i32
 ; GFX7: store <2 x i32> zeroinitializer
 ; GFX7: load i32

llvm/test/Transforms/LoopFusion/cannot_fuse.ll

 
 bb33.loopexit:                                    ; preds = %bb30
   br label %bb33
 
 bb33:                                             ; preds = %bb33.loopexit, %bb16, %bb34
   ret void
 }
 
-; Check that fusion detects the two canddates are not adjacent (the exit block
+; Check that fusion detects the two candidates are not adjacent (the exit block
 ; of the first candidate is not the preheader of the second candidate).
 
 ; CHECK: Performing Loop Fusion on function non_adjacent
 ; CHECK: Fusion Candidates:
 ; CHECK: *** Fusion Candidate Set ***
 ; CHECK-NEXT: [[LOOP1PREHEADER:bb[0-9]*]]
 ; CHECK-NEXT: [[LOOP2PREHEADER:bb[0-9]*]]
 ; CHECK-NEXT: ****************************

llvm/test/Transforms/LoopStrengthReduce/X86/lsr-insns-2.ll

 ; REGS:   %lsr.iv4 = phi
 ; REGS:   %lsr.iv2 = phi
 ; REGS:   %lsr.iv1 = phi
 ; REGS:   getelementptr i32, i32* %lsr.iv1, i64 1
 ; REGS:   getelementptr i32, i32* %lsr.iv2, i64 1
 ; REGS:   getelementptr i32, i32* %lsr.iv4, i64 1
 
 ; LLC checks that LSR prefers less instructions to less registers.
-; LSR should prefer complicated address to additonal add instructions.
+; LSR should prefer complicated address to additional add instructions.
 
 ; CHECK:      LBB0_2:
 ; CHECK-NEXT:   movl (%r{{.+}},
 ; CHECK-NEXT:   addl (%r{{.+}},
 ; CHECK-NEXT:   movl %e{{.+}}, (%r{{.+}},
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 

llvm/test/Transforms/LoopStrengthReduce/pr50765.ll

 ; RUN: opt -S -loop-reduce < %s | FileCheck %s
 ;
-;This test produces zero factor that becomes a denumerator and fails an assetion.
+;This test produces zero factor that becomes a denumerator and fails an assertion.
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @test() {
 ; CHECK-LABEL: test
 bb:
   %tmp = load i32, i32 addrspace(3)* undef, align 4

llvm/test/Transforms/LoopUnroll/full-unroll-heuristics.ll

 ; In this test we check how heuristics for complete unrolling work. We have
 ; three knobs:
 ;  1) -unroll-threshold
 ;  3) -unroll-percent-dynamic-cost-saved-threshold and
 ;  2) -unroll-dynamic-cost-savings-discount
 ;
 ; They control loop-unrolling according to the following rules:
-;  * If size of unrolled loop exceeds the absoulte threshold, we don't unroll
+;  * If size of unrolled loop exceeds the absolute threshold, we don't unroll
 ;    this loop under any circumstances.
 ;  * If size of unrolled loop is below the '-unroll-threshold', then we'll
 ;    consider this loop as a very small one, and completely unroll it.
 ;  * If a loop size is between these two tresholds, we only do complete unroll
 ;    it if estimated number of potentially optimized instructions is high (we
 ;    specify the minimal percent of such instructions).
 
 ; In this particular test-case, complete unrolling will allow later

llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -loop-unroll -unroll-force-peel-count=1 | FileCheck %s
 ; RUN: opt < %s -S -passes='loop-unroll<peeling;no-runtime>' -unroll-force-peel-count=1 | FileCheck %s
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-; Loop peeling must result in valid scope declartions
+; Loop peeling must result in valid scope declarations
 
 define internal fastcc void @test01(i8* %p0, i8* %p1, i8* %p2) unnamed_addr align 2 {
 ; CHECK-LABEL: @test01(
 ; CHECK-NEXT:  for.body47.lr.ph:
 ; CHECK-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata !0)
 ; CHECK-NEXT:    br label [[FOR_BODY47_PEEL_BEGIN:%.*]]
 ; CHECK:       for.body47.peel.begin:
 ; CHECK-NEXT:    br label [[FOR_BODY47_PEEL:%.*]]

llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll

 for.end:
   %.lcssa.lcssa = phi i32 [ %.lcssa, %for.latch ]
   %inc.lcssa.lcssa = phi i32 [ 7, %for.latch ]
   ret i32 0
 }
 
 
 ; Has a positive dependency between two stores. Still valid.
-; The negative dependecy is in unroll-and-jam-disabled.ll
+; The negative dependency is in unroll-and-jam-disabled.ll
 define void @test7(i32 %I, i32 %E, i32* noalias nocapture %A, i32* noalias nocapture readonly %B) #0 {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[E:%.*]], 0
 ; CHECK-NEXT:    [[CMP128:%.*]] = icmp ne i32 [[I:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP128]], [[CMP]]
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FOR_PREHEADER:%.*]], label [[FOR_END:%.*]]
 ; CHECK:       for.preheader:

llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll

 }
 
 ; The source code:
 ;
 ;void foo4(double *A, double *B, int *trigger) {
 ;
 ;  for (int i=0; i<10000; i += 16) {
 ;    if (trigger[i] < 100) {
-;          A[i] = B[i*2] + trigger[i]; << non-cosecutive access
+;          A[i] = B[i*2] + trigger[i]; << non-consecutive access
 ;    }
 ;  }
 ;}
 
 define void @foo4(double* nocapture %A, double* nocapture readonly %B, i32* nocapture readonly %trigger) local_unnamed_addr #0 {
 ; AVX-LABEL: @foo4(
 ; AVX-NEXT:  entry:
 ; AVX-NEXT:    br label [[FOR_BODY:%.*]]

llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll

for.body:
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 
 
-; Unconditioal accesses with gaps under Optsize scenario again, with unknown
+; Unconditional accesses with gaps under Optsize scenario again, with unknown
 ; trip-count this time, in order to check the behavior of folding-the-tail
 ; (folding the remainder loop into the main loop using masking) together with
 ; interleaved-groups. Folding-the-tail turns the accesses to conditional which
 ; requires proper masking. In addition we need to mask out the gaps (all
 ; because we are not allowed to use an epilog due to optsize).
 ; When enable-masked-interleaved-access is disabled, the interleave-groups will
 ; be invalidated during cost-model checks. So there we check for no epilogue
 ; and for scalarized conditional accesses.

llvm/test/Transforms/LoopVectorize/skip-iterations.ll

 ; RUN: opt < %s  -loop-vectorize -force-vector-width=4 -dce -instcombine -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 ; tests skipping iterations within a VF through break/continue/gotos.
 
 ; The main difficulty in vectorizing these loops in test1,test2 and test3 is
 ; safely speculating that the widened load of A[i] should not fault if the
 ; scalarized loop does not fault. For example, the
 ; original load in the scalar loop may not fault, but the last iteration of the
-; vectorized load can fault (if it crosses a page boudary for example).
+; vectorized load can fault (if it crosses a page boundary for example).
 ; This last vector iteration is where *one* of the
 ; scalar iterations lead to the early exit.
 
 ; int test(int *A, int Length) {
 ;   for (int i = 0; i < Length; i++) {
 ;     if (A[i] > 10.0) goto end;
 ;     A[i] = 0;
 ;   }

llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

 ; RUN: opt -loop-vectorize -force-vector-width=4 -enable-vplan-native-path -S %s | FileCheck %s
 
 ; Test that VPlan native path is able to widen select instruction in the
 ; innermost loop under different conditions when outer loop is marked to be
 ; vectorized. These conditions include following:
 ; * Inner and outer loop invariant select condition
 ; * Select condition depending on outer loop iteration variable.
-; * Select condidition depending on inner loop iteration variable.
-; * Select conditition depending on both outer and inner loop iteration
+; * Select condition depending on inner loop iteration variable.
+; * Select condition depending on both outer and inner loop iteration
 ;   variables.
 
 define void @loop_invariant_select(double* noalias nocapture %out, i1 %select, double %a, double %b) {
 ; CHECK-LABEL: @loop_invariant_select(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x double> poison, double [[A:%.*]], i32 0

llvm/test/Transforms/LowerTypeTests/cfi-direct-call.ll

 ; as it may be overriden at run time.
 ; CHECK-NEXT:   call void @internal_default_def()
 
 ; Internal function with hidden visibility defined outside the module
 ; generates a jump table entry and is renamed to *.cfi: route direct call
 ; to the actual function, not jump table
 ; CHECK-NEXT:   call void @internal_hidden_def.cfi()
 
-; dso_local function with defailt visibility can be short-circuited
+; dso_local function with default visibility can be short-circuited
 ; CHECK-NEXT:   call void @dsolocal_default_def.cfi()
 
 ; Local call - no action
 ; CHECK-NEXT:   call void @local_b
 
 ; CHECK-NEXT:   ret i8 1
 
 ; CHECK: declare hidden void @internal_hidden_def.cfi()
 ; CHECK: declare hidden void @external_decl.cfi_jt()

llvm/test/Transforms/MergeFunc/vector-GEP-crash.ll

 ; RUN: opt -mergefunc -disable-output < %s
-; This used to cause a crash when compairing the GEPs
+; This used to cause a crash when comparing the GEPs
 
 define void @foo(<2 x i64*>) {
   %tmp = getelementptr i64, <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
   ret void
 }
 
 define void @bar(<2 x i64*>) {
   %tmp = getelementptr i64, <2 x i64*> %0, <2 x i64> <i64 0, i64 0>
   ret void
 }

llvm/test/Transforms/Reassociate/xor_reassoc.ll

 ;
   %1 = ptrtoint i32* undef to i64
   %2 = xor i64 %1, ptrtoint (<{}>* @xor_bug1_data to i64)
   %3 = and i64 undef, %2
   ret void
 }
 
 ; The bug was that when the compiler optimize "(x | c1)" ^ "(x & c2)", it may
-; swap the two xor-subexpressions if they are not in canoninical order; however,
+; swap the two xor-subexpressions if they are not in canonical order; however,
 ; when optimizer swaps two sub-expressions, if forgot to swap the cached value
 ; of c1 and c2 accordingly, hence cause the problem.
 ;
 define i32 @xor_bug2(i32, i32, i32, i32) {
 ; CHECK-LABEL: @xor_bug2(
 ; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP0:%.*]], 123
 ; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[TMP1:%.*]], 3456789
 ; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], 4567890

llvm/test/Transforms/SROA/preserve-nonnull.ll

entry:
   %buf = alloca ptr
   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %buf, ptr align 8 %arg, i64 8, i1 false)
   %ret = load ptr, ptr %buf, align 8, !nonnull !0
   ret ptr %ret
 }
 
 ; Make sure we properly handle the !nonnull attribute when we convert
 ; a pointer load to an integer load.
-; FIXME: While this doesn't do anythnig actively harmful today, it really
+; FIXME: While this doesn't do anything actively harmful today, it really
 ; should propagate the !nonnull metadata to range metadata. The irony is, it
 ; *does* initially, but then we lose that !range metadata before we finish
 ; SROA.
 define ptr @propagate_nonnull_to_int() {
 ; CHECK-LABEL: define ptr @propagate_nonnull_to_int(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    %[[A:.*]] = alloca ptr
 ; CHECK-NEXT:    store ptr inttoptr (i64 42 to ptr), ptr %[[A]]

llvm/test/Transforms/SampleProfile/inline-mergeprof-dup.ll

 !10 = distinct !DILexicalBlock(scope: !6, file: !1, line: 10)
 !11 = !DILocation(line: 12, scope: !6)
 !12 = distinct !DISubprogram(name: "sum", scope: !1, file: !1, line: 3, type: !7, scopeLine: 3, virtualIndex: 6, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
 !13 = !DILocation(line: 4, scope: !12)
 !14 = !DILocation(line: 5, scope: !12)
 !15 = !DILocation(line: 6, scope: !12)
 
 
-;; Check the profile of funciton sum is only merged once though the original callsite is replicted.
+;; Check the profile of function sum is only merged once though the original callsite is replicted.
 ; CHECK: name: "sum"
 ; CHECK-NEXT: {!"function_entry_count", i64 46}
 ; CHECK: !{!"branch_weights", i32 11, i32 37}
 ; CHECK: !{!"branch_weights", i32 11, i32 1}

llvm/test/Transforms/SimplifyCFG/X86/remove-debug.ll

 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -hoist-common-insts=true | FileCheck %s
 
-; TODO: Track the acutal DebugLoc of the hoisted instruction when no-line
+; TODO: Track the actual DebugLoc of the hoisted instruction when no-line
 ; DebugLoc is supported (https://reviews.llvm.org/D24180)
 
 ; Checks if the debug info for hoisted "x = i" is removed and
 ; the debug info for hoisted "bar()" is set as line 0
 ; int x;
 ; void bar();
 ; void baz();
 ;

llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll

 b:
   call void @helper(i32 1) nounwind
   ret void
 bees:
   call void @helper(i32 2) nounwind
   ret void
 }
 
-; Test edge splitting when the default target has icmp and unconditinal
+; Test edge splitting when the default target has icmp and unconditional
 ; branch
 define i1 @test9(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    switch i32 [[X:%.*]], label [[BEES:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[A:%.*]]
 ; CHECK-NEXT:    i32 1, label [[END:%.*]]
 ; CHECK-NEXT:    i32 2, label [[END]]

llvm/test/Transforms/SimplifyCFG/switch_thread.ll

 A:              ; preds = %0
   call void @foo1( )
   ;; This switch is always statically determined.
   switch i32 %V, label %E [
   i32 4, label %C
   i32 17, label %C
   i32 42, label %D
   ]
-;; unreacahble.
+;; unreachable.
 C:              ; preds = %A, %A
   call void @DEAD( )
   ret void
 T:              ; preds = %0
   call void @foo1( )
   call void @foo1( )
   ret void
 D:              ; preds = %A, %0
   call void @foo1( )
   ret void
 E:              ; preds = %A, %0
   ret void
 
 }
 

llvm/test/tools/llvm-objcopy/COFF/basic-copy.test

 Test plain passthrough copying with llvm-objcopy, by checking that obj2yaml
 produces identical output for both input and output object files/executables.
 (Intentionally not comparing to the original input yaml, in case there are
 superficial differences like line endings.) In order to have a check of the
 whole file and not just individual fields with FileCheck, checking with
 obj2yaml+cmp instead of llvm-readobj+cmp, as llvm-readobj also prints file
 details that can differ between otherwise equal files (such as file offsets).
 
 Actual copied object files/executables can differ in, among others, the
 following aspects:
 - The padding of executable sections (lld uses 0xcc, which is int3 on x86)
 - The actual layout of the string table (it can be filled linearly,
-  strings can be dedupliated, the table can be optimized by sharing tails
+  strings can be deduplicated, the table can be optimized by sharing tails
   of longer strings; different parts in llvm do each of these three options)
 - The size indication for an empty/missing string table can either be 4
   or left out altogether
 - Alignment of section data
 - Checksums
 
 RUN: yaml2obj %p/Inputs/i386-obj.yaml -o %t.i386.o
 RUN: llvm-objcopy %t.i386.o %t.i386-copy.o

llvm/test/tools/llvm-objcopy/COFF/remove-section.test

 # SYMBOLS-PRE-NEXT: AUX scnlen {{.*}} assoc 3 comdat 2
 # SYMBOLS-PRE-NEXT: {{.*}}(sec 3){{.*}} foo
 # SYMBOLS-PRE-NEXT: {{.*}}(sec 1){{.*}} main
 # SYMBOLS-PRE-EMPTY:
 #
 #
 # Removing the .bss section removes one symbol and its aux symbol,
 # and updates the section indices in symbols pointing to later
-# symbols, including the aux section defintitions.
+# symbols, including the aux section definitions.
 #
 # Testing that the absolute symbol @feat.00 survives the section number
 # mangling.
 #
 # SECTIONS-REMOVE-BSS: Sections:
 # SECTIONS-REMOVE-BSS-NEXT: Idx Name
 # SECTIONS-REMOVE-BSS-NEXT: 0 .text
 # SECTIONS-REMOVE-BSS-NEXT: 1 .comdat

llvm/test/tools/llvm-readobj/ELF/call-graph-profile.test

Relocations:
       - Offset: 0x10
         Symbol: 0x4 ## This index goes past the end of the symbol table.
         Type:   R_X86_64_NONE
   - Name:    .strtab
     Type:    SHT_STRTAB
     Content: "0041004200" ## '\0', 'A', '\0', 'B', '\0'
 Symbols:
   - StName: 1    ## 'A'
-  - StName: 0xFF ## An arbitrary currupted index in the string table.
+  - StName: 0xFF ## An arbitrary corrupted index in the string table.
   - StName: 3    ## 'B'
 
 ## Check we report a warning when a relocation section is not present.
 # RUN: yaml2obj %s --docnum=3 -o %t4.o
 # RUN: llvm-readobj %t4.o --cg-profile 2>&1 | FileCheck %s -DFILE=%t4.o --check-prefix=LLVM-NO-RELOC
 # RUN: llvm-readobj %t4.o --elf-cg-profile 2>&1 | FileCheck %s -DFILE=%t4.o --check-prefix=LLVM-NO-RELOC
 
 # LLVM-NO-RELOC:      warning: '[[FILE]]': relocation section for a call graph section doesn't exist

llvm/test/tools/llvm-readobj/ELF/dynamic-reloc.test

 # LLVM-NONE-NOT:  {{.}}
 
 --- !ELF
 FileHeader:
   Class: ELFCLASS64
   Data:  ELFDATA2LSB
   Type:  ET_DYN
 
-## Check that we dump all possbile dynamic relocation sections.
+## Check that we dump all possible dynamic relocation sections.
 # RUN: yaml2obj --docnum=2 %s -o %t2.1
 # RUN: llvm-readobj --dyn-relocations %t2.1 2>&1 | \
 # RUN:   FileCheck %s --implicit-check-not=warning: --check-prefix=LLVM-RELOCS
 # RUN: llvm-readelf --dyn-relocations %t2.1 2>&1 | \
 # RUN:   FileCheck %s --implicit-check-not=warning: --strict-whitespace \
 # RUN:     --match-full-lines --check-prefixes=GNU-RELOCS,GNU-PLTREL
 
 ## 7 == DT_RELA.

llvm/test/tools/llvm-readobj/ELF/mips-options-sec.test

ContentArray: [ [[KIND=0x1]],           ## Kind. ODK_REGINFO == 1.
                     0x0, 0x0, 0x0, 0x0,     ## Kind-specific information.
                     0xA, 0xB, 0xC, 0xD,     ## ODK_REGINFO: bit-mask of used general registers.
                     0x11, 0x22, 0x33, 0x44, ## ODK_REGINFO: unused padding field.
                     0x55, 0x66, 0x77, 0x88, ## ODK_REGINFO: bit-mask of used co-processor registers (0).
                     0x99, 0xAA, 0xBB, 0xCC, ## ODK_REGINFO: bit-mask of used co-processor registers (1).
                     0xDD, 0xEE, 0xFF, 0x1E, ## ODK_REGINFO: bit-mask of used co-processor registers (2).
                     0x2E, 0x3E, 0x4E, 0x5E, ## ODK_REGINFO: bit-mask of used co-processor registers (3).
                     0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, ## ODK_REGINFO: gp register value.
-## A descriptor for one more arbirtary supported option.
+## A descriptor for one more arbitrary supported option.
                     0x1, 0x28, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
                     0x0, 0x0,  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
                     0x0, 0x0,  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
                     0x0, 0x0,  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
   - Type:   SHT_PROGBITS
     ShName: [[NAME=<none>]]
 
 ## Check we report a warning when we are unable to find the .MIPS.options section due to an error.

llvm/test/tools/obj2yaml/ELF/offset.yaml

 ## Check how the "Offset" field is dumped by obj2yaml.
-## For each section we calulate the expected offset.
+## For each section we calculate the expected offset.
 ## When it does not match the actual offset, we emit the "Offset" key.
 
 # RUN: yaml2obj %s -o %t1.o
 # RUN: obj2yaml %t1.o | FileCheck %s --check-prefix=BASIC
 
 #   BASIC:      --- !ELF
 #   BASIC-NEXT: FileHeader:
 #   BASIC-NEXT:   Class: ELFCLASS64

llvm/tools/llvm-ar/llvm-ar.cpp

 }
 
 static int ar_main(int argc, char **argv) {
   SmallVector<const char *, 0> Argv(argv + 1, argv + argc);
   StringSaver Saver(Alloc);
 
   cl::ExpandResponseFiles(Saver, getRspQuoting(makeArrayRef(argv, argc)), Argv);
 
-  // Get BitMode from enviorment variable "OBJECT_MODE" for AIX OS, if
+  // Get BitMode from environment variable "OBJECT_MODE" for AIX OS, if
   // specified.
   if (object::Archive::getDefaultKindForHost() == object::Archive::K_AIXBIG) {
     BitMode = getBitMode(getenv("OBJECT_MODE"));
     if (BitMode == BitModeTy::Unknown)
       BitMode = BitModeTy::Bit32;
   }
 
   for (ArrayRef<const char *>::iterator ArgIt = Argv.begin();

llvm/tools/llvm-cov/CoverageReport.cpp

 /// Prints a horizontal divider long enough to cover the given column
 /// widths.
 void renderDivider(ArrayRef<size_t> ColumnWidths, raw_ostream &OS) {
   size_t Length = std::accumulate(ColumnWidths.begin(), ColumnWidths.end(), 0);
   for (size_t I = 0; I < Length; ++I)
     OS << '-';
 }
 
-/// Return the color which correponds to the coverage percentage of a
+/// Return the color which corresponds to the coverage percentage of a
 /// certain metric.
 template <typename T>
 raw_ostream::Colors determineCoveragePercentageColor(const T &Info) {
   if (Info.isFullyCovered())
     return raw_ostream::GREEN;
   return Info.getPercentCovered() >= 80.0 ? raw_ostream::YELLOW
                                           : raw_ostream::RED;
 }

llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp

Error linkDebugInfo(object::ObjectFile &File, const Options &Options,
   DebugInfoLinker.setErrorHandler(ReportErr);
   DebugInfoLinker.setWarningHandler(ReportWarn);
   DebugInfoLinker.setNumThreads(Options.NumThreads);
   DebugInfoLinker.setNoODR(!Options.DoODRDeduplication);
   DebugInfoLinker.setVerbosity(Options.Verbose);
   DebugInfoLinker.setUpdate(!Options.DoGarbageCollection);
 
   std::vector<std::unique_ptr<DWARFFile>> ObjectsForLinking(1);
-  std::vector<std::unique_ptr<AddressesMap>> AddresssMapForLinking(1);
+  std::vector<std::unique_ptr<AddressesMap>> AddressMapForLinking(1);
   std::vector<std::string> EmptyWarnings;
 
   std::unique_ptr<DWARFContext> Context = DWARFContext::create(File);
 
   // Unknown debug sections would be removed. Display warning
   // for such sections.
   for (SectionName Sec : Context->getDWARFObj().getSectionNames()) {
     if (isDebugSection(Sec.Name) && !knownByDWARFUtil(Sec.Name))
       warning(
           formatv("'{0}' is not currently supported: section will be skipped",
                   Sec.Name),
           Options.InputFileName);
   }
 
   // Add object files to the DWARFLinker.
-  AddresssMapForLinking[0] =
+  AddressMapForLinking[0] =
       std::make_unique<ObjFileAddressMap>(*Context, Options, File);
 
-  ObjectsForLinking[0] = std::make_unique<DWARFFile>(
-      File.getFileName(), &*Context, AddresssMapForLinking[0].get(),
-      EmptyWarnings);
+  ObjectsForLinking[0] =
+      std::make_unique<DWARFFile>(File.getFileName(), &*Context,
+                                  AddressMapForLinking[0].get(), EmptyWarnings);
 
   for (size_t I = 0; I < ObjectsForLinking.size(); I++)
     DebugInfoLinker.addObjectFile(*ObjectsForLinking[I]);
 
   // Link debug info.
   if (Error Err = DebugInfoLinker.link())
     return Err;
 
   OutStreamer.finish();
   return Error::success();
 }
 
 } // end of namespace dwarfutil
 } // end of namespace llvm

llvm/tools/llvm-exegesis/lib/Analysis.cpp

if (RSC.SCDesc->isValid()) {
     OS << "<td>" << RSC.SCDesc->NumMicroOps << "</td>";
     // Latencies.
     OS << "<td><ul>";
     for (int I = 0, E = RSC.SCDesc->NumWriteLatencyEntries; I < E; ++I) {
       const auto *const Entry =
           SubtargetInfo_->getWriteLatencyEntry(RSC.SCDesc, I);
       OS << "<li>" << Entry->Cycles;
       if (RSC.SCDesc->NumWriteLatencyEntries > 1) {
-        // Dismabiguate if more than 1 latency.
+        // Disambiguate if more than 1 latency.
         OS << " (WriteResourceID " << Entry->WriteResourceID << ")";
       }
       OS << "</li>";
     }
     OS << "</ul></td>";
     // inverse throughput.
     OS << "<td>";
     writeMeasurementValue<kEscapeHtml>(

llvm/tools/llvm-objdump/MachODump.cpp

static const char *get_symbol_32(uint32_t sect_offset, SectionRef S,
   uint64_t n_value64;
   return get_symbol_64(sect_offset, S, info, n_value64, ReferenceValue);
 }
 
 namespace {
 
 // These are structs in the Objective-C meta data and read to produce the
 // comments for disassembly.  While these are part of the ABI they are no
-// public defintions.  So the are here not in include/llvm/BinaryFormat/MachO.h
+// public definitions.  So the are here not in include/llvm/BinaryFormat/MachO.h
 // .
 
 // The cfstring object in a 64-bit Mach-O file.
 struct cfstring64_t {
   uint64_t isa;        // class64_t * (64-bit pointer)
   uint64_t flags;      // flag bits
   uint64_t characters; // char * (64-bit pointer)
   uint64_t length;     // number of non-NULL characters in above

llvm/tools/llvm-objdump/OtoolOpts.td

 include "llvm/Option/OptParser.td"
 
 def help : Flag<["--"], "help">, HelpText<"print help">;
 def help_hidden : Flag<["--"], "help-hidden">,
   HelpText<"print help for hidden flags">;
 
 def arch : Separate<["-"], "arch">,
   HelpText<"select slice of universal Mach-O file">;
 def C : Flag<["-"], "C">, HelpText<"print linker optimization hints">;
 def d : Flag<["-"], "d">, HelpText<"print data section">;
 def D : Flag<["-"], "D">, HelpText<"print shared library id">;
 def f : Flag<["-"], "f">, HelpText<"print universal headers">;
 def G : Flag<["-"], "G">, HelpText<"print data-in-code table">;
 def h : Flag<["-"], "h">, HelpText<"print mach header">;
 def I : Flag<["-"], "I">, HelpText<"print indirect symbol table">;
 def j : Flag<["-"], "j">, HelpText<"print opcode bytes">;
-def l : Flag<["-"], "l">, HelpText<"print load commnads">;
+def l : Flag<["-"], "l">, HelpText<"print load commands">;
 def L : Flag<["-"], "L">, HelpText<"print used shared libraries">;
 def mcpu_EQ : Joined<["-"], "mcpu=">, HelpText<"select cpu for disassembly">;
 def o : Flag<["-"], "o">, HelpText<"print Objective-C segment">;
 def p : Separate<["-"], "p">,
   MetaVarName<"<function name>">,
   HelpText<"start disassembly at <function name>">;
 def P : Flag<["-"], "P">, HelpText<"print __TEXT,__info_plist section as strings">;
 def : Flag<["-"], "q">, Flags<[HelpHidden]>,

llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp

cl::opt<bool> DumpIdExtras("id-extras",
                            cl::cat(TypeOptions), cl::sub(DumpSubcommand));
 cl::list<uint32_t> DumpIdIndex(
     "id-index", cl::CommaSeparated,
     cl::desc("only dump ids with the specified hexadecimal type index"),
     cl::cat(TypeOptions), cl::sub(DumpSubcommand));
 
 cl::opt<bool> DumpTypeDependents(
     "dependents",
-    cl::desc("In conjunection with -type-index and -id-index, dumps the entire "
+    cl::desc("In conjunction with -type-index and -id-index, dumps the entire "
              "dependency graph for the specified index instead of "
              "just the single record with the specified index"),
     cl::cat(TypeOptions), cl::sub(DumpSubcommand));
 
 // SYMBOL OPTIONS
 cl::opt<bool> DumpGlobals("globals", cl::desc("dump Globals symbol records"),
                           cl::cat(SymbolOptions), cl::sub(DumpSubcommand));
 cl::opt<bool> DumpGlobalExtras("global-extras", cl::desc("dump Globals hashes"),

llvm/tools/llvm-profgen/PerfReader.cpp

emitWarningSummary(
       UnmatchedRange, TotalRangeNum,
       "of samples are from ranges that do not belong to any functions.");
   emitWarningSummary(
       RangeCrossFunc, TotalRangeNum,
       "of samples are from ranges that do cross function boundaries.");
   emitWarningSummary(
       BogusRange, TotalRangeNum,
       "of samples are from ranges that have range start after or too far from "
-      "range end acrossing the unconditinal jmp.");
+      "range end across the unconditional jmp.");
 }
 
 void PerfScriptReader::parsePerfTraces() {
   // Parse perf traces and do aggregation.
   parseAndAggregateTrace();
 
   emitWarningSummary(NumLeafExternalFrame, NumTotalSample,
                      "of samples have leaf external frame in call stack.");

llvm/tools/llvm-profgen/ProfiledBinary.h

struct PrologEpilogTracker {
   }
 };
 
 // Track function byte size under different context (outlined version as well as
 // various inlined versions). It also provides query support to get function
 // size with the best matching context, which is used to help pre-inliner use
 // accurate post-optimization size to make decisions.
 // TODO: If an inlinee is completely optimized away, ideally we should have zero
-// for its context size, currently we would misss such context since it doesn't
+// for its context size, currently we would miss such context since it doesn't
 // have instructions. To fix this, we need to mark all inlinee with entry probe
 // but without instructions as having zero size.
 class BinarySizeContextTracker {
 public:
   // Add instruction with given size to a context
   void addInstructionForContext(const SampleContextFrameVector &Context,
                                 uint32_t InstrSize);
 

llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp

static void printHelp(StringRef ToolName, const SymbolizerOptTable &Tbl,
   OS << "\nPass @FILE as argument to read options from FILE.\n";
 }
 
 static opt::InputArgList parseOptions(int Argc, char *Argv[], bool IsAddr2Line,
                                       StringSaver &Saver,
                                       SymbolizerOptTable &Tbl) {
   StringRef ToolName = IsAddr2Line ? "llvm-addr2line" : "llvm-symbolizer";
   // The environment variable specifies initial options which can be overridden
-  // by commnad line options.
+  // by command line options.
   Tbl.setInitialOptionsFromEnvironment(IsAddr2Line ? "LLVM_ADDR2LINE_OPTS"
                                                    : "LLVM_SYMBOLIZER_OPTS");
   bool HasError = false;
   opt::InputArgList Args =
       Tbl.parseArgs(Argc, Argv, OPT_UNKNOWN, Saver, [&](StringRef Msg) {
         errs() << ("error: " + Msg + "\n");
         HasError = true;
       });

llvm/tools/llvm-xray/xray-account.cpp

enum class SortField {
   SUM,
   FUNC,
 };
 
 static cl::opt<SortField> AccountSortOutput(
     "sort", cl::desc("sort output by this field"), cl::value_desc("field"),
     cl::sub(Account), cl::init(SortField::FUNCID),
     cl::values(clEnumValN(SortField::FUNCID, "funcid", "function id"),
-               clEnumValN(SortField::COUNT, "count", "funciton call counts"),
+               clEnumValN(SortField::COUNT, "count", "function call counts"),
                clEnumValN(SortField::MIN, "min", "minimum function durations"),
                clEnumValN(SortField::MED, "med", "median function durations"),
                clEnumValN(SortField::PCT90, "90p", "90th percentile durations"),
                clEnumValN(SortField::PCT99, "99p", "99th percentile durations"),
                clEnumValN(SortField::MAX, "max", "maximum function durations"),
                clEnumValN(SortField::SUM, "sum", "sum of call durations"),
                clEnumValN(SortField::FUNC, "func", "function names")));
 static cl::alias AccountSortOutput2("s", cl::aliasopt(AccountSortOutput),

llvm/tools/llvm-xray/xray-graph.cpp

 // structure representing the call stack for that function.
 // If the record is an EXIT record it checks computes computes the ammount of
 // time the function took to complete and then stores that information in an
 // edge of the graph. If there is no matching ENTER record the function tries
 // to recover by assuming that there were EXIT records which were missed, for
 // example caused by tail call elimination and if the option is enabled then
 // then tries to recover from this.
 //
-// This funciton will also error if the records are out of order, as the trace
+// This function will also error if the records are out of order, as the trace
 // is expected to be sorted.
 //
 // The graph generated has an immaginary root for functions called by no-one at
 // FuncId 0.
 //
 // FIXME: Refactor this and account subcommand to reduce code duplication.
 Error GraphRenderer::accountRecord(const XRayRecord &Record) {
   using std::make_error_code;

llvm/unittests/ADT/FallibleIteratorTest.cpp

Error dec() {
     if (C[Idx].second == ValidLink)
       return Error::success();
     return make_error<StringError>("cant get prev object in (mock) collection",
                                    inconvertibleErrorCode());
   }
 
   friend bool operator==(const FallibleCollectionWalker &LHS,
                          const FallibleCollectionWalker &RHS) {
-    assert(&LHS.C == &RHS.C && "Comparing iterators across collectionss.");
+    assert(&LHS.C == &RHS.C && "Comparing iterators across collections.");
     return LHS.Idx == RHS.Idx;
   }
 
 private:
   FallibleCollection &C;
   unsigned Idx;
 };
 

llvm/unittests/ADT/SequenceTest.cpp

-//===- SequenceTest.cpp - Unit tests for a sequence abstraciton -----------===//
+//===- SequenceTest.cpp - Unit tests for a sequence abstraction -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/Sequence.h"

llvm/unittests/Analysis/MemorySSATest.cpp

TEST_F(MemorySSATest, CreateALoad) {
   // Add the load
   B.SetInsertPoint(Merge);
   LoadInst *LoadInst = B.CreateLoad(B.getInt8Ty(), PointerArg);
 
   // MemoryPHI should already exist.
   MemoryPhi *MP = MSSA.getMemoryAccess(Merge);
   EXPECT_NE(MP, nullptr);
 
-  // Create the load memory acccess
+  // Create the load memory access
   MemoryUse *LoadAccess = cast<MemoryUse>(Updater.createMemoryAccessInBB(
       LoadInst, MP, Merge, MemorySSA::Beginning));
   MemoryAccess *DefiningAccess = LoadAccess->getDefiningAccess();
   EXPECT_TRUE(isa<MemoryPhi>(DefiningAccess));
   MSSA.verifyMemorySSA();
 }
 TEST_F(MemorySSATest, CreateLoadsAndStoreUpdater) {
   // We create a diamond, then build memoryssa with no memory accesses, and
TEST_F(MemorySSATest, CreateALoadUpdater) {
   // MemoryPHI should be created when inserting the def
   MemoryPhi *MP = MSSA.getMemoryAccess(Merge);
   EXPECT_NE(MP, nullptr);
 
   // Add the load
   B.SetInsertPoint(Merge, Merge->begin());
   LoadInst *LoadInst = B.CreateLoad(B.getInt8Ty(), PointerArg);
 
-  // Create the load memory acccess
+  // Create the load memory access
   MemoryUse *LoadAccess = cast<MemoryUse>(Updater.createMemoryAccessInBB(
       LoadInst, nullptr, Merge, MemorySSA::Beginning));
   Updater.insertUse(LoadAccess);
   MemoryAccess *DefiningAccess = LoadAccess->getDefiningAccess();
   EXPECT_TRUE(isa<MemoryPhi>(DefiningAccess));
   MSSA.verifyMemorySSA();
 }
 
TEST_F(MemorySSATest, Irreducible) {
   B.CreateBr(LoopMainBB);
   B.SetInsertPoint(LoopMainBB);
   B.CreateCondBr(B.getTrue(), LoopStartBB, AfterLoopBB);
   B.SetInsertPoint(AfterLoopBB);
   Argument *FirstArg = &*F->arg_begin();
   setupAnalyses();
   MemorySSA &MSSA = *Analyses->MSSA;
   MemorySSAUpdater Updater(&MSSA);
-  // Create the load memory acccess
+  // Create the load memory access
   LoadInst *LoadInst = B.CreateLoad(B.getInt8Ty(), FirstArg);
   MemoryUse *LoadAccess = cast<MemoryUse>(Updater.createMemoryAccessInBB(
       LoadInst, nullptr, AfterLoopBB, MemorySSA::Beginning));
   Updater.insertUse(LoadAccess);
   MSSA.verifyMemorySSA();
 }
 
 TEST_F(MemorySSATest, MoveToBeforeLiveOnEntryInvalidatesCache) {

llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp

TEST_F(CoreAPIsStandardTest, EmptyLookup) {
 
   ES.lookup(LookupKind::Static, makeJITDylibSearchOrder(&JD), SymbolLookupSet(),
             SymbolState::Ready, OnCompletion, NoDependenciesToRegister);
 
   EXPECT_TRUE(OnCompletionRun) << "OnCompletion was not run for empty query";
 }
 
 TEST_F(CoreAPIsStandardTest, ResolveUnrequestedSymbol) {
-  // Test that all symbols in a MaterializationUnit materialize corretly when
+  // Test that all symbols in a MaterializationUnit materialize correctly when
   // only a subset of symbols is looked up.
   // The aim here is to ensure that we're not relying on the query to set up
   // state needed to materialize the unrequested symbols.
 
   cantFail(JD.define(std::make_unique<SimpleMaterializationUnit>(
       SymbolFlagsMap({{Foo, FooSym.getFlags()}, {Bar, BarSym.getFlags()}}),
       [this](std::unique_ptr<MaterializationResponsibility> R) {
         cantFail(R->notifyResolved({{Foo, FooSym}, {Bar, BarSym}}));
TEST_F(CoreAPIsStandardTest, FailAfterMaterialization) {
   BarR->failMaterialization();
 
   // Verify that both queries failed.
   EXPECT_TRUE(OnFooReadyRun) << "Query for Foo did not run";
   EXPECT_TRUE(OnBarReadyRun) << "Query for Bar did not run";
 }
 
 TEST_F(CoreAPIsStandardTest, FailMaterializerWithUnqueriedSymbols) {
-  // Make sure that symbols with no queries aganist them still
+  // Make sure that symbols with no queries against them still
   // fail correctly.
 
   bool MaterializerRun = false;
   auto MU = std::make_unique<SimpleMaterializationUnit>(
       SymbolFlagsMap(
           {{Foo, JITSymbolFlags::Exported}, {Bar, JITSymbolFlags::Exported}}),
       [&](std::unique_ptr<MaterializationResponsibility> R) {
         MaterializerRun = true;

llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp

TEST_F(OpenMPIRBuilderTest, CreateReductions) {
   EXPECT_NE(Outlined, nullptr);
 
   // Check that the lock variable was created with the expected name.
   GlobalVariable *LockVar =
       M->getGlobalVariable(".gomp_critical_user_.reduction.var");
   EXPECT_NE(LockVar, nullptr);
 
   // Find the allocation of a local array that will be used to call the runtime
-  // reduciton function.
+  // reduction function.
   BasicBlock &AllocBlock = Outlined->getEntryBlock();
   Value *LocalArray = nullptr;
   for (Instruction &I : AllocBlock) {
     if (AllocaInst *Alloc = dyn_cast<AllocaInst>(&I)) {
       if (!Alloc->getAllocatedType()->isArrayTy() ||
           !Alloc->getAllocatedType()->getArrayElementType()->isPointerTy())
         continue;
       LocalArray = Alloc;

llvm/utils/TableGen/CodeGenSchedule.h

class CodeGenSchedModels {
 
   // Per-operand SchedReadWrite types.
   std::vector<CodeGenSchedRW> SchedWrites;
   std::vector<CodeGenSchedRW> SchedReads;
 
   // List of unique SchedClasses.
   std::vector<CodeGenSchedClass> SchedClasses;
 
-  // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
+  // Any inferred SchedClass has an index greater than NumInstrSchedClasses.
   unsigned NumInstrSchedClasses;
 
   RecVec ProcResourceDefs;
   RecVec ProcResGroups;
 
   // Map each instruction to its unique SchedClass index considering the
   // combination of it's itinerary class, SchedRW list, and InstRW records.
   using InstClassMapTy = DenseMap<Record*, unsigned>;

llvm/utils/TableGen/DAGISelMatcher.h

class Matcher {
   // The next matcher node that is executed after this one.  Null if this is the
   // last stage of a match.
   std::unique_ptr<Matcher> Next;
   size_t Size; // Size in bytes of matcher and all its children (if any).
   virtual void anchor();
 public:
   enum KindTy {
     // Matcher state manipulation.
-    Scope,                // Push a checking scope.
-    RecordNode,           // Record the current node.
-    RecordChild,          // Record a child of the current node.
-    RecordMemRef,         // Record the memref in the current node.
-    CaptureGlueInput,     // If the current node has an input glue, save it.
-    MoveChild,            // Move current node to specified child.
-    MoveParent,           // Move current node to parent.
+    Scope,            // Push a checking scope.
+    RecordNode,       // Record the current node.
+    RecordChild,      // Record a child of the current node.
+    RecordMemRef,     // Record the memref in the current node.
+    CaptureGlueInput, // If the current node has an input glue, save it.
+    MoveChild,        // Move current node to specified child.
+    MoveParent,       // Move current node to parent.
 
     // Predicate checking.
-    CheckSame,            // Fail if not same as prev match.
-    CheckChildSame,       // Fail if child not same as prev match.
+    CheckSame,      // Fail if not same as prev match.
+    CheckChildSame, // Fail if child not same as prev match.
     CheckPatternPredicate,
-    CheckPredicate,       // Fail if node predicate fails.
-    CheckOpcode,          // Fail if not opcode.
-    SwitchOpcode,         // Dispatch based on opcode.
-    CheckType,            // Fail if not correct type.
-    SwitchType,           // Dispatch based on type.
-    CheckChildType,       // Fail if child has wrong type.
-    CheckInteger,         // Fail if wrong val.
-    CheckChildInteger,    // Fail if child is wrong val.
-    CheckCondCode,        // Fail if not condcode.
-    CheckChild2CondCode,  // Fail if child is wrong condcode.
+    CheckPredicate,      // Fail if node predicate fails.
+    CheckOpcode,         // Fail if not opcode.
+    SwitchOpcode,        // Dispatch based on opcode.
+    CheckType,           // Fail if not correct type.
+    SwitchType,          // Dispatch based on type.
+    CheckChildType,      // Fail if child has wrong type.
+    CheckInteger,        // Fail if wrong val.
+    CheckChildInteger,   // Fail if child is wrong val.
+    CheckCondCode,       // Fail if not condcode.
+    CheckChild2CondCode, // Fail if child is wrong condcode.
     CheckValueType,
     CheckComplexPat,
     CheckAndImm,
     CheckOrImm,
     CheckImmAllOnesV,
     CheckImmAllZerosV,
     CheckFoldableChainNode,
 
-    // Node creation/emisssion.
+    // Node creation/emission.
     EmitInteger,          // Create a TargetConstant
     EmitStringInteger,    // Create a TargetConstant from a string.
     EmitRegister,         // Create a register.
     EmitConvertToTarget,  // Convert a imm/fpimm to target imm/fpimm
     EmitMergeInputChains, // Merge together a chains for an input.
     EmitCopyToReg,        // Emit a copytoreg into a physreg.
     EmitNode,             // Create a DAG node
     EmitNodeXForm,        // Run a SDNodeXForm

llvm/utils/TableGen/GlobalISelEmitter.cpp

return std::accumulate(
       [](unsigned A, const std::unique_ptr<InstructionMatcher> &Matcher) {
         return A + Matcher->countRendererFns();
       });
 }
 
 bool OperandPredicateMatcher::isHigherPriorityThan(
     const OperandPredicateMatcher &B) const {
   // Generally speaking, an instruction is more important than an Int or a
-  // LiteralInt because it can cover more nodes but theres an exception to
+  // LiteralInt because it can cover more nodes but there's an exception to
   // this. G_CONSTANT's are less important than either of those two because they
   // are more permissive.
 
   const InstructionOperandMatcher *AOM =
       dyn_cast<InstructionOperandMatcher>(this);
   const InstructionOperandMatcher *BOM =
       dyn_cast<InstructionOperandMatcher>(&B);
   bool AIsConstantInsn = AOM && AOM->getInsnMatcher().isConstantInstruction();
Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   //    and
   // 2. We need to reset the generation of the IDs in M somewhere between
   //    addInstructionMatcher and emit
   //
   // FIXME: Long term, we don't want to have to rely on this implicit
   // naming being the same. One possible solution would be to have
   // explicit operator for operation capture and reference those.
   // The plus side is that it would expose opportunities to share
-  // the capture accross rules. The downside is that it would
+  // the capture across rules. The downside is that it would
   // introduce a dependency between predicates (captures must happen
   // before their first use.)
   InstructionMatcher &InsnMatcherTemp = M.addInstructionMatcher(Src->getName());
   unsigned TempOpIdx = 0;
   auto InsnMatcherOrError =
       createAndImportSelDAGMatcher(M, InsnMatcherTemp, Src, TempOpIdx);
   if (auto Error = InsnMatcherOrError.takeError())
     return std::move(Error);

llvm/utils/UpdateTestChecks/common.py

for m in function_re.finditer(raw_tool_output):
                 args_and_sig,
                 attrs,
                 is_backend):
               self._func_dict[prefix][func].scrub = scrubbed_extra
               self._func_dict[prefix][func].args_and_sig = args_and_sig
             else:
               # This means a previous RUN line produced a body for this function
               # that is different from the one produced by this current RUN line,
-              # so the body can't be common accross RUN lines. We use None to
+              # so the body can't be common across RUN lines. We use None to
               # indicate that.
               self._func_dict[prefix][func] = None
         else:
           if prefix not in self._processed_prefixes:
             self._func_dict[prefix][func] = function_body(
                 scrubbed_body, scrubbed_extra, args_and_sig, attrs,
                 func_name_separator)
             self._func_order[prefix].append(func)

llvm/utils/docker/build_docker_image.sh

 For example, running:
 $ build_docker_image.sh -s debian10 -d mydocker/debian10-clang -t latest \
   -p clang -i install-clang -i install-clang-resource-headers
 will produce two docker images:
     mydocker/debian10-clang-build:latest - an intermediate image used to compile
       clang.
     mydocker/clang-debian10:latest       - a small image with preinstalled clang.
 Please note that this example produces a not very useful installation, since it
-doesn't override CMake defaults, which produces a Debug and non-boostrapped
+doesn't override CMake defaults, which produces a Debug and non-bootstrapped
 version of clang.
 
 To get a 2-stage clang build, you could use this command:
 $ ./build_docker_image.sh -s debian10 -d mydocker/clang-debian10 -t "latest" \
     -p clang -i stage2-install-clang -i stage2-install-clang-resource-headers \ 
     -- \ 
     -DLLVM_TARGETS_TO_BUILD=Native -DCMAKE_BUILD_TYPE=Release \ 
     -DBOOTSTRAP_CMAKE_BUILD_TYPE=Release \ 

llvm/utils/git/github-automation.py

def execute_command(self) -> bool:
                     branch = m.group(3)
                     return self.create_pull_request(owner, repo, branch)
 
         print("Do not understand input:")
         print(sys.stdin.readlines())
         return False
 
 parser = argparse.ArgumentParser()
-parser.add_argument('--token', type=str, required=True, help='GitHub authentiation token')
+parser.add_argument('--token', type=str, required=True, help='GitHub authentication token')
 parser.add_argument('--repo', type=str, default=os.getenv('GITHUB_REPOSITORY', 'llvm/llvm-project'),
                     help='The GitHub repository that we are working with in the form of <owner>/<repo> (e.g. llvm/llvm-project)')
 subparsers = parser.add_subparsers(dest='command')
 
 issue_subscriber_parser = subparsers.add_parser('issue-subscriber')
 issue_subscriber_parser.add_argument('--label-name', type=str, required=True)
 issue_subscriber_parser.add_argument('--issue-number', type=int, required=True)
 
 release_workflow_parser = subparsers.add_parser('release-workflow')
-release_workflow_parser.add_argument('--llvm-project-dir', type=str, default='.', help='directory containing the llvm-project checout')
+release_workflow_parser.add_argument('--llvm-project-dir', type=str, default='.', help='directory containing the llvm-project checkout')
 release_workflow_parser.add_argument('--issue-number', type=int, required=True, help='The issue number to update')
 release_workflow_parser.add_argument('--phab-token', type=str, help='Phabricator conduit API token. See https://reviews.llvm.org/settings/user/<USER>/page/apitokens/')
 release_workflow_parser.add_argument('--branch-repo-token', type=str,
                                      help='GitHub authentication token to use for the repository where new branches will be pushed. Defaults to TOKEN.')
 release_workflow_parser.add_argument('--branch-repo', type=str, default='llvm/llvm-project-release-prs',
                                      help='The name of the repo where new branches will be pushed (e.g. llvm/llvm-project)')
 release_workflow_parser.add_argument('sub_command', type=str, choices=['print-release-branch', 'auto'],
                                      help='Print to stdout the name of the release branch ISSUE_NUMBER should be backported to')

llvm/utils/gn/secondary/lldb/tools/lldb-test/BUILD.gn

deps = [
     "//lldb/source/Plugins:LldbAllPlugins",
     "//lldb/source/Symbol",
     "//lldb/source/Target",
     "//lldb/source/Utility",
     "//lldb/source/Version",
     "//llvm/lib/Support",
   ]
 
-  # XXX commment
+  # XXX comment
   include_dirs = [ "//lldb/source" ]
   sources = [
     "FormatUtil.cpp",
     "SystemInitializerTest.cpp",
     "lldb-test.cpp",
   ]
 }

llvm/utils/lit/lit/ProgressBar.py

class TerminalController:
     result, the above code will still work on terminals that do not
     support color, except that their output will not be colored.
     Also, this means that you can test whether the terminal supports a
     given action by simply testing the truth value of the
     corresponding instance variable:
 
         >>> term = TerminalController()
         >>> if term.CLEAR_SCREEN:
-        ...     print('This terminal supports clearning the screen.')
+        ...     print('This terminal supports clearing the screen.')
 
     Finally, if the width and height of the terminal are known, then
     they will be stored in the `COLS` and `LINES` attributes.
     """
     # Cursor movement:
     BOL = ''             #: Move the cursor to the beginning of the line
     UP = ''              #: Move the cursor up one line
     DOWN = ''            #: Move the cursor down one line

llvm/utils/lit/lit/TestRunner.py

 # command in the target shell so that the line number is seen in lit's verbose
 # mode.
 #
 # This regex captures ARG.  ARG must not contain a right parenthesis, which
 # terminates %dbg.  ARG must not contain quotes, in which ARG might be enclosed
 # during expansion.
 #
 # COMMAND that follows %dbg(ARG) is also captured. COMMAND can be
-# empty as a result of conditinal substitution.
+# empty as a result of conditional substitution.
 kPdbgRegex = '%dbg\\(([^)\'"]*)\\)(.*)'
 
 class ShellEnvironment(object):
 
     """Mutable shell environment containing things like CWD and env vars.
 
     Environment variables are not implemented, but cwd tracking is. In addition,
     we maintain a dir stack for pushd/popd.

llvm/utils/unicode-case-fold.py

 
 # Computes the stride of a list of mappings. The list should have at least two
 # mappings. All mappings in the list are assumed to have the same stride.
 def stride(block):
     return stride2(block[0], block[1])
 
 
 # b is a list of mappings. All the mappings are assumed to have the same
-# shift and the stride between adjecant mappings (if any) is constant.
+# shift and the stride between adjacent mappings (if any) is constant.
 def dump_block(b):
     global body
 
     if len(b) == 1:
         # Special case for handling blocks of length 1. We don't even need to
         # emit the "if (C < X) return C" check below as all characters in this
         # range will be caught by the "C < X" check emitted by the first
         # non-trivial block.

llvm/utils/update_analyze_test_checks.py

 6. Apply your patch from step 1 and rebuild your local binaries.
 7. Re-run this script on affected regression tests.
 8. Check the diffs to ensure the script has done something reasonable.
 9. Submit a patch including the regression test diffs for review.
 
 A common pattern is to have the script insert complete checking of every
 instruction. Then, edit it down to only check the relevant instructions.
 The script is designed to make adding checks to a test case fast, it is *not*
-designed to be authoratitive about what constitutes a good test!
+designed to be authoritative about what constitutes a good test!
 """
 
 from __future__ import print_function
 
 import argparse
 import os         # Used to advertise this file's name ("autogenerated_note").
 import sys
 import re

llvm/utils/update_cc_test_checks.py

else:
       for line_info in ti.iterlines(output_lines):
         idx = line_info.line_number
         line = line_info.line
         args = line_info.args
         include_line = True
         m = common.CHECK_RE.match(line)
         if m and m.group(1) in prefix_set:
           continue  # Don't append the existing CHECK lines
-        # Skip special separator comments added by commmon.add_global_checks.
+        # Skip special separator comments added by common.add_global_checks.
         if line.strip() == '//' + common.SEPARATOR:
           continue
         if idx in line2func_list:
           added = set()
           for spell, mangled, search in line2func_list[idx]:
             # One line may contain multiple function declarations.
             # Skip if the mangled name has been added before.
             # The line number may come from an included file, we simply require