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kito-cheng (Kito Cheng)
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User Since
Oct 20 2016, 2:25 AM (243 w, 4 d)

Recent Activity

Mon, Jun 14

kito-cheng added inline comments to D104069: [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch..
Mon, Jun 14, 8:58 PM · Restricted Project

Tue, Jun 8

kito-cheng accepted D103790: [RISCV][NFC] Add a single space after comma for VType.

LGTM

Tue, Jun 8, 8:14 PM · Restricted Project

Fri, Jun 4

kito-cheng updated the diff for D103228: [PoC][RISCV] Using pragma to register vector intrinsic.

Reupload.

Fri, Jun 4, 1:08 AM · Restricted Project, Restricted Project
kito-cheng updated the diff for D103228: [PoC][RISCV] Using pragma to register vector intrinsic.
  • Using less invasive way to add intrinsic functions.
Fri, Jun 4, 1:08 AM · Restricted Project, Restricted Project

Thu, Jun 3

kito-cheng added a comment to D103603: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C.

The testcase I provided in last comment could be compile successfully with aarch64-gcc, but failed on clang.

Thu, Jun 3, 3:19 AM · Restricted Project
kito-cheng added a comment to D103603: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C.

Testcase for AArch64/SVE:

#include <arm_sve.h>
Thu, Jun 3, 3:15 AM · Restricted Project

Wed, Jun 2

kito-cheng added a comment to D103174: RISCV: honour `.option relax` in assembly.

I would suggest few more line on testcase:

Wed, Jun 2, 10:24 AM · Restricted Project

Thu, May 27

kito-cheng added a comment to D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division.

Personally I prefer to deprecate -mno-div soon, but based on the rule for RISC-V GNU toolchain, it need to wait Zmmul extension frozen.
My plan is deprecate the -mno-div and emit warning to tell user should use Zmmul instead once it frozen.

Thu, May 27, 6:13 AM · Restricted Project, Restricted Project
kito-cheng added inline comments to D103228: [PoC][RISCV] Using pragma to register vector intrinsic.
Thu, May 27, 12:33 AM · Restricted Project, Restricted Project

Wed, May 26

kito-cheng updated the diff for D103228: [PoC][RISCV] Using pragma to register vector intrinsic.

Minor cleanup

Wed, May 26, 11:53 PM · Restricted Project, Restricted Project
kito-cheng updated the summary of D103228: [PoC][RISCV] Using pragma to register vector intrinsic.
Wed, May 26, 11:49 PM · Restricted Project, Restricted Project
kito-cheng updated the summary of D103228: [PoC][RISCV] Using pragma to register vector intrinsic.
Wed, May 26, 11:48 PM · Restricted Project, Restricted Project
kito-cheng added reviewers for D103228: [PoC][RISCV] Using pragma to register vector intrinsic: asb, rogfer01, khchen, HsiangKai, craig.topper.
Wed, May 26, 11:48 PM · Restricted Project, Restricted Project
kito-cheng requested review of D103228: [PoC][RISCV] Using pragma to register vector intrinsic.
Wed, May 26, 11:46 PM · Restricted Project, Restricted Project
kito-cheng added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

If .option norelax is the agreed-upon choice (is it?), can I get a stamp?

I did not participate in the meetings you have ... and I am confused about the state now.

Wed, May 26, 11:08 PM · Restricted Project
kito-cheng added a comment to D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division.

We have Zmmul extension in the ISA spec now, that's equivalent to -mno-div , so I suggest we should go forward to implement that extension rather than -mno-div.

Wed, May 26, 10:10 AM · Restricted Project, Restricted Project

Tue, May 25

kito-cheng added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

I think an assembler only option should be spelled as -Wa,*. The driver option isn't useful and should just be avoided.

For -mno-relax, I think there can be arguments that the assembler generation may be affected (to appease assembler, for example) so a driver option is needed.

If the driver option -mno-relax is still preferred over -Wa,-mno-relax, I can abandon this and submit another one passing -mno-relax to GNU as for -fno-integrated-as.

Tue, May 25, 7:59 PM · Restricted Project
kito-cheng added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

GCC pass -mno-relax to assembler now: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=3b0a7d624e64eeb81e4d5e8c62c46d86ef521857

Tue, May 25, 6:31 AM · Restricted Project

Mon, May 24

kito-cheng added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

After discussion with Jim W, we think it's OK to pass -mno-relax to as for GCC, and we could sent patch recently, but keep emitting .option norelax for this moment to make sure the compatibility, and remove that later after 1 or 2 GCC version (that's means 1~2 years in generally)

Mon, May 24, 7:48 PM · Restricted Project
kito-cheng added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

Personally I prefer keep compatible with GNU toolchain behavior on this, so this patch is LGTM.

Mon, May 24, 6:50 PM · Restricted Project

May 12 2021

kito-cheng added a comment to D102386: [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount()..

Maybe you could pre-commit the test case to easier demonstrate the change of this patch?

May 12 2021, 11:38 PM · Restricted Project
kito-cheng added a comment to D98136: [RISCV][RFC] Initially support the K-extension instructions on the LLVM MC layer.

Could you handle k* extension for ELF attribute?

May 12 2021, 12:21 AM · Restricted Project

Apr 15 2021

kito-cheng added a comment to D100611: [Clang] Add clang attribute `clang_builtin_alias`..

Could you also check the compiler diagnostic messages? it will report __builtin_rvv_vadd_vv_i8m1 or vadd_generic if argument type mis-match, which one you expected? I assume without __clang_riscv_builtin_alias clang will report vadd_generic?

Apr 15 2021, 9:51 PM · Restricted Project
kito-cheng added a comment to D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker.
Apr 15 2021, 9:40 PM · Restricted Project
kito-cheng added a reviewer for D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker: MaskRay.
Apr 15 2021, 8:43 PM · Restricted Project
kito-cheng added a comment to D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker.

Few more word for this issue, the option order is matter for linker both for GNU ld and lld, in the test @arcbbb provided, ABC will treat as undefined in a.lds if the order is wrong.

Apr 15 2021, 8:43 PM · Restricted Project
kito-cheng added inline comments to D100611: [Clang] Add clang attribute `clang_builtin_alias`..
Apr 15 2021, 7:48 PM · Restricted Project

Apr 7 2021

kito-cheng added a comment to D99930: [test-suite] Fix CLAMR build with glibc 2.32+.

I don't know who is the right people to add as reviewer here, and I saw @MaskRay and @lenary you guys has reviewed this repo before, and most important is I know you guys :P so could you help me to review that or find the right people to review that? Thanks :)

Apr 7 2021, 9:41 PM
kito-cheng added reviewers for D99930: [test-suite] Fix CLAMR build with glibc 2.32+: MaskRay, lenary.
Apr 7 2021, 9:38 PM

Apr 6 2021

kito-cheng added a comment to D99930: [test-suite] Fix CLAMR build with glibc 2.32+.

News of Glibc 2.32:
https://sourceware.org/pipermail/libc-announce/2020/000029.html

Apr 6 2021, 1:50 AM
kito-cheng requested review of D99930: [test-suite] Fix CLAMR build with glibc 2.32+.
Apr 6 2021, 1:47 AM

Apr 1 2021

kito-cheng added a comment to D99320: [RISCV] [1/2] Add intrinsic for Zbb extension.

Created an issue for continue discuses on riscv-c-api-doc
https://github.com/riscv/riscv-c-api-doc/issues/19

Apr 1 2021, 10:31 AM · Restricted Project, Restricted Project
kito-cheng added a comment to D99148: [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat..

General code gen behavior change is look good to me.

Apr 1 2021, 8:07 AM · Restricted Project

Mar 30 2021

kito-cheng added a comment to D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not..

I just found an issue is unrelated this patch, but related to fp16, RISC-V GCC using the traditional libgcc function name scheme like __extendhfdf2(__<op><srcT><dstT><N_OP>) rather than __gnu_f2h_ieee (__gnu_*2*_ieee).

Function used in GCC:

  • __extendhfsf2 for half -> float
  • __truncsfhf2 for float -> half
  • __extendhfdf2 for double -> half
  • __truncdfhf2 for half -> double

Yes. This was my finding as well. I taught llvm and compiler-rt about them in this patch (unmerged). Would this be useful to revisit?

Mar 30 2021, 7:24 AM · Restricted Project

Mar 29 2021

kito-cheng accepted D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not..

LGTM for NaN-boxing behavior.

Mar 29 2021, 6:24 PM · Restricted Project

Mar 25 2021

kito-cheng added a comment to D98670: [RISCV] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled, but Zfh is not..

I just found an issue is unrelated this patch, but related to fp16, RISC-V GCC using the traditional libgcc function name scheme like __extendhfdf2(__<op><srcT><dstT><N_OP>) rather than __gnu_f2h_ieee (__gnu_*2*_ieee).

Mar 25 2021, 2:40 AM · Restricted Project
kito-cheng added inline comments to D99319: [RISCV] [2/2] Add intrinsic for Zbb extension.
Mar 25 2021, 2:20 AM · Restricted Project, Restricted Project, Restricted Project

Mar 17 2021

kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..
  • Add more verbose message during reading GCC multilib configuration.
  • Add test case to verify verbose messages.
Mar 17 2021, 8:20 PM · Restricted Project

Mar 16 2021

kito-cheng added a comment to D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

This still doesn't report that the multilib configuration came from GCC when it succeeds, does it? I suppose that's not a deal-breaker, but it would be nice to have. Would it be difficult to implement?

Mar 16 2021, 8:46 PM · Restricted Project
kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

Address jrtc27's and luismarques comment

Mar 16 2021, 9:55 AM · Restricted Project

Mar 15 2021

kito-cheng added a comment to D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'..

Provide more implementation detail on GCC,

  • if a letter are used as a prefix of multi-char constraint, then it can't be used as a single letter constraint
    • e.g. If we defined vr and vm then we can't define v as constraint
  • constraint with same prefix should have same length
    • e.g. If we defined vr and vm then we can't define vrr since has different length.
Mar 15 2021, 8:08 AM · Restricted Project
kito-cheng added a comment to D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'..

GCC use vr for vector register and vm for vector mask register.

Mar 15 2021, 7:04 AM · Restricted Project

Mar 5 2021

kito-cheng added reviewers for D98012: [RFC][doc] Document that RISC-V's __fp16 has different behavior: SjoerdMeijer, simon_tatham, stuij.
Mar 5 2021, 12:16 AM · Restricted Project
kito-cheng requested review of D98012: [RFC][doc] Document that RISC-V's __fp16 has different behavior.
Mar 5 2021, 12:13 AM · Restricted Project

Mar 4 2021

kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

Reupload

Mar 4 2021, 11:40 PM · Restricted Project
kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..
  • Fix build issue.
  • Address Jim Lin's and Zakk's comment
Mar 4 2021, 11:39 PM · Restricted Project
kito-cheng added a comment to D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

Here is another solution for flexible multi-lib configuration I consider before:

Mar 4 2021, 11:04 PM · Restricted Project
kito-cheng added inline comments to D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..
Mar 4 2021, 12:55 AM · Restricted Project
kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

Address MaskRay's comment and apply clang-format.

Mar 4 2021, 12:54 AM · Restricted Project
kito-cheng added inline comments to D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..
Mar 4 2021, 12:43 AM · Restricted Project
kito-cheng added reviewers for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.: asb, khchen, luismarques, abidh.
Mar 4 2021, 12:01 AM · Restricted Project

Mar 3 2021

kito-cheng updated the diff for D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..

Minor clean up

Mar 3 2021, 11:56 PM · Restricted Project
kito-cheng requested review of D97916: [Driver][RISCV] Support parsing multi-lib config from GCC..
Mar 3 2021, 11:51 PM · Restricted Project
kito-cheng added a comment to D97912: [doc] Document that __fp16 will apply default argument promotion rule..

Update SUMMARY, first version I just incorrectly said ACLE didn't clarify the default argument promotion rule, but I found that in ARM ABI spec later.

Mar 3 2021, 11:35 PM · Restricted Project
kito-cheng updated the summary of D97912: [doc] Document that __fp16 will apply default argument promotion rule..
Mar 3 2021, 11:34 PM · Restricted Project
kito-cheng updated the summary of D97912: [doc] Document that __fp16 will apply default argument promotion rule..
Mar 3 2021, 10:44 PM · Restricted Project
kito-cheng requested review of D97912: [doc] Document that __fp16 will apply default argument promotion rule..
Mar 3 2021, 10:42 PM · Restricted Project

Mar 2 2021

kito-cheng requested review of D97759: [doc] Fix description of _Float16.
Mar 2 2021, 1:48 AM · Restricted Project, Restricted Project

Feb 1 2021

kito-cheng added inline comments to D95781: [RISCV] Add new vector instructions in v0.10..
Feb 1 2021, 6:12 AM · Restricted Project

Jan 25 2021

kito-cheng added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

Could you also update macros and attributes which implemented in https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931

Jan 25 2021, 1:31 AM · Restricted Project, Restricted Project

Jan 24 2021

kito-cheng accepted D94403: [RISCV] Implement new architecture extension macros.

LGTM

Jan 24 2021, 7:14 PM · Restricted Project
kito-cheng accepted D94931: [RISCV] Add attribute support for all supported extensions.

LGTM

Jan 24 2021, 7:11 PM · Restricted Project

Jan 22 2021

kito-cheng added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

In the mean time I will park this change, and add 'v' implying its subfeatures in clang, since this would catch most cases we expect users to use (I don't think manually enabling features is a common use case). I can then later look at a more detailed/complete fix when enabling features directly with -mattr.

Jan 22 2021, 1:50 AM · Restricted Project

Jan 21 2021

kito-cheng added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

@jrtc27 just let you know I have same concern too, that's one major reason why we don't upstream those extension on GNU toolchain... we are intend to introduce an internal revision number on ELF attribute in near future, e.g. v-ext 0.9.1 / v0p9p1 to prevent compatible issue here.

Jan 21 2021, 7:43 PM · Restricted Project, Restricted Project
kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

Note from the last sync up call, it's ok to landing that once review is done without refactor, refactor could be done separately after LLVM 12 release, that's won't be a blocker issue for this patch.

Jan 21 2021, 7:22 PM · Restricted Project
kito-cheng added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

Doesn't this mean that if you only enable zvlsseg, you'll be able to use the instruction in that extension but not the vsetvli instruction that you need to program the VL register?

@craig.topper To be honest, I'm not at all familiar with the v extension or any of the zv* extensions. I wrote this in response to D94931 which says that V should imply zv* but not the other way around. Looking back now at D85069 it looks there was some discussion suggesting which way around it should be, so it could be this patch is unnecessary and breaks stuff. Do you have any better understand of the vector spec as to which way round is correct?

@kito-cheng Similarly, do you know if the correct order of implication/requirements is well defined somewhere. If there are gcc/binutils patches what does it do here?

Jan 21 2021, 7:04 PM · Restricted Project
kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.
In D94403#2512232, @asb wrote:

@kito-cheng could you please confirm that this patch handles sub-extensions in the same way GCC does. i.e. -march=rv32izbb0p92 defines __riscv_zbb but NOT __riscv_b?

Jan 21 2021, 8:00 AM · Restricted Project
kito-cheng accepted D94403: [RISCV] Implement new architecture extension macros.

I believe the behavior has aligned to GCC now.

Jan 21 2021, 7:59 AM · Restricted Project
kito-cheng added inline comments to D94931: [RISCV] Add attribute support for all supported extensions.
Jan 21 2021, 7:55 AM · Restricted Project
kito-cheng added a comment to D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal..

Add a dedicated test file to demonstrate and verify the ABI would be better.

Jan 21 2021, 7:33 AM · Restricted Project

Jan 19 2021

kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

I think maybe we could extract the arch parser from driver[1] to llvm/lib/Support, so that we could just maintain one parser for driver and assembler, and there is also other potential user for that, like the C front-end for the target attribute, e.g. __attribute__ ((target ("arch=rv64gcv"))), and the linker can re-use that to read/merge/write the attribute too.

[1] https://github.com/llvm/llvm-project/blob/main/clang/lib/Driver/ToolChains/Arch/RISCV.cpp#L171

I was thinking about this too and was going to discuss it on Thursday's call. At the very least, even if we don't move the parser, the number of places that extension version numbers are add and used throughout the tools seems to call for it being centralised somewhere.

Jan 19 2021, 1:36 AM · Restricted Project
kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.

Just note how current GCC implemented, GCC implement that like implied extension, e.g. V implied Zvamo and Zvlsseg, so __riscv_zvamo is naturally defined when V-ext is enabled.

Jan 19 2021, 1:33 AM · Restricted Project
kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

I think maybe we could extract the arch parser from driver[1] to llvm/lib/Support, so that we could just maintain one parser for driver and assembler, and there is also other potential user for that, like the C front-end for the target attribute, e.g. __attribute__ ((target ("arch=rv64gcv"))), and the linker can re-use that to read/merge/write the attribute too.

Jan 19 2021, 1:24 AM · Restricted Project

Jan 17 2021

kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.

Thanks you implement that on clang, I think it's really great to included that in LLVM 12 release.

Jan 17 2021, 7:50 PM · Restricted Project

Jan 12 2021

kito-cheng added inline comments to D94579: [RISCV] add the MC layer support of P extension.
Jan 12 2021, 10:42 PM · Restricted Project
kito-cheng added a comment to D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

Jan 12 2021, 7:05 PM · Restricted Project
kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

It won't be a struct in clang's type system. It's it own special builtin type. I hope we can control the codegen of that type and emit it as multiple allocas/loads/stores. I haven't looked at this yet. Clang can also emit fixed size memcpys of structs which would be broken for this. So we are going to need to customize clang.

Jan 12 2021, 6:54 PM · Restricted Project

Jan 10 2021

kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

This patch removes the existing restriction for this. I've modified
StructType::isSized to consider a struct containing scalable vectors
as unsized so the verifier won't allow loads/stores/allocas of these
structs.

Jan 10 2021, 11:21 PM · Restricted Project

Jan 7 2021

kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

Don't allow function arguments or returns to use structs containing scalable vectors unless they are intrinsics.

Jan 7 2021, 4:57 AM · Restricted Project

Jan 5 2021

kito-cheng added a comment to D93826: [RISCV] Don't print zext.b alias..

Note from gnu toolchain side, GCC will detect bintuils version and behavior during configure time and set different default behavior according the version or feature support test result, but I know clang/llvm doing different way on this part.

Jan 5 2021, 5:03 AM · Restricted Project

Dec 21 2020

kito-cheng added inline comments to D93613: [RISCV] Add new V instructions and aliases in v1.0-08a0b46..
Dec 21 2020, 2:26 AM · Restricted Project

Dec 19 2020

kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

64 bit splat on rv32 code gen sequence is LGTM, but I think that's all I can review :P

Dec 19 2020, 7:11 PM · Restricted Project

Dec 17 2020

kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

I was wondering if we could do something like (with a0=lo and a1=hi):

vmv.v.x vX, a1
vsll.vx vX, vX, /*32*/
vor.vx vX, vX, a0

And then do a .vv operation.

We can then optimize for a sign-extended 32-bit value later. What do you think?

Dec 17 2020, 9:20 AM · Restricted Project
kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

Also, it will not handle 64-bit scalars in RV32, but I don't believe that's
actually supported in the spec?

Dec 17 2020, 6:50 AM · Restricted Project

Dec 16 2020

kito-cheng added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related implementation, but I could be wrong since I am not LLVM expert, in case you have implemented, you need a test case for that.

Dec 16 2020, 7:28 AM · Restricted Project, Restricted Project

Dec 10 2020

kito-cheng added inline comments to D92479: [RISCV] remove redundant instruction when eliminate frame index.
Dec 10 2020, 10:54 PM · Restricted Project
kito-cheng added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 10 2020, 5:42 AM · Restricted Project

Dec 9 2020

kito-cheng added a comment to D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions.

Spec changes has been merged :)

Dec 9 2020, 7:25 PM · Restricted Project

Dec 8 2020

kito-cheng added a comment to D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions.

That's LGTM too, just waiting the spec merge :)

Dec 8 2020, 1:03 AM · Restricted Project

Dec 7 2020

kito-cheng added inline comments to D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 9:10 PM · Restricted Project

Nov 11 2020

kito-cheng added a comment to D91319: [RISCV] ELF attribute for B and V extension..

I think zv* need to set too, seems like we should have more word about extension is consisted with several sub-extensions on the ELF attribute spec.

Nov 11 2020, 11:44 PM · Restricted Project

Nov 10 2020

kito-cheng added a comment to D90738: [RISCV] Support Zfh half-precision floating-point extension..

Could you add zfh to ELF attribute output?

Nov 10 2020, 6:38 PM · Restricted Project

Oct 14 2020

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

@MaskRay Thanks, that's first time I know the suffix -SAME :P

Oct 14 2020, 8:43 PM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog:

  • Update testcase according to MaskRay's suggestion.
Oct 14 2020, 8:41 PM · Restricted Project, Restricted Project
kito-cheng added reviewers for D89288: [RISCV] Enable the use of the old sptbr name: luismarques, lenary.
Oct 14 2020, 7:41 PM · Restricted Project
kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

RISCV supports -mcpu with default empty arch to align gcc's -mtune behavior since clang didn't support -mtune before. But now clang has -mtune, is it a good idea to remove those options? (ex. rocket-rv32/rv64, sifive-7-rv32/64)

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Oct 14 2020, 1:06 AM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog

  • Fix wording in comment
  • Add more comment in testcase
  • Fix format issue.
Oct 14 2020, 1:02 AM · Restricted Project, Restricted Project

Oct 13 2020

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Oct 13 2020, 8:52 PM · Restricted Project, Restricted Project

Oct 12 2020

kito-cheng added inline comments to D89244: [RISCV][ASAN] Fix TLS offsets.
Oct 12 2020, 7:59 PM · Restricted Project

Oct 7 2020

kito-cheng requested review of D89025: [RISCV] Add -mtune support.
Oct 7 2020, 8:45 PM · Restricted Project, Restricted Project