- User Since
- Oct 20 2016, 2:25 AM (169 w, 2 d)
Fri, Jan 10
It seems to me that all remarks have already been addressed. Is there anything holding this patch? For it pretty much LGTM.
Thu, Jan 9
Seems like this patch mixed with LTO related changes? Could you clean it up?
Nov 14 2019
In addition, I think my testcase is so weird and it does not make sense there are different isa extension are used in the same compilation unit...
Nov 8 2019
Oct 16 2019
Oct 8 2019
Sep 17 2019
Sep 12 2019
Sep 2 2019
Aug 1 2019
Jul 2 2019
Jul 1 2019
Add 2 test cases.
@MaskRay Thanks, I'll add test case soon :)
Feb 19 2019
Feb 10 2019
- Update test/MC/RISCV/rvi-pseudos-invalid.s
Feb 5 2019
- Fix parseBareSymbol with a constant symbols.
- Rebase to D55325
Jan 24 2019
@jrtc27 feel free to upload your one, it's just a 5 minute quick patch :P
Jan 23 2019
Jan 16 2019
- Update testcase, R_RISCV_RELAX won't bind with symbol to fit binutils's behavior.
Jan 14 2019
- Add missing tests
Jan 10 2019
Okay, I'll take a look :)
- Merge emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol
- Fix wrong operand type and syntax for floating point load instruction.
Oct 15 2018
rv32e arch and ilp32e ABI is decoupling in GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.
Oct 4 2018
GCC using 5 as threshold to decide using jump table or not for RISC-V and LLVM using 4.
Sep 26 2018
Sep 17 2018
Aug 29 2018
Aug 22 2018
- Add test.
- Move declaration of RelaxCandidate.
- Add comment.
- Update testcase
Aug 13 2018
- Rename functions
- emitLoadSymbolAddress -> emitLoadSymbolAddressHi
- emitLoadWithSymbol -> emitLoadSymbol
- emitStoreWithSymbol -> emitStoreSymbol
- Return shouldForceImediateOperand to true for new pseudo instructions.
- Add negative test
Aug 9 2018
- Add default case in switch.
Aug 2 2018
Rearrange order for testcase.
- Update testcase for rv32i-aliases-invalid.s and rv64i-aliases-invalid.s
- Fix rv32i-invalid.s
- Add addw, sllw, srlw and sraw including testcase.
- Add comment in testcase.
Jul 31 2018
ping, Alex, could you commit that?
May 16 2018
May 13 2018
May 10 2018
- Change fixup value of R_RISCV_RELAX to a constant 0 value for consistent with binutils's implementation.
May 8 2018
- Add 2 test cases to show .option rvc and .option norvc in inline asm will not effect the code gen.
May 1 2018
- Add testcase for warning/failure cases.
Apr 24 2018
- Fix coding style issue.
- Add more instructions to testcase.
- Make emitDirectiveOptionRVC and emitDirectiveOptionNoRVC to pure virtual function.
- Return nullptr rather than RISCVTargetStreamer in createRISCVObjectTargetStreamer, because we have pure virtual function in RISCVTargetStreamer now.
Apr 19 2018
Apr 12 2018
- Add test case.
Apr 4 2018
Long time ago, GCC also accept upper case too, but I have no idea why Andrew change that? I guess one possible reason is because multi-lib?
- Reorder marco define into canonical order which specified in ISA manual.
- Add missing test for marco.
- Add testcase for TargetFeature: riscv, riscv32 and riscv64
Mar 28 2018
- Define riscv_atomic, riscv_flen, riscv_fdiv and riscv_fsqr, and add test for those marco.
- Handle riscv, riscv32 and riscv64 in RISCVTargetInfo::hasFeature.
- Fix several coding style issue.
- Breaking the long lines in test case.
- Add comment for RISCVTargetInfo::hasFeature.
Mar 21 2018
Update revision according Alex's review.
Mar 20 2018
Mar 11 2018
Add test cases for the correct inputs.
Mar 9 2018
Mar 8 2018
This version only update variable name which changed in last version by accident.
Mar 7 2018
Mar 6 2018
Feb 27 2018
LGTM, and I've tested this patch with https://reviews.llvm.org/D42958
Feb 26 2018
So, do we want to enable this flag only based on a CMake macro like COMPILER_RT_HAS_FINT128_FLAG, or always add -fforce-enable-int128 to compiler-rt builds for RISCV32?
- Add testcase.
- Remove muldi3 support for RV64 in lib/builtins/riscv/mul3.S, because compiler-rt already provide a general version for muldi3.
- Rename lib/builtins/riscv/mul3.S to lib/builtins/riscv/mulsi3.S for matching compiler-rt's naming convention.
Feb 23 2018
Feb 22 2018
Feb 20 2018
LGTM for RISC-V part :)
Feb 19 2018
Feb 11 2018
Feb 8 2018
Feb 6 2018
clean up some useless check code.