qcolombet (Quentin Colombet)
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User Since
Dec 17 2012, 10:03 AM (291 w, 1 d)

Recent Activity

Mon, Jun 18

qcolombet added a comment to D47999: MIR YAML TracksRegLiveness default to true in yaml parser.

Either changing the default (trackLiveness == true by default) or printing it is fine.

Mon, Jun 18, 8:35 AM

Jun 15 2018

qcolombet added a comment to D41098: [InlineSpiller] Fix a crash due to lack of forward progress from remat.

Are you okay with us solving this just for STATEPOINTs at the moment by essentially just disabling remats for STATEPOINT uses?

Jun 15 2018, 9:31 AM
qcolombet added a comment to D47999: MIR YAML TracksRegLiveness default to true in yaml parser.

Hi Puyan,

Jun 15 2018, 8:58 AM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Hi Konstantin,

Jun 15 2018, 8:57 AM

May 25 2018

qcolombet added a comment to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..

Do you agree we could drop this patch?

May 25 2018, 8:48 AM

May 24 2018

qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

With the test case fixed

May 24 2018, 11:24 AM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Up to you for the logging. We can keep it.

May 24 2018, 11:21 AM

May 23 2018

qcolombet updated subscribers of D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Doesn't the target already do this? At least there's a CoveredBySubRegs flag in the Register .td class ...

May 23 2018, 1:09 PM
qcolombet accepted D46809: [GlobalISel] NFCI, Getting GlobalISel ~5% faster.
May 23 2018, 12:49 PM

May 22 2018

qcolombet accepted D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.
May 22 2018, 6:24 PM

May 18 2018

qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Would it work to instead use RegUnits, so that we first collect all saved/restored RegUnits, and then check which registers have all their RegUnits saved?

May 18 2018, 2:56 PM
qcolombet accepted D43982: [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank.
May 18 2018, 2:43 PM
qcolombet accepted D46640: [GlobalMerge] Exit early if only one global is to be merged.
May 18 2018, 2:38 PM
qcolombet added a comment to D46809: [GlobalISel] NFCI, Getting GlobalISel ~5% faster.

Nice finding Roman.

May 18 2018, 2:37 PM
qcolombet added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

As you can see I left VMOVRRD ARM instruction as FIXME since it is more complicated copy.

May 18 2018, 1:58 PM

May 15 2018

qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

E.g., on x86 saving xmm0 is not enough to say that ymm0 is preservered even if ymm0 doesn’t have any other sub reg.

May 15 2018, 4:29 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Just reread what you said, you indeed want the other way.
The problem is that the big register is not necessarily covered by the sub regs. So you have to check for that.

May 15 2018, 4:27 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

I was thinking about this the other way around: if all the subreg of a register are saved that doesn’t imply the register itself is saved.
The way you describe with adding the sub regs works great. I thought you wanted the other way :P

May 15 2018, 4:25 PM
qcolombet added inline comments to D46640: [GlobalMerge] Exit early if only one global is to be merged.
May 15 2018, 4:21 PM

May 11 2018

qcolombet updated subscribers of D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.

Yes, please remove these.

May 11 2018, 3:05 PM
qcolombet added a comment to D46640: [GlobalMerge] Exit early if only one global is to be merged.

Looks sensible to me.

May 11 2018, 3:00 PM
qcolombet accepted D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 11 2018, 12:50 PM
qcolombet added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

The general direction makes sense and I agree you probably don't want to implement the full isEquivalentTo stuff I was talking about.
A general pointer you might have missed. We already track copy like instructions through isRegSequenceLike, isExtractSubRegLike and so on. These are more complicated than just plain copies though (e.g., VMOVRRD should already be supported).

May 11 2018, 12:50 PM
qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

This loop (per what determineCalleeSaves does) will only add any of the registers that getCalleeSavedRegs() returns

May 11 2018, 12:31 PM

May 7 2018

qcolombet accepted D46490: [MachineVerifier][GlobalISel] Verifying generic extends and truncates.
May 7 2018, 12:59 PM
qcolombet accepted D46455: [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all vregs.

Nice!

May 7 2018, 12:54 PM
qcolombet added inline comments to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 7 2018, 12:50 PM
qcolombet accepted D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

Thanks for your patience, LGTM.

May 7 2018, 12:50 PM
qcolombet accepted D46039: Fix compile time hang in LSR.

LGTM with the nits fixed

May 7 2018, 12:43 PM
qcolombet requested changes to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Thanks for double checking. Now, I don't think some part of the patch makes sense. See my inline comment.
Basically, we should have to augment whatever determineCalleeSaved gives us, otherwise that means this information is just flawed.

May 7 2018, 12:40 PM

May 4 2018

qcolombet added inline comments to D46039: Fix compile time hang in LSR.
May 4 2018, 9:02 AM
qcolombet added a comment to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..

Good catch!

May 4 2018, 8:59 AM
qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Hi Jonas,

May 4 2018, 8:55 AM
qcolombet added a comment to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.

With not llc you can still check specifics in FileCheck whereas with XFAIL you usually don't put checks at all.
In this case, I would expect a not llc + filecheck of some error message.

May 4 2018, 8:44 AM

May 3 2018

qcolombet added inline comments to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 3 2018, 5:01 PM
qcolombet added a comment to D46338: [GlobalISel][Legalizer] LegalizerInfo verifier: checking that legalization rules cover all type indices.

Couple of nits on the tests.

May 3 2018, 4:57 PM
qcolombet accepted D46284: [MachineLICM] Debug intrinsics shouldn't affect hoist decisions.

LGTM

May 3 2018, 4:29 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Hi Jonas,

May 3 2018, 4:24 PM
qcolombet accepted D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..
May 3 2018, 3:52 PM
qcolombet accepted D45157: [RegUsageInfoCollector] Don't assume the alias of a defined reg is always already in the set..

You're right, re-reading the comment indeed, not all the aliases are here (nor should they be!).

May 3 2018, 3:48 PM
qcolombet added a comment to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

The new result isn't better than old result, neither worse. Do you think we should do transformation on this test case?

May 3 2018, 3:44 PM

Apr 27 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 27 2018, 5:17 PM
qcolombet accepted D46078: [MIR] Reset unique MBB numbering in MachineFunction::reset().
Apr 27 2018, 5:08 PM

Apr 24 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 24 2018, 5:04 PM

Apr 23 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 23 2018, 4:04 PM
qcolombet accepted D44700: [GlobalISel] Improving InstructionSelect's performance by reducing MatchTable.

Hi Roman,

Apr 23 2018, 2:01 PM
qcolombet added inline comments to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..
Apr 23 2018, 1:51 PM
qcolombet added a comment to D45157: [RegUsageInfoCollector] Don't assume the alias of a defined reg is always already in the set..

I am not sure I like the patch in the sense that the comment for UsedPhysRegsMask (in ’MachineRegisterInfo.h) explicitly said that it should contain all the aliases.

Apr 23 2018, 1:44 PM
Herald added a reviewer for D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg': javed.absar.

A while back, with Hal, we talked about having something like:
bool TargetInstrInfo::isEquivalentTo(GenericOpcode, ExpectedOperand)

Apr 23 2018, 1:31 PM
qcolombet accepted D45817: [PostRASink] extend the live-in check for all aliased registers.

LGTM with small nits.

Apr 23 2018, 1:23 PM
qcolombet added a comment to D45968: StackSlotColoring: Decide colors per stack ID.

Disclaimer: I haven't never looked at how this pass actually works so take my comments with a grain of salt!

Apr 23 2018, 1:15 PM
qcolombet added a comment to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

High level comment to help me dive into your changes.
See inlined.

Apr 23 2018, 1:09 PM
qcolombet committed rL330631: [CODE_OWNERS] Update my email address..
[CODE_OWNERS] Update my email address.
Apr 23 2018, 12:14 PM

Mar 22 2018

qcolombet added a comment to D44304: [MIPS GlobalISel] Select add i32, i32.

Do you have any comments on the regbankselect part?

Mar 22 2018, 10:20 AM

Mar 19 2018

qcolombet committed rL327942: [ShrinkWrap] Take into account landing pad.
[ShrinkWrap] Take into account landing pad
Mar 19 2018, 7:47 PM

Mar 14 2018

qcolombet accepted D43353: [X86] Add phony registers for high halves of E[A-D]X, E[SD]I, E[BS]P and EIP.

Hi Krzysztof,

Mar 14 2018, 9:12 PM
qcolombet added a comment to D43093: [FastISel] Sink local value materializations to first use.

FWIW, LGTM now.

Mar 14 2018, 9:02 PM

Mar 5 2018

qcolombet added a comment to D43353: [X86] Add phony registers for high halves of E[A-D]X, E[SD]I, E[BS]P and EIP.

Hi Krzysztof,

Mar 5 2018, 3:55 PM

Feb 27 2018

qcolombet added a comment to D43093: [FastISel] Sink local value materializations to first use.

Hi Reid,

Feb 27 2018, 1:29 PM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Hi Konstantin,

Feb 27 2018, 10:15 AM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

The %1 assignment is dead but not marked as such. I'm not 100% sure whether it is allowed to omit dead flags.

Feb 27 2018, 10:15 AM

Feb 26 2018

qcolombet accepted D43409: [GISel]: Don't assert when constraining Registers which are uses if there's no regclass..
Feb 26 2018, 9:30 AM
qcolombet added a comment to D43409: [GISel]: Don't assert when constraining Registers which are uses if there's no regclass..

Any chance you could add a test case?

Feb 26 2018, 9:29 AM

Feb 21 2018

qcolombet accepted D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

Hi Geoff,

Feb 21 2018, 1:03 PM
qcolombet added inline comments to D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
Feb 21 2018, 10:50 AM

Feb 16 2018

qcolombet added a comment to D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

FYI, I've revert the original commit in r325421.

Feb 16 2018, 7:15 PM
qcolombet committed rL325421: Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding".
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Feb 16 2018, 7:08 PM
qcolombet accepted D43270: [GISel][Tablegen]: Make GlobalISelEmitter rule prioritization similar to that of selectionDAG.

Hi Aditya,

Feb 16 2018, 1:24 PM
qcolombet accepted D43253: bitcode support change for fast flags compatibility.

Thanks all for the great feedbacks!

Feb 16 2018, 11:04 AM
qcolombet accepted D43310: [AArch64][GlobalISel] Fix an assert fail/miscompile when fp16 types are copied to GPR register banks.

Hi Amara,

Feb 16 2018, 9:26 AM

Feb 13 2018

qcolombet accepted D43206: [GISel]: Add pattern matcher for FMUL and FADD.
Feb 13 2018, 10:02 AM
qcolombet added a comment to D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

(though it may require the interface to be changed slightly since we'll need the opcode)

Feb 13 2018, 9:45 AM

Feb 12 2018

qcolombet accepted D43090: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic.
Feb 12 2018, 1:58 PM

Feb 9 2018

qcolombet added inline comments to D43090: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic.
Feb 9 2018, 5:52 PM
qcolombet added inline comments to D43090: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic.
Feb 9 2018, 4:28 PM
qcolombet added a comment to D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

Hi Geoff,

Feb 9 2018, 2:37 PM
qcolombet added inline comments to D43090: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic.
Feb 9 2018, 11:27 AM

Feb 8 2018

qcolombet added a comment to D39304: [IR] redefine 'reassoc' fast-math-flag and add 'trans' fast-math-flag.

BTW, while writing the RFC, I realized that we could potentially generated incorrect code if we were silently downgrade a post-r317488 bitcode with a pre-r317488 compiler. (I.e., running fast math optimizations whereas we only wanted reassoc)

Feb 8 2018, 5:37 PM
qcolombet added a comment to D39304: [IR] redefine 'reassoc' fast-math-flag and add 'trans' fast-math-flag.

That's http://lists.llvm.org/pipermail/llvm-dev/2018-February/121114.html

Feb 8 2018, 5:35 PM
qcolombet added a comment to D39304: [IR] redefine 'reassoc' fast-math-flag and add 'trans' fast-math-flag.

I think we have to create a new version of the IR since the bits changed meaning (we can't just flip 'on' new bits).

Feb 8 2018, 4:56 PM
qcolombet added a comment to D39304: [IR] redefine 'reassoc' fast-math-flag and add 'trans' fast-math-flag.

Hi Sanjay,

Feb 8 2018, 3:44 PM
qcolombet resigned from D41762: [DWARF] Incorrect prologue end line record..

For the review itself, I leave this to @aprantl. I was just providing insights on the shrink-wrapping question :).

Feb 8 2018, 9:28 AM

Feb 6 2018

qcolombet accepted D42984: GlobalISel: Always check operand types when executing match table.

LGTM

Feb 6 2018, 4:43 PM

Feb 5 2018

qcolombet added a comment to D42877: [GlobalISel] Print/Parse FailedISel MachineFunction property.

Hi Roman.

Feb 5 2018, 10:17 AM

Feb 2 2018

qcolombet accepted D42861: [ReleaseNotes] Add note for enabling GlobalISel for AArch64 -O0.

LGTM

Feb 2 2018, 1:00 PM
qcolombet accepted D42860: [ReleaseNotes] Add note for the new -fexperimental-isel flag..

LGTM

Feb 2 2018, 1:00 PM
qcolombet accepted D42832: [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy..

One question below.

Feb 2 2018, 9:31 AM
qcolombet accepted D37775: Add a verifier test to check the access on both sides of COPY are the same.

LGTM, coordinate with the x86 changes and you should be good to go!

Feb 2 2018, 9:27 AM

Feb 1 2018

qcolombet added inline comments to D42667: SplitKit: Fix liveness recomputation in some remat cases..
Feb 1 2018, 11:08 AM
qcolombet accepted D42697: [GlobalISel] Constrain the dest reg of IMPLICT_DEF.

While I was here, I notice that selectCopy was not using getRegClassForTypeOnBank. Could you double check this is intended?

Feb 1 2018, 11:07 AM
qcolombet accepted D42667: SplitKit: Fix liveness recomputation in some remat cases..

LGTM with the nitpicks mentioned by Krzysztof.

Feb 1 2018, 10:48 AM

Jan 31 2018

qcolombet accepted D42103: [LSR] Don't force bases of foldable formulae to the final type..

LGTM

Jan 31 2018, 10:15 AM

Jan 30 2018

qcolombet added a comment to D42600: [WIP][Shrink-wrap]split restore point.

Just two remarks:

  • So far shrink-wrapping was solely an analysis pass, i.e., it didn't modify the input code
  • Ideally I'd like we postpone creating new blocks until we decided where we are going to insert the code, otherwise we'll end up with blocks to clean-up later on
Jan 30 2018, 5:10 PM
qcolombet added a comment to D41585: [Greedy RegAlloc] Take into account the cost of local intervals when selecting split candidate..

Ah makes sense.

Jan 30 2018, 9:56 AM
qcolombet added a comment to D42103: [LSR] Don't force bases of foldable formulae to the final type..

Let's leave the patch as is.

Jan 30 2018, 9:53 AM

Jan 29 2018

qcolombet accepted D42103: [LSR] Don't force bases of foldable formulae to the final type..

Alright, LGTM then.
Please also patches the two other places I mentioned assuming you can have a test case for them.

Jan 29 2018, 4:16 PM
qcolombet committed rL323710: [RAFast] Don't dereference MBB::end.
[RAFast] Don't dereference MBB::end
Jan 29 2018, 3:44 PM
qcolombet accepted D42565: [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern.

Got a chat with Roman off-line and turns out the problem I mentioned is worked around by everything single target, so indeed no test cases!
LGTM then

Jan 29 2018, 12:03 PM
qcolombet accepted D42607: [LoopStrengthReduce, x86] don't add cost for a cmp that will be macro-fused (PR35681).

Couple of nits on the test case.

Jan 29 2018, 11:02 AM

Jan 26 2018

qcolombet added inline comments to D42565: [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern.
Jan 26 2018, 5:17 PM