- User Since
- Dec 17 2012, 10:03 AM (381 w, 2 d)
Tue, Mar 31
Where do these patterns come from?
I would expect they would be eliminated by InstCombine in the IR.
Tue, Mar 10
Mar 9 2020
Feb 27 2020
Feb 26 2020
I understand that cross copies are bad, but what I don't understand is why don't we form an extended load? That would apply nicely to your example.
Something just stroke me, why don't you use the FPR bank for all 16-bit values then?
s16 operations, if legal, just get selected to gpr32 regclass instructions. E.g.
%ld:gpr(s16) = G_LOAD ... => %ld:gpr32 = LDR_16 ...
Thanks for the clarification Amara.
Feb 25 2020
Feb 24 2020
- Handle PhysReg and Non-SSA code in general
Here are a few examples of the dump we get:
- No Depth limit:
(lldb) p MI.dumpr(MRI, -1) %1:_(<4 x s16>) = G_BUILD_VECTOR %6:_(s16), %7:_(s16), %8:_(s16), %9:_(s16) %6:_(s16) = G_FPTRUNC %17:_(s32) %17:_(s32) = COPY $s0 %7:_(s16) = G_FPTRUNC %15:_(s32) %15:_(s32) = COPY $s0 %8:_(s16) = G_FPTRUNC %13:_(s32) %13:_(s32) = COPY $s0 %9:_(s16) = G_FPTRUNC %11:_(s32) %11:_(s32) = COPY $s0
- Use UINT_MAX instead of Optional to ease the use of the method in the debugger
- Use the dedicated formatted_raw_ostream to pad column
Feb 21 2020
Does that match your view of our conversation?
9708279c725..618dec2aeff master -> master
I've been concerned about the register live-ins too (I'm less concerned about the successors issue). Is there documentation on the original decision to disallow physical register live-ins for MBBs before register allocation? We could then check to see if we're violating the original reasoning.
- Use SmallDenseMap instead of DenseMap
I think the argument that because it's possible to do the wrong thing if you try hard enough that you have to protect against that is rather flawed and inconsistent with the existing code in LLVM.
That's true (although you'd need a third vreg with no defs/uses to do it) but as you say there's no reason to do so.
My long term plan for the intra/inter-pass cache is based about caching based on the register too.
Switch the caching to register instead of instruction.
Feb 20 2020
Feb 10 2020
Feb 5 2020
LGTM with a nit. Use a reference instead of a pointer (or check the pointer and fallback to the old addNewBlock when the pointer is nullptr)
Feb 3 2020
Jan 30 2020
Jan 27 2020
and having the builder silently ignore the explicitly setInsertPt. I think that behavior should be opt-in only to CSE, and obvious when it's being done.
Jan 24 2020
Thanks @arsenm for the review!
- Fix typo in comment
- Don't increase depth on COPYs
- Use Register instead of unsigned in added unitests
I do think copies should be ignored for depth. Other places generally try to treat intervening copies as irrelevant
Jan 23 2020
Jan 21 2020
Dec 16 2019
I would rather we keep it. Although like you said we could piggyback on addRegBankSelect, it is clearer to have a separate method and that's consistent with the other GISel passes.
Dec 5 2019
Dec 4 2019
Dec 3 2019
One nit below.
Dec 2 2019
Looks reasonable (haven't looked at the ARM part.)
The change in shrink wrapping doesn't look correct to me though. Is that particular change require?
Nov 21 2019
Nov 15 2019
Nov 13 2019
Nov 6 2019
Nov 4 2019
Are you planning on fixing the regression in the near future? If so splitting the patches this way seems fine
@arsenm ping^2 on the AMDGPU test changes.
Nov 1 2019
Thanks for the test case!
Oct 31 2019
For the test case, couldn't you add a isVariadic instruction with different patterns in one of the TableGen test?
Looks sensible to me.
Oct 30 2019
Oct 29 2019
@arsenm ping on the AMDGPU test changes.
Oct 28 2019
Thanks Philip for double checking.
Oct 25 2019
Oct 24 2019
I found a latent bug that has now more chances to trigger with the relaxations that this patch brings.
I've updated the patch to fix the bug, but I have now a bunch of "regressions" on AMDGPU test cases because the fix is too conservative.
Is this still okay to land?
- Fix a latent bug
- Update AMDGPU tests
Oct 23 2019
- Remove ADJUSTxxx operations in the tests
Oct 22 2019
Oct 21 2019
Thanks for the quick review @arsenm!
Oct 18 2019
Oct 17 2019
- Replace some unsigned into Register
This was just a patch to illustrate a possible direction.
Oct 16 2019
- Remove asserts already covered by the verifier
- Put .getType calls into a variable.
- Replace check with an assertion
- Update comments with pre-conditions