qcolombet (Quentin Colombet)
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User Since
Dec 17 2012, 10:03 AM (301 w, 17 h)

Recent Activity

Mon, Sep 17

qcolombet added a comment to D52061: [RegisterCoalescer] Only look at main ranges in valuesIdentical/followCopyChain.

But I still believe that trying to spot the identical case in subranges is pointless because we have already proved that the values are identical in main ranges. It is impossible for the values to be not identical in subranges; it's just a bit tricky to fix up the code to demonstrate that.

Mon, Sep 17, 9:30 AM
qcolombet added a comment to D52131: [GISel][NFC]: Make MachineIRBuilder fully stateless.

Hi Aditya,

Mon, Sep 17, 9:18 AM
qcolombet added a comment to D52127: [MF][MBB]: Add the ability to register callbacks for removal and insertion of MachineInstrs.

Hi Aditya,

Mon, Sep 17, 9:12 AM
qcolombet added a comment to D51849: [RegisterCoalescer] Avoid "Use not jointly dominated by defs" in removePartialRedundancy.

I finally tracked down why I couldn't get a mir test before: Compiling a ll file as usual, arriving at RegisterCoalescer, the numbering of the MBBs was not quite in order. Using -stop-before names the MBBs in the mir according to those out-of-order numbers, but reading the mir in again with -run-pass fails to preserve it. Instead it renumbers the MBBs in order. RegisterCoalescing processes MBBs with the same loop depth and critical edgeness and connectedness in numbering order, so the pass behaved differently.

Mon, Sep 17, 9:11 AM
qcolombet added a comment to D52052: [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled.

Could you elaborate on the exact constraints?

Mon, Sep 17, 9:05 AM · Restricted Project

Fri, Sep 14

qcolombet added a comment to D52061: [RegisterCoalescer] Only look at main ranges in valuesIdentical/followCopyChain.

The fix here is to only detect an "identical erase" in the main range.

Fri, Sep 14, 9:25 AM
qcolombet added a comment to D52052: [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled.

Could you elaborate on that part?

But it is not possible since can generate incorrect code in terms of exec mask.

Fri, Sep 14, 9:23 AM · Restricted Project

Thu, Sep 13

qcolombet added a comment to D51953: [GlobalISel] Add a new IR canonicalization pass.

FWIW, I am still not convince this is a good thing to match SDISel behavior at O0, but this is the least bad solution of doing that IMHO.

Thu, Sep 13, 10:12 AM
qcolombet added a comment to D52010: RegAllocFast: Rewrite and improve.

Hi Matthias,

Thu, Sep 13, 9:52 AM
qcolombet added inline comments to D51953: [GlobalISel] Add a new IR canonicalization pass.
Thu, Sep 13, 9:46 AM
qcolombet accepted D51953: [GlobalISel] Add a new IR canonicalization pass.

Hi Amara,

Thu, Sep 13, 9:46 AM

Tue, Sep 11

qcolombet added a comment to D51953: [GlobalISel] Add a new IR canonicalization pass.

Hi Amara,

Tue, Sep 11, 3:46 PM

Mon, Sep 10

qcolombet added a comment to D51849: [RegisterCoalescer] Avoid "Use not jointly dominated by defs" in removePartialRedundancy.

Unfortunately I can only reproduce this in an ll test. Turning it into a mir test makes the problem go away.

Mon, Sep 10, 8:40 AM
qcolombet added a comment to D51848: [RegisterCoalescer] Fixup "Fixed inconsistent followCopyChain with subreg".

Hi Tim,

Mon, Sep 10, 8:38 AM
qcolombet added a comment to D51574: [LiveRangeCalc] Fixed findReachingDefs bug.

Hi Tim,

Mon, Sep 10, 8:34 AM

Wed, Sep 5

qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

If we agree that an input canonicalization pass is needed then doing this there adds much less complexity than teaching tablegen that G_ICMPs are special (or somehow adding legalisation rules to tablegen?).

Wed, Sep 5, 8:22 AM

Fri, Aug 31

qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

So overall I think we should have some form of IR canonicalization before translation for the majority of cases to be handled for -O0.

Fri, Aug 31, 10:19 AM
qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

It can't do that all the time, with these G_ICMPs for example it also has to swap the predicate (not that we even have imported patterns that could possibly match for AArch64).

Fri, Aug 31, 10:19 AM

Thu, Aug 30

qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

Going back to a higher-level description for all that stuff, I wonder if ISel could already handle this.

Thu, Aug 30, 10:06 AM
qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

how would it decide in which order to put those vregs in the generated instructions w/o explicitly checking for constants?

Thu, Aug 30, 9:09 AM
qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

Does that mean that something after the last InstCombine produces icmp's with the non-canonical operand order? If so maybe that something needs to be chased down and fixed instead.

Thu, Aug 30, 8:50 AM

Wed, Aug 29

qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

I agree with the motivation but I don’t think this is the right approach. I would prefer we run a canonicalization step even at O0 before GISel rather than duplicating this logic between IR and MI.
Jump tables are a different beast and have their place in here because they don’t really make sense to do on IR.

Wed, Aug 29, 8:44 AM

Tue, Aug 28

qcolombet added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

Hi Amara,

Tue, Aug 28, 5:36 PM

Aug 13 2018

qcolombet accepted D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.

Thanks for your patience.
LGTM.
One final nit below. Feel free to commit directly.

Aug 13 2018, 9:28 AM

Aug 8 2018

qcolombet added inline comments to D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.
Aug 8 2018, 2:46 PM

Aug 6 2018

qcolombet added inline comments to D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.
Aug 6 2018, 5:17 PM
qcolombet added a comment to D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.

To be more precise, the latest promotion should be correct, but if we want the full information of multiple extension, the current patch is I believe wrong.
E.g., zext (sext i8 to i16) to i32, doesn't give you the same warranties on the bit pattern than what zext i8 to i32 gives, whereas we won't be able to see that.

Aug 6 2018, 5:15 PM
qcolombet added a comment to D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.

To be more precise, the latest promotion should be correct, but if we want the full information of multiple extension, the current patch is I believe wrong.
E.g., zext (sext i8 to i16) to i32, doesn't give you the same warranties on the bit pattern than what zext i8 to i32 gives, whereas we won't be able to see that.

Aug 6 2018, 5:14 PM
qcolombet added a comment to D49512: [CodeGenPrepare] Add BothExtension type to PromotedInsts.

Shouldn't we keep only the latest type and kind of extension?

Aug 6 2018, 5:09 PM
qcolombet accepted D49913: Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructions.

LGTM.
Nitpicks on the comments.

Aug 6 2018, 4:38 PM

Jul 24 2018

qcolombet accepted D49735: [RegisterBankInfo] Ignore InstrMappings that create impossible to repair operands.

Silly me for not catching this during the first review.

Jul 24 2018, 11:56 AM

Jul 20 2018

qcolombet added a comment to D35481: Fix documentation of MachineInstr::getNumOperands.

Good catch!

Jul 20 2018, 5:20 PM

Jun 18 2018

qcolombet added a comment to D47999: MIR YAML TracksRegLiveness default to true in yaml parser.

Either changing the default (trackLiveness == true by default) or printing it is fine.

Jun 18 2018, 8:35 AM

Jun 15 2018

qcolombet added a comment to D41098: [InlineSpiller] Fix a crash due to lack of forward progress from remat.

Are you okay with us solving this just for STATEPOINTs at the moment by essentially just disabling remats for STATEPOINT uses?

Jun 15 2018, 9:31 AM
qcolombet added a comment to D47999: MIR YAML TracksRegLiveness default to true in yaml parser.

Hi Puyan,

Jun 15 2018, 8:58 AM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Hi Konstantin,

Jun 15 2018, 8:57 AM

May 25 2018

qcolombet added a comment to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..

Do you agree we could drop this patch?

May 25 2018, 8:48 AM

May 24 2018

qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

With the test case fixed

May 24 2018, 11:24 AM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Up to you for the logging. We can keep it.

May 24 2018, 11:21 AM

May 23 2018

qcolombet updated subscribers of D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Doesn't the target already do this? At least there's a CoveredBySubRegs flag in the Register .td class ...

May 23 2018, 1:09 PM
qcolombet accepted D46809: [GlobalISel] NFCI, Getting GlobalISel ~5% faster.
May 23 2018, 12:49 PM

May 22 2018

qcolombet accepted D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.
May 22 2018, 6:24 PM

May 18 2018

qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Would it work to instead use RegUnits, so that we first collect all saved/restored RegUnits, and then check which registers have all their RegUnits saved?

May 18 2018, 2:56 PM
qcolombet accepted D43982: [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank.
May 18 2018, 2:43 PM
qcolombet accepted D46640: [GlobalMerge] Exit early if only one global is to be merged.
May 18 2018, 2:38 PM
qcolombet added a comment to D46809: [GlobalISel] NFCI, Getting GlobalISel ~5% faster.

Nice finding Roman.

May 18 2018, 2:37 PM
qcolombet added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

As you can see I left VMOVRRD ARM instruction as FIXME since it is more complicated copy.

May 18 2018, 1:58 PM

May 15 2018

qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

E.g., on x86 saving xmm0 is not enough to say that ymm0 is preservered even if ymm0 doesn’t have any other sub reg.

May 15 2018, 4:29 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Just reread what you said, you indeed want the other way.
The problem is that the big register is not necessarily covered by the sub regs. So you have to check for that.

May 15 2018, 4:27 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

I was thinking about this the other way around: if all the subreg of a register are saved that doesn’t imply the register itself is saved.
The way you describe with adding the sub regs works great. I thought you wanted the other way :P

May 15 2018, 4:25 PM
qcolombet added inline comments to D46640: [GlobalMerge] Exit early if only one global is to be merged.
May 15 2018, 4:21 PM

May 11 2018

qcolombet updated subscribers of D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.

Yes, please remove these.

May 11 2018, 3:05 PM
qcolombet added a comment to D46640: [GlobalMerge] Exit early if only one global is to be merged.

Looks sensible to me.

May 11 2018, 3:00 PM
qcolombet accepted D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 11 2018, 12:50 PM
qcolombet added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

The general direction makes sense and I agree you probably don't want to implement the full isEquivalentTo stuff I was talking about.
A general pointer you might have missed. We already track copy like instructions through isRegSequenceLike, isExtractSubRegLike and so on. These are more complicated than just plain copies though (e.g., VMOVRRD should already be supported).

May 11 2018, 12:50 PM
qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

This loop (per what determineCalleeSaves does) will only add any of the registers that getCalleeSavedRegs() returns

May 11 2018, 12:31 PM

May 7 2018

qcolombet accepted D46490: [MachineVerifier][GlobalISel] Verifying generic extends and truncates.
May 7 2018, 12:59 PM
qcolombet accepted D46455: [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all vregs.

Nice!

May 7 2018, 12:54 PM
qcolombet added inline comments to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 7 2018, 12:50 PM
qcolombet accepted D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

Thanks for your patience, LGTM.

May 7 2018, 12:50 PM
qcolombet accepted D46039: Fix compile time hang in LSR.

LGTM with the nits fixed

May 7 2018, 12:43 PM
qcolombet requested changes to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Thanks for double checking. Now, I don't think some part of the patch makes sense. See my inline comment.
Basically, we should have to augment whatever determineCalleeSaved gives us, otherwise that means this information is just flawed.

May 7 2018, 12:40 PM

May 4 2018

qcolombet added inline comments to D46039: Fix compile time hang in LSR.
May 4 2018, 9:02 AM
qcolombet added a comment to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..

Good catch!

May 4 2018, 8:59 AM
qcolombet accepted D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Hi Jonas,

May 4 2018, 8:55 AM
qcolombet added a comment to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.

With not llc you can still check specifics in FileCheck whereas with XFAIL you usually don't put checks at all.
In this case, I would expect a not llc + filecheck of some error message.

May 4 2018, 8:44 AM

May 3 2018

qcolombet added inline comments to D46339: [GlobalISel][Legalizer] LegalizerInfo verifier: Follow Up.
May 3 2018, 5:01 PM
qcolombet added a comment to D46338: [GlobalISel][Legalizer] LegalizerInfo verifier: checking that legalization rules cover all type indices.

Couple of nits on the tests.

May 3 2018, 4:57 PM
qcolombet accepted D46284: [MachineLICM] Debug intrinsics shouldn't affect hoist decisions.

LGTM

May 3 2018, 4:29 PM
qcolombet added a comment to D46315: [RegUsageInfoCollector] Fix handling of callee saved registers with CSR optimization..

Hi Jonas,

May 3 2018, 4:24 PM
qcolombet accepted D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..
May 3 2018, 3:52 PM
qcolombet accepted D45157: [RegUsageInfoCollector] Don't assume the alias of a defined reg is always already in the set..

You're right, re-reading the comment indeed, not all the aliases are here (nor should they be!).

May 3 2018, 3:48 PM
qcolombet added a comment to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

The new result isn't better than old result, neither worse. Do you think we should do transformation on this test case?

May 3 2018, 3:44 PM

Apr 27 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 27 2018, 5:17 PM
qcolombet accepted D46078: [MIR] Reset unique MBB numbering in MachineFunction::reset().
Apr 27 2018, 5:08 PM

Apr 24 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 24 2018, 5:04 PM

Apr 23 2018

qcolombet added inline comments to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.
Apr 23 2018, 4:04 PM
qcolombet accepted D44700: [GlobalISel] Improving InstructionSelect's performance by reducing MatchTable.

Hi Roman,

Apr 23 2018, 2:01 PM
qcolombet added inline comments to D45156: [MachineVerifier] Verify the RegUsageInfo collected for the current function..
Apr 23 2018, 1:51 PM
qcolombet added a comment to D45157: [RegUsageInfoCollector] Don't assume the alias of a defined reg is always already in the set..

I am not sure I like the patch in the sense that the comment for UsedPhysRegsMask (in ’MachineRegisterInfo.h) explicitly said that it should contain all the aliases.

Apr 23 2018, 1:44 PM
Herald added a reviewer for D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg': javed.absar.

A while back, with Hal, we talked about having something like:
bool TargetInstrInfo::isEquivalentTo(GenericOpcode, ExpectedOperand)

Apr 23 2018, 1:31 PM
qcolombet accepted D45817: [PostRASink] extend the live-in check for all aliased registers.

LGTM with small nits.

Apr 23 2018, 1:23 PM
qcolombet added a comment to D45968: StackSlotColoring: Decide colors per stack ID.

Disclaimer: I haven't never looked at how this pass actually works so take my comments with a grain of salt!

Apr 23 2018, 1:15 PM
qcolombet added a comment to D45537: [CodeGenPrepare] Move Extension Instructions Through Logical And Shift Instructions.

High level comment to help me dive into your changes.
See inlined.

Apr 23 2018, 1:09 PM
qcolombet committed rL330631: [CODE_OWNERS] Update my email address..
[CODE_OWNERS] Update my email address.
Apr 23 2018, 12:14 PM

Mar 22 2018

qcolombet added a comment to D44304: [MIPS GlobalISel] Select add i32, i32.

Do you have any comments on the regbankselect part?

Mar 22 2018, 10:20 AM

Mar 19 2018

qcolombet committed rL327942: [ShrinkWrap] Take into account landing pad.
[ShrinkWrap] Take into account landing pad
Mar 19 2018, 7:47 PM

Mar 14 2018

qcolombet accepted D43353: [X86] Add phony registers for high halves of E[A-D]X, E[SD]I, E[BS]P and EIP.

Hi Krzysztof,

Mar 14 2018, 9:12 PM
qcolombet added a comment to D43093: [FastISel] Sink local value materializations to first use.

FWIW, LGTM now.

Mar 14 2018, 9:02 PM

Mar 5 2018

qcolombet added a comment to D43353: [X86] Add phony registers for high halves of E[A-D]X, E[SD]I, E[BS]P and EIP.

Hi Krzysztof,

Mar 5 2018, 3:55 PM

Feb 27 2018

qcolombet added a comment to D43093: [FastISel] Sink local value materializations to first use.

Hi Reid,

Feb 27 2018, 1:29 PM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Hi Konstantin,

Feb 27 2018, 10:15 AM
qcolombet added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

The %1 assignment is dead but not marked as such. I'm not 100% sure whether it is allowed to omit dead flags.

Feb 27 2018, 10:15 AM

Feb 26 2018

qcolombet accepted D43409: [GISel]: Don't assert when constraining Registers which are uses if there's no regclass..
Feb 26 2018, 9:30 AM
qcolombet added a comment to D43409: [GISel]: Don't assert when constraining Registers which are uses if there's no regclass..

Any chance you could add a test case?

Feb 26 2018, 9:29 AM

Feb 21 2018

qcolombet accepted D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

Hi Geoff,

Feb 21 2018, 1:03 PM
qcolombet added inline comments to D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
Feb 21 2018, 10:50 AM

Feb 16 2018

qcolombet added a comment to D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes.

FYI, I've revert the original commit in r325421.

Feb 16 2018, 7:15 PM
qcolombet committed rL325421: Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding".
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Feb 16 2018, 7:08 PM
qcolombet accepted D43270: [GISel][Tablegen]: Make GlobalISelEmitter rule prioritization similar to that of selectionDAG.

Hi Aditya,

Feb 16 2018, 1:24 PM