Mostly LLVM work.
- User Since
- Nov 2 2018, 7:48 AM (45 w, 4 d)
Rebased on master.
Refresh patch before committing.
Sun, Sep 15
@dsanders I agree that this patch addresses a real problem, and that there is currently a generalized lack of target-specific checks. AMDGPU seems to be the target with the most comprehensive set of checks (although I think it's mostly in the S.I. subtarget). Inspired by this patch we also submitted a patch to verify the immediates of MachineInstrs for the RISC-V target (D67397). The fact that invalid immediate operands just get silently processed (emitted in asm form, truncated in obj form) in nearly all targets is a good indicator that there is space for improvements, and that unrelated changes at any point might reveal latent bugs. Hopefully having more of this infrastructure in place will further encourage targets to add more checks. Still, I'm not sure adding a pass is the best way to accomplish this.
Fri, Sep 13
Thu, Sep 12
- Changes the FPRs Register identifiers, to ensure sequential enumeration:
- F0_32-F31_32 -> F0_F-F31_F
- F0_64-F31_64 -> F0_D-F31_D
- These were chosen instead of Fxx/Dxx to better match the ISA spec names, although both options were reasonable.
- Now makes straighforward use of FPR Register arithmetic.
- Adds static asserts regarding the register ordering.
- Updates the FPR register matching, since the tablegen matches now default to the 64-bit regs.
- Tightens some RegNo bounds checks that were too loose on master.
- Updates the title to reflect the changed scope of the patch.
Wed, Sep 11
Adds a MIR test. Changes the operand enum to a new namespace.
Tue, Sep 10
Wed, Sep 4
Added a test. Updated summary.
Sat, Aug 31
Fri, Aug 30
Rebased on master.
Thu, Aug 29
Wed, Aug 28
The main concerns have been addressed.
LGTM, assuming the typo in the comment is fixed.
Tue, Aug 27
Adds nounwind attribute to the RISC-V tests.
Mon, Aug 26
Sun, Aug 25
Wed, Aug 21
Tue, Aug 20
Overall LGTM. Can be merged after fixing at least the typo.
Mon, Aug 19
Aug 16 2019
Updated patch, marking comment as done.
Remove extraneous Register.h include.
Aug 15 2019
LGTM with the latest changes.
Convert RISCVOperand::KindTy from an enum to an enum class, to avoid collisions with Register.
Aug 14 2019
Aug 13 2019
Adds MC layer support, using the approach suggested by Shiva (thanks!), and updates the tests to test that additional support.
Updates the summary, so it no longer says MC layer support is missing.
Aug 12 2019
Jul 2 2019
Jun 25 2019
Jun 18 2019
Jun 17 2019
Jun 7 2019
Addresses the remaining review concerns.