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luismarques (Luís Marques)
Software/hardware engineer at lowRISC

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User Details

User Since
Nov 2 2018, 7:48 AM (45 w, 4 d)

Mostly LLVM work.

Recent Activity

Today

luismarques committed rG6cf896b284bb: [RISCV][NFC] Use NoRegister instead of 0 literal (authored by luismarques).
[RISCV][NFC] Use NoRegister instead of 0 literal
Tue, Sep 17, 6:33 AM
luismarques committed rL372120: [RISCV][NFC] Use NoRegister instead of 0 literal.
[RISCV][NFC] Use NoRegister instead of 0 literal
Tue, Sep 17, 6:32 AM
luismarques closed D67526: [RISCV][NFC] Use NoRegister instead of 0 literal.
Tue, Sep 17, 6:32 AM · Restricted Project
luismarques updated the diff for D67526: [RISCV][NFC] Use NoRegister instead of 0 literal.

Rebased on master.

Tue, Sep 17, 6:25 AM · Restricted Project
luismarques committed rG3d0fbafd0bce: [RISCV] Switch to the Machine Scheduler (authored by luismarques).
[RISCV] Switch to the Machine Scheduler
Tue, Sep 17, 4:15 AM
luismarques committed rL372106: [RISCV] Switch to the Machine Scheduler.
[RISCV] Switch to the Machine Scheduler
Tue, Sep 17, 4:14 AM
luismarques committed rG2d550d19b321: Revert Patch from Phabricator (authored by luismarques).
Revert Patch from Phabricator
Tue, Sep 17, 3:55 AM
luismarques committed rL372104: Revert Patch from Phabricator.
Revert Patch from Phabricator
Tue, Sep 17, 3:51 AM
luismarques committed rGe38695a0255c: Patch from Phabricator (authored by luismarques).
Patch from Phabricator
Tue, Sep 17, 2:44 AM
luismarques committed rL372092: Patch from Phabricator.
Patch from Phabricator
Tue, Sep 17, 2:44 AM

Yesterday

luismarques created D67640: [RISCV] Fix static analysis issues.
Mon, Sep 16, 4:24 PM · Restricted Project
luismarques updated the diff for D66973: [RISCV] Switch to the Machine Scheduler.

Refresh patch before committing.

Mon, Sep 16, 8:00 AM · Restricted Project

Sun, Sep 15

luismarques added a comment to D64650: Add a TargetMachineVerifier that runs along with the existing MachineVerifier.

@dsanders I agree that this patch addresses a real problem, and that there is currently a generalized lack of target-specific checks. AMDGPU seems to be the target with the most comprehensive set of checks (although I think it's mostly in the S.I. subtarget). Inspired by this patch we also submitted a patch to verify the immediates of MachineInstrs for the RISC-V target (D67397). The fact that invalid immediate operands just get silently processed (emitted in asm form, truncated in obj form) in nearly all targets is a good indicator that there is space for improvements, and that unrelated changes at any point might reveal latent bugs. Hopefully having more of this infrastructure in place will further encourage targets to add more checks. Still, I'm not sure adding a pass is the best way to accomplish this.

Sun, Sep 15, 4:25 PM · Restricted Project

Fri, Sep 13

luismarques accepted D66870: [Sanitizers] Add support for RISC-V 64-bit.

LGTM.

Fri, Sep 13, 12:06 PM · Restricted Project, Restricted Project
luismarques updated the summary of D67423: [RISCV] Rename FPRs and use Register arithmetic.
Fri, Sep 13, 4:10 AM · Restricted Project
luismarques added inline comments to D67423: [RISCV] Rename FPRs and use Register arithmetic.
Fri, Sep 13, 4:09 AM · Restricted Project

Thu, Sep 12

luismarques created D67526: [RISCV][NFC] Use NoRegister instead of 0 literal.
Thu, Sep 12, 3:12 PM · Restricted Project
luismarques updated the diff for D67423: [RISCV] Rename FPRs and use Register arithmetic.
  • Changes the FPRs Register identifiers, to ensure sequential enumeration:
    • F0_32-F31_32 -> F0_F-F31_F
    • F0_64-F31_64 -> F0_D-F31_D
    • These were chosen instead of Fxx/Dxx to better match the ISA spec names, although both options were reasonable.
  • Now makes straighforward use of FPR Register arithmetic.
  • Adds static asserts regarding the register ordering.
  • Updates the FPR register matching, since the tablegen matches now default to the 64-bit regs.
  • Tightens some RegNo bounds checks that were too loose on master.
  • Updates the title to reflect the changed scope of the patch.
Thu, Sep 12, 11:47 AM · Restricted Project

Wed, Sep 11

luismarques updated the diff for D67397: [RISCV] Add MachineInstr immediate verification.

Adds a MIR test. Changes the operand enum to a new namespace.

Wed, Sep 11, 4:21 PM · Restricted Project
luismarques committed rL371651: Request commit access for luismarques.
Request commit access for luismarques
Wed, Sep 11, 12:59 PM

Tue, Sep 10

luismarques added inline comments to D67423: [RISCV] Rename FPRs and use Register arithmetic.
Tue, Sep 10, 5:54 PM · Restricted Project
luismarques added a comment to D67423: [RISCV] Rename FPRs and use Register arithmetic.

It's worth noting that other targets (Mips and Sparc) call their floating point registers F0-F31 and D0-D31 (and there's also Q0-Q31 for Sparc) even though they're always referred to as %fX in the assembly. That would be an alternative resolution to the sorting issue, that also feels less hacky/surprising compared with the numerical-vs-alphabetical ordering subtleties.

Tue, Sep 10, 5:45 PM · Restricted Project
luismarques created D67423: [RISCV] Rename FPRs and use Register arithmetic.
Tue, Sep 10, 5:13 PM · Restricted Project
luismarques updated the summary of D67397: [RISCV] Add MachineInstr immediate verification.
Tue, Sep 10, 9:34 AM · Restricted Project
luismarques added a comment to D67397: [RISCV] Add MachineInstr immediate verification.

Is there a way to write a test for this? I realise any assembly goes through the parser, so will be caught before it hits this code. Is there another way of making this work? a MIR-based test?

Tue, Sep 10, 9:34 AM · Restricted Project
luismarques created D67397: [RISCV] Add MachineInstr immediate verification.
Tue, Sep 10, 7:17 AM · Restricted Project

Wed, Sep 4

luismarques updated the diff for D67046: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook.

Added a test. Updated summary.

Wed, Sep 4, 9:05 AM · Restricted Project

Sat, Aug 31

luismarques created D67046: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook.
Sat, Aug 31, 3:50 PM · Restricted Project

Fri, Aug 30

luismarques updated the diff for D66973: [RISCV] Switch to the Machine Scheduler.

Rebased on master.

Fri, Aug 30, 8:47 AM · Restricted Project
luismarques added inline comments to D66870: [Sanitizers] Add support for RISC-V 64-bit.
Fri, Aug 30, 6:23 AM · Restricted Project, Restricted Project
luismarques committed rGc2b3d527fab3: [RISCV] Fix a couple of tests' CHECKs (authored by luismarques).
[RISCV] Fix a couple of tests' CHECKs
Fri, Aug 30, 5:12 AM
luismarques committed rL370466: [RISCV] Fix a couple of tests' CHECKs.
[RISCV] Fix a couple of tests' CHECKs
Fri, Aug 30, 5:10 AM

Thu, Aug 29

luismarques created D66973: [RISCV] Switch to the Machine Scheduler.
Thu, Aug 29, 1:31 PM · Restricted Project
luismarques committed rGcf3b39391efa: [RISCV] Fix callee-saved-gprs.ll test ABIs (authored by luismarques).
[RISCV] Fix callee-saved-gprs.ll test ABIs
Thu, Aug 29, 7:09 AM
luismarques committed rL370359: [RISCV] Fix callee-saved-gprs.ll test ABIs.
[RISCV] Fix callee-saved-gprs.ll test ABIs
Thu, Aug 29, 7:09 AM

Wed, Aug 28

luismarques added a comment to D64715: [WIP][RISCV] Use RISCV_32_PCREL reloc for FDE initial location.

@edward-jones Could you please mark this as abandoned, since is has been superseded by D66419?

Wed, Aug 28, 7:09 AM · Restricted Project
luismarques added inline comments to D66278: [RISCV] Enable tail call opt for variadic function.
Wed, Aug 28, 7:03 AM · Restricted Project
luismarques accepted D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

The main concerns have been addressed.
LGTM, assuming the typo in the comment is fixed.

Wed, Aug 28, 6:22 AM · Restricted Project
luismarques accepted D66591: [RISCV] Correct Logic around ilp32e macros.

LGTM.

Wed, Aug 28, 6:14 AM · Restricted Project, Restricted Project

Tue, Aug 27

luismarques added inline comments to D66725: [DAGCombiner][TargetLowering] Target hook for FCOPYSIGN arg cast folding.
Tue, Aug 27, 4:55 PM · Restricted Project
luismarques added inline comments to D66725: [DAGCombiner][TargetLowering] Target hook for FCOPYSIGN arg cast folding.
Tue, Aug 27, 4:46 PM · Restricted Project
luismarques updated the diff for D66725: [DAGCombiner][TargetLowering] Target hook for FCOPYSIGN arg cast folding.

Adds nounwind attribute to the RISC-V tests.

Tue, Aug 27, 4:46 PM · Restricted Project
luismarques committed rGc894c6c98335: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass (authored by luismarques).
[RISCV] Implement RISCVRegisterInfo::getPointerRegClass
Tue, Aug 27, 2:38 PM
luismarques committed rL370113: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.
[RISCV] Implement RISCVRegisterInfo::getPointerRegClass
Tue, Aug 27, 2:37 PM
luismarques closed D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.
Tue, Aug 27, 2:37 PM · Restricted Project
luismarques added a comment to D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.

Ok, cool. I'm happy for this to land without a testcase.

Tue, Aug 27, 6:23 AM · Restricted Project
luismarques added a comment to D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.

This should be causing an assert everywhere it's used right now, shouldn't it? I'm confused that we're not seeing any of those asserts/failures in our testcases.

Tue, Aug 27, 4:29 AM · Restricted Project

Mon, Aug 26

luismarques created D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.
Mon, Aug 26, 10:20 AM · Restricted Project

Sun, Aug 25

luismarques created D66725: [DAGCombiner][TargetLowering] Target hook for FCOPYSIGN arg cast folding.
Sun, Aug 25, 7:12 PM · Restricted Project

Wed, Aug 21

luismarques committed rGf7cdff4ffdc3: [RISCV] Remove fix introduced by r369573, superseded by r369580 (authored by luismarques).
[RISCV] Remove fix introduced by r369573, superseded by r369580
Wed, Aug 21, 3:12 PM
luismarques committed rL369590: [RISCV] Remove fix introduced by r369573, superseded by r369580.
[RISCV] Remove fix introduced by r369573, superseded by r369580
Wed, Aug 21, 3:09 PM
luismarques committed rG4f488b594ae1: [RISCV] Fix use of side-effects in asserts in decoder functions (authored by luismarques).
[RISCV] Fix use of side-effects in asserts in decoder functions
Wed, Aug 21, 2:13 PM
luismarques committed rL369580: [RISCV] Fix use of side-effects in asserts in decoder functions.
[RISCV] Fix use of side-effects in asserts in decoder functions
Wed, Aug 21, 2:13 PM
luismarques committed rGc3bf3d14ea66: [RISCV] Add support for RVC HINT instructions (authored by luismarques).
[RISCV] Add support for RVC HINT instructions
Wed, Aug 21, 7:02 AM
luismarques committed rL369528: [RISCV] Add support for RVC HINT instructions.
[RISCV] Add support for RVC HINT instructions
Wed, Aug 21, 7:02 AM
luismarques closed D62592: [RISCV] Add support for RVC HINT instructions.
Wed, Aug 21, 7:02 AM · Restricted Project
luismarques retitled D62592: [RISCV] Add support for RVC HINT instructions from [RISCV] Add assembler support for RVC HINT instructions to [RISCV] Add support for RVC HINT instructions.
Wed, Aug 21, 7:01 AM · Restricted Project

Tue, Aug 20

luismarques accepted D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.

Overall LGTM. Can be merged after fixing at least the typo.

Tue, Aug 20, 4:46 AM · Restricted Project
luismarques added inline comments to D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.
Tue, Aug 20, 4:42 AM · Restricted Project

Mon, Aug 19

luismarques added inline comments to D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V.
Mon, Aug 19, 5:03 AM · Restricted Project

Aug 16 2019

luismarques added inline comments to D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V.
Aug 16 2019, 3:58 PM · Restricted Project
luismarques requested changes to D62190: [RISCV] Allow shrink wrapping for RISC-V.
Aug 16 2019, 3:46 PM · Restricted Project
luismarques requested changes to D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V.
Aug 16 2019, 10:37 AM · Restricted Project
luismarques added a reviewer for D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V: luismarques.
Aug 16 2019, 8:44 AM · Restricted Project
luismarques committed rGfa06e95898bd: [RISCV] Convert registers from unsigned to Register (authored by luismarques).
[RISCV] Convert registers from unsigned to Register
Aug 16 2019, 7:29 AM
luismarques added a reviewer for D62190: [RISCV] Allow shrink wrapping for RISC-V: luismarques.
Aug 16 2019, 7:29 AM · Restricted Project
Herald updated subscribers of D62190: [RISCV] Allow shrink wrapping for RISC-V.
Aug 16 2019, 7:27 AM · Restricted Project
luismarques committed rL369114: [RISCV] Convert registers from unsigned to Register.
[RISCV] Convert registers from unsigned to Register
Aug 16 2019, 7:27 AM
luismarques closed D66252: [RISCV] Convert registers from unsigned to Register.
Aug 16 2019, 7:27 AM · Restricted Project
luismarques added a comment to D66252: [RISCV] Convert registers from unsigned to Register.

Updated patch, marking comment as done.

Aug 16 2019, 5:20 AM · Restricted Project
luismarques updated the diff for D66252: [RISCV] Convert registers from unsigned to Register.

Remove extraneous Register.h include.

Aug 16 2019, 5:20 AM · Restricted Project

Aug 15 2019

luismarques added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 15 2019, 2:05 PM · Restricted Project
luismarques accepted D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.

LGTM with the latest changes.

Aug 15 2019, 12:55 PM · Restricted Project
luismarques accepted D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.

LGTM.

Aug 15 2019, 9:22 AM · Restricted Project, Restricted Project
luismarques added inline comments to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Aug 15 2019, 8:52 AM · Restricted Project, Restricted Project
luismarques added inline comments to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Aug 15 2019, 8:48 AM · Restricted Project, Restricted Project
luismarques accepted D66139: [RISCV] Support llvm-objdump -M no-aliases and -M numeric.
Aug 15 2019, 6:48 AM · Restricted Project
luismarques accepted D66002: [RISCV] Move architecture parsing code into its own function.
Aug 15 2019, 6:04 AM · Restricted Project, Restricted Project
luismarques added a comment to D66002: [RISCV] Move architecture parsing code into its own function.

LGTM.

Aug 15 2019, 5:59 AM · Restricted Project, Restricted Project
luismarques updated the diff for D66252: [RISCV] Convert registers from unsigned to Register.

Convert RISCVOperand::KindTy from an enum to an enum class, to avoid collisions with Register.

Aug 15 2019, 5:09 AM · Restricted Project

Aug 14 2019

luismarques added inline comments to D65950: [RISCV] Add Option for Printing Architectural Register Names.
Aug 14 2019, 3:17 PM · Restricted Project
luismarques added a comment to D66139: [RISCV] Support llvm-objdump -M no-aliases and -M numeric.

LGTM.

Aug 14 2019, 2:54 PM · Restricted Project
luismarques created D66252: [RISCV] Convert registers from unsigned to Register.
Aug 14 2019, 1:27 PM · Restricted Project

Aug 13 2019

luismarques updated the diff for D62592: [RISCV] Add support for RVC HINT instructions.

Adds MC layer support, using the approach suggested by Shiva (thanks!), and updates the tests to test that additional support.
Updates the summary, so it no longer says MC layer support is missing.

Aug 13 2019, 4:53 PM · Restricted Project

Aug 12 2019

luismarques accepted D66081: [RISCV] Fix ICE in isDesirableToCommuteWithShift.
Aug 12 2019, 6:50 AM · Restricted Project
luismarques added a comment to D66081: [RISCV] Fix ICE in isDesirableToCommuteWithShift.

LGTM.

Aug 12 2019, 6:45 AM · Restricted Project

Jul 2 2019

luismarques added inline comments to D63415: [AsmPrinter] Make the encoding of call sites in .gcc_except_table configurable.
Jul 2 2019, 4:06 AM · Restricted Project

Jun 25 2019

luismarques added a comment to D63411: [RISCV] Specify registers used in DWARF exception handling.
In D63411#1551719, @asb wrote:

Thanks for the patch! Do you have a reference for these being the appropriate values?

Jun 25 2019, 9:57 AM · Restricted Project

Jun 18 2019

luismarques added inline comments to D63433: [RISCV] Add RISCV-specific TargetTransformInfo.
Jun 18 2019, 2:26 AM · Restricted Project

Jun 17 2019

luismarques added inline comments to D62592: [RISCV] Add support for RVC HINT instructions.
Jun 17 2019, 6:57 AM · Restricted Project
luismarques committed rG2e46312ffd16: [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting (authored by luismarques).
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
Jun 17 2019, 3:52 AM
luismarques committed rL363544: [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting.
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
Jun 17 2019, 3:51 AM
luismarques closed D60294: [DAGCombiner] [CodeGenPrepare] Split large offsets from base addresses.
Jun 17 2019, 3:51 AM · Restricted Project

Jun 7 2019

luismarques updated the diff for D60294: [DAGCombiner] [CodeGenPrepare] Split large offsets from base addresses.

Addresses the remaining review concerns.

Jun 7 2019, 6:44 AM · Restricted Project

Jun 6 2019

luismarques committed rG711f36159695: [RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built (authored by luismarques).
[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built
Jun 6 2019, 3:12 AM
luismarques committed rL362693: [RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built.
[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built
Jun 6 2019, 3:11 AM
luismarques added inline comments to D61185: [RISCV] Add CostModel GEP tests.
Jun 6 2019, 2:50 AM · Restricted Project
luismarques committed rGcff7d2fdc9ef: [RISCV] Add CostModel GEP tests (authored by luismarques).
[RISCV] Add CostModel GEP tests
Jun 6 2019, 2:46 AM
luismarques committed rL362691: [RISCV] Add CostModel GEP tests.
[RISCV] Add CostModel GEP tests
Jun 6 2019, 2:45 AM
luismarques closed D61185: [RISCV] Add CostModel GEP tests.
Jun 6 2019, 2:45 AM · Restricted Project