Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

wangpc (Wang Pengcheng)
User

Projects

User does not belong to any projects.

User Details

User Since
Dec 15 2021, 8:11 AM (92 w, 4 d)

Recent Activity

Tue, Sep 19

wangpc committed rG61d819dd52f8: [RISCV] Add tests for memory constraint A (authored by wangpc).
[RISCV] Add tests for memory constraint A
Tue, Sep 19, 4:56 AM · Restricted Project, Restricted Project
wangpc closed D159530: [RISCV] Add tests for memory constraint A.
Tue, Sep 19, 4:56 AM · Restricted Project, Restricted Project
wangpc updated the summary of D159530: [RISCV] Add tests for memory constraint A.
Tue, Sep 19, 4:49 AM · Restricted Project, Restricted Project
wangpc updated the diff for D159530: [RISCV] Add tests for memory constraint A.

Remove nonnull and inbounds.

Tue, Sep 19, 4:49 AM · Restricted Project, Restricted Project

Mon, Sep 18

wangpc updated the diff for D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.
  • Rebase.
  • Don't optimize for constraint A.
Mon, Sep 18, 10:38 PM · Restricted Project, Restricted Project
wangpc requested review of D159530: [RISCV] Add tests for memory constraint A.
Mon, Sep 18, 10:25 PM · Restricted Project, Restricted Project
wangpc added inline comments to D154576: [RISCV] RISCV vector calling convention (1/2).
Mon, Sep 18, 10:19 PM · Restricted Project, Restricted Project, Restricted Project

Sun, Sep 17

wangpc updated the diff for D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs.
  • Rebase.
  • Address comments.
  • Add ReleaseNotes.
Sun, Sep 17, 11:32 PM · Restricted Project, Restricted Project, Restricted Project
wangpc committed rGcedf2ea7b50f: [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress (authored by wangpc).
[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress
Sun, Sep 17, 8:47 PM · Restricted Project, Restricted Project
wangpc closed D159429: [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress.
Sun, Sep 17, 8:47 PM · Restricted Project, Restricted Project
wangpc committed rG28efe4d38ece: [RISCV] Add tests for merging base offset of BlockAddress (authored by wangpc).
[RISCV] Add tests for merging base offset of BlockAddress
Sun, Sep 17, 8:47 PM · Restricted Project, Restricted Project
wangpc closed D159428: [RISCV] Add tests for merging base offset of BlockAddress.
Sun, Sep 17, 8:47 PM · Restricted Project, Restricted Project

Mon, Sep 11

wangpc planned changes to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

We may not need this.

Mon, Sep 11, 11:16 PM · Restricted Project, Restricted Project
wangpc added a comment to D159429: [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress.

Ping.

Mon, Sep 11, 11:11 PM · Restricted Project, Restricted Project
wangpc added a comment to D159428: [RISCV] Add tests for merging base offset of BlockAddress.

Ping.

Mon, Sep 11, 11:11 PM · Restricted Project, Restricted Project

Thu, Sep 7

wangpc committed rGb0ea2790c41d: [ASTImport]CXXBoolLiteralExpr should be handled explicitly in statement… (authored by jcsxky).
[ASTImport]CXXBoolLiteralExpr should be handled explicitly in statement…
Thu, Sep 7, 11:58 PM · Restricted Project, Restricted Project
wangpc closed D159479: [ASTImport]CXXBoolLiteralExpr should be handled explicitly in statement comparation.
Thu, Sep 7, 11:57 PM · Restricted Project, Restricted Project, Restricted Project

Wed, Sep 6

wangpc updated the diff for D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.

Rename sew_div_8 to sewDividedBy8.

Wed, Sep 6, 1:19 AM · Restricted Project, Restricted Project
wangpc added a comment to D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.

I wonder if it would be a good idea to add a function getSEW(MachineInstr) which gets the SEW from the Opcode or from the Operand, depending on how the pseudo tracks SEW. This indirection would remove the complication of having inconsistent pseudos. WDYT?

Wed, Sep 6, 1:00 AM · Restricted Project, Restricted Project
wangpc updated the summary of D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.
Wed, Sep 6, 12:57 AM · Restricted Project, Restricted Project
wangpc updated the diff for D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.

Rebase and do some refactors.

Wed, Sep 6, 12:57 AM · Restricted Project, Restricted Project

Tue, Sep 5

wangpc accepted D159431: [RISCV] adjust first sp size to use c.addi16sp..

LGTM.

Tue, Sep 5, 9:18 PM · Restricted Project, Restricted Project
wangpc retitled D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos from [WIP][RISCV] Remove SEW operand for SEW-aware pseudos to [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.
Tue, Sep 5, 7:22 AM · Restricted Project, Restricted Project
wangpc updated the diff for D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.

Resolved all issues.

Tue, Sep 5, 7:20 AM · Restricted Project, Restricted Project

Mon, Sep 4

wangpc abandoned D159427: [InlineAsm] Add constraint A to getMemConstraintName.

Closed as I want to use this patch to be familiar with Github workflow(https://github.com/llvm/llvm-project/pull/65292).
Thanks all!

Mon, Sep 4, 9:22 PM · Restricted Project, Restricted Project
wangpc requested review of D159427: [InlineAsm] Add constraint A to getMemConstraintName.
Mon, Sep 4, 6:23 AM · Restricted Project, Restricted Project
wangpc requested review of D159429: [RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress.
Mon, Sep 4, 6:23 AM · Restricted Project, Restricted Project
wangpc requested review of D159428: [RISCV] Add tests for merging base offset of BlockAddress.
Mon, Sep 4, 6:23 AM · Restricted Project, Restricted Project
wangpc added a comment to D159427: [InlineAsm] Add constraint A to getMemConstraintName.

Oops, we should have fixed it in D124431. Sorry @Jim, I didn't know it.

Mon, Sep 4, 5:56 AM · Restricted Project, Restricted Project
wangpc added a reviewer for D159427: [InlineAsm] Add constraint A to getMemConstraintName: Jim.
Mon, Sep 4, 5:54 AM · Restricted Project, Restricted Project
wangpc added a comment to D158568: [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics.

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

You can watch the talk that describes what StartAtCycle (which became AcquireAtCycle) is for: https://www.youtube.com/watch?v=XWBVLcdzmFg

Mon, Sep 4, 4:54 AM · Restricted Project, Restricted Project

Sat, Sep 2

wangpc added a comment to D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs.

I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please?

The patch is simple enough to not become a maintenance burden, and GCC already has it even though the ABI's unfinished, and the RV32E target itself is most likely going to be used for standalone bare metal programs where the exact ABI shouldn't matter too much as long as it works.

I'm asking because I'd really like to have this merged so that I could use Rust to target RV32E/RV64E. Right now I have to maintain my own toolchain, which is painful; if this got merged (even in an experimental fashion, like GCC has) I could just get upstream Rust to support it out-of-box.

Sat, Sep 2, 7:52 AM · Restricted Project, Restricted Project, Restricted Project

Fri, Sep 1

wangpc added a comment to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

Yes, the size will increase about 100KB for llc.
My intention is to unify the table (and make the code more consistent?). And if we can get SEW of pseudos from this table, then we don't need to specify the explict SEW imm in pseudos' operands (WIP).
For example:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
                  ixlenimm:$policy), []>

becomes:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
                  ixlenimm:$policy), []>,

This may simplify the generated patterns I think.

Won't that require adding more pseudos for each SEW. Many pseudos don't have SEW today.

I think almost all pseudos has HasSEWOp being true?
Edit: I get it. I won't add more pseduos, but remove the SEW operand for existed pseudos.

So there will 2 kinds of pseudos? Those with SEW in their name and those with an SEW operand?

Yes.
I just tried, if we remove the SEW operand of SEW-aware pseudos (load/store instructions are excluded in my experiment currently) operands and search SEW by RISCVVPseudosTable, we can reduce 30K of llc's text section and about 6000 lines of RISCVGenDAGISel.inc. But it will also add some complexities and make the RVV pseudos inconsistent.
I may post the patch after more investigations next week.

Posted in D159368.

Where does the 30K text section reduction come from? What code are we reducing?

There should be a comment in RISCVGenDAGISel.inc that says "Total Array size is" can give the reduction on that value. That's more interesting than lines.

Because we don't need to match and add SEW operand, the size of MatcherTable can be reduced by about 23000 bytes, I think most of the reduction comes from here. RISCVGenInstrInfo has some reductions too.
My proposal is removing SEW operand of load/store instructions and SEW-aware instrucitons like reductions, div, sqrt, etc. And the SEW value can searched by RISCVVPseudosTable (or, we can encode it in TSFlags like LMUL by using 2bits).

Is the matcher table in the .text section?

Fri, Sep 1, 10:40 AM · Restricted Project, Restricted Project
wangpc updated the summary of D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.
Fri, Sep 1, 10:34 AM · Restricted Project, Restricted Project
wangpc added a comment to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

Yes, the size will increase about 100KB for llc.
My intention is to unify the table (and make the code more consistent?). And if we can get SEW of pseudos from this table, then we don't need to specify the explict SEW imm in pseudos' operands (WIP).
For example:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
                  ixlenimm:$policy), []>

becomes:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
                  ixlenimm:$policy), []>,

This may simplify the generated patterns I think.

Won't that require adding more pseudos for each SEW. Many pseudos don't have SEW today.

I think almost all pseudos has HasSEWOp being true?
Edit: I get it. I won't add more pseduos, but remove the SEW operand for existed pseudos.

So there will 2 kinds of pseudos? Those with SEW in their name and those with an SEW operand?

Yes.
I just tried, if we remove the SEW operand of SEW-aware pseudos (load/store instructions are excluded in my experiment currently) operands and search SEW by RISCVVPseudosTable, we can reduce 30K of llc's text section and about 6000 lines of RISCVGenDAGISel.inc. But it will also add some complexities and make the RVV pseudos inconsistent.
I may post the patch after more investigations next week.

Posted in D159368.

Where does the 30K text section reduction come from? What code are we reducing?

There should be a comment in RISCVGenDAGISel.inc that says "Total Array size is" can give the reduction on that value. That's more interesting than lines.

Because we don't need to match and add SEW operand, the size of MatcherTable can be reduced by about 23000 bytes, I think most of the reduction comes from here. RISCVGenInstrInfo has some reductions too.
My proposal is removing SEW operand of load/store instructions and SEW-aware instrucitons like reductions, div, sqrt, etc. And the SEW value can be searched by RISCVVPseudosTable (or, we can encode it in TSFlags like LMUL by using 2bits).

Fri, Sep 1, 10:32 AM · Restricted Project, Restricted Project
wangpc requested review of D159368: [RISCV] Remove SEW operand for load/store and SEW-aware pseudos.
Fri, Sep 1, 10:32 AM · Restricted Project, Restricted Project
wangpc added a comment to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

Yes, the size will increase about 100KB for llc.
My intention is to unify the table (and make the code more consistent?). And if we can get SEW of pseudos from this table, then we don't need to specify the explict SEW imm in pseudos' operands (WIP).
For example:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
                  ixlenimm:$policy), []>

becomes:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
                  ixlenimm:$policy), []>,

This may simplify the generated patterns I think.

Won't that require adding more pseudos for each SEW. Many pseudos don't have SEW today.

I think almost all pseudos has HasSEWOp being true?
Edit: I get it. I won't add more pseduos, but remove the SEW operand for existed pseudos.

So there will 2 kinds of pseudos? Those with SEW in their name and those with an SEW operand?

Fri, Sep 1, 8:45 AM · Restricted Project, Restricted Project

Thu, Aug 31

wangpc added a comment to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

Yes, the size will increase about 100KB for llc.
My intention is to unify the table (and make the code more consistent?). And if we can get SEW of pseudos from this table, then we don't need to specify the explict SEW imm in pseudos' operands (WIP).
For example:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
                  ixlenimm:$policy), []>

becomes:

class VPseudoUSLoadNoMask<VReg RetClass,
                          int EEW> :
      Pseudo<(outs RetClass:$rd),
             (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
                  ixlenimm:$policy), []>,

This may simplify the generated patterns I think.

Won't that require adding more pseudos for each SEW. Many pseudos don't have SEW today.

Thu, Aug 31, 10:50 PM · Restricted Project, Restricted Project
wangpc added a comment to D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.

It looks like the InversePseudo table was only included for MCA directory. I wonder if this led to it only being a part of the llvm-mca binary, and not part of tools that do not depend on llvm-mca (such as llc). Could you check this by comparing the size of llc binary? It should have gotten larger after this change if it had not previously included the InversePseudo table.

Thu, Aug 31, 10:25 PM · Restricted Project, Restricted Project
wangpc requested review of D159333: [RISCV] Replace RISCVVInversePseudosTable with a SearchIndex.
Thu, Aug 31, 9:05 PM · Restricted Project, Restricted Project
wangpc committed rGc7a8a37f0779: [RISCV][NFC] Remove _TU in PseudoToVInst (authored by wangpc).
[RISCV][NFC] Remove _TU in PseudoToVInst
Thu, Aug 31, 7:50 PM · Restricted Project, Restricted Project
wangpc closed D159269: [RISCV][NFC] Remove _TU in PseudoToVInst.
Thu, Aug 31, 7:50 PM · Restricted Project, Restricted Project
wangpc retitled D159301: [RISCV][llvm-mca] Fix getLMUL values from [RISCV][llvm-mca] Fix Fix getLMUL values to [RISCV][llvm-mca] Fix getLMUL values.
Thu, Aug 31, 7:43 PM · Restricted Project, Restricted Project
wangpc accepted D158623: [RISCV] Reorder the stack frame objects..

LGTM, it seems reasonable to me, but please wait for @craig.topper to see if there are more comments.

Thu, Aug 31, 6:39 AM · Restricted Project, Restricted Project
wangpc requested review of D159269: [RISCV][NFC] Remove _TU in PseudoToVInst.
Thu, Aug 31, 4:36 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Thu, Aug 31, 2:03 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Thu, Aug 31, 1:02 AM · Restricted Project, Restricted Project
wangpc accepted D159253: [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants..

It seems reasonable to me.
LGTM.

Thu, Aug 31, 12:56 AM · Restricted Project, Restricted Project
wangpc committed rGf281543a4890: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm (authored by wangpc).
[RISCV] Teach RISCVMergeBaseOffset to handle inline asm
Thu, Aug 31, 12:41 AM · Restricted Project, Restricted Project
wangpc committed rG0d73259cf24b: [RISCV] Precommit test for D158062 (authored by wangpc).
[RISCV] Precommit test for D158062
Thu, Aug 31, 12:41 AM · Restricted Project, Restricted Project
wangpc closed D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.
Thu, Aug 31, 12:41 AM · Restricted Project, Restricted Project
wangpc closed D158149: [RISCV] Precommit test for D158062.
Thu, Aug 31, 12:41 AM · Restricted Project, Restricted Project
wangpc accepted D158149: [RISCV] Precommit test for D158062.
Thu, Aug 31, 12:07 AM · Restricted Project, Restricted Project

Wed, Aug 30

wangpc added a comment to D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.

Ping. Is it OK now?

Wed, Aug 30, 11:24 PM · Restricted Project, Restricted Project
wangpc accepted D159231: [RISCV] Set SEW on VPseudoTernaryWithTailPolicy and VPseudoTernaryWithTailPolicyRoundingMode.

LGTM.

Wed, Aug 30, 10:15 PM · Restricted Project, Restricted Project
wangpc added a comment to D159215: [RISCV] Fix crash during during i1 vector bitreverse lowering.

I was thinking about adding v1i256, v1i512, etc. Is it feasible?

Wed, Aug 30, 9:05 PM · Restricted Project, Restricted Project
wangpc accepted D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default..

LGTM.

Wed, Aug 30, 8:57 AM · Restricted Project, Restricted Project, Restricted Project
wangpc added inline comments to D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt.
Wed, Aug 30, 1:12 AM · Restricted Project, Restricted Project

Tue, Aug 29

wangpc added inline comments to D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default..
Tue, Aug 29, 8:39 PM · Restricted Project, Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Tue, Aug 29, 8:38 PM · Restricted Project, Restricted Project
wangpc added inline comments to D159145: [RISCV] Don't add -unaligned-scalar-mem to target features by default..
Tue, Aug 29, 7:40 PM · Restricted Project, Restricted Project, Restricted Project
wangpc accepted D158256: [RISCV] Fix assertion failure when zcmp extension is enabled..

LGTM.

Tue, Aug 29, 7:31 PM · Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Because the issues have been ongoing for a few hours now, I think it'd make sense to revert these changes while trying to determine what the appropriate fix is. @wangpc would you mind doing the revert?

Tue, Aug 29, 6:34 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

FYI this resulted in some pretty wild code size swings, in particular between -10% and -15% for tramp3d-v4 (http://llvm-compile-time-tracker.com/compare.php?from=6cde64a94986165547ae5237ac7dd4bddfc9f2a7&to=2916b125f686115deab2ba573dcaff3847566ab9&stat=size-text). Not sure whether that's an expected result of this change or not.

Tue, Aug 29, 5:46 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

This caused some linking errors with the GPU libc test suite, see https://lab.llvm.org/staging/#/builders/247/builds/5659.

clang++: error: ld.lld command failed with exit code 1 (use -v to see invocation)
[331/473] Linking CXX executable libc/test/src/__support/libc.test.src.__support.uint_test.__hermetic__.__build__
FAILED: libc/test/src/__support/libc.test.src.__support.uint_test.__hermetic__.__build__ 
: && /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./bin/clang++ --target=x86_64-unknown-linux-gnu -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -Wl,--color-diagnostics    -nostdlib -static libc/startup/gpu/amdgpu/CMakeFiles/libc.startup.gpu.amdgpu.crt1.dir/start.cpp.o libc/test/src/__support/CMakeFiles/libc.test.src.__support.uint_test.__hermetic__.__build__.dir/uint_test.cpp.o -o libc/test/src/__support/libc.test.src.__support.uint_test.__hermetic__.__build__  libc/test/UnitTest/libLibcTest.hermetic.a  libc/test/UnitTest/libLibcHermeticTestSupport.hermetic.a  libc/test/src/__support/liblibc.test.src.__support.uint_test.__hermetic__.libc.a  -mcpu=gfx906  --target=amdgcn-amd-amdhsa  -flto  -Wl,-mllvm,-amdgpu-lower-global-ctor-dtor=0 && :
ld.lld: error: undefined symbol: operator delete(void*, unsigned long)
>>> referenced by lto.tmp:(LlvmLibcUIntClassTest_ConstructorFromUInt128Tests::~LlvmLibcUIntClassTest_ConstructorFromUInt128Tests())
>>> referenced by lto.tmp:(LlvmLibcUIntClassTest_ConstructorFromUInt128Tests::~LlvmLibcUIntClassTest_ConstructorFromUInt128Tests())
>>> referenced by lto.tmp:(LlvmLibcUIntClassTest_BasicArithmeticInt128Tests::~LlvmLibcUIntClassTest_BasicArithmeticInt128Tests())
>>> referenced 41 more times
>>> did you mean: operator delete(void*)
>>> defined in: lto.tmp
clang++: error: ld.lld command failed with exit code 1 (use -v to see invocation)
Tue, Aug 29, 5:39 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Looks like this breaks tests on windows: http://45.33.8.238/win/83485/step_7.txt

Please take a look and revert for now if it takes a while to fix.

(Also, if the patch doesn't already do it, it probably shouldn't change defaults in clang-cl mode?)

Tue, Aug 29, 5:32 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc committed rG8c6d8381ea2f: [RISCV] Add isCommutable for pseudos without merge operand (authored by wangpc).
[RISCV] Add isCommutable for pseudos without merge operand
Tue, Aug 29, 12:52 AM · Restricted Project, Restricted Project
wangpc closed D158976: [RISCV] Add isCommutable for pseudos without merge operand.
Tue, Aug 29, 12:52 AM · Restricted Project, Restricted Project
wangpc committed rG2916b125f686: [clang] Enable sized deallocation by default in C++14 onwards (authored by wangpc).
[clang] Enable sized deallocation by default in C++14 onwards
Tue, Aug 29, 12:43 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc closed D112921: [clang] Enable sized deallocation by default in C++14 onwards.
Tue, Aug 29, 12:43 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Thanks all! I will land this patch later.
If there are some failures (especially libcxx part @Mordante :-) ), please help me to fix them. Thanks in advance!

Tue, Aug 29, 12:42 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Rebase.

Tue, Aug 29, 12:05 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project

Mon, Aug 28

wangpc added a comment to D158568: [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics.

Is there any example show how AcquireAtCycles can be used to model scheduling? It's all 0s by default? I don't really understand how it works. :-)

Mon, Aug 28, 11:38 PM · Restricted Project, Restricted Project
wangpc added inline comments to D112921: [clang] Enable sized deallocation by default in C++14 onwards.
Mon, Aug 28, 8:48 PM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc added inline comments to D158976: [RISCV] Add isCommutable for pseudos without merge operand.
Mon, Aug 28, 8:20 PM · Restricted Project, Restricted Project
wangpc updated the diff for D158976: [RISCV] Add isCommutable for pseudos without merge operand.

Exclude PseudoVMANDN and PseudoVMORN.

Mon, Aug 28, 8:19 PM · Restricted Project, Restricted Project
wangpc accepted D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td..

LGTM.

Mon, Aug 28, 7:51 PM · Restricted Project, Restricted Project
wangpc added a comment to D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt.

Gentle ping. :-)

Mon, Aug 28, 7:50 PM · Restricted Project, Restricted Project
wangpc added a comment to D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td..

I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108.
Is it right for this processor?

Mon, Aug 28, 7:47 PM · Restricted Project, Restricted Project
wangpc added a comment to D158976: [RISCV] Add isCommutable for pseudos without merge operand.

I'm not very familiar with how isCommutable works, but this change looks like a good idea as long as isCommutable only refers to the $rs2 and $rs1 operands, and does not say anything about commutability of $carry, $vl, or $sew.

Mon, Aug 28, 8:51 AM · Restricted Project, Restricted Project
wangpc updated the summary of D158976: [RISCV] Add isCommutable for pseudos without merge operand.
Mon, Aug 28, 8:42 AM · Restricted Project, Restricted Project
wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Gentle ping. Can I move forward and land this?

What name and email address would you like us to use for patch attribution?

Thanks! I have commit access.

Mon, Aug 28, 5:38 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project
wangpc requested review of D158976: [RISCV] Add isCommutable for pseudos without merge operand.
Mon, Aug 28, 3:46 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158956: [RISCV] Initial ISel support for the experimental zacas extension.
Mon, Aug 28, 1:56 AM · Restricted Project, Restricted Project

Sun, Aug 27

wangpc added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Gentle ping. Can I move forward and land this?

Sun, Aug 27, 9:08 PM · Restricted Project, Restricted Project, Restricted Project, Restricted Project

Aug 25 2023

wangpc added a comment to D158830: [RISCV][MC] Allow symbol diff expression directly as LI operand.

FYI: I think D157694 is related.

Aug 25 2023, 3:14 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Aug 25 2023, 12:37 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Aug 25 2023, 12:03 AM · Restricted Project, Restricted Project
wangpc added inline comments to D158623: [RISCV] Reorder the stack frame objects..
Aug 25 2023, 12:01 AM · Restricted Project, Restricted Project

Aug 24 2023

wangpc updated the diff for D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.

Rebase and address comments.

Aug 24 2023, 10:13 PM · Restricted Project, Restricted Project
wangpc updated the diff for D158149: [RISCV] Precommit test for D158062.

Rebase.

Aug 24 2023, 10:10 PM · Restricted Project, Restricted Project
wangpc added inline comments to D158716: [RFC][LV] VPlan-based cost model.
Aug 24 2023, 8:44 PM · Restricted Project, Restricted Project

Aug 23 2023

wangpc committed rG9a82bda9dedf: [RISCV] Fix assertion of getShuffleCost (authored by wangpc).
[RISCV] Fix assertion of getShuffleCost
Aug 23 2023, 5:13 AM · Restricted Project, Restricted Project
wangpc closed D158590: [RISCV] Fix assertion of getShuffleCost.
Aug 23 2023, 5:12 AM · Restricted Project, Restricted Project
wangpc added a comment to D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.

Ping.

Aug 23 2023, 5:11 AM · Restricted Project, Restricted Project
wangpc updated the diff for D158590: [RISCV] Fix assertion of getShuffleCost.

move test to reductions.ll.

Aug 23 2023, 5:09 AM · Restricted Project, Restricted Project
wangpc updated the diff for D158590: [RISCV] Fix assertion of getShuffleCost.

Address comment.

Aug 23 2023, 4:54 AM · Restricted Project, Restricted Project
wangpc updated the summary of D158590: [RISCV] Fix assertion of getShuffleCost.
Aug 23 2023, 3:25 AM · Restricted Project, Restricted Project
wangpc requested review of D158590: [RISCV] Fix assertion of getShuffleCost.
Aug 23 2023, 2:56 AM · Restricted Project, Restricted Project

Aug 22 2023

wangpc added inline comments to D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt.
Aug 22 2023, 2:51 AM · Restricted Project, Restricted Project