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jrtc27 (James Clarke)
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User Since
Jan 4 2017, 12:12 PM (145 w, 7 h)

Recent Activity

Yesterday

jrtc27 committed rG1ab27c74d4b1: [lld][WebAssembly] Fix static linking of -fPIC code with external undefined data (authored by jrtc27).
[lld][WebAssembly] Fix static linking of -fPIC code with external undefined data
Tue, Oct 15, 10:11 AM
jrtc27 committed rL374913: [lld][WebAssembly] Fix static linking of -fPIC code with external undefined data.
[lld][WebAssembly] Fix static linking of -fPIC code with external undefined data
Tue, Oct 15, 10:11 AM
jrtc27 closed D68991: [lld][WebAssembly] Fix static linking of -fPIC code with external undefined data.
Tue, Oct 15, 10:11 AM · Restricted Project
jrtc27 created D68991: [lld][WebAssembly] Fix static linking of -fPIC code with external undefined data.
Tue, Oct 15, 7:59 AM · Restricted Project

Tue, Oct 8

jrtc27 added a comment to D68559: [RISCV] Support fast calling convention.

I wonder whether it would be nicer to add CC_RISCV_FastCC as a function, much like CC_RISCV, instead, to match the current code style.

Tue, Oct 8, 8:45 AM · Restricted Project
jrtc27 added a comment to D58531: [clang] Specify type of pthread_create builtin.

I like the patch and I think it is fine.

Small nits:
Could we have a test for " we can detect dodgy pthread_create declarations" and maybe pthread[_attr]_t?
There is an unresolved comment by @shrines.
@probinson: "it seems straightforward enough although clearly needs clang-format-diff run over it."

I'll accept this assuming the above points are easy to fix and given that no one expressed concerns but only positive comments were made.

Tue, Oct 8, 8:26 AM · Restricted Project
jrtc27 updated the diff for D58531: [clang] Specify type of pthread_create builtin.

Rebased, added explicit no-warning test, clang-format'ed, updated assertion message.

Tue, Oct 8, 8:26 AM · Restricted Project
jrtc27 committed rG67f542aba72f: [Diagnostics] Silence -Wsizeof-array-div for character buffers (authored by jrtc27).
[Diagnostics] Silence -Wsizeof-array-div for character buffers
Tue, Oct 8, 4:33 AM
jrtc27 closed D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.
Tue, Oct 8, 4:33 AM · Restricted Project
jrtc27 committed rL374035: [Diagnostics] Silence -Wsizeof-array-div for character buffers.
[Diagnostics] Silence -Wsizeof-array-div for character buffers
Tue, Oct 8, 4:33 AM
jrtc27 updated the diff for D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.

Rebased

Tue, Oct 8, 4:23 AM · Restricted Project

Mon, Oct 7

jrtc27 committed rG66e276862781: [ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC (authored by jrtc27).
[ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC
Mon, Oct 7, 10:27 PM
jrtc27 committed rL374013: [ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC.
[ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC
Mon, Oct 7, 10:27 PM
jrtc27 committed rL374014: Request commit access for jrtc27.
Request commit access for jrtc27
Mon, Oct 7, 10:27 PM
jrtc27 closed D68368: [ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC.
Mon, Oct 7, 10:27 PM · Restricted Project, Restricted Project
jrtc27 updated the summary of D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.
Mon, Oct 7, 7:48 PM · Restricted Project
jrtc27 added a comment to D68542: [Mips] Always save RA when disabling frame pointer elimination.

I don't think you can have frame-pointer based stack unwinding under current Mips ABIs, albeit this might be useful for some stack scan based unwind. Not sure tho.

Mon, Oct 7, 8:26 AM · Restricted Project

Sun, Oct 6

jrtc27 added a comment to D68542: [Mips] Always save RA when disabling frame pointer elimination.

Note that the AArch64, ARM, PowerPC (32/64/64le), RISCV (32/64) and SystemZ backends all do this (Sparc gets it by virtue of register windowing so it half counts, and similarly X86 due to the hardware stack push), at least with my C test case (which was reduced to give the IR test case addd here); Mips is currently the odd one out.

Sun, Oct 6, 9:10 AM · Restricted Project
jrtc27 abandoned D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.

Fixed slightly differently by D66658 which landed over a month ago.

Sun, Oct 6, 8:22 AM · Restricted Project
jrtc27 added a comment to D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.

There's not a single word in the patch's description.

Sun, Oct 6, 7:30 AM · Restricted Project
jrtc27 added a comment to D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.

Having said that, the one warning this raised in FreeBSD (at least for our configuration) was a completely unnecessary use of a character buffer and could be cleaned up, so maybe this case is a useful one to catch. Does anyone else have an opinion on this?

Sun, Oct 6, 5:59 AM · Restricted Project

Sat, Oct 5

jrtc27 updated the diff for D68548: [Mips] Fix evaluating J-format branch targets.

Removed unwanted changes

Sat, Oct 5, 5:35 PM · Restricted Project
jrtc27 created D68548: [Mips] Fix evaluating J-format branch targets.
Sat, Oct 5, 5:30 PM · Restricted Project
jrtc27 updated the diff for D68542: [Mips] Always save RA when disabling frame pointer elimination.

Stray whitespace

Sat, Oct 5, 5:29 PM · Restricted Project
jrtc27 updated the diff for D68542: [Mips] Always save RA when disabling frame pointer elimination.

Updated existing tests

Sat, Oct 5, 5:29 PM · Restricted Project
jrtc27 created D68542: [Mips] Always save RA when disabling frame pointer elimination.
Sat, Oct 5, 12:55 PM · Restricted Project

Fri, Oct 4

jrtc27 created D68526: [Diagnostics] Silence -Wsizeof-array-div for character buffers.
Fri, Oct 4, 4:28 PM · Restricted Project

Wed, Oct 2

jrtc27 created D68368: [ItaniumMangle] Fix mangling of GNU __null in an expression to match GCC.
Wed, Oct 2, 6:35 PM · Restricted Project, Restricted Project

Wed, Sep 25

jrtc27 added inline comments to D68057: [mips] Relax jalr/jr instructions using R_MIPS_JALR relocation.
Wed, Sep 25, 3:29 PM · Restricted Project

Wed, Sep 18

jrtc27 requested changes to D66340: [RISCV] Support NonLazyBind.

A couple of minor remaining points.

Wed, Sep 18, 9:48 AM · Restricted Project

Sep 16 2019

jrtc27 added a comment to D67423: [RISCV] Rename FPRs and use Register arithmetic.

I'm still personally not fond of the Fx_F/Fx_D convention. The fact that F0_F < F1_F < F0_D < F1_D is highly surprising, especially when F0_32 < F0_64 < F1_32 < F1_64, and not what one would naively assume. I also don't know whether this peculiarity of TableGen is meant to be something that's relied upon. I know it doesn't match the ISA convention of always calling them Fx, but Fx and Dx have precedence in other backends and do not risk this same confusion. Moreover, the spec itself is highly inconsistent in how to refer to single and double precision floating point:

Sep 16 2019, 11:10 AM · Restricted Project
jrtc27 added inline comments to D66324: clang-misexpect: Profile Guided Validation of Performance Annotations in LLVM.
Sep 16 2019, 9:24 AM · Restricted Project, Restricted Project

Sep 15 2019

jrtc27 added inline comments to D60657: [RISCV] Fix evaluation of %pcrel_lo.
Sep 15 2019, 8:01 AM · Restricted Project

Sep 11 2019

jrtc27 added inline comments to D67397: [RISCV] Add MachineInstr immediate verification.
Sep 11 2019, 4:35 PM · Restricted Project

Sep 10 2019

jrtc27 added inline comments to D66973: [RISCV] Switch to the Machine Scheduler.
Sep 10 2019, 5:36 PM · Restricted Project
jrtc27 added inline comments to D67423: [RISCV] Rename FPRs and use Register arithmetic.
Sep 10 2019, 5:33 PM · Restricted Project
jrtc27 added a comment to D67423: [RISCV] Rename FPRs and use Register arithmetic.

Hm, I don't particularly like this (or at least the F parts of it); the tables are clear, whereas this seems very brittle.. e.g. when you add Q you have to also modify the places doing arithmetic on F and D registers.

Sep 10 2019, 5:27 PM · Restricted Project
jrtc27 added a comment to D66973: [RISCV] Switch to the Machine Scheduler.

%hi and %lo don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the %hi is always "consumed" by a relaxable %lo, things will work.

Does this apply even if there is another relocation between %hi and %lo?

Sep 10 2019, 5:13 PM · Restricted Project
jrtc27 added a comment to D64473: [Coding style change][lld] Rename variables for non-ELF ports..

I'm trying to merge this into our fork. The previous ELF patch was fine, but for this commit I'm having issues because the tool in D64123 doesn't produce this exact result, and so running it on our tree produces a ton of conflicts. Did you use a modified clang-llvm-rename for this (and if so could you please upload it), or are all the discrepancies changes you made by hand afterwards (or with a separate script you would be able to provide)?

Sep 10 2019, 11:05 AM · Restricted Project

Sep 8 2019

jrtc27 added a comment to D58531: [clang] Specify type of pthread_create builtin.

We've started running into this too in building the PS4 system. +jdoerfert who added pthread_create to the builtin list.

Looking at the patch, it seems straightforward enough although clearly needs clang-format-diff run over it.
I don't touch Clang that much so I'm reluctant to okay it myself.

@probinson Thanks for making me aware of this patch.

A separate point is whether it makes sense to be emitting this warning in the first place for GE_Missing_type. I'd argue that, if we don't know the type of the builtin, we should never emit the warning

@jrtc27 I hope the immediate need for this is gone after D58091 was finally committed? Given that I caused this mess I can take a look at the patch if you are still interested in it, are you?

Sep 8 2019, 8:18 AM · Restricted Project

Sep 4 2019

jrtc27 added inline comments to D67185: [RISCV] Add support for -ffixed-xX flags.
Sep 4 2019, 12:21 PM · Restricted Project, Restricted Project

Sep 3 2019

jrtc27 added inline comments to D66340: [RISCV] Support NonLazyBind.
Sep 3 2019, 3:10 AM · Restricted Project
jrtc27 requested changes to D66340: [RISCV] Support NonLazyBind.

Looks sensible in general, just various minor points.

Sep 3 2019, 3:04 AM · Restricted Project
jrtc27 added a reviewer for D60657: [RISCV] Fix evaluation of %pcrel_lo: jrtc27.
Sep 3 2019, 2:28 AM · Restricted Project
jrtc27 added a comment to D60657: [RISCV] Fix evaluation of %pcrel_lo.

@asb Would be great if you could review this; this is the revision I was referring to back in Boston.

Sep 3 2019, 2:25 AM · Restricted Project
jrtc27 abandoned D65291: [RISCV] Add Custom Parser for Atomic Memory Operands.

D65205 landed.

Sep 3 2019, 2:23 AM · Restricted Project

Aug 30 2019

jrtc27 added a comment to D66973: [RISCV] Switch to the Machine Scheduler.

%hi and %lo don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the %hi is always "consumed" by a relaxable %lo, things will work.

Aug 30 2019, 12:46 PM · Restricted Project

Jul 25 2019

jrtc27 added inline comments to D65205: [RISCV] Add Custom Parser for Atomic Memory Operands.
Jul 25 2019, 10:00 AM · Restricted Project
jrtc27 added a comment to D65205: [RISCV] Add Custom Parser for Atomic Memory Operands.

Is there a reason not to include them in the instruction operand string? It would mean you don't need the custom printer, no?

This is actually really complex. If I include the parens in the tablegen instruction definition, then we definitely cannot support 0(a0) because the parser requires a ( where the 0 is. If i don't include them in the instruction definition, then when parseMemBaseOp runs, it adds ( tokens into the Operands, which means later the register operand is not in the expected place in Operands when operand matching happens.

Jul 25 2019, 10:00 AM · Restricted Project
jrtc27 created D65291: [RISCV] Add Custom Parser for Atomic Memory Operands.
Jul 25 2019, 9:31 AM · Restricted Project

Jul 24 2019

jrtc27 added a comment to D65205: [RISCV] Add Custom Parser for Atomic Memory Operands.

Yeah this looks like a nice way to do it, better than making an InstAlias for each one. GNU as will accept any expression that evaluates to the constant 0 in place of the 0 (i.e. it's just an imm0, same logic as all the other [su]immX fields, other than discarding it). Could we not therefore reuse part of the generic parser, just with a tweak to drop the immediate if parsed and 0? Something like:

... snip ...

I am worried about this approach, mostly because of the lines like 1268 in parseMemOpBaseReg, where they're pushing on (/) tokens, which aren't in the instruction operand strings (any more). It does seem like these might complicate the pushing/popping more than necessary. I am also not sure we want to support bare register operands.

Jul 24 2019, 9:27 AM · Restricted Project
jrtc27 added a comment to D65205: [RISCV] Add Custom Parser for Atomic Memory Operands.

Yeah this looks like a nice way to do it, better than making an InstAlias for each one. GNU as will accept any expression that evaluates to the constant 0 in place of the 0 (i.e. it's just an imm0, same logic as all the other [su]immX fields, other than discarding it). Could we not therefore reuse part of the generic parser, just with a tweak to drop the immediate if parsed and 0? Something like:

Jul 24 2019, 6:54 AM · Restricted Project

Jul 8 2019

jrtc27 added inline comments to D63669: [RISCV] Allow parsing dot '.' in assembly.
Jul 8 2019, 2:33 PM · Restricted Project

Jul 5 2019

jrtc27 added inline comments to D61907: [RISCV] Leave pcrel_hi/pcrel_lo fixup pairs unresolved.
Jul 5 2019, 10:06 AM · Restricted Project
jrtc27 added a comment to D61907: [RISCV] Leave pcrel_hi/pcrel_lo fixup pairs unresolved.

@asb I prefer D60657 over this as it seems to cover everything, and this is a rather big hammer to be hitting the problem with (that GNU as manages to avoid needing). Have you had a look at that one?

Jul 5 2019, 10:06 AM · Restricted Project

Jul 3 2019

jrtc27 created D64139: [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references.
Jul 3 2019, 8:51 AM · Restricted Project
jrtc27 updated the diff for D57792: [RISCV] Support z and i operand modifiers.

Rebased

Jul 3 2019, 7:29 AM · Restricted Project
jrtc27 requested changes to D63273: [ELF][RISCV] Error on R_RISCV_PCREL_LO12_[IS] that point to absolute symbols.
Jul 3 2019, 5:15 AM · Restricted Project
jrtc27 added a comment to D63273: [ELF][RISCV] Error on R_RISCV_PCREL_LO12_[IS] that point to absolute symbols.

Seems like a good idea

Jul 3 2019, 5:15 AM · Restricted Project
jrtc27 added a comment to D63259: [ELF][RISCV] Allow R_RISCV_ADD in relocateNonAlloc().

Looks sensible to me

Jul 3 2019, 5:15 AM · Restricted Project

Jul 1 2019

jrtc27 added inline comments to D54296: [RISCV] Lower inline asm constraint A for RISC-V.
Jul 1 2019, 9:33 AM · Restricted Project
jrtc27 accepted D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.

I don't like the mismatch between LLD and BFD, but this is a definite improvement over the current state. I'm happy for this to be merged, with the intent that discussions about CALL/CALL_PLT continue in the RISC-V ABI world to get a consensus, specify it and then fix any implementations that deviate from it, whether that be BFD, LLD or both.

Jul 1 2019, 9:17 AM · Restricted Project
jrtc27 updated the diff for D57792: [RISCV] Support z and i operand modifiers.

Added nounwind to tests. Added full stops to comments.

Jul 1 2019, 8:29 AM · Restricted Project
jrtc27 abandoned D61866: [RISCV] Rename RISCVELFStreamer.{cpp,h} to RISCVTargetELFStreamer.{cpp,h}.
Jul 1 2019, 8:21 AM · Restricted Project
jrtc27 created D64012: [RISCV][NFC] Split PseudoCALL pattern out from instruction.
Jul 1 2019, 7:57 AM · Restricted Project
jrtc27 created D64011: [RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in comment.
Jul 1 2019, 7:56 AM · Restricted Project
jrtc27 added inline comments to D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Jul 1 2019, 4:24 AM · Restricted Project

Jun 20 2019

jrtc27 accepted D63220: [ELF][RISCV] Support GD/LD/IE/LE TLS models.

One minor pedantic stylistic comment but otherwise this seems fine to me.

Jun 20 2019, 8:00 AM · Restricted Project

Jun 18 2019

jrtc27 added a comment to D57792: [RISCV] Support z and i operand modifiers.
In D57792#1549678, @asb wrote:
In D57792#1549669, @asb wrote:

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

This is GCC not binutils, and I can't find them documented anywhere other than the source itself: https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/riscv/riscv.c?view=markup&revision=271293#l3181

Sorry, I meant GCC.

Thanks, this patch looks good to me. Tiny nit: LLVM coding guidelines prefer full sentences for comments, so the comments added to RISCVAsmPrinter.cpp should end in a full stop.

Jun 18 2019, 10:31 PM · Restricted Project
jrtc27 added a comment to D57332: [RISCV] Allow parsing of bare symbols with offsets.
In D57332#1549661, @asb wrote:

Is this being used in the wild and does it work sensibly with binutils? I'm seeing that binutils seems to be associating the addend with both the emitted R_RISCV_PCREL_HI20 relocation and R_RISCV_RELAX relocation. Maybe this is just a binutils bug and the addend is ignored by the linker but this does seem surprising...

$ cat t.s 
lla a5, a_symbol + (0xFF << 3)
$ ./riscv32-unknown-elf-as t.s
$ ./riscv32-unknown-elf-readelf -r a.out 

Relocation section '.rela.text' at offset 0xec contains 4 entries:
 Offset     Info    Type            Sym.Value  Sym. Name + Addend
00000000  00000617 R_RISCV_PCREL_HI2 00000000   a_symbol + 7f8
00000000  00000033 R_RISCV_RELAX                7f8
00000004  00000418 R_RISCV_PCREL_LO1 00000000   .L0  + 0
00000004  00000033 R_RISCV_RELAX                0
Jun 18 2019, 10:13 PM · Restricted Project
jrtc27 added a comment to D57792: [RISCV] Support z and i operand modifiers.
In D57792#1549669, @asb wrote:

Is there documentation on the operand modifiers supported by RISC-V binutils anywhere? I'm struggling to find anything...

Jun 18 2019, 10:11 PM · Restricted Project
jrtc27 added inline comments to D54296: [RISCV] Lower inline asm constraint A for RISC-V.
Jun 18 2019, 8:30 AM · Restricted Project

Jun 17 2019

jrtc27 added a comment to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.

Does that make a visible difference?

Jun 17 2019, 5:30 AM · Restricted Project
jrtc27 requested changes to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.

Still disagree about the behaviour of R_RISCV_CALL. You can't just choose the ABI that you want. Please at least put it back to R_PC. @ruiu do you have an opinion on this?

Jun 17 2019, 5:06 AM · Restricted Project

Jun 14 2019

jrtc27 added inline comments to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 14 2019, 6:12 AM · Restricted Project
jrtc27 added inline comments to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 14 2019, 6:11 AM · Restricted Project

Jun 13 2019

jrtc27 added inline comments to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 13 2019, 2:09 PM · Restricted Project
jrtc27 accepted D63132: [ELF][RISCV] Create dummy .sdata for __global_pointer$ if .sdata does not exist.

@jrtc27 Do this patch and D63076 look good now?

Jun 13 2019, 1:53 PM · Restricted Project
jrtc27 requested changes to D63220: [ELF][RISCV] Support GD/LD/IE/LE TLS models.
Jun 13 2019, 1:55 AM · Restricted Project

Jun 11 2019

jrtc27 added a comment to D63132: [ELF][RISCV] Create dummy .sdata for __global_pointer$ if .sdata does not exist.

GNU ld treats it as undefined:

Yes. That was why I created the patch to fix the musl -fpie -pie link error: ld.lld: error: relocation R_RISCV_PCREL_HI20 cannot refer to absolute symbol: __global_pointer$. This error is lld specific: in -pie/-shared mode, a PC relative relocation to an absolute symbol is not allowed.

In https://groups.google.com/forum/#!searchin/generic-abi/SHN_ABS|sort:date/generic-abi/MC4b4sqnKC0/oQgZxxwMmJAJ, Cary's interpretation of gABI is:

On the contrary, the only interpretation that makes sense to me is that it will not change because of relocation at link time or at load time.

If lld resolves the PC relative relocation statically, the value will be incorrect when the pie or shared object is loaded at runtime because the SHN_ABS symbol's value does not change. The best lld can do is to issue an error.

An alternative is to create a dummy .sdata in musl's Scrt1.o. I don't know how reasonable it is to have lla gp,__global_pointer$ in other code that might not define .sdata.

Jun 11 2019, 7:53 AM · Restricted Project
jrtc27 added inline comments to D63132: [ELF][RISCV] Create dummy .sdata for __global_pointer$ if .sdata does not exist.
Jun 11 2019, 7:30 AM · Restricted Project
jrtc27 added inline comments to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 11 2019, 7:14 AM · Restricted Project
jrtc27 added inline comments to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 11 2019, 7:14 AM · Restricted Project
jrtc27 requested changes to D63132: [ELF][RISCV] Create dummy .sdata for __global_pointer$ if .sdata does not exist.

GNU ld treats it as undefined:

Jun 11 2019, 6:53 AM · Restricted Project
jrtc27 requested changes to D63076: [ELF][RISCV] Support PLT, GOT, copy and relative relocations.
Jun 11 2019, 5:38 AM · Restricted Project

Jun 6 2019

jrtc27 updated the diff for D57795: [RISCV] Add FreeBSD targets.

Sorted OS case statements

Jun 6 2019, 7:27 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D61866: [RISCV] Rename RISCVELFStreamer.{cpp,h} to RISCVTargetELFStreamer.{cpp,h}.

Hm, actually, looking more closely, there seems to be inconsistency. Some backends use FooELFStreamer.cpp for an MCELFStreamer, and others for a ELF-specific target streamer. Some, like AArch64, even put both in the same file, so if you don't like this patch, I suppose the recommendation would be to do that?

Jun 6 2019, 5:50 AM · Restricted Project
jrtc27 added a comment to D61866: [RISCV] Rename RISCVELFStreamer.{cpp,h} to RISCVTargetELFStreamer.{cpp,h}.
In D61866#1532288, @asb wrote:

I think this is less confusing, but there's more to be gained by having a similar naming scheme to the other backends which right now all use FooELFStreamer.{cpp,h}.

I you feel strongly about this change, I'd consider making it for all in-tree backends.

Jun 6 2019, 5:45 AM · Restricted Project

Jun 3 2019

jrtc27 added a comment to D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.

Ping?

Jun 3 2019, 7:26 AM · Restricted Project

May 31 2019

jrtc27 added a comment to D60657: [RISCV] Fix evaluation of %pcrel_lo.

Thanks for this. I realize D58843 is a very heavy-handed approach so I'd be happy if we could avoid it cleanly with target-specific changes, however I'm not certain we would be able to cover all the combinations we would need to with patches like this?

For example would we be able to cover pairs that occur out of order?

May 31 2019, 6:09 AM · Restricted Project

May 16 2019

jrtc27 added a comment to D61584: [DebugInfo] Some fields do not need relocations even relax is enabled..

Why do we need this flag; can we not already determine this (either in generic code or the target backends)? Anything where all symbols referenced are not in SHF_EXECINSTR sections can be evaluated even with relaxations, which covers all these cases:

May 16 2019, 5:06 AM · Restricted Project

May 13 2019

jrtc27 created D61866: [RISCV] Rename RISCVELFStreamer.{cpp,h} to RISCVTargetELFStreamer.{cpp,h}.
May 13 2019, 10:34 AM · Restricted Project

May 2 2019

jrtc27 added a comment to D61464: [RiscV] Typo in register aliases.

Ouch; LGTM.

May 2 2019, 5:06 PM · Restricted Project, Restricted Project
jrtc27 edited reviewers for D61464: [RiscV] Typo in register aliases, added: asb; removed: echristo.
May 2 2019, 5:04 PM · Restricted Project, Restricted Project

Apr 18 2019

jrtc27 updated the diff for D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.

Also handle .bss where the zeroes are written to the file.

Apr 18 2019, 8:52 AM · Restricted Project
jrtc27 added inline comments to D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.
Apr 18 2019, 8:20 AM · Restricted Project
jrtc27 added inline comments to D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.
Apr 18 2019, 6:00 AM · Restricted Project

Apr 17 2019

jrtc27 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

The problem is that Length is the length of the CIE, i.e. the data structure itself; this means it isn't subject to relaxations and so the difference expression can be folded. I don't see much merit in teaching all the tools out there to check relocations for Length when we can instead just emit the "right" thing. I think the fix is to make sure we only return true from requiresDiffExpressionRelocations if a target is in a code section? MCSection::UseCodeAlign will tell you this (or you can use MCSectionELF::getFlags() & ELF::SHF_EXECINSTR to be less general), though perhaps it should be renamed to isCodeSection to match isVirtualSection.

Apr 17 2019, 6:55 AM · Restricted Project

Apr 16 2019

jrtc27 updated the diff for D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.

Updated affected tests.

Apr 16 2019, 11:15 AM · Restricted Project
jrtc27 created D60785: [ELF] Align file offset for .bss if first section in a PT_LOAD.
Apr 16 2019, 10:46 AM · Restricted Project