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jrtc27 (Jessica Clarke)
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Jan 4 2017, 12:12 PM (324 w, 6 d)

Recent Activity

Fri, Mar 24

jrtc27 added a comment to D146847: [NFC] Fix uninitialized member variable use in RVVEmitter::createRVVIntrinsics().

None of the other fields are initialised, so blindly initialising it alone to 0 here seems highly suspect. What's the actual case in which it's used whilst uninitialised?

Coverity complains about SR.PolicyBitMask being uninitialized when calling SemaRecords->push_back(SR)

Fri, Mar 24, 2:50 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D146847: [NFC] Fix uninitialized member variable use in RVVEmitter::createRVVIntrinsics().

The field should just be deleted. D126742 added it without any uses, and I don't know what the original intent was. Maybe it was used before the bitfields were added and it stuck around rather than being GC'ed. I don't know why Coverity would care about this though when it's never read from, there's nothing wrong with that, unless the warning is in fact that the field is entirely unreferenced?

Fri, Mar 24, 2:39 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D146847: [NFC] Fix uninitialized member variable use in RVVEmitter::createRVVIntrinsics().

None of the other fields are initialised, so blindly initialising it alone to 0 here seems highly suspect. What's the actual case in which it's used whilst uninitialised?

Fri, Mar 24, 2:23 PM · Restricted Project, Restricted Project

Wed, Mar 22

jrtc27 added inline comments to D146663: [RISCV] Add .insn support for compressed formats..
Wed, Mar 22, 3:39 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D146663: [RISCV] Add .insn support for compressed formats..
Wed, Mar 22, 2:53 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D146663: [RISCV] Add .insn support for compressed formats..
Wed, Mar 22, 2:43 PM · Restricted Project, Restricted Project

Tue, Mar 21

jrtc27 added inline comments to D85540: [llvm-libtool-darwin] Add support for -l and -L.
Tue, Mar 21, 11:29 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D146516: [RISCV][Zfa] Fix FROUND codegen bugs.
Tue, Mar 21, 9:57 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D146516: [RISCV][Zfa] Fix FROUND codegen bugs.
Tue, Mar 21, 9:56 AM · Restricted Project, Restricted Project
Herald added a project to D85540: [llvm-libtool-darwin] Add support for -l and -L: Restricted Project.
Tue, Mar 21, 9:51 AM · Restricted Project, Restricted Project

Mon, Mar 20

jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Mon, Mar 20, 10:02 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Mon, Mar 20, 11:38 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Mon, Mar 20, 11:32 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D145224: [LLVM][OHOS] Use emulated TLS for OHOS platform.
Mon, Mar 20, 9:16 AM · Restricted Project, Restricted Project

Sat, Mar 18

jrtc27 added inline comments to D144012: [SPARC][MC] Fix encoding of backwards BPr branches.
Sat, Mar 18, 4:02 PM · Restricted Project, Restricted Project

Thu, Mar 16

jrtc27 added a comment to D146270: [RISCV] Use LBU for extloadi8..

Are there any cases like with all the *W optimisations where it would be better to sign-extend, or is i32 special there due to the *W ops and for i8 the only cases where it's beneficial will already have become sextloads?

Thu, Mar 16, 8:15 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D146191: [MachineOutliner][MCP][RISCV] Don't run MCP on outlined functions.

Is there a reason we can't instead add the right live-outs?

Thu, Mar 16, 7:46 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D146269: MIPS: allow o32 abi with 64bit CPU and 64 abi with 32bit triple.

Tests?

Thu, Mar 16, 7:45 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 committed rG2be973e9d80b: workflows: Don't try and run llvm-bugs in forks (authored by jrtc27).
workflows: Don't try and run llvm-bugs in forks
Thu, Mar 16, 9:47 AM · Restricted Project
jrtc27 closed D146235: workflows: Don't try and run llvm-bugs in forks.
Thu, Mar 16, 9:47 AM · Restricted Project, Restricted Project
jrtc27 requested review of D146235: workflows: Don't try and run llvm-bugs in forks.
Thu, Mar 16, 9:39 AM · Restricted Project, Restricted Project

Mon, Mar 13

jrtc27 added inline comments to D145883: [Flang][RISCV] Emit target features for RISC-V.
Mon, Mar 13, 1:05 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D145883: [Flang][RISCV] Emit target features for RISC-V.
Mon, Mar 13, 11:04 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 requested changes to D145224: [LLVM][OHOS] Use emulated TLS for OHOS platform.
Mon, Mar 13, 10:13 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D123515: [RISCV] Support '.option arch' directive.

This patch is needed for zbb support as per: https://lore.kernel.org/all/20230117122447.y6tdsmsxqdwf76ri@orel/

Mon, Mar 13, 10:06 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D145883: [Flang][RISCV] Emit target features for RISC-V.
Mon, Mar 13, 1:29 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D145883: [Flang][RISCV] Emit target features for RISC-V.
Mon, Mar 13, 1:20 AM · Restricted Project, Restricted Project, Restricted Project

Sun, Mar 12

jrtc27 added inline comments to D145883: [Flang][RISCV] Emit target features for RISC-V.
Sun, Mar 12, 1:39 PM · Restricted Project, Restricted Project, Restricted Project

Sat, Mar 11

jrtc27 added inline comments to D144330: [MLIR][RISCV] Emit target-abi info for RISC-V.
Sat, Mar 11, 11:25 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144012: [SPARC][MC] Fix encoding of backwards BPr branches.
Sat, Mar 11, 4:17 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Sat, Mar 11, 2:54 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D123515: [RISCV] Support '.option arch' directive.
Sat, Mar 11, 12:55 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D123515: [RISCV] Support '.option arch' directive.

What happened to your new test?

Sat, Mar 11, 12:52 AM · Restricted Project, Restricted Project

Wed, Mar 8

jrtc27 added a comment to D145635: [ELF] Make --discard-locals default on riscv.

Anyway, this definitely still merits a review from @MaskRay given his commit to tackle the problem differently

Wed, Mar 8, 6:25 PM · Restricted Project
jrtc27 added inline comments to D145635: [ELF] Make --discard-locals default on riscv.
Wed, Mar 8, 6:24 PM · Restricted Project
jrtc27 added inline comments to D145635: [ELF] Make --discard-locals default on riscv.
Wed, Mar 8, 6:20 PM · Restricted Project
jrtc27 added a comment to D145635: [ELF] Make --discard-locals default on riscv.

Anyway this seems to contradict the approach chosen by D127826

Wed, Mar 8, 6:14 PM · Restricted Project
jrtc27 added inline comments to D145635: [ELF] Make --discard-locals default on riscv.
Wed, Mar 8, 6:13 PM · Restricted Project
jrtc27 added inline comments to rG42a5dda553e8: [RISCV] Add more testcases for overflow-intrinsics.ll.
Wed, Mar 8, 5:28 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D134129: [PATCH] [RISCV] Enable -msave-restore by default when optimizing for size.

At least with that this diff shows, the saving is small. I'd hope that we don't toggle -msave-restore for -Os/-Oz. Users can specify -msave-restore themselves.

Wed, Mar 8, 4:16 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D145205: [codegen][riscv] Emit CFI directives when using shadow call stack.
Wed, Mar 8, 2:30 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to rGdea96e7dcad8: [libc] Remove log10 from the list of riscv64 entrypoints..
Wed, Mar 8, 12:13 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to rGdea96e7dcad8: [libc] Remove log10 from the list of riscv64 entrypoints..
Wed, Mar 8, 12:07 PM · Restricted Project, Restricted Project

Tue, Mar 7

jrtc27 added a comment to D145539: [llvm/Target] Add Windows COFF support for RISC-V.

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

And how are you going to do that without a full PE/COFF specification for RISC-V?

Thanks for mentioning! If I am correct, PE/COFF specification has definitions of machine architecture in headers. In this part PE/COFF included RISC-V architecture types. It does not provide relocation types on RISC-V, so for now PE/COFF specification allows us to emit RISC-V COFF binaries without any relocations. This could be a use case for RISC-V UEFI applications where it's mainly statically linked without any relocations. If there are more demands on RISC-V PE/COFF which need relocations, the current PE/COFF specification will not support them and LLVM (after this patch) would raise fatal error instead.

I have limited information about RISC-V PE/COFF support as well; I don't know if other reviewers have different opinion about this part.

Tue, Mar 7, 8:09 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D145539: [llvm/Target] Add Windows COFF support for RISC-V.

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

Tue, Mar 7, 7:59 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D145539: [llvm/Target] Add Windows COFF support for RISC-V.

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Tue, Mar 7, 7:27 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D145471: [RISCV] Set how many bytes load from or store to stack slot.
Tue, Mar 7, 11:27 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D145237: [builtins] Only build float16/bfloat16 code if actually supported.
Tue, Mar 7, 11:24 AM · Restricted Project, Restricted Project

Mon, Mar 6

jrtc27 added inline comments to D145452: [libc] Add riscv64 syscall implementation..
Mon, Mar 6, 6:42 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D145346: [NFC] Simplify printstmt code.

This isn't NFC, the output changes

Mon, Mar 6, 4:11 AM · Restricted Project, Restricted Project, Restricted Project

Fri, Mar 3

jrtc27 added inline comments to D145214: [TSAN] add support for riscv64.
Fri, Mar 3, 11:24 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D123515: [RISCV] Support '.option arch' directive.
Fri, Mar 3, 11:17 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D123515: [RISCV] Support '.option arch' directive.
Fri, Mar 3, 11:14 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D140478: [RISCV] For Dwarf v5, emit indices into .debug_addr for range list entries.

@dblaikie

As I already replied earlier, there is not enough context to reach the MachineFunction from the symbol or determine if relaxation is enabled for the given address range.

Then won't this make the wrong decisions if the value varies between functions/subtargets?

Also, at the moment, the -mrelax/-mno-relax affects the entire compilation unit for the RISC-V.

Then wouldn't these be target features, rather than subtarget features? My understanding is that subtarget features generally can vary by function, whereas target features cannot.

Even if the command line flags don't support it, we could probably make a simple IR example with different relaxation per function? & so we probably should be able to handle that case.

It's a per-function feature that has implications for other functions in the same section (deleting code in one function at link time will shunt around the code in the rest of the section).

@dblaikie

As I already replied earlier, there is not enough context to reach the MachineFunction from the symbol or determine if relaxation is enabled for the given address range.

Then won't this make the wrong decisions if the value varies between functions/subtargets?

Also, at the moment, the -mrelax/-mno-relax affects the entire compilation unit for the RISC-V.

Then wouldn't these be target features, rather than subtarget features? My understanding is that subtarget features generally can vary by function, whereas target features cannot.

Even if the command line flags don't support it, we could probably make a simple IR example with different relaxation per function? & so we probably should be able to handle that case.

It's a per-function feature that has implications for other functions in the same section (deleting code in one function at link time will shunt around the code in the rest of the section).

What does it mean for it to be per-function? Can it vary at all between functions in the same module? (if not, why is it per-function?)

Fri, Mar 3, 9:43 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D145292: [test] Remove occurences of br undef in various llvm tests.

A cursory glance reveals numerous cases of ( i1, and cases of undefined variables (e.g. llvm/test/CodeGen/PowerPC/subreg-postra.ll).

Fri, Mar 3, 7:56 PM · Restricted Project, Restricted Project
jrtc27 committed rG3a748cd01bbf: [RISCV][NFC] Add PIC RUN/CHECK lines for jumptable.ll test (authored by jrtc27).
[RISCV][NFC] Add PIC RUN/CHECK lines for jumptable.ll test
Fri, Mar 3, 12:21 PM · Restricted Project, Restricted Project
jrtc27 committed rG6e8bcaafbaa4: [RISCV][NFC] Unify CHECK lines for jumptable.ll @below_threshold test (authored by jrtc27).
[RISCV][NFC] Unify CHECK lines for jumptable.ll @below_threshold test
Fri, Mar 3, 12:21 PM · Restricted Project, Restricted Project
jrtc27 committed rGe0fe8e641258: [RISCV][NFC] Add signext to jumptable.ll tests to avoid irrelevant sext.w (authored by jrtc27).
[RISCV][NFC] Add signext to jumptable.ll tests to avoid irrelevant sext.w
Fri, Mar 3, 12:21 PM · Restricted Project, Restricted Project

Thu, Mar 2

jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Thu, Mar 2, 5:06 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D140478: [RISCV] For Dwarf v5, emit indices into .debug_addr for range list entries.

@dblaikie

As I already replied earlier, there is not enough context to reach the MachineFunction from the symbol or determine if relaxation is enabled for the given address range.

Then won't this make the wrong decisions if the value varies between functions/subtargets?

Also, at the moment, the -mrelax/-mno-relax affects the entire compilation unit for the RISC-V.

Then wouldn't these be target features, rather than subtarget features? My understanding is that subtarget features generally can vary by function, whereas target features cannot.

Even if the command line flags don't support it, we could probably make a simple IR example with different relaxation per function? & so we probably should be able to handle that case.

Thu, Mar 2, 3:43 PM · Restricted Project, Restricted Project

Wed, Mar 1

jrtc27 added inline comments to D144936: [SPARC][IAS] Recognize more SPARCv9 instructions/pseudoinstructions.
Wed, Mar 1, 9:10 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144012: [SPARC][MC] Fix encoding of backwards BPr branches.
Wed, Mar 1, 9:01 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Wed, Mar 1, 8:43 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144941: [m68k] Add TLS Support.
Wed, Mar 1, 7:58 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144941: [m68k] Add TLS Support.
Wed, Mar 1, 5:36 AM · Restricted Project, Restricted Project

Feb 24 2023

jrtc27 added a comment to D143115: [lld][RISCV] Introduce handling for R_RISCV_PLT32 relocation.

@kito-cheng @jrtc27: Can I just confirm the ABI development process? We obviously went through a whole ratification exercise before, but how does it now work for these kind of additions? I'm mainly concerned about merging support for something that's added to the psABI doc, but then having to change it later if it's viewed as not "final". I guess this shouldn't happen, as a consequence of the PR merging policy but it's still a bit unclear how it intersects with any future ratification process that might be requested by RISC-V International.

Though FWIW, I think the path of getting broad consensus on the proposal and then considering it 'done' is just fine - I'm not sure extra layers of sign-off would be helpful for incremental improvements like this. And in case I missed a hidden layer of bureaucracy, I _think_ the x86_64 psABI is evolved in a similar way.

Feb 24 2023, 10:18 PM · Restricted Project, Restricted Project

Feb 22 2023

jrtc27 added a comment to D144530: [RISCV] MC layer support for SiFive VCIX vendor extension..

Normally we use the less cumbersome “MC layer” rather than “assembler and dis-assembler” (which also shouldn’t be hyphenated)

Feb 22 2023, 2:06 AM · Restricted Project, Restricted Project

Feb 21 2023

jrtc27 added a comment to D143673: [lld][RISCV] Implement GP relaxation for R_RISCV_HI20/R_RISCV_LO12_I/R_RISCV_LO12_S..

@MaskRay here's some data I collected on SPEC2006 .text size and dynamic instruction counts with and without GP relaxation using the GNU linker. I also measured using GP as a callee-saved register. https://docs.google.com/spreadsheets/d/14V7cPbyc80AcGHzsMaw9hYb232dzRbGCmTApnxj-SpU/edit?usp=sharing

Feb 21 2023, 1:04 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Feb 21 2023, 7:31 AM · Restricted Project, Restricted Project

Feb 20 2023

jrtc27 added a comment to D143708: [RISCV] Support emulated TLS.

Didn't notice before, but why emutls_generic.ll rather than emutls.ll? The suffix doesn't add any value as far as I can see. It's as generic as any other RISC-V CodeGen test.

Feb 20 2023, 4:12 PM · Restricted Project, Restricted Project

Feb 18 2023

jrtc27 added inline comments to D136400: [llvm-ocaml] Migrate from naked pointers to prepare for OCaml 5.
Feb 18 2023, 12:27 PM · Restricted Project, Restricted Project

Feb 16 2023

jrtc27 added a comment to D143708: [RISCV] Support emulated TLS.

Whilst I would encourage wherever this got copied from be cleaned up in a similar manner, I don't think:

  1. this patch for one backend should be blocked on cleaning up a test in another backend
  2. a lower-quality test for another backend should be justification for committing a lower-quality test to this backend
Feb 16 2023, 10:52 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D142822: [clang] ASTImporter: Fix importing of va_list types and declarations.
Feb 16 2023, 4:52 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D143437: [llvm] Use pointer index type for more GEP offsets (pre-codegen).
Feb 16 2023, 4:38 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143437: [llvm] Use pointer index type for more GEP offsets (pre-codegen).
Feb 16 2023, 3:27 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143437: [llvm] Use pointer index type for more GEP offsets (pre-codegen).
Feb 16 2023, 2:59 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D144215: [WIP][RISCV] Accept zicntr and zihpm command line options.

https://github.com/riscv/riscv-isa-manual/releases/tag/archive has an assortment of past specs, including the 2.2 you're after

Feb 16 2023, 2:39 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143708: [RISCV] Support emulated TLS.
Feb 16 2023, 1:50 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D143708: [RISCV] Support emulated TLS.

The consensus from the RISC-V LLVM sync-up call was that it makes sense to go ahead with this on the basis their are users, the infrastructure in LLVM already exists to use it etc, and it's a tiny patch to enable etc.

In which case, assuming no-one who wasn't able to make it to the call wanted to raise strong objections, we can hopefully focus on code review of this patch and move it forwards.

I have a mild objection but I am fine if my opinion is overthrown. I think OpenBSD developers should take on the work to migrate to ELF TLS, not using this definitely.

-femulated-tls can be used for the current *-linux-android* and *-openbsd* target triples, and OpenBSD RISC-V, but not others. The test should be changed to use openbsd, not linux-gnu.

Feb 16 2023, 1:46 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143437: [llvm] Use pointer index type for more GEP offsets (pre-codegen).
Feb 16 2023, 10:40 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143437: [llvm] Use pointer index type for more GEP offsets (pre-codegen).
Feb 16 2023, 10:35 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144168: StackProtector: instrument noreturn paths before the call.
Feb 16 2023, 1:32 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144168: StackProtector: instrument noreturn paths before the call.
Feb 16 2023, 1:27 AM · Restricted Project, Restricted Project

Feb 15 2023

jrtc27 added a comment to D143982: [RISCV][CodeGen] Add codegen pattern for experimental zfa extension (FLI and FCVTMOD not included).

You don’t need to mention FCVTMOD given it does not apply to C/C++.

Feb 15 2023, 10:00 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..
Feb 15 2023, 8:51 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143317: [m68k] Add TLS support.
Feb 15 2023, 5:39 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D143345: [RFC][RISCV] Don't disassemble `addi`s with relocations as `mv`s.

It'd be really cool if we could use the relocation to print %pcrel_lo(sym) instead of 0. But I don't know how much work that would be.

I can work on that if there is agreement that we should go in that direction. Makes sense to me, but I wonder if some people will push back against that, regardless of implementation concerns.

Feb 15 2023, 5:37 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension.
Feb 15 2023, 8:10 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension.
Feb 15 2023, 8:01 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D143248: Emit CFI directives in epilogue and enable CFIFixup pass for RISC-V..

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

Feb 15 2023, 5:43 AM · Restricted Project, Restricted Project

Feb 14 2023

jrtc27 added a comment to D143982: [RISCV][CodeGen] Add codegen pattern for experimental zfa extension (FLI and FCVTMOD not included).

You don’t need to mention FCVTMOD given it does not apply to C/C++.

Feb 14 2023, 2:29 AM · Restricted Project, Restricted Project

Feb 13 2023

jrtc27 accepted D143953: [RISCV] Accept zicsr and zifencei command line options.

Personally happy with the concept then, seems consistent and overall helpful, just some nits

Feb 13 2023, 5:22 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D143953: [RISCV] Accept zicsr and zifencei command line options.

@jrtc27 Not sure if this changes your take, but I realized the variant being introduced is maybe much less interesting than I'd first thought. We generally make no effort to make sure an extension was defined in the spec version corresponding to our base revision. Given that, we have a bunch of cases where we allow I2.0 + some random extension. Given that, this one stops looking all that interesting. It doesn't actually set much precedent - because we already did that, a long time ago.

If you agree with that framing, I'll rework the description.

Feb 13 2023, 4:47 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D143953: [RISCV] Accept zicsr and zifencei command line options.

I'm fine with this approach but I think they should be filtered out of the ELF attributes, maybe also preprocessor macros? That is, treating them as a redundant no-op in the driver rather than like a true extension.

Feb 13 2023, 4:13 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D143468: [CMake] Remove custom ccache CMake logic.
Feb 13 2023, 9:30 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 accepted D143924: [RISCV][docs] Describe status of zicsr and zifencei.
Feb 13 2023, 9:04 AM · Restricted Project, Restricted Project

Feb 10 2023

jrtc27 added inline comments to D137309: [clang] Added Swift support for RISCV.
Feb 10 2023, 8:50 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D143619: [llvm][codegen] Disallow default Emulated TLS for RISCV.

@paulkirth, I agree that shipping a working compiler is more important than parity with the other compilers, but in this particular case we simply face a simple to fix bug caused by component owner tyranny :) We should simply fix this bug and move forward.

Feb 10 2023, 12:46 AM · Restricted Project, Restricted Project

Feb 9 2023

jrtc27 added inline comments to D143673: [lld][RISCV] Implement GP relaxation for R_RISCV_HI20/R_RISCV_LO12_I/R_RISCV_LO12_S..
Feb 9 2023, 3:23 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D143673: [lld][RISCV] Implement GP relaxation for R_RISCV_HI20/R_RISCV_LO12_I/R_RISCV_LO12_S..
Feb 9 2023, 3:10 PM · Restricted Project, Restricted Project