Page MenuHomePhabricator

jrtc27 (Jessica Clarke)
User

Projects

User does not belong to any projects.

User Details

User Since
Jan 4 2017, 12:12 PM (281 w, 2 d)

Recent Activity

Wed, May 25

jrtc27 added inline comments to D126392: [RISCV] Use two ADDIs to do some stack pointer adjustments..
Wed, May 25, 5:38 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D126085: [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores.

Technically it's may not will so you can just hard-wire it to 1...

Wed, May 25, 2:16 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D126392: [RISCV] Use two ADDIs to do some stack pointer adjustments..

For reference, this is the exact text in the psABI spec:

Wed, May 25, 10:09 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D126392: [RISCV] Use two ADDIs to do some stack pointer adjustments..

Doesn't this run the risk of temporarily misaligning the stack (e.g. for Val == 2064)? The psABI says using such a non-standard ABI within a function is fine and that kernels should realign stacks before calling signal handlers. Both FreeBSD and Linux correctly do this for signal handlers so as to not make assumptions about whether userspace is following the standard ABI, but both assume that the kernel itself is following the standard ABI, and so do not realign the stack in their exception entry points, causing the stack to be misaligned if an interrupt is taken in between. Whether this is a bug or not in the kernels is debatable, but with a more careful splitting of Val it should be possible to avoid anyway?

Wed, May 25, 10:08 AM · Restricted Project, Restricted Project

Fri, May 20

jrtc27 added inline comments to D126088: [RISCV] Add clarifying asserts to getFrameIndexReference [NFC].
Fri, May 20, 2:21 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D126088: [RISCV] Add clarifying asserts to getFrameIndexReference [NFC].
Fri, May 20, 1:26 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D126085: [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores.

Is this meant to be "it works" or "it works without trapping for emulation"? Pretty much every EEI out there has misaligned accesses guaranteed to work, just not quickly, and in those cases you'd still want to avoid them as the inlined byte-wise code is far faster.

Fri, May 20, 1:12 PM · Restricted Project, Restricted Project

Thu, May 19

jrtc27 added inline comments to rG3e5b1e9ccfae: [RISCV] Add test showing codegen for unaligned loads and stores of scalar types.
Thu, May 19, 9:12 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D125905: [RISCV] Fix state persistence bugs (PR55548).
Thu, May 19, 7:54 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D125947: [RISCV] Add default ABI for archs with only F extension.

Also, the tests where you have codegen changes rather than preserving a soft-float ABI should probably be put up for review separately by adding an explicit hard single-float ABI, as those seem worthwhile for reducing noise

Thu, May 19, 10:19 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D125947: [RISCV] Add default ABI for archs with only F extension.

It's currently this way in order to be compatible with GCC. Changing this requires consensus from both toolchains to ensure compatibility is preserved. See https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13 for some discussion on this.

Thu, May 19, 10:17 AM · Restricted Project, Restricted Project, Restricted Project

Wed, May 18

jrtc27 added inline comments to D125905: [RISCV] Fix state persistence bugs (PR55548).
Wed, May 18, 9:57 AM · Restricted Project, Restricted Project

Thu, May 12

jrtc27 added a comment to D124212: [sanitizer] Use canonical syscalls everywhere.

There's a lot of really quite wonky whitespace reformatting in this diff

FWIW, I have already a draft for fixing this. Will create a revision tomorrow.

EDIT: I mean the build failure on sparc64 ;).

Thanks. Sorry for the breakage. It appears that sparc64 is the only 64-bit target without newfstatat syscall.

Thu, May 12, 1:08 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D124212: [sanitizer] Use canonical syscalls everywhere.

There's a lot of really quite wonky whitespace reformatting in this diff

Thu, May 12, 11:54 AM · Restricted Project, Restricted Project

Mon, May 9

jrtc27 added inline comments to D125272: [clang] Add -fcheck-new support.
Mon, May 9, 6:06 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D125272: [clang] Add -fcheck-new support.
Mon, May 9, 6:05 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D125272: [clang] Add -fcheck-new support.
Mon, May 9, 5:48 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D125272: [clang] Add -fcheck-new support.
Mon, May 9, 3:45 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D125247: [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4..
Mon, May 9, 2:39 PM · Restricted Project, Restricted Project

Thu, May 5

jrtc27 added a comment to D124988: [DAGCombiner] Fold (sext/zext undef) -> 0 and aext(undef) -> undef..

What's the justification for 0 rather than undef? That the high bits need to be guaranteed equal even for undef input?

Thu, May 5, 10:49 AM · Restricted Project, Restricted Project

Mon, May 2

jrtc27 added a comment to D124794: [LLD][RISCV][NFC] Allow GNU linker to run RISCV LLD tests.

What happens when we want to use LLD-specific options or are checking LLD-specific messages? Those tests aren't going to pass. Do we then need to annotate LLD tests with REQUIRES: lld-is-actually-lld? Is there any precedent for doing this on other architectures? This doesn't feel right to me.

Mon, May 2, 12:20 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D124794: [LLD][RISCV][NFC] Allow GNU linker to run RISCV LLD tests.

Why can't people just symlink GNU ld to ld.lld?

Mon, May 2, 12:13 PM · Restricted Project, Restricted Project

Fri, Apr 29

jrtc27 added inline comments to rGf91690f7db96: [RISCV] Don't merge addi into load/store address if addi has a FrameIndex….
Fri, Apr 29, 6:29 PM · Restricted Project, Restricted Project

Apr 22 2022

jrtc27 added a comment to D123679: [RISCV] Don't getDebugLoc for the end node of MBB iterator.

Use update_mir_test_checks.py, don’t hand-write specific check lines

Apr 22 2022, 7:44 AM · Restricted Project, Restricted Project

Apr 21 2022

jrtc27 added a comment to D124217: [AMDGPU] Allow finer grain control of an unaligned access speed.

What are the units?..

Apr 21 2022, 5:16 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D123364: [RISCV] Precommit test for D122634.
  • The commit message for the reverting commit should explain why patch is being reverted.
Apr 21 2022, 5:52 AM · Restricted Project, Restricted Project

Apr 19 2022

jrtc27 added a comment to D123264: [RISCV] Pre-RA expand pseudos pass.
  • Although I haven't run into that problem, I think it's still possible for an ADDI to become out of range of the AUIPC it refers to, if other passes move them too far apart. For branches we have the branch relaxation pass to solve essentially the same problem. Are we going to need a similar pass for AUIPC/ADDI? Or can we prevent this from happening?
Apr 19 2022, 10:26 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D123264: [RISCV] Pre-RA expand pseudos pass.
Apr 19 2022, 10:21 AM · Restricted Project, Restricted Project

Apr 18 2022

jrtc27 added a comment to D123970: [RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL.

Might be clearer as let isCommutable = 1/true in on each def? There aren't that many of them, so that keeps it self-documenting and avoids long argument lists.

Apr 18 2022, 5:43 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D100835: [WIP][LLD][RISCV] Linker Relaxation.

a could be preempted, so no, it has to go via the PLT for that specific example.

Apr 18 2022, 7:58 AM · Restricted Project, Restricted Project

Apr 11 2022

jrtc27 added inline comments to D123181: [RISCV] [NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp.
Apr 11 2022, 1:27 PM · Restricted Project, Restricted Project

Apr 9 2022

jrtc27 added a comment to D123458: [LSR][RISCV] Improve test coverage for LSR in RISC-V.

The test case file names are uninformative, and having both reduce-2/3 and reduce2/3 doesn't seem like a good idea

Apr 9 2022, 9:10 PM · Restricted Project, Restricted Project

Apr 7 2022

jrtc27 added a comment to D122635: [RISCV] Filter out instructions which contain unsafe things when outlining.

And can we please have regression tests for these cases?

Apr 7 2022, 3:55 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D122635: [RISCV] Filter out instructions which contain unsafe things when outlining.

The commit message says JumpTableIndex but isJTI is already checked?

Apr 7 2022, 3:55 PM · Restricted Project, Restricted Project

Apr 5 2022

jrtc27 added a comment to D123143: SelectionDAG: Swap operands of atomic_store.

This will be a lot of fun downstream...

Apr 5 2022, 10:11 AM · Restricted Project, Restricted Project

Apr 2 2022

jrtc27 added inline comments to D122951: [RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64..
Apr 2 2022, 3:56 AM · Restricted Project, Restricted Project

Apr 1 2022

jrtc27 added inline comments to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Apr 1 2022, 4:00 AM · Restricted Project, Restricted Project

Mar 28 2022

jrtc27 added inline comments to D122580: RegAllocGreedy: Roll back successful recolorings on failure.
Mar 28 2022, 10:12 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D122580: RegAllocGreedy: Roll back successful recolorings on failure.
Mar 28 2022, 10:11 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D122580: RegAllocGreedy: Roll back successful recolorings on failure.
Mar 28 2022, 9:44 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D122580: RegAllocGreedy: Roll back successful recolorings on failure.

Comments on the RISC-V test to keep it consistent with all the others

Mar 28 2022, 6:25 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D122556: [RISCV] Add definitions for Xiangshan processors..
Mar 28 2022, 6:16 AM · Restricted Project, Restricted Project, Restricted Project

Mar 23 2022

jrtc27 added a comment to D122335: [clang] Emit crash reproduction as a single tar file.

As a developer who often deals with crashes locally this is more annoying; currently I can just point tools at the shell script and C file in /tmp and let them go to work reducing, but now I have to also extract the files

Mar 23 2022, 6:37 PM · Restricted Project
jrtc27 added a comment to D121270: Update memref type doc on aliasing guarantee across memory spaces.

Address spaces can also be used for the exact same memory but a different representation of the pointers, which can come with semantic differences; we use them in CHERI LLVM to differentiate between traditional integer addresses and CHERI capabilities, with the latter having associated bounds and permissions to provide spatial safety.

Mar 23 2022, 8:00 AM · Restricted Project, Restricted Project

Mar 21 2022

jrtc27 added a comment to D122208: [RISCV] Optimize (select Cond, X, 0) --> and (sext Cond), X.

Are you sure this is a code size win with RVC? Also much less likely to be macro-op fused; conditional branch followed by a move is one of the things you can easily fuse, and some cores already implement predicated execution for short forward conditional branches.

Mar 21 2022, 9:39 PM · Restricted Project, Restricted Project

Mar 18 2022

jrtc27 added a comment to D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori.

There's a whole set of these you could do; why this one in particular? And what about it makes it RV32-specific?

Mar 18 2022, 6:00 PM · Restricted Project, Restricted Project

Mar 17 2022

jrtc27 added a comment to D121654: [RISCV] Ensure PseudoLA* can be hoisted.

Does:

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f52965dab759..299c68da7c2f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3769,6 +3769,15 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
   }
 }
 
+template SDValue RISCVTargetLowering::getAddr<GlobalAddressSDNode>(
+    GlobalAddressSDNode *N, SelectionDAG &DAG, bool IsLocal) const;
+template SDValue RISCVTargetLowering::getAddr<BlockAddressSDNode>(
+    BlockAddressSDNode *N, SelectionDAG &DAG, bool IsLocal) const;
+template SDValue RISCVTargetLowering::getAddr<ConstantPoolSDNode>(
+    ConstantPoolSDNode *N, SelectionDAG &DAG, bool IsLocal) const;
+template SDValue RISCVTargetLowering::getAddr<JumpTableSDNode>(
+    JumpTableSDNode *N, SelectionDAG &DAG, bool IsLocal) const;
+
 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);

fix the error for you?

I'd be happy to review and approve a patch with this change but I think the fastest resolution to getting the bot back to green would be to revert and then recommit with this change added. The bot has been broken for over 24 hours so we would like to get it back online as soon as possible, thank you for your quick response. :)

Mar 17 2022, 7:24 PM · Restricted Project, Restricted Project
jrtc27 committed rG63ea7797dd5b: [RISCV] Fix buildbot breakage by explicitly instantiating templates (authored by jrtc27).
[RISCV] Fix buildbot breakage by explicitly instantiating templates
Mar 17 2022, 7:23 PM · Restricted Project
jrtc27 added a comment to D121654: [RISCV] Ensure PseudoLA* can be hoisted.

Does:

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f52965dab759..299c68da7c2f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3769,6 +3769,15 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
   }
 }
Mar 17 2022, 4:26 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D121654: [RISCV] Ensure PseudoLA* can be hoisted.

My guess as to what the problem is is that this has perturbed inlining heuristics such that the ConstantPoolSDNode template instantiation no longer exists in the output object file, as we don't explicitly instantiate any of them, only implicitly via their uses?

Mar 17 2022, 4:13 PM · Restricted Project, Restricted Project
jrtc27 added a comment to D121654: [RISCV] Ensure PseudoLA* can be hoisted.

I have confirmed that this patch cause a miscompile on our sanitizer-ppc64be-linux #4255 bot, please investigate and fix this as soon as possible, thank you.

Mar 17 2022, 4:05 PM · Restricted Project, Restricted Project

Mar 16 2022

jrtc27 added a comment to D121840: [RFC][WIP][RISCV] Fold ADDI of LLA + Load/Store code sequences.

This then duplicates the AUIPC though and scales as 2*N rather than N+2. If you want to do this properly you really need to have a peephole pass that runs after the pseudo has been expanded.

Mar 16 2022, 12:28 PM · Restricted Project, Restricted Project
jrtc27 committed rG659363c0ccfb: [RISCV] Ensure PseudoLA* can be hoisted (authored by jrtc27).
[RISCV] Ensure PseudoLA* can be hoisted
Mar 16 2022, 11:46 AM · Restricted Project
jrtc27 committed rG883f75563946: [NFC][RISCV] Pre-commit tests for hoisting of PseudoLLA/PseudoLA* (authored by jrtc27).
[NFC][RISCV] Pre-commit tests for hoisting of PseudoLLA/PseudoLA*
Mar 16 2022, 11:46 AM · Restricted Project
jrtc27 closed D121654: [RISCV] Ensure PseudoLA* can be hoisted.
Mar 16 2022, 11:46 AM · Restricted Project, Restricted Project

Mar 15 2022

jrtc27 added inline comments to D121654: [RISCV] Ensure PseudoLA* can be hoisted.
Mar 15 2022, 8:47 PM · Restricted Project, Restricted Project
jrtc27 updated the diff for D121654: [RISCV] Ensure PseudoLA* can be hoisted.
  • Renamed test case
  • Delete TODO as fixed
Mar 15 2022, 8:44 PM · Restricted Project, Restricted Project

Mar 14 2022

jrtc27 added inline comments to D121654: [RISCV] Ensure PseudoLA* can be hoisted.
Mar 14 2022, 10:32 PM · Restricted Project, Restricted Project
jrtc27 requested review of D121654: [RISCV] Ensure PseudoLA* can be hoisted.
Mar 14 2022, 5:41 PM · Restricted Project, Restricted Project

Mar 4 2022

jrtc27 added inline comments to D92105: [RISCV] Add pre-emit pass to make more instructions compressible.
Mar 4 2022, 11:56 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D120967: [NFC] Divide tests into smaller files.

With one exception, every RISC-V Clang CodeGen test (and with 9 exceptions, every RISC-V LLVM CodeGen test) is kebab-case not snake_case

Mar 4 2022, 9:16 AM · Restricted Project, Restricted Project

Mar 2 2022

jrtc27 added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

Never mind, I see you added a test for that case

Mar 2 2022, 11:42 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

Does a double with r for RV32 work with that fix? That's supposed to give the low half of the register. You might need to also deal with the register pair class?

Mar 2 2022, 11:41 AM · Restricted Project, Restricted Project, Restricted Project

Mar 1 2022

jrtc27 added a comment to D120695: [RISCV] Move class RISCVPassConfig declaration to RISCVTargetMachine.h for downstream. NFC.

Why do you need to derive from any of them. Just modify them. It's so much more painful to do it the way you're suggesting. I say this as a downstream that makes significant changes to instruction selection and adds totally new ABIs.

Mar 1 2022, 7:01 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to rGc752eb4ae197: [RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC.
Mar 1 2022, 7:51 AM
jrtc27 added inline comments to rGc752eb4ae197: [RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC.
Mar 1 2022, 7:48 AM
jrtc27 added a comment to D120695: [RISCV] Move class RISCVPassConfig declaration to RISCVTargetMachine.h for downstream. NFC.

Note that git grep ' : public TargetPassConfig' llvm/lib/Target turns up 21 results, exactly one for each backend, and every single one lives in the backend's TargetMachine.cpp. So moving it to a header, or adding a second one, would go against the convention of every single backend in tree.

Mar 1 2022, 7:43 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D120695: [RISCV] Move class RISCVPassConfig declaration to RISCVTargetMachine.h for downstream. NFC.

Inheriting from the pass doesn't make sense, just change the implementations. The TargetPassConfig has access to the TM for a reason. As someone with significant downstream changes I am sympathetic to changing upstream code to be more accommodating, but this change just seems motivated by an arbitrary downstream decision that goes against the intent of LLVM's structure just to avoid the occasional merge conflict (RISCVPassConfig hardly changes much).

Mar 1 2022, 7:38 AM · Restricted Project, Restricted Project
jrtc27 added a comment to D120702: [RISCV] emit .option directive when generate assembly file.

We already rejected this in the past. They’re unnecessary if you don’t bogusly drop flags when assembling.

Mar 1 2022, 4:13 AM · Restricted Project

Feb 27 2022

jrtc27 added inline comments to D93298: [RISCV] add the MC layer support of Zfinx extension.
Feb 27 2022, 7:51 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added inline comments to D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified.
Feb 27 2022, 7:49 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Feb 27 2022, 7:43 PM · Restricted Project, Restricted Project
jrtc27 committed rG6aa8521fdb7a: [RISCV] Fix parseBareSymbol to not double-parse top-level operators (authored by jrtc27).
[RISCV] Fix parseBareSymbol to not double-parse top-level operators
Feb 27 2022, 12:49 PM
jrtc27 closed D120635: [RISCV] Fix parseBareSymbol to not double-parse top-level operators.
Feb 27 2022, 12:49 PM · Restricted Project
jrtc27 requested review of D120635: [RISCV] Fix parseBareSymbol to not double-parse top-level operators.
Feb 27 2022, 12:00 PM · Restricted Project

Feb 26 2022

jrtc27 added inline comments to D118549: apply two more cases for store combine.
Feb 26 2022, 5:00 PM · Restricted Project, Restricted Project

Feb 24 2022

jrtc27 added a comment to D120518: const correctness for getTargetTransformInfo.

This isn't const *correctness*, this is adding a new restriction. The existing code is totally correct, but this potentially makes downstream code no longer correct.

Maintaining state in TTI is definitely bad, so this is a good restriction

Feb 24 2022, 2:19 PM · Restricted Project
jrtc27 added a comment to D120518: const correctness for getTargetTransformInfo.

This isn't const *correctness*, this is adding a new restriction. The existing code is totally correct, but this potentially makes downstream code no longer correct.

Feb 24 2022, 2:14 PM · Restricted Project

Feb 18 2022

jrtc27 added a comment to D118987: [analyzer] Add failing test case demonstrating buggy taint propagation.

It seems like the clang-ve-ninja doesn't really want to accept any patches from me :D
I hope it's not personal. Let's be friends bot, please.

Link to the breakage: https://lab.llvm.org/buildbot/#/builders/91/builds/3818

I'm inviting @simoll for resolving this, and the underlying issue to prevent future breakages and reverts.

Feb 18 2022, 2:20 PM · Restricted Project
jrtc27 added a comment to D120130: [RISCV] Fix zfinx test error in rust.

I'm unconvinced this is quite the right fix for the bug. I agree we need this code, but I disagree that this code should be needed when Zfinx isn't in use. Without Zfinx, we should never have GFPR* be legal in the first place, surely?

Feb 18 2022, 7:26 AM · Restricted Project
jrtc27 added a comment to D120130: [RISCV] Fix zfinx test error in rust.

Missing test

Tests are in the rust environment.

Feb 18 2022, 7:24 AM · Restricted Project
jrtc27 added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:

I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream.

Since I don't have a rust environment

There is no requirement, indeed. LLVM devs are not responsible to keep ""experimental rust + llvm@head" working.

Feb 18 2022, 7:11 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

@krasimir Since I don't have a rust environment, can you help me to test if D120130 works?

Feb 18 2022, 6:54 AM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

It appears that this is causing an assertion segfault in a rustc test over at our experimental rust + llvm@head bot:
https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706
The test is https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. These two lines appear to cause it (code compiles fine when removed):

The assertion:

Impossible reg-to-reg copy
UNREACHABLE executed at [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350

...

Feb 18 2022, 5:55 AM · Restricted Project, Restricted Project, Restricted Project

Feb 17 2022

jrtc27 added inline comments to D119788: [AArch64] Add support for -march=native for Apple M1 CPU.
Feb 17 2022, 8:37 PM · Restricted Project, Restricted Project, Restricted Project
jrtc27 added a comment to D120094: [CallingConv] Generate isCCArgumentReg() predicate via tablegen.

Revision summary seems to be totally lacking any explanation of what this actually is for. Also how is this meant to interact with architectures like MIPS where return value registers aren't argument registers (v0 and v1); is it meant to include those or not? The name suggests it does, but the old function name suggested it didn't (and was just a stub outside of X86?).

Feb 17 2022, 5:02 PM · Restricted Project, Restricted Project
jrtc27 added inline comments to D116774: AST: Move __va_list tag back to std conditionally on AArch64..
Feb 17 2022, 11:18 AM · Restricted Project
jrtc27 accepted D116773: AST: Make getEffectiveDeclContext() a member function of ItaniumMangleContextImpl. NFCI..

This makes sense to me but I don't know if you want someone with more authority in these parts to review it

Feb 17 2022, 10:51 AM · Restricted Project
jrtc27 accepted D116774: AST: Move __va_list tag back to std conditionally on AArch64..

Thanks, looks good to me

Feb 17 2022, 10:50 AM · Restricted Project
jrtc27 added inline comments to D118333: [RISCV] Use computeTargetABI from llc as well as clang.
Feb 17 2022, 8:20 AM · Restricted Project, Restricted Project
jrtc27 added inline comments to D120001: [JITLink] Add R_RISCV_SUB6 relocation.
Feb 17 2022, 7:24 AM · Restricted Project
jrtc27 added inline comments to D116774: AST: Move __va_list tag back to std conditionally on AArch64..
Feb 17 2022, 6:45 AM · Restricted Project

Feb 16 2022

jrtc27 added a comment to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

I suppose we inherited this bug from PowerPC. @nemanjai maybe you want to fix this for PowerPC?

X86 is the same from the looks of it. The only other implementation of PostprocessISelDAG is AMDGPU which does things a bit differently and doesn't seem to have an equivalent "check for uses".

With the current post-processing on X86 I don't thin you could get a failure. None of the opcodes that are being looked for have chain outputs so they can't be the root.

Feb 16 2022, 6:44 PM · Restricted Project
jrtc27 added a comment to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.

I suppose we inherited this bug from PowerPC. @nemanjai maybe you want to fix this for PowerPC?

Feb 16 2022, 6:10 PM · Restricted Project
jrtc27 added inline comments to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.
Feb 16 2022, 6:08 PM · Restricted Project
jrtc27 added inline comments to D119934: [RISCV] Fix a mistake in PostprocessISelDAG.
Feb 16 2022, 5:56 PM · Restricted Project

Feb 12 2022

jrtc27 requested changes to D109037: [RISCV] Enable shrink wrap by default.
Feb 12 2022, 10:08 AM · Restricted Project
jrtc27 reopened D109037: [RISCV] Enable shrink wrap by default.

Reverted due to https://github.com/llvm/llvm-project/issues/53662

Feb 12 2022, 10:08 AM · Restricted Project
jrtc27 added a comment to D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

I objected and still believe this patch is fundamentally wrong. The problem needs solving elsewhere, not like this. Please revert.

Although this solution is far from perfect, it does improve code quality. Could you please show a test case that gets wrong or worse assembly by this patch?
I suggest we can keep it and go on searching better solutions.

Feb 12 2022, 7:11 AM · Restricted Project
jrtc27 added a comment to D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.

I objected and still believe this patch is fundamentally wrong. The problem needs solving elsewhere, not like this. Please revert.

Feb 12 2022, 4:45 AM · Restricted Project