Today

grimar added a comment to D34689: [LLD][ELF] Pre-create ThunkSections at Target specific intervals.

Just a minor nit I noticed.

Fri, Aug 18, 1:47 AM
sam_parker committed rL311148: [AArch64] Remove DecodeAuthLoadWriteback.
[AArch64] Remove DecodeAuthLoadWriteback
Fri, Aug 18, 1:40 AM
Diffusion closed D36741: [AArch64] Remove DecodeAuthLoadWriteback by committing rL311148: [AArch64] Remove DecodeAuthLoadWriteback.
Fri, Aug 18, 1:40 AM
chandlerc added a comment to D36864: [Profile] backward propagate profile data in jump-threading.

Really, really nice find here. A bunch of comments below, but they're all pretty minor on the whole.

Fri, Aug 18, 1:40 AM
peter.smith updated the diff for D34689: [LLD][ELF] Pre-create ThunkSections at Target specific intervals.

Thanks for the comment, I've updated the diff with the change from Mb to Mib.

Fri, Aug 18, 1:40 AM
coby added a reviewer for D36793: [X86AsmParser] Refactoring, (almost) NFC.: m_zuckerman.
Fri, Aug 18, 1:38 AM
coby added a comment to D35621: X86 Asm can't work properly with symbolic Scale.

Coby, Reid, is eveything OK? Could you get LGTM?

Fri, Aug 18, 1:37 AM
grimar updated the diff for D36145: [ELF] - Do not segfault when doing logical and/or operations on symbols that have no output sections..
  • Addressed review comment.
Fri, Aug 18, 1:32 AM
NoQ accepted D36851: [analyzer] Fix modeling of ctors.

After the FIXME about record layout is addressed, i guess the next action item is to make sure the trivial constructor for the empty base is not evaluated conservatively (doh!). Because whatever bindings we make, for now they'd be blown away immediately during "construction".

Fri, Aug 18, 1:25 AM
chandlerc added a comment to D36858: [x86] Teach the cmov converter to aggressively convert cmovs with memory operands into control flow..

I've run this across SPEC CPU 2006 and the LLVM test suite on my Haswell system.

Fri, Aug 18, 1:21 AM
grimar added inline comments to D36256: [ELF] Don't output headers into a segment if there's no space for them.
Fri, Aug 18, 1:21 AM · lld
grimar updated the diff for D36262: [ELF] - Do not forget to fill last bytes of PT_LOADs with trap instructions..
  • Addressed review comment.
Fri, Aug 18, 1:00 AM
javed.absar accepted D36796: [ARM] Add missing patterns for insert_subvector..

LGTM. Maybe elaborate a bit more on the summary part

Fri, Aug 18, 12:59 AM
avt77 added a comment to D35621: X86 Asm can't work properly with symbolic Scale.

Coby, Reid, is eveything OK? Could you get LGTM?

Fri, Aug 18, 12:50 AM
alexshap updated the diff for D36851: [analyzer] Fix modeling of ctors.

Skip the default binding for empty bases.

Fri, Aug 18, 12:32 AM
courbet added a comment to D33987: [MergeICmps][WIP] Initial MergeICmps prototype.

Ping

Fri, Aug 18, 12:08 AM

Yesterday

jonpa added a comment to D36795: [SystemZ] Increase number of LOCRs emitted by passing regalloc hints.

Oh, and just comment on this:

BTW, I don't quite understand the purpose of updateRegAllocHint(). It seems to be run during coalescing, but that's before getRegAllocationHints() has ever been called. So what is being updated?

I understand this is about something else: maintaining the MachineRegisterInfo set/getRegAllocationHint data. It seems the ARM target sets up the MRI hints in a special pass ahead of time, and then *uses* the MRI hints in its implementation of getRegAllocationHints. However, for this to be useful the MRI hints need to be updated for the effects of register coalescing; the updateRegAllocHint allows the target to do just that.

Since your implementation of getRegAllocationHints doesn't actually make any use of the MRI hints, you don't need to implement updateRegAllocHint either.

Thu, Aug 17, 11:52 PM
asb committed rL311147: Refine report_fatal_error guidance after post-commit review.
Refine report_fatal_error guidance after post-commit review
Thu, Aug 17, 11:46 PM
t-tye added inline comments to D36862: AMDGPU: Handle non-temporal loads and stores.
Thu, Aug 17, 11:33 PM
davidxl created D36864: [Profile] backward propagate profile data in jump-threading.
Thu, Aug 17, 11:16 PM
dberris updated the diff for D36615: [XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove synthetic references in .text.

Rebase

Thu, Aug 17, 11:09 PM
dberris updated the diff for D36816: [XRay][compiler-rt] Support sled versioning for custom event sleds.

Rebase

Thu, Aug 17, 11:06 PM
t-tye accepted D36861: AMDGPU/NFC: Rename few things in SIMemoryLegalizer:.

LGTM

Thu, Aug 17, 11:05 PM
kristof.beyls added a comment to D36717: [test-suite] Add SPEC CPU 2017.

One more remark: The 'ref' dataset of 638.imagick_s on all the computers I tried on took between 2 and 3 hours. Submitted results to SPEC are in a similar range. Unfortunately timeit.py has a 7200 seconds (2 hours) limit hardcoded (for --limit-cpu and --timeout). I had to remove that limit to be able to have a successful run.

Can we make the limit configurable or set higher?

Thu, Aug 17, 10:56 PM
asb committed rL311146: Give guidance on report_fatal_error in CodingStandards.rst and….
Give guidance on report_fatal_error in CodingStandards.rst and…
Thu, Aug 17, 10:30 PM
asb closed D36826: Give guidance on report_fatal_error in CodingStandards.rst and ProgrammersManual.rst by committing rL311146: Give guidance on report_fatal_error in CodingStandards.rst and….
Thu, Aug 17, 10:30 PM
dberris committed rL311145: [XRay][compiler-rt][NFC] Expand the PIC test case for XRay.
[XRay][compiler-rt][NFC] Expand the PIC test case for XRay
Thu, Aug 17, 10:28 PM
dberris closed D36863: [XRay][compiler-rt][NFC] Expand the PIC test case for XRay by committing rL311145: [XRay][compiler-rt][NFC] Expand the PIC test case for XRay.
Thu, Aug 17, 10:28 PM
dberris added inline comments to D36816: [XRay][compiler-rt] Support sled versioning for custom event sleds.
Thu, Aug 17, 10:24 PM
dberlin added a comment to D36680: [test-suite] Adding Pathfinder Benchmark.

This is the same as what i said on D36682 :)

Thu, Aug 17, 10:13 PM
dberris created D36863: [XRay][compiler-rt][NFC] Expand the PIC test case for XRay.
Thu, Aug 17, 10:13 PM
dberlin added a comment to D36682: [test-suite] Adding miniAMR Benchmark.

TL;DR This statement is slightyl different, but also has no effect.
It is also a statement that is more or less required by statute/regulation.

Thu, Aug 17, 10:13 PM
dberris added a comment to D36615: [XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove synthetic references in .text.

Thanks, @pcc -- PTAL?

Thu, Aug 17, 10:08 PM
dberlin added a comment to D36683: [test-suite] Adding miniFE Benchmark.

The statements are, AFAIK, best viewed as statements of provenance, and are fairly normal for government released works (some are even required by statute)
They do not change or affect the license in any way.

Thu, Aug 17, 10:07 PM
dberris updated the diff for D36816: [XRay][compiler-rt] Support sled versioning for custom event sleds.

Address comments.

Thu, Aug 17, 10:03 PM
kzhuravl added a dependent revision for D36861: AMDGPU/NFC: Rename few things in SIMemoryLegalizer:: D36862: AMDGPU: Handle non-temporal loads and stores.
Thu, Aug 17, 10:00 PM
kzhuravl added a dependency for D36862: AMDGPU: Handle non-temporal loads and stores: D36861: AMDGPU/NFC: Rename few things in SIMemoryLegalizer:.
Thu, Aug 17, 10:00 PM
kzhuravl created D36862: AMDGPU: Handle non-temporal loads and stores.
Thu, Aug 17, 9:59 PM
kzhuravl retitled D36861: AMDGPU/NFC: Rename few things in SIMemoryLegalizer: from AMDGPU: Rename few things in SIMemoryLegalizer: to AMDGPU/NFC: Rename few things in SIMemoryLegalizer:.
Thu, Aug 17, 9:58 PM
dberris added a dependent revision for D36816: [XRay][compiler-rt] Support sled versioning for custom event sleds: D36615: [XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove synthetic references in .text.
Thu, Aug 17, 9:57 PM