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bjope (Bjorn Pettersson)
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User Since
Sep 26 2016, 7:58 AM (142 w, 6 h)

Recent Activity

Today

bjope committed rG83773b77a5a4: [LV] Deny irregular types in interleavedAccessCanBeWidened (authored by bjope).
[LV] Deny irregular types in interleavedAccessCanBeWidened
Mon, Jun 17, 5:00 AM
bjope committed rL363547: [LV] Deny irregular types in interleavedAccessCanBeWidened.
[LV] Deny irregular types in interleavedAccessCanBeWidened
Mon, Jun 17, 4:59 AM
bjope closed D63386: [LV] Deny irregular types in interleavedAccessCanBeWidened.
Mon, Jun 17, 4:59 AM · Restricted Project

Yesterday

bjope added a reviewer for D63386: [LV] Deny irregular types in interleavedAccessCanBeWidened: craig.topper.
Sun, Jun 16, 8:36 AM · Restricted Project
bjope created D63386: [LV] Deny irregular types in interleavedAccessCanBeWidened.
Sun, Jun 16, 8:35 AM · Restricted Project
bjope added a reviewer for D63385: [ConstantFolding] Add constant folding for smul.fix and smul.fix.sat: leonardchan.
Sun, Jun 16, 8:26 AM · Restricted Project
bjope added a child revision for D63384: [ConstantFolding] Refactor ConstantFoldScalarCall. NFC: D63385: [ConstantFolding] Add constant folding for smul.fix and smul.fix.sat.
Sun, Jun 16, 8:26 AM · Restricted Project
bjope created D63385: [ConstantFolding] Add constant folding for smul.fix and smul.fix.sat.
Sun, Jun 16, 8:26 AM · Restricted Project
bjope added a parent revision for D63385: [ConstantFolding] Add constant folding for smul.fix and smul.fix.sat: D63384: [ConstantFolding] Refactor ConstantFoldScalarCall. NFC.
Sun, Jun 16, 8:26 AM · Restricted Project
bjope created D63384: [ConstantFolding] Refactor ConstantFoldScalarCall. NFC.
Sun, Jun 16, 8:26 AM · Restricted Project

Mon, Jun 10

bjope added a comment to D62088: [compiler-rt][builtins] Scaled Integer log10().

Please add test cases for scale=0 and scale=width as I assume those need special handling (UB right now?).
And if scale=0 and scale=width needs special handling, then I guess scale=1 and scale=width-1 are new boundary values so I maybe it would be nice to have tests for those scales as well.

Mon, Jun 10, 10:40 PM · Restricted Project, Restricted Project
bjope accepted D63083: [DebugInfo][Docs] Document that prologue/epilogue variable location changes are ignored.

Looks good to me (matching my assumptions about why prolog/epilog is special).
Just a minor nit inline.

Mon, Jun 10, 10:38 AM · Restricted Project

Fri, May 24

bjope committed rGb4771425f53c: Use the DataLayout::typeSizeEqualsStoreSize helper. NFC (authored by bjope).
Use the DataLayout::typeSizeEqualsStoreSize helper. NFC
Fri, May 24, 2:18 AM
bjope committed rL361613: Use the DataLayout::typeSizeEqualsStoreSize helper. NFC.
Use the DataLayout::typeSizeEqualsStoreSize helper. NFC
Fri, May 24, 2:17 AM
bjope added a comment to D61940: [DebugInfo] Don't always extend variable locations when the reg location is unchanging.

Is the intention to change the behavior for prologues as well here? The description mentions that we do a different analysis for the epilogues. But with this patch we no longer ignore register clobbering for "FrameSetup" (collectChangingRegs used to ignore FrameSetup code).

Fri, May 24, 1:39 AM · Restricted Project
bjope committed rGd63a2bb35fb2: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores (authored by bjope).
[DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores
Fri, May 24, 1:33 AM
bjope committed rL361605: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.
[DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores
Fri, May 24, 1:33 AM
bjope closed D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.
Fri, May 24, 1:33 AM · Restricted Project

Thu, May 23

bjope added inline comments to D62223: [DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold.
Thu, May 23, 2:51 PM · Restricted Project
bjope updated the diff for D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.

Now calling the new helper in DataLayout typeSizeEqualsStoreSize().

Thu, May 23, 8:14 AM · Restricted Project

Wed, May 22

bjope added inline comments to D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.
Wed, May 22, 3:20 PM · Restricted Project
bjope updated the diff for D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.

Add a helper in DataLayout "isTypeStoreSized()" as suggested in the review.
Open for suggestions regarding the name (or is it clear enough what it means?).

Wed, May 22, 3:10 PM · Restricted Project
bjope added inline comments to D62223: [DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold.
Wed, May 22, 12:05 PM · Restricted Project
bjope added a comment to D62088: [compiler-rt][builtins] Scaled Integer log10().

I don't know much about compiler-rt, and neither what the procedure is for adding new builtins.
Maybe try to find some more reviewers (someone that has been doing/reviewing this kind of additions before).

Wed, May 22, 10:44 AM · Restricted Project, Restricted Project
bjope updated the diff for D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.

Just a minor fix to use "Type *" instead of "auto *".

Wed, May 22, 5:34 AM · Restricted Project
bjope created D62250: [DSE] Bugfix to avoid PartialStoreMerging involving non byte-sized stores.
Wed, May 22, 5:31 AM · Restricted Project

Mon, May 20

bjope added inline comments to D61940: [DebugInfo] Don't always extend variable locations when the reg location is unchanging.
Mon, May 20, 2:38 PM · Restricted Project
bjope committed rGeee0f2330dcf: [AMDGPU] Fix std::array initializers to avoid warnings with older tool chains. (authored by bjope).
[AMDGPU] Fix std::array initializers to avoid warnings with older tool chains.
Mon, May 20, 9:42 AM
bjope committed rL361171: [AMDGPU] Fix std::array initializers to avoid warnings with older tool chains..
[AMDGPU] Fix std::array initializers to avoid warnings with older tool chains.
Mon, May 20, 9:38 AM

May 17 2019

bjope accepted D55720: [Intrinsic] Signed Fixed Point Saturation Multiplication Intrinsic.

LGTM! (if all comments from other reviewers has been taken care of) (maybe you should wait another day to see if anyone else object, but I think this patch has been open for a long time so there have been plenty of time for comments already)

May 17 2019, 8:32 AM · Restricted Project

May 15 2019

bjope added inline comments to D55720: [Intrinsic] Signed Fixed Point Saturation Multiplication Intrinsic.
May 15 2019, 7:35 AM · Restricted Project
bjope added a reviewer for D61940: [DebugInfo] Don't always extend variable locations when the reg location is unchanging: bjope.

Adding myself as reviewer to remember to look at this patch.

May 15 2019, 5:30 AM · Restricted Project

May 14 2019

bjope added a comment to D61181: [WIP][DebugInfo] Avoid SelectionDAG un-necessarily debug-referring to dead VRegs.

Sorry. I realize that I've completely forgotten to look at this. I'll try to find some time before the end of the week.

May 14 2019, 8:57 AM · Restricted Project

May 13 2019

bjope added inline comments to D61061: [MachineFunction] Base support for call site info tracking.
May 13 2019, 10:22 AM · debug-info
bjope added a comment to D60715: [ISEL][X86] Tracking of registers that forward call arguments.

FYI: I have no further comments.

May 13 2019, 9:43 AM · debug-info

May 10 2019

bjope added inline comments to D55720: [Intrinsic] Signed Fixed Point Saturation Multiplication Intrinsic.
May 10 2019, 12:07 PM · Restricted Project

May 9 2019

bjope committed rG8d19e94f1303: [CodeGen] Use "DL.getPointerSizeInBits" instead of "8 * DL.getPointerSize". NFC (authored by bjope).
[CodeGen] Use "DL.getPointerSizeInBits" instead of "8 * DL.getPointerSize". NFC
May 9 2019, 1:07 AM
bjope committed rL360315: [CodeGen] Use "DL.getPointerSizeInBits" instead of "8 * DL.getPointerSize". NFC.
[CodeGen] Use "DL.getPointerSizeInBits" instead of "8 * DL.getPointerSize". NFC
May 9 2019, 1:06 AM

May 8 2019

bjope added inline comments to D59272: [DebugInfo] Select debug intrinsic line-numbers more carefully when promoting dbg.declare.
May 8 2019, 10:18 AM · Restricted Project

May 7 2019

bjope accepted D61499: Make sub-registers index names case sensitive in the MIRParser.

LGTM!

May 7 2019, 6:01 AM · Restricted Project
bjope added inline comments to D61625: Debug Info: Support address space attributes on rvalue references..
May 7 2019, 2:03 AM · Restricted Project, debug-info

May 2 2019

bjope added a comment to D60311: MIR printer should lowercase sub-register names to be in sync with parser?.

I'm suggesting to replace this with a solution where the subregister name is case sensitive (in MIR parser).
See: http://lists.llvm.org/pipermail/llvm-dev/2019-May/132081.html

May 2 2019, 6:23 AM · Restricted Project

May 1 2019

bjope added a comment to D61400: [SelectionDAG] Utilize ARM shift behavior.

Wouldn't it be better/safer to create ARMISD shift opcodes to handle this behaviour?

May 1 2019, 3:07 PM · Restricted Project

Apr 29 2019

bjope committed rG820994572c63: [DAG] Refactor DAGCombiner::ReassociateOps (authored by bjope).
[DAG] Refactor DAGCombiner::ReassociateOps
Apr 29 2019, 10:50 AM
bjope committed rL359476: [DAG] Refactor DAGCombiner::ReassociateOps.
[DAG] Refactor DAGCombiner::ReassociateOps
Apr 29 2019, 10:50 AM
bjope closed D61199: [DAG] Refactor DAGCombiner::ReassociateOps.
Apr 29 2019, 10:49 AM · Restricted Project
bjope added inline comments to D61062: Keep call site info valid through the backend.
Apr 29 2019, 12:58 AM · debug-info

Apr 28 2019

bjope updated the summary of D61199: [DAG] Refactor DAGCombiner::ReassociateOps.
Apr 28 2019, 12:51 PM · Restricted Project
bjope updated the summary of D61199: [DAG] Refactor DAGCombiner::ReassociateOps.
Apr 28 2019, 12:51 PM · Restricted Project
bjope updated the diff for D61199: [DAG] Refactor DAGCombiner::ReassociateOps.

Address review comments from @spatel (thanks!).

Apr 28 2019, 12:46 PM · Restricted Project

Apr 26 2019

bjope added inline comments to D61198: [IRBuilder][DebugInfo] Don't pick DebugLocs for new instructions from debug intrinsics.
Apr 26 2019, 10:29 AM · Restricted Project
bjope added inline comments to D61199: [DAG] Refactor DAGCombiner::ReassociateOps.
Apr 26 2019, 10:08 AM · Restricted Project
bjope added reviewers for D61199: [DAG] Refactor DAGCombiner::ReassociateOps: spatel, craig.topper, tstellar.
Apr 26 2019, 9:59 AM · Restricted Project
bjope created D61199: [DAG] Refactor DAGCombiner::ReassociateOps.
Apr 26 2019, 9:52 AM · Restricted Project

Apr 25 2019

bjope added inline comments to D59687: [DebugInfo] Prologue inserter need to insert DW_OP_deref_size.
Apr 25 2019, 6:08 AM · Restricted Project, debug-info
bjope added inline comments to D61061: [MachineFunction] Base support for call site info tracking.
Apr 25 2019, 12:21 AM · debug-info

Apr 24 2019

bjope added a comment to D60831: [DebugInfo@O2][LoopVectorize] pr39024: Vectorized code linenos step through loop even after completion.

This will be my last comment on the topic and then everyone can get back to work :-). I agree with the LLVM IR requirement that one not to lie to application developers; lies are worse than nothing. However, I don't feel that you have adequately explained why attributing to any of the available (file, line) mappings for an instruction that has been merged is incorrect and not 100% reliable. Just because we can't include all contributing mappings for a merged instruction doesn't make any one unreliable; I see attributing to any one of a set of mappings as 100% correct, even though it is only partial information.

Sorry for jumping in after you said you would stop, but I have been away.
Personally I find this example compelling: When there's an if/then/else construct, and some instruction is hoisted above the if, you could assign it to (for example) the source location of the 'then' block. Now in your training run, the 'then' block can be given 100% of executions (because that's what the hoisted instruction says) even if the 'else' block was chosen 100% of the time. I find the resulting profile is "incorrect and not 100% reliable" and when used for PGO will produce sub-optimal code. It is hard to imagine any other valid conclusion for this use-case.

As Adrian mentioned, being able to attribute multiple locations would be preferable to attributing line 0, and I hope we can make that happen in the future.

Apr 24 2019, 7:38 AM · debug-info, Restricted Project

Apr 23 2019

bjope committed rG71e8c6f20fe4: Add "const" in GetUnderlyingObjects. NFC (authored by bjope).
Add "const" in GetUnderlyingObjects. NFC
Apr 23 2019, 11:57 PM
bjope committed rL359072: Add "const" in GetUnderlyingObjects. NFC.
Add "const" in GetUnderlyingObjects. NFC
Apr 23 2019, 11:57 PM
bjope closed D61038: Add "const" in GetUnderlyingObjects.
Apr 23 2019, 11:57 PM · Restricted Project
bjope added a comment to D61038: Add "const" in GetUnderlyingObjects.

Seems like a NFC.
Looks awesome to me - const correctness for the win!

Apr 23 2019, 11:10 PM · Restricted Project
bjope created D61038: Add "const" in GetUnderlyingObjects.
Apr 23 2019, 2:20 PM · Restricted Project
bjope added inline comments to D58704: Initial (incomplete) implementation of JITLink - A replacement for RuntimeDyld..
Apr 23 2019, 1:52 PM · Restricted Project
bjope added inline comments to D60715: [ISEL][X86] Tracking of registers that forward call arguments.
Apr 23 2019, 1:45 PM · debug-info
bjope added inline comments to D60715: [ISEL][X86] Tracking of registers that forward call arguments.
Apr 23 2019, 1:37 PM · debug-info
bjope committed rGf97b29be884c: [DAGCombiner] Combine OR as ADD when no common bits are set (authored by bjope).
[DAGCombiner] Combine OR as ADD when no common bits are set
Apr 23 2019, 3:02 AM
bjope committed rL358965: [DAGCombiner] Combine OR as ADD when no common bits are set.
[DAGCombiner] Combine OR as ADD when no common bits are set
Apr 23 2019, 2:59 AM
bjope closed D59758: [DAGCombiner] Combine OR as ADD when no common bits are set.
Apr 23 2019, 2:59 AM · Restricted Project
bjope added inline comments to D53701: [Analyzer] Instead of recording comparisons in interator checkers do an eager state split.
Apr 23 2019, 2:19 AM · Restricted Project

Apr 19 2019

bjope added a comment to D59758: [DAGCombiner] Combine OR as ADD when no common bits are set.

LGTM (see inline for a couple of nits) - but I'd prefer that someone with AMDGPU knowledge (@arsenm @nhaehnle @rampitec ?) confirm those diffs too.

Apr 19 2019, 3:09 AM · Restricted Project
bjope committed rG18b0442560cc: [LibTooling] Fix -Wsign-compare after r358697 (authored by bjope).
[LibTooling] Fix -Wsign-compare after r358697
Apr 19 2019, 2:11 AM
bjope committed rC358745: [LibTooling] Fix -Wsign-compare after r358697.
[LibTooling] Fix -Wsign-compare after r358697
Apr 19 2019, 2:11 AM
bjope committed rL358745: [LibTooling] Fix -Wsign-compare after r358697.
[LibTooling] Fix -Wsign-compare after r358697
Apr 19 2019, 2:11 AM
bjope committed rG238c9d6308df: [CodeGen] Add "const" to MachineInstr::mayAlias (authored by bjope).
[CodeGen] Add "const" to MachineInstr::mayAlias
Apr 19 2019, 2:07 AM
bjope committed rL358744: [CodeGen] Add "const" to MachineInstr::mayAlias.
[CodeGen] Add "const" to MachineInstr::mayAlias
Apr 19 2019, 2:07 AM
bjope closed D60856: [CodeGen] Add "const" to MachineInstr::mayAlias.
Apr 19 2019, 2:06 AM · Restricted Project

Apr 18 2019

bjope created D60856: [CodeGen] Add "const" to MachineInstr::mayAlias.
Apr 18 2019, 1:17 AM · Restricted Project

Apr 17 2019

bjope added a comment to D59758: [DAGCombiner] Combine OR as ADD when no common bits are set.

If there still are worries about this, then maybe I can do the visitADD refactoring in a separate patch? And then I can limit this patch to the part where we start to use visitADDLike from visitOR.

Apr 17 2019, 11:12 AM · Restricted Project
bjope added a comment to D59758: [DAGCombiner] Combine OR as ADD when no common bits are set.

ping!

Apr 17 2019, 11:00 AM · Restricted Project
bjope added a comment to D60715: [ISEL][X86] Tracking of registers that forward call arguments.

Looks generally good. But...

Apr 17 2019, 12:18 AM · debug-info

Apr 15 2019

bjope added inline comments to D60311: MIR printer should lowercase sub-register names to be in sync with parser?.
Apr 15 2019, 2:10 AM · Restricted Project
bjope added inline comments to D60311: MIR printer should lowercase sub-register names to be in sync with parser?.
Apr 15 2019, 2:09 AM · Restricted Project
bjope committed rG60569363a589: [SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry (authored by bjope).
[SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry
Apr 15 2019, 12:19 AM
bjope committed rL358372: [SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry.
[SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry
Apr 15 2019, 12:19 AM
bjope closed D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 15 2019, 12:19 AM · Restricted Project

Apr 12 2019

bjope updated the diff for D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

Rebased. Corrected typos in the test cases.

Apr 12 2019, 2:09 PM · Restricted Project
bjope added inline comments to D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 12 2019, 8:32 AM · Restricted Project
bjope added inline comments to D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 12 2019, 8:32 AM · Restricted Project
bjope added a comment to D60522: [KnownBits] Add computeForAddCarry().

LGTM! (with a nit in the test case)

Apr 12 2019, 4:56 AM · Restricted Project

Apr 11 2019

bjope updated the diff for D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

Updated to use a KnownBits::computeForAddCarry helper. I added a simple
implementation here, but the idea is to replace it by the improved version
from D60522 instead (if we land that patch before this one).

Apr 11 2019, 8:47 AM · Restricted Project
bjope added inline comments to D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 11 2019, 2:19 AM · Restricted Project
bjope added inline comments to D60522: [KnownBits] Add computeForAddCarry().
Apr 11 2019, 2:02 AM · Restricted Project
bjope updated the diff for D59758: [DAGCombiner] Combine OR as ADD when no common bits are set.

Removed the add_zext_ifpos_vec_splat2 test from test/CodeGen/X86/signbit-shift.ll again (as suggested by @lebedev.ri). That test was only added to demonstrate why add_zext_ifpos_vec_splat gets an extra movdqa with this patch (due to unfortunate reg constraints), but it did not contribute anything new when it comes to testing "signbit-shift".

Apr 11 2019, 1:28 AM · Restricted Project
bjope updated subscribers of D59648: [BasicAliasAnalysis] Fix computation for arrays > half of address space.
Apr 11 2019, 12:22 AM · Restricted Project

Apr 10 2019

bjope updated the diff for D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

Simplified based on feedback.

Apr 10 2019, 5:21 AM · Restricted Project
bjope added inline comments to D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 10 2019, 4:48 AM · Restricted Project
bjope retitled D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits from [SelectionDAG] Let computeKnownBits handle OR-like ADDs better to [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.
Apr 10 2019, 2:39 AM · Restricted Project
bjope updated the diff for D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

Use KnownBits::computeForAddSub instead, and do it for both ADD* and SUB* nodes.

Apr 10 2019, 2:38 AM · Restricted Project
bjope added a comment to D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

We have an accurate known bits implementation for adds in KnownBits::computeForAddSub(), which should handle this and more automatically. We use it to compute add known bits in IR. Is there a reason why it's not used for SDAG known bits?

Hmm, good point. In general because of IR Value vs DAG SDValue. But clearly that function should work here..

Apr 10 2019, 1:21 AM · Restricted Project

Apr 9 2019

bjope updated the diff for D60460: [SelectionDAG] Use KnownBits::computeForAddSub in SelectionDAG::computeKnownBits.

Added a unittest (by using the AArch64SelectionDAGTest unittest framework).

Apr 9 2019, 1:07 PM · Restricted Project