[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[wangpc]

Summary

This commit includes the necessary changes to clang and LLVM to support
codegen of RVE and the ilp32e/lp64e ABIs.

The differences between RVE and RVI are:

• RVE reduces the integer register count to 16(x0-x16).
• The ABI should be ilp32e for 32 bits and lp64e for 64 bits.

RVE can be combined with all current standard extensions.

The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:

• Only 6 integer argument registers (rather than 8).
• Only 2 callee-saved registers (rather than 12).
• A Stack Alignment of 32bits (rather than 128bits).
• ilp32e isn't compatible with D ISA extension.

If ilp32e or lp64 is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.

To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.

FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.

[lenary]

• Provide correct datalayout
• Add clang support and tests
• Modify fp reservation code so we don't always use a frame pointer, even if we conservatively reserve it when using ilp32e + D extension.

[jrtc27]

clang/lib/CodeGen/TargetInfo.cpp

10323 ↗

(On Diff #316800)

I think it'd be better to have a NumArgGPRs(EAABI ? 6 : 8) here as having a default value that gets overwritten is more error-prone (and harder to follow).

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

17040

Underscores with camel-case isn't great. Maybe ArgIGPRs and ArgEGPRs or similar?

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

116

Shouldn't this all be done by the generic stack realignment code like any other allocation? Or is the issue because it's _register spills_ not explicit allocas?

llvm/test/CodeGen/RISCV/stack-realignment.ll

3–5

Multiple prefixes is a bad idea with update_llc_test_checks.py, and why is this one done differently from the rest?

[lenary]

• Add Variadic Testcase

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

17247

I missed that I need to cover this case.

I'm going to upload a testcase based on your example, but I'm not quite convinced it's correct. It does seem to align the stack correctly for the fp64, but that's maybe not the right thing to be doing here?

I haven't managed to execute the assembly in the testcase, but I thought adding the testcase was important.

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

14

I went back and thinking about this, we just need to make sure fp is reserved for later, rather than overriding hasFP, so we don't need to reserve FP unnecessarily.

Iterating over used registers to find FP64 registers didn't fill me with joy, and if you override canRealignStackFrame, it seems you just get very incorrect stack management (where the code just… doesn't bother to realign the stack before saving/restoring).

[lenary]

Address @jrtc27's Feedback:

• Cleaned up Clang's RISC-V ABI Lowering Code
• Cleaned up tests
• Cleaned up leftover method implementation
• Updated fp reservation comment
• Cleaned up names

[lenary]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

116

Yeah the issue is because it’s register spills. I have a nice long commit message I wrote that I should update the summary with.

Comment updated nonetheless

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

40 ↗

(On Diff #316806)

I forgot this was left in after some experimentation I did. Will remove it in the next update.

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

28

These check lines are left over from before. will remove

llvm/test/CodeGen/RISCV/stack-realignment.ll

3–5

It also doesn’t help to avoid duplication here.

[khchen]

Hi, I would like to add ilp32e ABI support in llvm
Is there anyone working on this?
It seem the one thing missed is ilp32e ABI should disallow D ISA extension.
Is there anything else?

[asb]

In D70401#2733003, @khchen wrote:

Hi, I would like to add ilp32e ABI support in llvm
Is there anyone working on this?
It seem the one thing missed is ilp32e ABI should disallow D ISA extension.
Is there anything else?

Nobody is currently working on this on the lowRISC side, so please do pick this up if you're interested. I can't quite recall the open issues I'm afraid.

[zixuan-wu]

Hi, all. Why is it not continued?

[khchen]

In D70401#3172457, @zixuan-wu wrote:

Hi, all. Why is it not continued?

Sorry, I have to work on other tasks so stop the rv32e implementation work.
Are you interest to finish it? I could share my patches to you.

[zixuan-wu]

In D70401#3172750, @khchen wrote:

In D70401#3172457, @zixuan-wu wrote:

Hi, all. Why is it not continued?

Sorry, I have to work on other tasks so stop the rv32e implementation work.
Are you interest to finish it? I could share my patches to you.

Is it (D70401) good enough to solve or complete rv32e issue?

[khchen]

Is it (D70401) good enough to solve or complete rv32e issue?

It need to

1. disallow ilp32e ABI with D ISA extension. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/3f81fae0412bb9ad4002a4ade508be7aa5e1599b/riscv-cc.adoc#ilp32e-calling-convention
2. emit predefined marco in header (__riscv_e)
3. markSuperRegs for X16-X31
4. update tests after rebase on main.

[zixuan-wu]

In D70401#3175266, @khchen wrote:

Is it (D70401) good enough to solve or complete rv32e issue?

It need to

1. disallow ilp32e ABI with D ISA extension. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/3f81fae0412bb9ad4002a4ade508be7aa5e1599b/riscv-cc.adoc#ilp32e-calling-convention
2. emit predefined marco in header (__riscv_e)
3. markSuperRegs for X16-X31
4. update tests after rebase on main.

Nice. If no body objects, @pcwang-thead will take this task and re-draft a review.

[lenary]

In D70401#3188138, @zixuan-wu wrote:

In D70401#3175266, @khchen wrote:

Is it (D70401) good enough to solve or complete rv32e issue?

It need to

1. disallow ilp32e ABI with D ISA extension. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/3f81fae0412bb9ad4002a4ade508be7aa5e1599b/riscv-cc.adoc#ilp32e-calling-convention
2. emit predefined marco in header (__riscv_e)
3. markSuperRegs for X16-X31
4. update tests after rebase on main.

Nice. If no body objects, @pcwang-thead will take this task and re-draft a review.

Please do feel free to commandeer the current patch. I cannot continue to work on it (so, you won't see review comments from me).

[• pcwang-thead]

• Rebase.
• Reserve x16-x31 when using RV32E.
• Make ilp32e incompatible with D extension.
• Update/Add tests.

[• pcwang-thead]

• Add macro __riscv_32e.

[• pcwang-thead]

• Update tests.

[• pcwang-thead]

• Fix tests.

[• pcwang-thead]

ping.

[• pcwang-thead]

Update tests.

[• pcwang-thead]

Gentle ping.

We are testing this patch and I'd like to get some nice advice.

[khchen]

1. please add a check here and a clang cc1 test for it.
2. Have you try to run llvm-test-suite with rv32e config on qemu?

llvm/lib/Support/TargetParser.cpp

339 ↗

(On Diff #396384)

why do we need to change the order?

[• pcwang-thead]

llvm/lib/Support/TargetParser.cpp

339 ↗

(On Diff #396384)

IMO, when e is combined with d, e should have higher priority so that the default ABI will be ilp32e and then this error will be reported.

[zixuan-wu]

This comment was removed by zixuan-wu.

[zixuan-wu]

It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are no workable environment such as runtime and kernel for ilp32e in GNU series tools.
And we can not run llvm-test-suite in baremental environment(NOT linux but elf triple). So I have a question about how to test llvm in elf triple and environment? Is there any test case llvm community normally uses and accepts?

[zixuan-wu]

Sorry for the wrong action of commandeer, @pcwang-thead will still be the author.

[khchen]

In D70401#3325419, @zixuan-wu wrote:

It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are no workable environment such as runtime and kernel for ilp32e in GNU series tools.
And we can not run llvm-test-suite in baremental environment(NOT linux but elf triple). So I have a question about how to test llvm in elf triple and environment? Is there any test case llvm community normally uses and accepts?

I believe you can try QEMU, I tried it before.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/JE0aG-Mr0u4/m/tfFoITv7AgAJ
For llvm-test-suite, you could disable some non-baremental tests manually.
I found some issues in my local rv32e implementation by running llvm-test-suite before, it's why I think it's good to have a test.

Maybe the other reviewers have different opinions about this.
@luismarques @jrtc27 @asb @kito-cheng What do you think?

[• pcwang-thead]

In D70401#3250049, @khchen wrote:

1. please add a check here and a clang cc1 test for it.
2. Have you try to run llvm-test-suite with rv32e config on qemu?

1. Thanks, I may do it later. And here is a question: the comment says It is illegal to specify 'e' extensions with 'f' and 'd'.

While ilp32e says:

The ILP32E calling convention is not compatible with ISAs that have registers that require load and store alignments of more than 32 bits. In particular, this calling convention must not be used with the D ISA extension.

And, the RV32E chapter in RISCV ISA manual says:

RV32E can be combined with all current standard extensions.

If I understand correctly, E can't be combined with D in current specification since E must use ILP32E calling convention.

2. I have run llvm-test-suite with rv32e on qemu, and found no major fault for current implementation. Some tests are disabled because they can't run on bare mental (sees Disabled llvm-test-suite cases).

There are some failed tests due to floating-point precision, but I saw the same result when run with rv32imc on bare mental. I haven't taken the time to find out the reason, but I guess it may be soft-float issues.

[khchen]

In D70401#3384758, @pcwang-thead wrote:

In D70401#3250049, @khchen wrote:

1. please add a check here and a clang cc1 test for it.
2. Have you try to run llvm-test-suite with rv32e config on qemu?

1. Thanks, I may do it later. And here is a question: the comment says It is illegal to specify 'e' extensions with 'f' and 'd'.

While ilp32e says:

The ILP32E calling convention is not compatible with ISAs that have registers that require load and store alignments of more than 32 bits. In particular, this calling convention must not be used with the D ISA extension.

And, the RV32E chapter in RISCV ISA manual says:

RV32E can be combined with all current standard extensions.

If I understand correctly, E can't be combined with D in current specification since E must use ILP32E calling convention.

IMO, at least clang need to follows the gcc's implementation.
I guess gcc implementation follow riscv-elf-psabi-doc, @kito-cheng could you please confirm that?

2. I have run llvm-test-suite with rv32e on qemu, and found no major fault for current implementation. Some tests are disabled because they can't run on bare mental (sees Disabled llvm-test-suite cases).

There are some failed tests due to floating-point precision, but I saw the same result when run with rv32imc on bare mental. I haven't taken the time to find out the reason, but I guess it may be soft-float issues.

Thanks for testing!! I also tested your patch locally,
Could you please make sure all gcc and clang results are the same in your failed tests?

I found https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
Did you have same issue?

my build option:

$/path/to/rv32e-gcc/bin/riscv32-unknown-elf-gcc -march=rv32e -mabi=ilp32e 2003-05-26-Shorts.c
$./bin/clang --target=riscv32 -march=rv32e -mabi=ilp32e --gcc-toolchain=/path/to/rv32e-gcc/ 2003-05-26-Shorts.c

clang output:

   ui = 3318069411 (0xc5c5b8a3)         UL-ui = 0 (0xafafafaf)                            
ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = -2060025877491592863 (0xe369516100000000)       
                                                                                          
    i = -976897885 (0xc5c5b8a3) L-i = 0 (0xafafafb0)                                      
 i* i = -1912031287 (0x8e08b7c9)        L/ i = 6996953267980741613 (0x611a2bed00000001)   
                                                                                          
us    = 47267 (0xb8a3)          UL-us = -4195947477825748992 (0xc5c50000afafafaf)         
us*us = 2234169289 (0x852ab7c9)   UL/us = 1452874783539635691 (0x1429a5eb0000f397)        
                                                                                          
 s    = -18269 (0xffffb8a3)     L-s = -4195666002849038335 (0xc5c60000afafafaf)           
 s* s = 333756361 (0x13e4b7c9)  L/ s = -7718140893307295808 (0x94e3a7c00001201b)          
                                                                                          
ub    = 163 (0xa3)              UL-ub = -4195745167686238208 (0xc5c5b800afafafaf)         
ub*ub = 26569 (0x67c9)          UL/ub = 2350833624863004346 (0x209fd6ba0113eca9)          
                                                                                          
 b    = -93 (0xffffffa3)                L-b = -4195744068174610431 (0xc5c5b900afafafaf)   
 b* b = 8649 (0x21c9)                   L/b = -1938405340110362979 (0xe519669d00dd1421)

gcc output:

   ui = 3318069411 (0xc5c5b8a3)         UL-ui = -5787213829993660416 (0xafafafaf00000000)
ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = 3815330145 (0xe3695161)

    i = -976897885 (0xc5c5b8a3) L-i = -5787213825698693120 (0xafafafb000000000)
 i* i = -1912031287 (0x8e08b7c9)        L/ i = 5924072429 (0x1611a2bed)

us    = 47267 (0xb8a3)          UL-us = -5787213826675638272 (0xafafafafc5c50000)
us*us = 2234169289 (0x852ab7c9)   UL/us = 267830203885035 (0xf3971429a5eb)

 s    = -18269 (0xffffb8a3)     L-s = -5787213826675572736 (0xafafafafc5c60000)
 s* s = 333756361 (0x13e4b7c9)  L/ s = 316777810864064 (0x1201b94e3a7c0)

ub    = 163 (0xa3)              UL-ub = -5787213826675591168 (0xafafafafc5c5b800)
ub*ub = 26569 (0x67c9)          UL/ub = 77665829736404666 (0x113eca9209fd6ba)

 b    = -93 (0xffffffa3)                L-b = -5787213826675590912 (0xafafafafc5c5b900)
 b* b = 8649 (0x21c9)                   L/b = 62228105663178397 (0xdd1421e519669d)

[kito-cheng]

If I understand correctly, E can't be combined with D in current specification since E must use ILP32E calling convention.

Calling convention and extensions are separated, calling convention are specify the how argument passing and the register convention, so ILP32E *can* use with -march=rv32efd, but it can't pass or return floating point type in FPR.

Just like we can ILP32 for -march=rv32ifd and LP64 with -march=rv64ifd, you may confused about the opposite combination like ILP32D with -march=rv32i and LP64D with -march=rv64i is not work, that's because it require pass or return floating point type in FPR, but FPR isn't existing in such ISA config.

[kito-cheng]

Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so here is note from my site:

RISC-V psABI doc still say "we don't guarantee the stability of ILP32E", the reason is RV32E still not a ratified extension, but as psABI chair, what I can say is we intend to do NOT change as possible.

As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so I support ilp32e should be supported on LLVM upstream.

[• pcwang-thead]

In D70401#3395340, @kito-cheng wrote:

Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so here is note from my site:

RISC-V psABI doc still say "we don't guarantee the stability of ILP32E", the reason is RV32E still not a ratified extension, but as psABI chair, what I can say is we intend to do NOT change as possible.

As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so I support ilp32e should be supported on LLVM upstream.

Thanks! I will spend some time to make this patch compatible with GCC implementation, please feel free to give some comments and suggestions!

[• pcwang-thead]

In D70401#3391561, @khchen wrote:

I found https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
Did you have same issue?

I got the same issue, but it may be not this patch's problem.
Here is the reduced case:

#include <stdio.h>

unsigned long long getL() { return 0xafafafafc5c5b8a3ull; }
int main(int argc, char **argv) {
  unsigned long long UL = getL();     /* 0xafafafafc5c5b8a3 */
  unsigned int ui = (unsigned int)UL; /* 0xc5c5b8a3 =  3318069411 */
  printf("ui = %u (0x%x)\t\tUL-ui = %lld (0x%llx)\n", ui, ui, UL - ui, UL - ui);
}

GCC output is:

ui = 3318069411 (0xc5c5b8a3)            UL-ui = -5787213829993660416 (0xafafafaf00000000)

LLVM output is:

ui = 3318069411 (0xc5c5b8a3)            UL-ui = 0 (0xafafafaf)

The problem is the way to pass arguments to printf.
GCC asm:

	li	a4,-1347440640
	addi	sp,sp,-24
	addi	a4,a4,-81
	sw	a4,8(sp)
	lw	a5,8(sp)
	li	a2,-976896000
	addi	a2,a2,-1885
	lui	a0,%hi(.LC1)
	sw	a5,0(sp)
	li	a3,0
	li	a5,0
	mv	a1,a2
	addi	a0,a0,%lo(.LC1)
	sw	ra,20(sp)
	sw	a3,4(sp)
	call	printf

LLVM asm:

	addi	sp, sp, -16
	sw	ra, 12(sp)                      # 4-byte Folded Spill
	sw	s0, 8(sp)                       # 4-byte Folded Spill
	addi	s0, sp, 16
	andi	sp, sp, -8
	lui	a0, 719611
	addi	a5, a0, -81
	sw	a5, 4(sp)
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	lui	a1, 810076
	addi	a1, a1, -1885
	sw	zero, 0(sp)
	mv	a2, a1
	mv	a4, zero
	call	printf

Both GCC and LLVM pass format string and two ui by a0, a1, a2, the difference is how they pass rest variadic arguments.
UL-ui is with 2*XLEN size, so it will be spilt to two part (low and high 32-bits). Low part is 0x00000000, high part is 0xafafafaf.
For GCC:

First UL-ui: low -> a3, high -> a4
Second UL-ui: low -> a5, high -> stack.0

For LLVM:

First UL-ui: low -> a4, high -> a5
Second UL-ui: low -> stack.0, high -> stack.1

Because we use GLIBC compiled by GCC while linking with LLVM's output, so in printf's view:

a3 -> undefined, so it is zero.
a4 -> low part, 0x00000000
a5 -> high part, 0xafafafaf
stack.0 -> low part, 0x00000000
stack.1 -> not used

It get 0x0000000000000000 and 0x00000000afafafaf for two UL-ui (seen as the output).

In the ABI specification, it says (Integer Calling Convention):

In the base integer calling convention, variadic arguments are passed in the same manner as named arguments, with one exception. Variadic arguments with 2×XLEN-bit alignment and size at most 2×XLEN bits are passed in an aligned register pair (i.e., the first register in the pair is even-numbered), or on the stack by value if none is available. After a variadic argument has been passed on the stack, all future arguments will also be passed on the stack (i.e. the last argument register may be left unused due to the aligned register pair rule).

And this is what LLVM do for ILP32E currently.

I saw the same issue on Github(Inconsistent variadic argument passing behavior between ilp32 and ilp32e for long long/double), so shall LLVM be compatible with GCC's behavior?
@kito-cheng @khchen

[• pcwang-thead]

• Support FastCC and disable GHC on RV32E.
• Don't use aligned registers to pass variadic arguments.
• Set stack alignment to 4-bytes for types with length of 2*XLEN.
• Add some tests.

[• pcwang-thead]

Rebase and fix test errors.

[• pcwang-thead]

Refactor.

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

116

I am wondering whether we need construct another new RegisterClass for RV32E instead of GPR, for example eGPR, so that the num and other info such as weight, etc of RegisterClass can adjust. Then the reserved logic is not necessary.

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

515–519

I think this 16 should be adjusted as above logic for rv32e

[• pcwang-thead]

• Rebase.
• Align libcall stack size to getStackAlign().

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

515–519

Thanks. :-)

[luojia]

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

[• pcwang-thead]

In D70401#3873347, @luojia wrote:

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when RV32E/ilp32e is ratified.

1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

[StephenFan]

In D70401#3873874, @pcwang-thead wrote:

In D70401#3873347, @luojia wrote:

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when RV32E/ilp32e is ratified.

1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

RV32E/ilp32e has been ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan to proceed with this patch? :)

[• pcwang-thead]

In D70401#3948829, @StephenFan wrote:

In D70401#3873874, @pcwang-thead wrote:

In D70401#3873347, @luojia wrote:

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when RV32E/ilp32e is ratified.

1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

RV32E/ilp32e has been ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan to proceed with this patch? :)

I will follow the proceeding of spec and finish this patch, but I don't think they have been ratified.
There are some changes about RV32E/RV64E, but I think they are still proposal.
And, there are still some issues we need to fix in the psabi:

• Add the LP64E ABI, to support RV64E
• ilp32e issue

[• pcwang-thead]

Rebase.

If D143570 is committed, I will do some works to support of RV64E/lp64e.

[recallmenot]

Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
I tried replacing my distros llvm and clang with a patched version of this like this:

git clone https://aur.archlinux.org/llvm-git.git
cd llvm-git
mkdir src
cd src
git clone https://github.com/llvm/llvm-project.git
cd llvm-project
arc patch D70401
cd ../..
mv llvm-config.h src/
makepkg -es
sudo pacman -Rd --nodeps clang llvm
makepkg -eid

but that bricked my xfce-wayland-manjaro DE (one screen black)
And in config.toml if I put

[build]
target = "riscv32i-unknown-none-elf"
rustflags = [
	"-C", "target-feature=+e,+c"
]

then build with cargo build
LLVM still complains it doesn't implement CodeGen for RV32E yet
What am I doing wrong?
Ended up reverting to repository llvm and clang, desktop now works again but CodeGen is obviously missing.

[• pcwang-thead]

In D70401#4204511, @recallmenot wrote:

Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
I tried replacing my distros llvm and clang with a patched version of this like this:

git clone https://aur.archlinux.org/llvm-git.git
cd llvm-git
mkdir src
cd src
git clone https://github.com/llvm/llvm-project.git
cd llvm-project
arc patch D70401
cd ../..
mv llvm-config.h src/
makepkg -es
sudo pacman -Rd --nodeps clang llvm
makepkg -eid

but that bricked my xfce-wayland-manjaro DE (one screen black)
And in config.toml if I put

[build]
target = "riscv32i-unknown-none-elf"
rustflags = [
	"-C", "target-feature=+e,+c"
]

then build with cargo build
LLVM still complains it doesn't implement CodeGen for RV32E yet
What am I doing wrong?
Ended up reverting to repository llvm and clang, desktop now works again but CodeGen is obviously missing.

I don't see any obvious problem here.
I am not familiar with rust. Is riscv32i-unknown-none-elf a valid target for rustc, it should be something like riscv32-unknown-elf in LLVM I think. And is target-feature=+e,+c the right way to specify features?
Can you please provide the whole command/arguments passed to LLVM?

[• pcwang-thead]

• Rebase.
• Add base support of RV64E/lp64e.

Any feedbacks are welcomed.

[recallmenot]

In D70401#4205333, @pcwang-thead wrote:

In D70401#4204511, @recallmenot wrote:

Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
I tried replacing my distros llvm and clang with a patched version of this like this:

git clone https://aur.archlinux.org/llvm-git.git
cd llvm-git
mkdir src
cd src
git clone https://github.com/llvm/llvm-project.git
cd llvm-project
arc patch D70401
cd ../..
mv llvm-config.h src/
makepkg -es
sudo pacman -Rd --nodeps clang llvm
makepkg -eid

but that bricked my xfce-wayland-manjaro DE (one screen black)
And in config.toml if I put

[build]
target = "riscv32i-unknown-none-elf"
rustflags = [
	"-C", "target-feature=+e,+c"
]

then build with cargo build
LLVM still complains it doesn't implement CodeGen for RV32E yet
What am I doing wrong?
Ended up reverting to repository llvm and clang, desktop now works again but CodeGen is obviously missing.

I don't see any obvious problem here.
I am not familiar with rust. Is riscv32i-unknown-none-elf a valid target for rustc, it should be something like riscv32-unknown-elf in LLVM I think. And is target-feature=+e,+c the right way to specify features?
Can you please provide the whole command/arguments passed to LLVM?

Yeah so I looked at the at the target files of rustc, telling rustc to do RV32I will indeed result in RV32 and the way to enable the E and C features seems to be correct, BUT:
rust uses their own "special sauce" version of llvm and rustc needs to be built against that to enable the new features. I tried to apply (patch) the diff directly to rusts llvm branch but there were many errors, and I couldn't figure out how to apply them manually since some things are different.
I'm stuck, this is all way beyond my understanding. Sorry I can't test it for you guys.
What I did was:

git clone https://github.com/rust-lang/rust.git
cd rust
nvim config.toml

[llvm]
download-ci-llvm = false

then I started building with

./x.py build

and as soon as the rust-llvm source was downloaded completely I aborted (CTRL+C).

then downloaded the raw diff from this page (button top right) into the rust llvm dir, opened a terminal in that dir and tried to patch with

patch -p1 < D70401.diff

but that gives lots of errors
resolving them manually seems way beyond me, especially since patch seems to already use fuzzy matching

[• pcwang-thead]

In D70401#4226549, @recallmenot wrote:

In D70401#4205333, @pcwang-thead wrote:

In D70401#4204511, @recallmenot wrote:

Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
I tried replacing my distros llvm and clang with a patched version of this like this:

git clone https://aur.archlinux.org/llvm-git.git
cd llvm-git
mkdir src
cd src
git clone https://github.com/llvm/llvm-project.git
cd llvm-project
arc patch D70401
cd ../..
mv llvm-config.h src/
makepkg -es
sudo pacman -Rd --nodeps clang llvm
makepkg -eid

but that bricked my xfce-wayland-manjaro DE (one screen black)
And in config.toml if I put

[build]
target = "riscv32i-unknown-none-elf"
rustflags = [
	"-C", "target-feature=+e,+c"
]

then build with cargo build
LLVM still complains it doesn't implement CodeGen for RV32E yet
What am I doing wrong?
Ended up reverting to repository llvm and clang, desktop now works again but CodeGen is obviously missing.

I don't see any obvious problem here.
I am not familiar with rust. Is riscv32i-unknown-none-elf a valid target for rustc, it should be something like riscv32-unknown-elf in LLVM I think. And is target-feature=+e,+c the right way to specify features?
Can you please provide the whole command/arguments passed to LLVM?

Yeah so I looked at the at the target files of rustc, telling rustc to do RV32I will indeed result in RV32 and the way to enable the E and C features seems to be correct, BUT:
rust uses their own "special sauce" version of llvm and rustc needs to be built against that to enable the new features. I tried to apply (patch) the diff directly to rusts llvm branch but there were many errors, and I couldn't figure out how to apply them manually since some things are different.
I'm stuck, this is all way beyond my understanding. Sorry I can't test it for you guys.
What I did was:

git clone https://github.com/rust-lang/rust.git
cd rust
nvim config.toml

[llvm]
download-ci-llvm = false

then I started building with

./x.py build

and as soon as the rust-llvm source was downloaded completely I aborted (CTRL+C).

then downloaded the raw diff from this page (button top right) into the rust llvm dir, opened a terminal in that dir and tried to patch with

patch -p1 < D70401.diff

but that gives lots of errors
resolving them manually seems way beyond me, especially since patch seems to already use fuzzy matching

So it seems that rust uses its own llvm branch based on released llvm branch, so I think you may download old version of this patch which is near the baseline of rust llvm branch and try again. :-)

[kekcheburec]

This comment was removed by kekcheburec.

[david-sawatzke]

Hey I've tried using this patch (roughly following https://noxim.xyz/blog/rust-ch32v003/).

It uses the older version of this patch for the rust llvm version (here the llvm tree https://github.com/Noxime/llvm-project/tree/rv32e) and I use rust commit 0939ec13 (together with the small patch for the RVE).

I've experience some issues that results in corruption of $sp, the following is the smallest reproduction (hopefully small enough):
Code:

rust
#![no_std]

pub fn test()  {
}

which, with the following .ll for release builds:

source_filename = "miscomp_repro.8b6a426d3b54bd13-cgu.0"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32"

define dso_local void @_ZN13miscomp_repro4test17h065760f827b95d43E() unnamed_addr #0 {
start:
  ret void
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "target-cpu"="generic-rv32" "target-features"="+e,+c" }

results in this assembly:

	.text
	.attribute	4, 4
	.attribute	5, "rv32e1p9_c2p0"
	.file	"miscomp_repro.8b6a426d3b54bd13-cgu.0"
	.section	.text._ZN13miscomp_repro4test17h065760f827b95d43E,"ax",@progbits
	.globl	_ZN13miscomp_repro4test17h065760f827b95d43E
	.p2align	1
	.type	_ZN13miscomp_repro4test17h065760f827b95d43E,@function
_ZN13miscomp_repro4test17h065760f827b95d43E:
	mv	sp, s0
	ret
.Lfunc_end0:
	.size	_ZN13miscomp_repro4test17h065760f827b95d43E, .Lfunc_end0-_ZN13miscomp_repro4test17h065760f827b95d43E

	.section	".note.GNU-stack","",@progbits

Since s0 isn't required to have any specific contents (and in the larger project this was extracted from doesn't), this corrupts the stack pointer. Large functions using the stack first save sp to 0, so not all functions have this issue. This also happens (but more verbose) in debug builds, but works fine with the exact same toolchain using the riscv32i target.

Here is the repro with some further output, I hope this patch and not something else is to blame (if so, sorry in advance).

miscomp_repro.zip42 KBDownload

[• pcwang-thead]

In D70401#4409782, @david-sawatzke wrote:

Hey I've tried using this patch (roughly following https://noxim.xyz/blog/rust-ch32v003/).

It uses the older version of this patch for the rust llvm version (here the llvm tree https://github.com/Noxime/llvm-project/tree/rv32e) and I use rust commit 0939ec13 (together with the small patch for the RVE).

I've experience some issues that results in corruption of $sp, the following is the smallest reproduction (hopefully small enough):
Code:

rust
#![no_std]

pub fn test()  {
}

which, with the following .ll for release builds:

source_filename = "miscomp_repro.8b6a426d3b54bd13-cgu.0"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32"

define dso_local void @_ZN13miscomp_repro4test17h065760f827b95d43E() unnamed_addr #0 {
start:
  ret void
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "target-cpu"="generic-rv32" "target-features"="+e,+c" }

results in this assembly:

	.text
	.attribute	4, 4
	.attribute	5, "rv32e1p9_c2p0"
	.file	"miscomp_repro.8b6a426d3b54bd13-cgu.0"
	.section	.text._ZN13miscomp_repro4test17h065760f827b95d43E,"ax",@progbits
	.globl	_ZN13miscomp_repro4test17h065760f827b95d43E
	.p2align	1
	.type	_ZN13miscomp_repro4test17h065760f827b95d43E,@function
_ZN13miscomp_repro4test17h065760f827b95d43E:
	mv	sp, s0
	ret
.Lfunc_end0:
	.size	_ZN13miscomp_repro4test17h065760f827b95d43E, .Lfunc_end0-_ZN13miscomp_repro4test17h065760f827b95d43E

	.section	".note.GNU-stack","",@progbits

Since s0 isn't required to have any specific contents (and in the larger project this was extracted from doesn't), this corrupts the stack pointer. Large functions using the stack first save sp to 0, so not all functions have this issue. This also happens (but more verbose) in debug builds, but works fine with the exact same toolchain using the riscv32i target.

Here is the repro with some further output, I hope this patch and not something else is to blame (if so, sorry in advance).

miscomp_repro.zip42 KBDownload

Thanks for reporting this.
I tried to compile your .ll on my local machine with newest patch, I didn't see the problem. I don't know if it is the bug in older version of this patch, so I suggest you to update the patch and try again. :-)
By the way, you can provide the log when you compile the .ll with -mllvm -print-after-all option (and -mllvm -debug if your llvm is a debug build). It can be helpful for me to figure out which part is wrong.

[david-sawatzke]

Thank you for the reply, I've compiled this with the most recent patch and also didn't see a problem (but can't get it running with rustc). Building the .ll with the older patch, the same issue also occurs, so I *do* think its the old patch version?
Here is the log output for the riscv32e

llvm_output81 KBDownload

(and as a sanity check riscv32i)

llvm_output_riscv32i80 KBDownload

The errant code seems to get introduced here:

# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
# Machine code for function _ZN13miscomp_repro4test17h065760f827b95d43E: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten, TracksDebugUserValues

bb.0.start:
  $x2 = frame-destroy ADDI $x8, 0
  PseudoRET

[• pcwang-thead]

In D70401#4411560, @david-sawatzke wrote:

Thank you for the reply, I've compiled this with the most recent patch and also didn't see a problem (but can't get it running with rustc). Building the .ll with the older patch, the same issue also occurs, so I *do* think its the old patch version?
Here is the log output for the riscv32e

llvm_output81 KBDownload

(and as a sanity check riscv32i)

llvm_output_riscv32i80 KBDownload

The errant code seems to get introduced here:

# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
# Machine code for function _ZN13miscomp_repro4test17h065760f827b95d43E: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten, TracksDebugUserValues

bb.0.start:
  $x2 = frame-destroy ADDI $x8, 0
  PseudoRET

Thanks! It seems that the problem is that we do wrong FP adjustment here.
But, as you can see, this patch does almost nothing to RISCVFrameLowering. So I think the bug may have been fixed somewhere else (I do remember there is a bug fix but I can't remember the differential ID).
So I would suggest you to use newest patch or do some bitsecting to find the bug fix commit if you don't bother. :-)

[• pcwang-thead]

Rebase

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

998

Hi, @wangpc it's hidden bug that out of range registers are saved/restored in prologue/epilogue

[wangpc]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

998

Thanks! We don't need to save X16-X31 for interrupt functions.

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

66–69

Here also need adjust for rve.

[wangpc]

• Rebase.
• Fix PEI bugs of interrupt functions.

[koute]

I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please?

The patch is simple enough to not become a maintenance burden, and GCC already has it even though the ABI's unfinished, and the RV32E target itself is most likely going to be used for standalone bare metal programs where the exact ABI shouldn't matter too much as long as it works.

I'm asking because I'd really like to have this merged so that I could use Rust to target RV32E/RV64E. Right now I have to maintain my own toolchain, which is painful; if this got merged (even in an experimental fashion, like GCC has) I could just get upstream Rust to support it out-of-box.

[wangpc]

In D70401#4635875, @koute wrote:

I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please?

The patch is simple enough to not become a maintenance burden, and GCC already has it even though the ABI's unfinished, and the RV32E target itself is most likely going to be used for standalone bare metal programs where the exact ABI shouldn't matter too much as long as it works.

I'm asking because I'd really like to have this merged so that I could use Rust to target RV32E/RV64E. Right now I have to maintain my own toolchain, which is painful; if this got merged (even in an experimental fashion, like GCC has) I could just get upstream Rust to support it out-of-box.

@asb @kito-cheng @jrtc27 What do you think about?

[craig.topper]

clang/lib/CodeGen/Targets/RISCV.cpp

491

4-bytes -> 4-byte

clang/test/Preprocessor/riscv-target-features.c

6

__riscv_64e too

llvm/lib/Support/RISCVISAInfo.cpp

987–989

This needs to be rebased. These FIXMEs were removed.

[luojia]

In D70401#4635875, @koute wrote:

I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please?

The patch is simple enough to not become a maintenance burden, and GCC already has it even though the ABI's unfinished, and the RV32E target itself is most likely going to be used for standalone bare metal programs where the exact ABI shouldn't matter too much as long as it works.

I'm asking because I'd really like to have this merged so that I could use Rust to target RV32E/RV64E. Right now I have to maintain my own toolchain, which is painful; if this got merged (even in an experimental fashion, like GCC has) I could just get upstream Rust to support it out-of-box.

I agree. Lots of our Rust work on low-level RISC-V cores (embedded, monitor hart, etc.) rely on RVE and they depend on RVE support on LLVM. We've waited for LLVM upstream support for an amount of years; considering how much time the community have waited for, RVE codegen can be accepted even if it's marked experimental.

[wangpc]

• Rebase.
• Address comments.
• Add ReleaseNotes.

[zixuan-wu]

ping?

[kekcheburec]

In D70401#4653409, @zixuan-wu wrote:

ping?

Pong 😂

[zixuan-wu]

LGTM if nobody objects.

[wangpc]

@asb @kito-cheng @jrtc27 @craig.topper
Can I commit this since the support of RVE is really of great importance for some downstreams? If there are some problems, I will be there to fix them.
If we all agree with this, I will mark RVE as exprimental and commit it then.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

17586

This code has been rewritten recently. Please rebase

[asb]

First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience.

I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at least get it to match what GCC actually implements (spec. That said, I've not really vocalised that concern clearly up to now - so that's my bad.

Matching what GCC does by setting stack alignment to 4 bytes for 2xlen types seems fine - except this doesn't seem to be documented explicitly in the current ABI doc (it notes the stack if 4 byte aligned, but you could have that be the case and still require it to be realigned when storing objects with a greater alignment requirement, surely?).

Having different alignment requirements _only_ on the stack does seem ugly, but I can't think of something off hand that would realistically break with this.

@wangpc do you want to update this with the suggested documentation in the release notes and RISCVUsage on the support being "experimental"?

[wangpc]

• Rebase.
• Mask as experimental.

[wangpc]

In D70401#4655408, @asb wrote:

First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience.

I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at least get it to match what GCC actually implements (spec. That said, I've not really vocalised that concern clearly up to now - so that's my bad.

Matching what GCC does by setting stack alignment to 4 bytes for 2xlen types seems fine - except this doesn't seem to be documented explicitly in the current ABI doc (it notes the stack if 4 byte aligned, but you could have that be the case and still require it to be realigned when storing objects with a greater alignment requirement, surely?).

Having different alignment requirements _only_ on the stack does seem ugly, but I can't think of something off hand that would realistically break with this.

@wangpc do you want to update this with the suggested documentation in the release notes and RISCVUsage on the support being "experimental"?

Thanks! I added a note to the RISCVUsage. There won't be experimental-e like other experimental extensions as it is already ratified and adds no instruction, it is experimental just because the support is experimental.

For ABI part, I don't know if @kito-cheng has some updates/comments.

[asb]

Thanks, I'll take another look. Rereading my previous comment I just wanted to clarify one part so it's not misunderstood. I said " I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at least get it to match what GCC actually implements" - I wanted to be very clear this isn't a criticism of those trying to maintain the ABI doc, it's about companies who want to ship RVE hardware and software not contributing to that process.

[koute]

Sorry for the comment spam, but could we please get this merged in finally? (:

To people who hold the decision making power as to whether this is merged: are there still any blockers left, considering the consensus was to merge it? What's the hold up? Is there anything I can do to help?

[craig.topper]

LGTM

[wangpc]

@craig.topper Thanks!
@asb Hi Alex, I'd like to get another approval from you. Are there any more concerns?

[jrtc27]

GCC only ever defines __riscv_32e

clang/lib/Basic/Targets/RISCV.cpp

215

Ugh, these don't align with the normal pattern. riscv_e already exists in the spec, can we just leave riscv_32e as deprecated for RV32E and not introduce the old-style __riscv_64e?

clang/lib/Basic/Targets/RISCV.h

142

Does it matter we don't undo the effects of the RVE ABI here?

[jrtc27]

In D70401#4657098, @jrtc27 wrote:

GCC only ever defines __riscv_32e

Hm, seems the comments about __riscv_32e were from months ago, ignore them if they aren't correct or have become outdated...

[wangpc]

In D70401#4657101, @jrtc27 wrote:

In D70401#4657098, @jrtc27 wrote:

GCC only ever defines __riscv_32e

Hm, seems the comments about __riscv_32e were from months ago, ignore them if they aren't correct or have become outdated...

FYI: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/52

[hlvlad]

Hello, could we please merge this 🙂?

[koute]

Again, sorry for the spam, but I second @hlvlad; it's been a month since I last commented and we still made no progress in merging this PR. Could we please somehow get this merged before the next LLVM branch point in January? I really don't want this to be delayed yet another half a year, and time's running out. At this point I don't care if I'm going to annoy people; I'm willing to do whatever it takes to help and drive this forward.

@asb: Could we please get an extra review and/or approval as requested here?

In D70401#4657097, @wangpc wrote:

@asb Hi Alex, I'd like to get another approval from you. Are there any more concerns?

clang/docs/ReleaseNotes.rst

 
 LoongArch Support
 ^^^^^^^^^^^^^^^^^
 
 RISC-V Support
 ^^^^^^^^^^^^^^
 - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the
   aliases ``-m[no-]strict-align``.
+- CodeGen of RV32E/RV64E was supported experimentally.
+- CodeGen of ilp32e/lp64e was supported experimentally.
 
 - Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f
   for RV64.
 
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 
 CUDA Support

clang/lib/Basic/Targets/RISCV.h

RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : RISCVTargetInfo(Triple, Opts) {
     IntPtrType = SignedInt;
     PtrDiffType = SignedInt;
     SizeType = UnsignedInt;
     resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }
 
   bool setABI(const std::string &Name) override {
+    if (Name == "ilp32e") {
+      ABI = Name;
+      resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32");
+      return true;
+    }
+
     if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
       ABI = Name;
       return true;
     }
     return false;
   }
 
   void setMaxAtomicWidth() override {
     MaxAtomicPromoteWidth = 128;
 
     if (ISAInfo->hasExtension("a"))
       MaxAtomicInlineWidth = 32;
   }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
 public:
   RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : RISCVTargetInfo(Triple, Opts) {
     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
     IntMaxType = Int64Type = SignedLong;
     resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
   }
 
   bool setABI(const std::string &Name) override {
+    if (Name == "lp64e") {
+      ABI = Name;
+      resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64");
+      return true;
+    }
+
     if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
       ABI = Name;
       return true;
     }
     return false;
   }
 
   void setMaxAtomicWidth() override {

clang/lib/Basic/Targets/RISCV.cpp

void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   StringRef ABIName = getABI();
   if (ABIName == "ilp32f" || ABIName == "lp64f")
     Builder.defineMacro("__riscv_float_abi_single");
   else if (ABIName == "ilp32d" || ABIName == "lp64d")
     Builder.defineMacro("__riscv_float_abi_double");
   else
     Builder.defineMacro("__riscv_float_abi_soft");
 
-  if (ABIName == "ilp32e")
+  if (ABIName == "ilp32e" || ABIName == "lp64e")
     Builder.defineMacro("__riscv_abi_rve");
 
   Builder.defineMacro("__riscv_arch_test");
 
   for (auto &Extension : ISAInfo->getExtensions()) {
     auto ExtName = Extension.first;
     auto ExtInfo = Extension.second;
 
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   auto VScale = getVScaleRange(Opts);
   if (VScale && VScale->first && VScale->first == VScale->second)
     Builder.defineMacro("__riscv_v_fixed_vlen",
                         Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock));
 
   if (FastUnalignedAccess)
     Builder.defineMacro("__riscv_misaligned_fast");
   else
     Builder.defineMacro("__riscv_misaligned_avoid");
+
+  if (ISAInfo->hasExtension("e")) {
+    if (Is64Bit)
+      Builder.defineMacro("__riscv_64e");
+    else
+      Builder.defineMacro("__riscv_32e");
+  }
 }
 
 static constexpr Builtin::Info BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
   {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
 #include "clang/Basic/BuiltinsRISCVVector.def"
bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
 
   if (llvm::is_contained(Features, "+experimental"))
     HasExperimental = true;
 
+  if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+    Diags.Report(diag::err_invalid_feature_combination)
+        << "ILP32E cannot be used with the D ISA extension";
+    return false;
+  }
   return true;
 }
 
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);
 }
 

clang/lib/CodeGen/CodeGenModule.cpp

createTargetCodeGenInfo(CodeGenModule &CGM) {
   case llvm::Triple::riscv64: {
     StringRef ABIStr = Target.getABI();
     unsigned XLen = Target.getPointerWidth(LangAS::Default);
     unsigned ABIFLen = 0;
     if (ABIStr.ends_with("f"))
       ABIFLen = 32;
     else if (ABIStr.ends_with("d"))
       ABIFLen = 64;
-    return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen);
+    bool EABI = ABIStr.ends_with("e");
+    return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI);
   }
 
   case llvm::Triple::systemz: {
     bool SoftFloat = CodeGenOpts.FloatABI == "soft";
     bool HasVector = !SoftFloat && Target.getABI() == "vector";
     return createSystemZTargetCodeGenInfo(CGM, HasVector, SoftFloat);
   }
 

clang/lib/CodeGen/TargetInfo.h

 std::unique_ptr<TargetCodeGenInfo>
 createPPC64TargetCodeGenInfo(CodeGenModule &CGM);
 
 std::unique_ptr<TargetCodeGenInfo>
 createPPC64_SVR4_TargetCodeGenInfo(CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind,
                                    bool SoftFloatABI);
 
 std::unique_ptr<TargetCodeGenInfo>
-createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen);
+createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen,
+                             bool EABI);
 
 std::unique_ptr<TargetCodeGenInfo>
 createCommonSPIRTargetCodeGenInfo(CodeGenModule &CGM);
 
 std::unique_ptr<TargetCodeGenInfo>
 createSPIRVTargetCodeGenInfo(CodeGenModule &CGM);
 
 std::unique_ptr<TargetCodeGenInfo>

clang/lib/CodeGen/Targets/RISCV.cpp

 class RISCVABIInfo : public DefaultABIInfo {
 private:
   // Size of the integer ('x') registers in bits.
   unsigned XLen;
   // Size of the floating point ('f') registers in bits. Note that the target
   // ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target
   // with soft float ABI has FLen==0).
   unsigned FLen;
-  static const int NumArgGPRs = 8;
-  static const int NumArgFPRs = 8;
+  const int NumArgGPRs;
+  const int NumArgFPRs;
+  const bool EABI;
   bool detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
                                       llvm::Type *&Field1Ty,
                                       CharUnits &Field1Off,
                                       llvm::Type *&Field2Ty,
                                       CharUnits &Field2Off) const;
 
 public:
-  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen)
-      : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen) {}
+  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen,
+               bool EABI)
+      : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), NumArgGPRs(EABI ? 6 : 8),
+        NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {}
 
   // DefaultABIInfo's classifyReturnType and classifyArgumentType are
   // non-virtual, but computeInfo is virtual, so we overload it.
   void computeInfo(CGFunctionInfo &FI) const override;
 
   ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft,
                                   int &ArgFPRsLeft) const;
   ABIArgInfo classifyReturnType(QualType RetTy) const;
if (RetTy->isComplexType() && FLen) {
       IsRetIndirect = getContext().getTypeSize(EltTy) > FLen;
     } else {
       // This is a normal scalar > 2*XLen, such as fp128 on RV32.
       IsRetIndirect = true;
     }
   }
 
   int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
-  int ArgFPRsLeft = FLen ? NumArgFPRs : 0;
+  int ArgFPRsLeft = NumArgFPRs;
   int NumFixedArgs = FI.getNumRequiredArgs();
 
   int ArgNum = 0;
   for (auto &ArgInfo : FI.arguments()) {
     bool IsFixed = ArgNum < NumFixedArgs;
     ArgInfo.info =
         classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft, ArgFPRsLeft);
     ArgNum++;
if (IsCandidate && NeededArgGPRs <= ArgGPRsLeft &&
                                                Field2Off);
     }
   }
 
   uint64_t NeededAlign = getContext().getTypeAlign(Ty);
   // Determine the number of GPRs needed to pass the current argument
   // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
   // register pairs, so may consume 3 registers.
+  // TODO: To be compatible with GCC's behaviors, we don't align registers
+  // currently if we are using ILP32E calling convention. This behavior may be
+  // changed when RV32E/ILP32E is ratified.
   int NeededArgGPRs = 1;
   if (!IsFixed && NeededAlign == 2 * XLen)
-    NeededArgGPRs = 2 + (ArgGPRsLeft % 2);
+    NeededArgGPRs = 2 + (EABI && XLen == 32 ? 0 : (ArgGPRsLeft % 2));
   else if (Size > XLen && Size <= 2 * XLen)
     NeededArgGPRs = 2;
 
   if (NeededArgGPRs > ArgGPRsLeft) {
     NeededArgGPRs = ArgGPRsLeft;
   }
 
   ArgGPRsLeft -= NeededArgGPRs;
Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
   // Empty records are ignored for parameter passing purposes.
   if (isEmptyRecord(getContext(), Ty, true)) {
     return Address(CGF.Builder.CreateLoad(VAListAddr),
                    CGF.ConvertTypeForMem(Ty), SlotSize);
   }
 
   auto TInfo = getContext().getTypeInfoInChars(Ty);
 
+  // TODO: To be compatible with GCC's behaviors, we force arguments with
+  // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`,
+  // `unsigned long long` and `double` to have 4-byte alignment. This
+  // behavior may be changed when RV32E/ILP32E is ratified.
+  if (EABI && XLen == 32)
+    TInfo.Align = std::min(TInfo.Align, CharUnits::fromQuantity(4));
+
   // Arguments bigger than 2*Xlen bytes are passed indirectly.
   bool IsIndirect = TInfo.Width > 2 * SlotSize;
 
   return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TInfo,
                           SlotSize, /*AllowHigherAlign=*/true);
 }
 
 ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
   int TySize = getContext().getTypeSize(Ty);
   // RV64 ABI requires unsigned 32 bit integers to be sign extended.
   if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
     return ABIArgInfo::getSignExtend(Ty);
   return ABIArgInfo::getExtend(Ty);
 }
 
 namespace {
 class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
 public:
   RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
-                         unsigned FLen)
-      : TargetCodeGenInfo(std::make_unique<RISCVABIInfo>(CGT, XLen, FLen)) {}
+                         unsigned FLen, bool EABI)
+      : TargetCodeGenInfo(
+            std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {}
 
   void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                            CodeGen::CodeGenModule &CGM) const override {
     const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
     if (!FD) return;
 
     const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
     if (!Attr)
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
 
     Fn->addFnAttr("interrupt", Kind);
   }
 };
 } // namespace
 
 std::unique_ptr<TargetCodeGenInfo>
 CodeGen::createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen,
-                                      unsigned FLen) {
-  return std::make_unique<RISCVTargetCodeGenInfo>(CGM.getTypes(), XLen, FLen);
+                                      unsigned FLen, bool EABI) {
+  return std::make_unique<RISCVTargetCodeGenInfo>(CGM.getTypes(), XLen, FLen,
+                                                  EABI);
 }

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
     return A->getValue();
 
   // 2. Choose a default based on the target architecture.
   //
   // rv32g | rv32*d -> ilp32d
   // rv32e -> ilp32e
   // rv32* -> ilp32
   // rv64g | rv64*d -> lp64d
+  // rv64e -> lp64e
   // rv64* -> lp64
   StringRef Arch = getRISCVArch(Args, Triple);
 
   auto ParseResult = llvm::RISCVISAInfo::parseArchString(
       Arch, /* EnableExperimentalExtension */ true);
   // Ignore parsing error, just go 3rd step.
   if (!llvm::errorToBool(ParseResult.takeError()))
     return (*ParseResult)->computeDefaultABI();
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
     // Bypass if target cpu's default march is empty.
     if (MArch != "")
       return MArch;
   }
 
   // 3. Choose a default based on `-mabi=`
   //
   // ilp32e -> rv32e
+  // lp64e -> rv64e
   // ilp32 | ilp32f | ilp32d -> rv32imafdc
   // lp64 | lp64f | lp64d -> rv64imafdc
   if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
     StringRef MABI = A->getValue();
 
     if (MABI.equals_insensitive("ilp32e"))
       return "rv32e";
+    else if (MABI.equals_insensitive("lp64e"))
+      return "rv64e";
     else if (MABI.starts_with_insensitive("ilp32"))
       return "rv32imafdc";
     else if (MABI.starts_with_insensitive("lp64")) {
       if (Triple.isAndroid())
         return "rv64imafdcv_zba_zbb_zbs";
 
       return "rv64imafdc";
     }

clang/test/CodeGen/RISCV/riscv32-abi.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |^entry:" --version 2
 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=ILP32-ILP32F-ILP32D,ILP32-ILP32F,ILP32 %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=ILP32-ILP32F-ILP32D,ILP32F-ILP32D,ILP32-ILP32F,ILP32F %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-abi ilp32d -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=ILP32-ILP32F-ILP32D,ILP32F-ILP32D,ILP32D %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-abi ilp32e %s -o - \
+// RUN:     | FileCheck -check-prefixes=ILP32-ILP32F-ILP32D,ILP32-ILP32F,ILP32,ILP32E %s
 
 #include <stddef.h>
 #include <stdint.h>
 
 // ILP32-ILP32F-ILP32D-LABEL: define dso_local void @f_void
 // ILP32-ILP32F-ILP32D-SAME: () #[[ATTR0:[0-9]+]] {
 // ILP32-ILP32F-ILP32D:  entry:
 //

 // ILP32-ILP32F-ILP32D-SAME: () #[[ATTR0]] {
 // ILP32-ILP32F-ILP32D:  entry:
 //
 union float16_u f_ret_float16_u(void) {
   return (union float16_u){1.0};
 }
 
 //// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+// ILP32E: {{.*}}
 // ILP32F: {{.*}}

clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c

+// RUN: not %clang_cc1 -triple riscv32 -target-feature +d -emit-llvm -target-abi ilp32e %s 2>&1 \
+// RUN:     | FileCheck -check-prefix=ILP32E-WITH-FD %s
+
+// ILP32E-WITH-FD: error: invalid feature combination: ILP32E cannot be used with the D ISA extension

clang/test/CodeGen/RISCV/riscv32-vararg.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
-// RUN:     | FileCheck %s
+// RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32F
 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-feature +f -target-abi ilp32d -emit-llvm %s -o - \
-// RUN:     | FileCheck %s
+// RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32D
+// RUN: %clang_cc1 -triple riscv32 -target-abi ilp32e -emit-llvm %s -o - \
+// RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32E
 
 #include <stddef.h>
 #include <stdint.h>
 
 struct tiny {
   uint8_t a, b, c, d;
 };
 struct small {
int f_va_1(char *fmt, ...) {
 
   return v;
 }
 
 // An "aligned" register pair (where the first register is even-numbered) is
 // used to pass varargs with 2x xlen alignment and 2x xlen size. Ensure the
 // correct offsets are used.
 
-// CHECK-LABEL: define dso_local double @f_va_2
-// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[VA:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[V:%.*]] = alloca double, align 8
-// CHECK-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
-// CHECK-NEXT:    call void @llvm.va_start(ptr [[VA]])
-// CHECK-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
-// CHECK-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
-// CHECK-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
-// CHECK-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
-// CHECK-NEXT:    store double [[TMP1]], ptr [[V]], align 8
-// CHECK-NEXT:    call void @llvm.va_end(ptr [[VA]])
-// CHECK-NEXT:    [[TMP2:%.*]] = load double, ptr [[V]], align 8
-// CHECK-NEXT:    ret double [[TMP2]]
+// CHECK-ILP32F-LABEL: define dso_local double @f_va_2
+// CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32F-NEXT:  entry:
+// CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
+// CHECK-ILP32F-NEXT:    store double [[TMP1]], ptr [[V]], align 8
+// CHECK-ILP32F-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32F-NEXT:    ret double [[TMP2]]
+//
+// CHECK-ILP32D-LABEL: define dso_local double @f_va_2
+// CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32D-NEXT:  entry:
+// CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
+// CHECK-ILP32D-NEXT:    store double [[TMP1]], ptr [[V]], align 8
+// CHECK-ILP32D-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32D-NEXT:    ret double [[TMP2]]
+//
+// CHECK-ILP32E-LABEL: define dso_local double @f_va_2
+// CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32E-NEXT:  entry:
+// CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 8
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load double, ptr [[ARGP_CUR]], align 4
+// CHECK-ILP32E-NEXT:    store double [[TMP0]], ptr [[V]], align 8
+// CHECK-ILP32E-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32E-NEXT:    ret double [[TMP1]]
 //
 double f_va_2(char *fmt, ...) {
   __builtin_va_list va;
 
   __builtin_va_start(va, fmt);
   double v = __builtin_va_arg(va, double);
   __builtin_va_end(va);
 
   return v;
 }
 
 // Two "aligned" register pairs.
 
-// CHECK-LABEL: define dso_local double @f_va_3
-// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[VA:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[V:%.*]] = alloca double, align 8
-// CHECK-NEXT:    [[W:%.*]] = alloca i32, align 4
-// CHECK-NEXT:    [[X:%.*]] = alloca double, align 8
-// CHECK-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
-// CHECK-NEXT:    call void @llvm.va_start(ptr [[VA]])
-// CHECK-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
-// CHECK-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
-// CHECK-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
-// CHECK-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
-// CHECK-NEXT:    store double [[TMP1]], ptr [[V]], align 8
-// CHECK-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
-// CHECK-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
-// CHECK-NEXT:    store i32 [[TMP2]], ptr [[W]], align 4
-// CHECK-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 7
-// CHECK-NEXT:    [[ARGP_CUR3_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP3]], i32 -8)
-// CHECK-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3_ALIGNED]], i32 8
-// CHECK-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP4:%.*]] = load double, ptr [[ARGP_CUR3_ALIGNED]], align 8
-// CHECK-NEXT:    store double [[TMP4]], ptr [[X]], align 8
-// CHECK-NEXT:    call void @llvm.va_end(ptr [[VA]])
-// CHECK-NEXT:    [[TMP5:%.*]] = load double, ptr [[V]], align 8
-// CHECK-NEXT:    [[TMP6:%.*]] = load double, ptr [[X]], align 8
-// CHECK-NEXT:    [[ADD:%.*]] = fadd double [[TMP5]], [[TMP6]]
-// CHECK-NEXT:    ret double [[ADD]]
+// CHECK-ILP32F-LABEL: define dso_local double @f_va_3
+// CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32F-NEXT:  entry:
+// CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32F-NEXT:    [[W:%.*]] = alloca i32, align 4
+// CHECK-ILP32F-NEXT:    [[X:%.*]] = alloca double, align 8
+// CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
+// CHECK-ILP32F-NEXT:    store double [[TMP1]], ptr [[V]], align 8
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32F-NEXT:    store i32 [[TMP2]], ptr [[W]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 7
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR3_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP3]], i32 -8)
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3_ALIGNED]], i32 8
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP4:%.*]] = load double, ptr [[ARGP_CUR3_ALIGNED]], align 8
+// CHECK-ILP32F-NEXT:    store double [[TMP4]], ptr [[X]], align 8
+// CHECK-ILP32F-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[TMP5:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32F-NEXT:    [[TMP6:%.*]] = load double, ptr [[X]], align 8
+// CHECK-ILP32F-NEXT:    [[ADD:%.*]] = fadd double [[TMP5]], [[TMP6]]
+// CHECK-ILP32F-NEXT:    ret double [[ADD]]
+//
+// CHECK-ILP32D-LABEL: define dso_local double @f_va_3
+// CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32D-NEXT:  entry:
+// CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32D-NEXT:    [[W:%.*]] = alloca i32, align 4
+// CHECK-ILP32D-NEXT:    [[X:%.*]] = alloca double, align 8
+// CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
+// CHECK-ILP32D-NEXT:    store double [[TMP1]], ptr [[V]], align 8
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32D-NEXT:    store i32 [[TMP2]], ptr [[W]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 7
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR3_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP3]], i32 -8)
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3_ALIGNED]], i32 8
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP4:%.*]] = load double, ptr [[ARGP_CUR3_ALIGNED]], align 8
+// CHECK-ILP32D-NEXT:    store double [[TMP4]], ptr [[X]], align 8
+// CHECK-ILP32D-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[TMP5:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32D-NEXT:    [[TMP6:%.*]] = load double, ptr [[X]], align 8
+// CHECK-ILP32D-NEXT:    [[ADD:%.*]] = fadd double [[TMP5]], [[TMP6]]
+// CHECK-ILP32D-NEXT:    ret double [[ADD]]
+//
+// CHECK-ILP32E-LABEL: define dso_local double @f_va_3
+// CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32E-NEXT:  entry:
+// CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca double, align 8
+// CHECK-ILP32E-NEXT:    [[W:%.*]] = alloca i32, align 4
+// CHECK-ILP32E-NEXT:    [[X:%.*]] = alloca double, align 8
+// CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 8
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load double, ptr [[ARGP_CUR]], align 4
+// CHECK-ILP32E-NEXT:    store double [[TMP0]], ptr [[V]], align 8
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32E-NEXT:    store i32 [[TMP1]], ptr [[W]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 8
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP2:%.*]] = load double, ptr [[ARGP_CUR3]], align 4
+// CHECK-ILP32E-NEXT:    store double [[TMP2]], ptr [[X]], align 8
+// CHECK-ILP32E-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[TMP3:%.*]] = load double, ptr [[V]], align 8
+// CHECK-ILP32E-NEXT:    [[TMP4:%.*]] = load double, ptr [[X]], align 8
+// CHECK-ILP32E-NEXT:    [[ADD:%.*]] = fadd double [[TMP3]], [[TMP4]]
+// CHECK-ILP32E-NEXT:    ret double [[ADD]]
 //
 double f_va_3(char *fmt, ...) {
   __builtin_va_list va;
 
   __builtin_va_start(va, fmt);
   double v = __builtin_va_arg(va, double);
   int w = __builtin_va_arg(va, int);
   double x = __builtin_va_arg(va, double);
   __builtin_va_end(va);
 
   return v + x;
 }
 
-// CHECK-LABEL: define dso_local i32 @f_va_4
-// CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[VA:%.*]] = alloca ptr, align 4
-// CHECK-NEXT:    [[V:%.*]] = alloca i32, align 4
-// CHECK-NEXT:    [[LD:%.*]] = alloca fp128, align 16
-// CHECK-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
-// CHECK-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
-// CHECK-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
-// CHECK-NEXT:    [[RET:%.*]] = alloca i32, align 4
-// CHECK-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
-// CHECK-NEXT:    call void @llvm.va_start(ptr [[VA]])
-// CHECK-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
-// CHECK-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
-// CHECK-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
-// CHECK-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
-// CHECK-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
-// CHECK-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 16
-// CHECK-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
-// CHECK-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
-// CHECK-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
-// CHECK-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
-// CHECK-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
-// CHECK-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
-// CHECK-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
-// CHECK-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
-// CHECK-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
-// CHECK-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
-// CHECK-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
-// CHECK-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
-// CHECK-NEXT:    call void @llvm.va_end(ptr [[VA]])
-// CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
-// CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
-// CHECK-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
-// CHECK-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
-// CHECK-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
-// CHECK-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
-// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
-// CHECK-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
-// CHECK-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
-// CHECK-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
-// CHECK-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
-// CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
-// CHECK-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
-// CHECK-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
-// CHECK-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
-// CHECK-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
-// CHECK-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
-// CHECK-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
-// CHECK-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
-// CHECK-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
-// CHECK-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
-// CHECK-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
-// CHECK-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
-// CHECK-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
-// CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
-// CHECK-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
-// CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
-// CHECK-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK-NEXT:    [[B20:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
-// CHECK-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
-// CHECK-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
-// CHECK-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
-// CHECK-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
-// CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
-// CHECK-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
-// CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
-// CHECK-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK-NEXT:    [[B24:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
-// CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
-// CHECK-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
-// CHECK-NEXT:    [[C26:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
-// CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
-// CHECK-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
-// CHECK-NEXT:    [[D28:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
-// CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
-// CHECK-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
-// CHECK-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
-// CHECK-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
-// CHECK-NEXT:    ret i32 [[TMP20]]
+// CHECK-ILP32F-LABEL: define dso_local i32 @f_va_4
+// CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32F-NEXT:  entry:
+// CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca i32, align 4
+// CHECK-ILP32F-NEXT:    [[LD:%.*]] = alloca fp128, align 16
+// CHECK-ILP32F-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
+// CHECK-ILP32F-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
+// CHECK-ILP32F-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
+// CHECK-ILP32F-NEXT:    [[RET:%.*]] = alloca i32, align 4
+// CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
+// CHECK-ILP32F-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 16
+// CHECK-ILP32F-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
+// CHECK-ILP32F-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
+// CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
+// CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
+// CHECK-ILP32F-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32F-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
+// CHECK-ILP32F-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
+// CHECK-ILP32F-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
+// CHECK-ILP32F-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
+// CHECK-ILP32F-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
+// CHECK-ILP32F-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
+// CHECK-ILP32F-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
+// CHECK-ILP32F-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
+// CHECK-ILP32F-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
+// CHECK-ILP32F-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
+// CHECK-ILP32F-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
+// CHECK-ILP32F-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
+// CHECK-ILP32F-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
+// CHECK-ILP32F-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
+// CHECK-ILP32F-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
+// CHECK-ILP32F-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
+// CHECK-ILP32F-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
+// CHECK-ILP32F-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
+// CHECK-ILP32F-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
+// CHECK-ILP32F-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
+// CHECK-ILP32F-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
+// CHECK-ILP32F-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
+// CHECK-ILP32F-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
+// CHECK-ILP32F-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-ILP32F-NEXT:    [[B20:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
+// CHECK-ILP32F-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
+// CHECK-ILP32F-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
+// CHECK-ILP32F-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
+// CHECK-ILP32F-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
+// CHECK-ILP32F-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
+// CHECK-ILP32F-NEXT:    [[B24:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
+// CHECK-ILP32F-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
+// CHECK-ILP32F-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
+// CHECK-ILP32F-NEXT:    [[C26:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
+// CHECK-ILP32F-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
+// CHECK-ILP32F-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
+// CHECK-ILP32F-NEXT:    [[D28:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
+// CHECK-ILP32F-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
+// CHECK-ILP32F-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
+// CHECK-ILP32F-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32F-NEXT:    ret i32 [[TMP20]]
+//
+// CHECK-ILP32D-LABEL: define dso_local i32 @f_va_4
+// CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32D-NEXT:  entry:
+// CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca i32, align 4
+// CHECK-ILP32D-NEXT:    [[LD:%.*]] = alloca fp128, align 16
+// CHECK-ILP32D-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
+// CHECK-ILP32D-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
+// CHECK-ILP32D-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
+// CHECK-ILP32D-NEXT:    [[RET:%.*]] = alloca i32, align 4
+// CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
+// CHECK-ILP32D-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 16
+// CHECK-ILP32D-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
+// CHECK-ILP32D-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
+// CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
+// CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
+// CHECK-ILP32D-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32D-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
+// CHECK-ILP32D-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
+// CHECK-ILP32D-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
+// CHECK-ILP32D-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
+// CHECK-ILP32D-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
+// CHECK-ILP32D-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
+// CHECK-ILP32D-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
+// CHECK-ILP32D-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
+// CHECK-ILP32D-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
+// CHECK-ILP32D-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
+// CHECK-ILP32D-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
+// CHECK-ILP32D-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
+// CHECK-ILP32D-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
+// CHECK-ILP32D-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
+// CHECK-ILP32D-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
+// CHECK-ILP32D-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
+// CHECK-ILP32D-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
+// CHECK-ILP32D-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
+// CHECK-ILP32D-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
+// CHECK-ILP32D-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
+// CHECK-ILP32D-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
+// CHECK-ILP32D-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
+// CHECK-ILP32D-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
+// CHECK-ILP32D-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-ILP32D-NEXT:    [[B20:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
+// CHECK-ILP32D-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
+// CHECK-ILP32D-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
+// CHECK-ILP32D-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
+// CHECK-ILP32D-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
+// CHECK-ILP32D-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
+// CHECK-ILP32D-NEXT:    [[B24:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
+// CHECK-ILP32D-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
+// CHECK-ILP32D-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
+// CHECK-ILP32D-NEXT:    [[C26:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
+// CHECK-ILP32D-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
+// CHECK-ILP32D-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
+// CHECK-ILP32D-NEXT:    [[D28:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
+// CHECK-ILP32D-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
+// CHECK-ILP32D-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
+// CHECK-ILP32D-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32D-NEXT:    ret i32 [[TMP20]]
+//
+// CHECK-ILP32E-LABEL: define dso_local i32 @f_va_4
+// CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
+// CHECK-ILP32E-NEXT:  entry:
+// CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
+// CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca i32, align 4
+// CHECK-ILP32E-NEXT:    [[LD:%.*]] = alloca fp128, align 16
+// CHECK-ILP32E-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
+// CHECK-ILP32E-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
+// CHECK-ILP32E-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
+// CHECK-ILP32E-NEXT:    [[RET:%.*]] = alloca i32, align 4
+// CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.va_start(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
+// CHECK-ILP32E-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 4
+// CHECK-ILP32E-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
+// CHECK-ILP32E-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
+// CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
+// CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
+// CHECK-ILP32E-NEXT:    call void @llvm.va_end(ptr [[VA]])
+// CHECK-ILP32E-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
+// CHECK-ILP32E-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
+// CHECK-ILP32E-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
+// CHECK-ILP32E-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
+// CHECK-ILP32E-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
+// CHECK-ILP32E-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
+// CHECK-ILP32E-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
+// CHECK-ILP32E-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
+// CHECK-ILP32E-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
+// CHECK-ILP32E-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
+// CHECK-ILP32E-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
+// CHECK-ILP32E-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
+// CHECK-ILP32E-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
+// CHECK-ILP32E-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
+// CHECK-ILP32E-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
+// CHECK-ILP32E-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
+// CHECK-ILP32E-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
+// CHECK-ILP32E-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
+// CHECK-ILP32E-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
+// CHECK-ILP32E-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
+// CHECK-ILP32E-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
+// CHECK-ILP32E-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
+// CHECK-ILP32E-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
+// CHECK-ILP32E-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-ILP32E-NEXT:    [[B20:%.*]] = getelementptr inbounds [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
+// CHECK-ILP32E-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
+// CHECK-ILP32E-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
+// CHECK-ILP32E-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
+// CHECK-ILP32E-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
+// CHECK-ILP32E-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
+// CHECK-ILP32E-NEXT:    [[B24:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
+// CHECK-ILP32E-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
+// CHECK-ILP32E-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
+// CHECK-ILP32E-NEXT:    [[C26:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
+// CHECK-ILP32E-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
+// CHECK-ILP32E-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
+// CHECK-ILP32E-NEXT:    [[D28:%.*]] = getelementptr inbounds [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
+// CHECK-ILP32E-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
+// CHECK-ILP32E-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
+// CHECK-ILP32E-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
+// CHECK-ILP32E-NEXT:    ret i32 [[TMP20]]
 //
 int f_va_4(char *fmt, ...) {
   __builtin_va_list va;
 
   __builtin_va_start(va, fmt);
   int v = __builtin_va_arg(va, int);
   long double ld = __builtin_va_arg(va, long double);
   struct tiny ts = __builtin_va_arg(va, struct tiny);

clang/test/CodeGen/RISCV/riscv64-abi.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |^entry:" --version 2
 // RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=LP64-LP64F-LP64D,LP64-LP64F,LP64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=LP64-LP64F-LP64D,LP64F-LP64D,LP64-LP64F,LP64F %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-abi lp64d -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=LP64-LP64F-LP64D,LP64F-LP64D,LP64D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-abi lp64e %s -o - \
+// RUN:     | FileCheck -check-prefixes=LP64-LP64F-LP64D,LP64-LP64F,LP64,LP64E %s
 
 #include <stddef.h>
 #include <stdint.h>
 
 // LP64-LP64F-LP64D-LABEL: define dso_local void @f_void
 // LP64-LP64F-LP64D-SAME: () #[[ATTR0:[0-9]+]] {
 // LP64-LP64F-LP64D:  entry:
 //

 // LP64-LP64F-LP64D-LABEL: define dso_local i64 @f_ret_float16_u
 // LP64-LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64-LP64F-LP64D:  entry:
 //
 union float16_u f_ret_float16_u(void) {
   return (union float16_u){1.0};
 }
 
+//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+// LP64E: {{.*}}

clang/test/CodeGen/RISCV/riscv64-vararg.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - | FileCheck %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm %s -o - \
 // RUN:     | FileCheck %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-feature +f -target-abi lp64d -emit-llvm %s -o - \
 // RUN:     | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-abi lp64e -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
 
 #include <stddef.h>
 #include <stdint.h>
 
 struct tiny {
   uint16_t a, b, c, d;
 };
 

clang/test/Preprocessor/riscv-target-features.c

 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 // RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 
+// CHECK-NOT: __riscv_32e {{.*$}}
+// CHECK-NOT: __riscv_64e {{.*$}}
 // CHECK-NOT: __riscv_a {{.*$}}
 // CHECK-NOT: __riscv_atomic
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
 // CHECK-NOT: __riscv_d {{.*$}}
 // CHECK-NOT: __riscv_f {{.*$}}
 // CHECK-NOT: __riscv_flen {{.*$}}
 // CHECK-NOT: __riscv_fdiv {{.*$}}

 // RUN: -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // CHECK-D-EXT: __riscv_d 2002000{{$}}
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32e -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefixes=CHECK-E-EXT,CHECK-RV32E %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64e -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefixes=CHECK-E-EXT,CHECK-RV64E %s
+// CHECK-RV32E: __riscv_32e 1
+// CHECK-RV64E: __riscv_64e 1
+// CHECK-E-EXT: __riscv_abi_rve 1
+// CHECK-E-EXT: __riscv_e 2000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN: -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang --target=riscv64-unknown-linux-gnu \
 // RUN: -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // CHECK-F-EXT: __riscv_f 2002000{{$}}
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32

 // RUN: %clang --target=riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-DOUBLE %s
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i -mabi=ilp32e -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ILP32E %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i -mabi=lp64e -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-LP64E %s
+// CHECK-ILP32E: __riscv_abi_rve 1
+// CHECK-LP64E: __riscv_abi_rve 1
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN: -march=rv32ih -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
 // RUN: %clang --target=riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ih -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
 // CHECK-H-EXT: __riscv_h 1000000{{$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \

llvm/docs/RISCVUsage.rst

.. table:: Ratified Extensions by Status
 
      ===============  =========================================================
      Extension        Status
      ===============  =========================================================
      ``A``            Supported
      ``C``            Supported
      ``D``            Supported
      ``F``            Supported
+     ``E``            Supported (`See note <#riscv-rve-note>`__)
      ``H``            Assembly Support
      ``M``            Supported
      ``Smaia``        Supported
      ``Ssaia``        Supported
      ``Svinval``      Assembly Support
      ``Svnapot``      Assembly Support
      ``Svpbmt``       Supported
      ``V``            Supported
.. table:: Ratified Extensions by Status
      ===============  =========================================================
 
 Assembly Support
   LLVM supports the associated instructions in assembly.  All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported.  Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension.
 
 Supported
   Fully supported by the compiler.  This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.
 
+.. _riscv-rve-note:
+
+``E``
+  Support of RV32E/RV64E and ilp32e/lp64e ABIs are experimental. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments. Furthermore, we set the stack alignment to 4 bytes for types with length of 2*XLEN.
+
 .. _riscv-scalar-crypto-note1:
 
 ``Zbkb``, ``Zbkx``
   Pattern matching support for these instructions is incomplete.
 
 .. _riscv-scalar-crypto-note2:
 
 ``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``

llvm/docs/ReleaseNotes.rst

* The Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks,
   are still experimental.  To use the C intrinsics for these extensions,
   ``-menable-experimental-extensions`` needs to be passed to Clang.
 * XSfcie extension and SiFive CSRs and instructions that were associated with
   it have been removed. None of these CSRs and instructions were part of
   "SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project
   needs to work with SiFive to define and document real extension names for
   individual CSRs and instructions.
 * ``-mcpu=sifive-p450`` was added.
+* CodeGen of RV32E/RV64E was supported experimentally.
+* CodeGen of ilp32e/lp64e was supported experimentally.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 Changes to the Windows Target
 -----------------------------
 
 * The LLVM filesystem class ``UniqueID`` and function ``equivalent()``

llvm/include/llvm/Support/RISCVAttributes.h

enum AttrType : unsigned {
   STACK_ALIGN = 4,
   ARCH = 5,
   UNALIGNED_ACCESS = 6,
   PRIV_SPEC = 8,
   PRIV_SPEC_MINOR = 10,
   PRIV_SPEC_REVISION = 12,
 };
 
-enum StackAlign { ALIGN_4 = 4, ALIGN_16 = 16 };
+enum StackAlign { ALIGN_4 = 4, ALIGN_8 = 8, ALIGN_16 = 16 };
 
 enum { NOT_ALLOWED = 0, ALLOWED = 1 };
 
 } // namespace RISCVAttrs
 } // namespace llvm
 
 #endif

llvm/lib/Support/RISCVISAInfo.cpp

Error RISCVISAInfo::checkDependency() {
   if ((HasZcmt || Exts.count("zcmp")) && Exts.count("d") &&
       (HasC || Exts.count("zcd")))
     return createStringError(
         errc::invalid_argument,
         Twine("'") + (HasZcmt ? "zcmt" : "zcmp") +
         "' extension is incompatible with '" + (HasC ? "c" : "zcd") +
         "' extension when 'd' extension is enabled");
 
   if (XLen != 32 && Exts.count("zcf"))
     return createStringError(errc::invalid_argument,
                              "'zcf' is only supported for 'rv32'");
 
   return Error::success();
 }
 
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
RISCVISAInfo::postProcessAndChecking(std::unique_ptr<RISCVISAInfo> &&ISAInfo) {
 
   if (Error Result = ISAInfo->checkDependency())
     return std::move(Result);
   return std::move(ISAInfo);
 }
 
 StringRef RISCVISAInfo::computeDefaultABI() const {
   if (XLen == 32) {
+    if (hasExtension("e"))
+      return "ilp32e";
     if (hasExtension("d"))
       return "ilp32d";
     if (hasExtension("f"))
       return "ilp32f";
-    if (hasExtension("e"))
-      return "ilp32e";
     return "ilp32";
   } else if (XLen == 64) {
+    if (hasExtension("e"))
+      return "lp64e";
     if (hasExtension("d"))
       return "lp64d";
     if (hasExtension("f"))
       return "lp64f";
-    if (hasExtension("e"))
-      return "lp64e";
     return "lp64";
   }
   llvm_unreachable("Invalid XLEN");
 }
 
 bool RISCVISAInfo::isSupportedExtensionWithVersion(StringRef Ext) {
   if (Ext.empty())
     return false;

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

 /// If there are varargs that were passed in a0-a7, the data in those registers
 /// must be copied to the varargs save area on the stack.
 void RISCVCallLowering::saveVarArgRegisters(
     MachineIRBuilder &MIRBuilder, CallLowering::IncomingValueHandler &Handler,
     IncomingValueAssigner &Assigner, CCState &CCInfo) const {
   MachineFunction &MF = MIRBuilder.getMF();
   const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
-  ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs();
+  ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI());
   MachineRegisterInfo &MRI = MF.getRegInfo();
   unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
   MachineFrameInfo &MFI = MF.getFrameInfo();
   RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
 
   // Size of the vararg save area. For now, the varargs save area is either
   // zero or large enough to hold a0-a7.
   int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
   } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
              TargetABI != ABI_Unknown) {
     // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
     errs()
         << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
     TargetABI = ABI_Unknown;
   }
 
+  if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
+       (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
+      FeatureBits[RISCV::FeatureStdExtD])
+    report_fatal_error("ILP32E cannot be used with the D ISA extension");
+
   if (TargetABI != ABI_Unknown)
     return TargetABI;
 
   // If no explicit ABI is given, try to compute the default ABI.
   auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
   if (!ISAInfo)
     report_fatal_error(ISAInfo.takeError());
   return getTargetABI((*ISAInfo)->computeDefaultABI());

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                                StringRef StringValue) {}
 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
   TargetABI = ABI;
 }
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
                                                bool EmitStackAlign) {
-  if (STI.hasFeature(RISCV::FeatureRVE))
-    report_fatal_error("Codegen not yet implemented for RVE");
-
-  if (EmitStackAlign)
+  if (EmitStackAlign) {
+    if (TargetABI == RISCVABI::ABI_ILP32E)
+      emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
+    else if (TargetABI == RISCVABI::ABI_LP64E)
+      emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_8);
+    else
       emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
+  }
 
   auto ParseResult = RISCVFeatures::parseFeatureBits(
       STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
     report_fatal_error(ParseResult.takeError());
   } else {
     auto &ISAInfo = *ParseResult;
     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());

llvm/lib/Target/RISCV/RISCVCallingConv.td

 //===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This describes the calling conventions for the RISC-V architecture.
 //
 //===----------------------------------------------------------------------===//
 
 // The RISC-V calling convention is handled with custom code in
 // RISCVISelLowering.cpp (CC_RISCV).
 
+def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>;
+
 def CSR_ILP32_LP64
-    : CalleeSavedRegs<(add X1, X8, X9, (sequence "X%u", 18, 27))>;
+    : CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>;
 
 def CSR_ILP32F_LP64F
     : CalleeSavedRegs<(add CSR_ILP32_LP64,
                        F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
 
 def CSR_ILP32D_LP64D
     : CalleeSavedRegs<(add CSR_ILP32_LP64,
                        F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
 
 // Interrupt handler needs to save/restore all registers that are used,
 // both Caller and Callee saved registers.
 def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;
 
 // Same as CSR_Interrupt, but including all 32-bit FP registers.
 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
                                              (sequence "F%u_F", 0, 31))>;
 
 // Same as CSR_Interrupt, but including all 64-bit FP registers.
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
                                              (sequence "F%u_D", 0, 31))>;
+
+// Same as CSR_Interrupt, but excluding X16-X31.
+def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt,
+                                        (sequence "X%u", 16, 31))>;
+
+// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.
+def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt,
+                                                (sequence "X%u", 16, 31))>;
+
+// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.
+def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,
+                                                (sequence "X%u", 16, 31))>;

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureStdExtZicsr
     : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
                        "'zicsr' (CSRs)">;
 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
                                 AssemblerPredicate<(all_of FeatureStdExtZicsr),
                                 "'Zicsr' (CSRs)">;
 
+def FeatureStdExtI
+    : SubtargetFeature<"i", "HasStdExtI", "true",
+                       "'I' (Base Integer Instruction Set)">;
+def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">,
+                           AssemblerPredicate<(all_of FeatureStdExtI),
+                           "'I' (Base Integer Instruction Set)">;
+
 def FeatureStdExtM
     : SubtargetFeature<"m", "HasStdExtM", "true",
                        "'M' (Integer Multiplication and Division)">;
 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
                            AssemblerPredicate<(all_of FeatureStdExtM),
                            "'M' (Integer Multiplication and Division)">;
 
 def FeatureStdExtZmmul

llvm/lib/Target/RISCV/RISCVFrameLowering.h

 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/Support/TypeSize.h"
 
 namespace llvm {
 class RISCVSubtarget;
 
 class RISCVFrameLowering : public TargetFrameLowering {
 public:
-  explicit RISCVFrameLowering(const RISCVSubtarget &STI)
-      : TargetFrameLowering(StackGrowsDown,
-                            /*StackAlignment=*/Align(16),
-                            /*LocalAreaOffset=*/0,
-                            /*TransientStackAlignment=*/Align(16)),
-        STI(STI) {}
+  explicit RISCVFrameLowering(const RISCVSubtarget &STI);
 
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const;
 
   StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
                                      Register &FrameReg) const override;

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/Support/LEB128.h"
 
 #include <algorithm>
 
 using namespace llvm;
 
+static Align getABIStackAlignment(RISCVABI::ABI ABI) {
+  if (ABI == RISCVABI::ABI_ILP32E)
+    return Align(4);
+  if (ABI == RISCVABI::ABI_LP64E)
+    return Align(8);
+  return Align(16);
+}
+
+RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI)
+    : TargetFrameLowering(StackGrowsDown,
+                          getABIStackAlignment(STI.getTargetABI()),
+                          /*LocalAreaOffset=*/0,
+                          /*TransientStackAlignment=*/Align(16)),
+      STI(STI) {}
+
 static const Register AllPopRegs[] = {
     RISCV::X1,  RISCV::X8,  RISCV::X9,  RISCV::X18, RISCV::X19,
     RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
     RISCV::X25, RISCV::X26, RISCV::X27};
 
 // For now we use x3, a.k.a gp, as pointer to shadow call stack.
 // User should not use x3 in their asm.
 static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   //  | calleespill  | <- FI[-1]
   //  | this_frame   | <- FI[0]
   //
   // For negative frame indices, the offset from the frame pointer will differ
   // depending on which of these groups the frame index applies to.
   // The following calculates the correct offset knowing the number of callee
   // saved registers spilt by the two methods.
   if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
-    // Calculate the size of the frame managed by the libcall. The libcalls are
-    // implemented such that the stack will always be 16 byte aligned.
-    unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
+    // Calculate the size of the frame managed by the libcall. The stack
+    // alignment of these libcalls should be the same as how we set it in
+    // getABIStackAlignment.
+    unsigned LibCallFrameSize =
+        alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
     RVFI->setLibCallStackSize(LibCallFrameSize);
   }
 
   // FIXME (note copied from Lanai): This appears to be overallocating.  Needs
   // investigation. Get the number of bytes to allocate from the FrameInfo.
   uint64_t StackSize = getStackSizeWithRVVPadding(MF);
   uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
   uint64_t RVVStackSize = RVFI->getRVVStackSize();
void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
   // Mark BP as used if function has dedicated base pointer.
   if (hasBP(MF))
     SavedRegs.set(RISCVABI::getBPReg());
 
   // If interrupt is enabled and there are calls in the handler,
   // unconditionally save all Caller-saved registers and
   // all FP registers, regardless whether they are used.
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
   if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
 
     static const MCPhysReg CSRegs[] = { RISCV::X1,      /* ra */
       RISCV::X5, RISCV::X6, RISCV::X7,                  /* t0-t2 */
       RISCV::X10, RISCV::X11,                           /* a0-a1, a2-a7 */
       RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
       RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31 /* t3-t6 */
     };
 
     for (auto Reg : CSRegs)
+      // Only save x0-x15 for RVE.
+      if (Reg < RISCV::X16 || !Subtarget.isRVE())
         SavedRegs.set(Reg);
 
-    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
+    // According to psABI, if ilp32e/lp64e ABIs are used with an ISA that
+    // has any of the registers x16-x31 and f0-f31, then these registers are
+    // considered temporaries, so we should also save x16-x31 here.
+    if (STI.getTargetABI() == RISCVABI::ABI_ILP32E ||
+        STI.getTargetABI() == RISCVABI::ABI_LP64E) {
+      for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
+        SavedRegs.set(Reg);
+    }
+
+    if (Subtarget.hasStdExtF()) {
 
       // If interrupt is enabled, this list contains all FP registers.
       const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
 
       for (unsigned i = 0; Regs[i]; ++i)
         if (RISCV::FPR16RegClass.contains(Regs[i]) ||
             RISCV::FPR32RegClass.contains(Regs[i]) ||
             RISCV::FPR64RegClass.contains(Regs[i]))

llvm/lib/Target/RISCV/RISCVISelLowering.h

bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
                      ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
                      bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
                      std::optional<unsigned> FirstMaskArgument);
 
 bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
                   CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                   CCState &State);
 
-ArrayRef<MCPhysReg> getArgGPRs();
+ArrayRef<MCPhysReg> getArgGPRs(const RISCVABI::ABI ABI);
 
 } // end namespace RISCV
 
 namespace RISCVVIntrinsicsTable {
 
 struct RISCVVIntrinsicInfo {
   unsigned IntrinsicID;
   uint8_t ScalarOperand;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 static cl::opt<bool>
     RV64LegalI32("riscv-experimental-rv64-legal-i32", cl::ReallyHidden,
                  cl::desc("Make i32 a legal type for SelectionDAG on RV64."));
 
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
-  if (Subtarget.isRVE())
-    report_fatal_error("Codegen not yet implemented for RVE");
-
   RISCVABI::ABI ABI = Subtarget.getTargetABI();
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
 
   if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
       !Subtarget.hasStdExtF()) {
     errs() << "Hard-float 'f' ABI can't be used for a target that "
                 "doesn't support the F instruction set extension (ignoring "
                           "target-abi)\n";
     ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
   } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&
              !Subtarget.hasStdExtD()) {
     errs() << "Hard-float 'd' ABI can't be used for a target that "
               "doesn't support the D instruction set extension (ignoring "
               "target-abi)\n";
     ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
   }
 
   switch (ABI) {
   default:
     report_fatal_error("Don't know how to lower this ABI");
   case RISCVABI::ABI_ILP32:
+  case RISCVABI::ABI_ILP32E:
+  case RISCVABI::ABI_LP64E:
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64:
   case RISCVABI::ABI_LP64F:
   case RISCVABI::ABI_LP64D:
     break;
   }
 

 // frontend must modify the prototype so a pointer with the sret annotation is
 // passed as the first argument. This is not necessary for large scalar
 // returns.
 // * Struct return values and varargs should be coerced to structs containing
 // register-size fields in the same situations they would be for fixed
 // arguments.
 
 static const MCPhysReg ArgFPR16s[] = {
   RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
   RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
 };
 static const MCPhysReg ArgFPR32s[] = {
   RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
   RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
 };
 static const MCPhysReg ArgFPR64s[] = {
   RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
   RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
 };
 // This is an interim calling convention and it may be changed in the future.
 static const MCPhysReg ArgVRs[] = {
     RISCV::V8,  RISCV::V9,  RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
     RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
     RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23};
 static const MCPhysReg ArgVRM2s[] = {RISCV::V8M2,  RISCV::V10M2, RISCV::V12M2,
                                      RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
                                      RISCV::V20M2, RISCV::V22M2};
 static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
                                      RISCV::V20M4};
 static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8};
 
-ArrayRef<MCPhysReg> RISCV::getArgGPRs() {
-  static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+ArrayRef<MCPhysReg> RISCV::getArgGPRs(const RISCVABI::ABI ABI) {
+  // The GPRs used for passing arguments in the ILP32* and LP64* ABIs, except
+  // the ILP32E ABI.
+  static const MCPhysReg ArgIGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
                                        RISCV::X13, RISCV::X14, RISCV::X15,
                                        RISCV::X16, RISCV::X17};
+  // The GPRs used for passing arguments in the ILP32E/ILP64E ABI.
+  static const MCPhysReg ArgEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+                                       RISCV::X13, RISCV::X14, RISCV::X15};
+
+  if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
+    return ArrayRef(ArgEGPRs);
+
+  return ArrayRef(ArgIGPRs);
+}
+
+static ArrayRef<MCPhysReg> getFastCCArgGPRs(const RISCVABI::ABI ABI) {
+  // The GPRs used for passing arguments in the FastCC, X5 and X6 might be used
+  // for save-restore libcall, so we don't use them.
+  static const MCPhysReg FastCCIGPRs[] = {
+      RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
+      RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7,  RISCV::X28,
+      RISCV::X29, RISCV::X30, RISCV::X31};
+
+  // The GPRs used for passing arguments in the FastCC when using ILP32E/ILP64E.
+  static const MCPhysReg FastCCEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+                                          RISCV::X13, RISCV::X14, RISCV::X15,
+                                          RISCV::X7};
 
-  return ArrayRef(ArgGPRs);
+  if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
+    return ArrayRef(FastCCEGPRs);
+
+  return ArrayRef(FastCCIGPRs);
 }
 
 // Pass a 2*XLEN argument that has been split into two XLEN values through
 // registers or the stack as necessary.
 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
                                 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
                                 MVT ValVT2, MVT LocVT2,
-                                ISD::ArgFlagsTy ArgFlags2) {
+                                ISD::ArgFlagsTy ArgFlags2, bool EABI) {
   unsigned XLenInBytes = XLen / 8;
-  ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs();
+  const RISCVSubtarget &STI =
+      State.getMachineFunction().getSubtarget<RISCVSubtarget>();
+  ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(STI.getTargetABI());
+
   if (Register Reg = State.AllocateReg(ArgGPRs)) {
     // At least one half can be passed via register.
     State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
                                      VA1.getLocVT(), CCValAssign::Full));
   } else {
     // Both halves must be passed on the stack, with proper alignment.
-    Align StackAlign =
-        std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign());
+    // TODO: To be compatible with GCC's behaviors, we force them to have 4-byte
+    // alignment. This behavior may be changed when RV32E/ILP32E is ratified.
+    Align StackAlign(XLenInBytes);
+    if (!EABI || XLen != 32)
+      StackAlign = std::max(StackAlign, ArgFlags1.getNonZeroOrigAlign());
     State.addLoc(
         CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
                             State.AllocateStack(XLenInBytes, StackAlign),
                             VA1.getLocVT(), CCValAssign::Full));
     State.addLoc(CCValAssign::getMem(
         ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)),
         LocVT2, CCValAssign::Full));
     return false;
bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // UseGPRForF64 if targeting soft-float ABIs or an FLEN=32 ABI, if passing a
   // variadic argument, or if no F64 argument registers are available.
   bool UseGPRForF64 = true;
 
   switch (ABI) {
   default:
     llvm_unreachable("Unexpected ABI");
   case RISCVABI::ABI_ILP32:
+  case RISCVABI::ABI_ILP32E:
   case RISCVABI::ABI_LP64:
+  case RISCVABI::ABI_LP64E:
     break;
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_LP64F:
     UseGPRForF16_F32 = !IsFixed;
     break;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
     UseGPRForF16_F32 = !IsFixed;
if (UseGPRForF16_F32 &&
       (ValVT == MVT::f16 || ValVT == MVT::bf16 || ValVT == MVT::f32)) {
     LocVT = XLenVT;
     LocInfo = CCValAssign::BCvt;
   } else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) {
     LocVT = MVT::i64;
     LocInfo = CCValAssign::BCvt;
   }
 
-  ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs();
+  ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(ABI);
 
   // If this is a variadic argument, the RISC-V calling convention requires
   // that it is assigned an 'even' or 'aligned' register if it has 8-byte
   // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
   // be used regardless of whether the original argument was split during
   // legalisation or not. The argument will not be passed by registers if the
   // original type is larger than 2*XLEN, so the register alignment rule does
   // not apply.
+  // TODO: To be compatible with GCC's behaviors, we don't align registers
+  // currently if we are using ILP32E calling convention. This behavior may be
+  // changed when RV32E/ILP32E is ratified.
   unsigned TwoXLenInBytes = (2 * XLen) / 8;
   if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes &&
-      DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
+      DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes &&
+      ABI != RISCVABI::ABI_ILP32E) {
     unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
     // Skip 'odd' register if necessary.
     if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1)
       State.AllocateReg(ArgGPRs);
   }
 
   SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
   SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
if (ValVT.isScalarInteger() && ArgFlags.isSplitEnd() &&
       PendingLocs.size() <= 2) {
     assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
     // Apply the normal calling convention rules to the first half of the
     // split argument.
     CCValAssign VA = PendingLocs[0];
     ISD::ArgFlagsTy AF = PendingArgFlags[0];
     PendingLocs.clear();
     PendingArgFlags.clear();
-    return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
-                               ArgFlags);
+    return CC_RISCVAssign2XLen(
+        XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags,
+        ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E);
   }
 
   // Allocate to a register if possible, or else a stack slot.
   Register Reg;
   unsigned StoreSizeBytes = XLen / 8;
   Align StackAlign = Align(XLen / 8);
 
   if ((ValVT == MVT::f16 || ValVT == MVT::bf16) && !UseGPRForF16_F32)
if (!Reg) {
         LocVT = ValVT;
         StoreSizeBytes = ValVT.getStoreSize();
         // Align vectors to their element sizes, being careful for vXi1
         // vectors.
         StackAlign = MaybeAlign(ValVT.getScalarSizeInBits() / 8).valueOrOne();
       }
     }
   } else {
     Reg = State.AllocateReg(ArgGPRs);
   }
 
   unsigned StackOffset =
       Reg ? 0 : State.AllocateStack(StoreSizeBytes, StackAlign);
 
   // If we reach this point and PendingLocs is non-empty, we must be at the
   // end of a split argument that must be passed indirectly.
   if (!PendingLocs.empty()) {
static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
   assert(VA.isRegLoc() && "Expected register VA assignment");
 
   Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
   RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
   SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
   SDValue Hi;
   if (HiVA.isMemLoc()) {
     // Second half of f64 is passed on the stack.
     int FI = MFI.CreateFixedObject(4, HiVA.getLocMemOffset(),
                                    /*IsImmutable=*/true);
     SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
     Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
                      MachinePointerInfo::getFixedStack(MF, FI));
   } else {
     // Second half of f64 is passed in another GPR.
     Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
     RegInfo.addLiveIn(HiVA.getLocReg(), HiVReg);
     Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
   }
   return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
 }
 
 // FastCC has less than 1% performance improvement for some particular
 // benchmark. But theoretically, it may has benenfit for some cases.
 bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
                             unsigned ValNo, MVT ValVT, MVT LocVT,
                             CCValAssign::LocInfo LocInfo,
                             ISD::ArgFlagsTy ArgFlags, CCState &State,
                             bool IsFixed, bool IsRet, Type *OrigTy,
                             const RISCVTargetLowering &TLI,
                             std::optional<unsigned> FirstMaskArgument) {
-
-  // X5 and X6 might be used for save-restore libcall.
-  static const MCPhysReg GPRList[] = {
-      RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
-      RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7,  RISCV::X28,
-      RISCV::X29, RISCV::X30, RISCV::X31};
-
   if (LocVT == MVT::i32 || LocVT == MVT::i64) {
-    if (unsigned Reg = State.AllocateReg(GPRList)) {
+    if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
   }
 
   const RISCVSubtarget &Subtarget = TLI.getSubtarget();
 
   if (LocVT == MVT::f16 &&
bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
   }
 
   // Check if there is an available GPR before hitting the stack.
   if ((LocVT == MVT::f16 &&
        (Subtarget.hasStdExtZhinx() || Subtarget.hasStdExtZhinxmin())) ||
       (LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
       (LocVT == MVT::f64 && Subtarget.is64Bit() &&
        Subtarget.hasStdExtZdinx())) {
-    if (unsigned Reg = State.AllocateReg(GPRList)) {
+    if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
   }
 
   if (LocVT == MVT::f16) {
     unsigned Offset2 = State.AllocateStack(2, Align(2));
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
if (unsigned Reg =
             allocateRVVReg(ValVT, ValNo, FirstMaskArgument, State, TLI)) {
       // Fixed-length vectors are located in the corresponding scalable-vector
       // container types.
       if (ValVT.isFixedLengthVector())
         LocVT = TLI.getContainerForFixedLengthVector(LocVT);
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     } else {
       // Try and pass the address via a "fast" GPR.
-      if (unsigned GPRReg = State.AllocateReg(GPRList)) {
+      if (unsigned GPRReg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
         LocInfo = CCValAssign::Indirect;
         LocVT = TLI.getSubtarget().getXLenVT();
         State.addLoc(CCValAssign::getReg(ValNo, ValVT, GPRReg, LocVT, LocInfo));
       } else if (ValVT.isFixedLengthVector()) {
         auto StackAlign =
             MaybeAlign(ValVT.getScalarSizeInBits() / 8).valueOrOne();
         unsigned StackOffset =
             State.AllocateStack(ValVT.getStoreSize(), StackAlign);
SDValue RISCVTargetLowering::LowerFormalArguments(
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
   case CallingConv::SPIR_KERNEL:
   case CallingConv::GRAAL:
     break;
   case CallingConv::GHC:
+    if (Subtarget.isRVE())
+      report_fatal_error("GHC calling convention is not supported on RVE!");
     if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
       report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
                          "(Zdinx/D) instruction set extensions");
   }
 
   const Function &Func = MF.getFunction();
   if (Func.hasFnAttribute("interrupt")) {
     if (!Func.arg_empty())
for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
     InVals.push_back(ArgValue);
   }
 
   if (any_of(ArgLocs,
              [](CCValAssign &VA) { return VA.getLocVT().isScalableVector(); }))
     MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
 
   if (IsVarArg) {
-    ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs();
+    ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI());
     unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
     const TargetRegisterClass *RC = &RISCV::GPRRegClass;
     MachineFrameInfo &MFI = MF.getFrameInfo();
     MachineRegisterInfo &RegInfo = MF.getRegInfo();
     RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
 
     // Size of the vararg save area. For now, the varargs save area is either
     // zero or large enough to hold a0-a7.
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   MVT XLenVT = Subtarget.getXLenVT();
 
   MachineFunction &MF = DAG.getMachineFunction();
 
   // Analyze the operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
-  if (CallConv == CallingConv::GHC)
+  if (CallConv == CallingConv::GHC) {
+    if (Subtarget.isRVE())
+      report_fatal_error("GHC calling convention is not supported on RVE!");
     ArgCCInfo.AnalyzeCallOperands(Outs, RISCV::CC_RISCV_GHC);
-  else
+  } else
     analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI,
                       CallConv == CallingConv::Fast ? RISCV::CC_RISCV_FastCC
                                                     : RISCV::CC_RISCV);
 
   // Check if it's really possible to do a tail call.
   if (IsTailCall)
     IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
 
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
     auto &VA = RVLocs[i];
     // Copy the value out
     SDValue RetValue =
         DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
     // Glue the RetValue to the end of the call sequence
     Chain = RetValue.getValue(1);
     Glue = RetValue.getValue(2);
 
     if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
       assert(VA.needsCustom());
       SDValue RetValue2 = DAG.getCopyFromReg(Chain, DL, RVLocs[++i].getLocReg(),
                                              MVT::i32, Glue);
       Chain = RetValue2.getValue(1);
       Glue = RetValue2.getValue(2);
       RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
                              RetValue2);
     }
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
     return CSR_NoRegs_SaveList;
   if (MF->getFunction().hasFnAttribute("interrupt")) {
     if (Subtarget.hasStdExtD())
       return CSR_XLEN_F64_Interrupt_SaveList;
     if (Subtarget.hasStdExtF())
-      return CSR_XLEN_F32_Interrupt_SaveList;
-    return CSR_Interrupt_SaveList;
+      return Subtarget.isRVE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
+                               : CSR_XLEN_F32_Interrupt_SaveList;
+    return Subtarget.isRVE() ? CSR_Interrupt_RVE_SaveList
+                             : CSR_Interrupt_SaveList;
   }
 
   switch (Subtarget.getTargetABI()) {
   default:
     llvm_unreachable("Unrecognized ABI");
+  case RISCVABI::ABI_ILP32E:
+  case RISCVABI::ABI_LP64E:
+    return CSR_ILP32E_LP64E_SaveList;
   case RISCVABI::ABI_ILP32:
   case RISCVABI::ABI_LP64:
     return CSR_ILP32_LP64_SaveList;
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_LP64F:
     return CSR_ILP32F_LP64F_SaveList;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // Reserve the base register if we need to realign the stack and allocate
   // variable-sized objects at runtime.
   if (TFI->hasBP(MF))
     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
 
   // Additionally reserve dummy register used to form the register pair
   // beginning with 'x0' for instructions that take register pairs.
   markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
 
+  // There are only 16 GPRs for RVE.
+  if (Subtarget.isRVE())
+    for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
+      markSuperRegs(Reserved, Reg);
+
   // V registers for code generation. We handle them manually.
   markSuperRegs(Reserved, RISCV::VL);
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
   markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
 
   // Floating point environment registers.
RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID CC) const {
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
   if (CC == CallingConv::GHC)
     return CSR_NoRegs_RegMask;
   switch (Subtarget.getTargetABI()) {
   default:
     llvm_unreachable("Unrecognized ABI");
+  case RISCVABI::ABI_ILP32E:
+  case RISCVABI::ABI_LP64E:
+    return CSR_ILP32E_LP64E_RegMask;
   case RISCVABI::ABI_ILP32:
   case RISCVABI::ABI_LP64:
     return CSR_ILP32_LP64_RegMask;
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_LP64F:
     return CSR_ILP32F_LP64F_RegMask;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVInsertReadWriteCSRPass(*PR);
   initializeRISCVInsertWriteVXRMPass(*PR);
   initializeRISCVDAGToDAGISelPass(*PR);
   initializeRISCVInitUndefPass(*PR);
   initializeRISCVMoveMergePass(*PR);
   initializeRISCVPushPopOptPass(*PR);
 }
 
-static StringRef computeDataLayout(const Triple &TT) {
-  if (TT.isArch64Bit())
+static StringRef computeDataLayout(const Triple &TT,
+                                   const TargetOptions &Options) {
+  StringRef ABIName = Options.MCOptions.getABIName();
+  if (TT.isArch64Bit()) {
+    if (ABIName == "lp64e")
+      return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64";
+
     return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
+  }
   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
+
+  if (ABIName == "ilp32e")
+    return "e-m:e-p:32:32-i64:64-n32-S32";
+
   return "e-m:e-p:32:32-i64:64-n32-S128";
 }
 
 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
                                            std::optional<Reloc::Model> RM) {
   return RM.value_or(Reloc::Static);
 }
 
 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        std::optional<Reloc::Model> RM,
                                        std::optional<CodeModel::Model> CM,
                                        CodeGenOptLevel OL, bool JIT)
-    : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
+    : LLVMTargetMachine(T, computeDataLayout(TT, Options), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
   initAsmInfo();
 
   // RISC-V supports the MachineOutliner.
   setMachineOutliner(true);
   setSupportsDefaultOutlining(true);

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=ILP32E
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=LP64
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=LP64E
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32F
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=LP64F
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32D
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=LP64D
 
 @var = global [32 x float] zeroinitializer
 
-; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
-; fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.
+; All floating point registers are temporaries for the ilp32, ilp32e, lp64e and lp64
+; ABIs. fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.
 
 ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
 ; something appropriate.
 
 define void @callee() nounwind {
 ; ILP32-LABEL: callee:
 ; ILP32:       # %bb.0:
 ; ILP32-NEXT:    lui a0, %hi(var)
 ; ILP32-NEXT:    flw fa5, %lo(var)(a0)
 ; ILP32-NEXT:    flw fa4, %lo(var+4)(a0)
 ; ILP32-NEXT:    flw fa3, %lo(var+8)(a0)
 ; ILP32-NEXT:    flw fa2, %lo(var+12)(a0)
 ; ILP32-NEXT:    addi a1, a0, %lo(var)
 ; ILP32-NEXT:    flw fa1, 16(a1)

 ; ILP32-NEXT:    fsw fa0, 20(a1)
 ; ILP32-NEXT:    fsw fa1, 16(a1)
 ; ILP32-NEXT:    fsw fa2, %lo(var+12)(a0)
 ; ILP32-NEXT:    fsw fa3, %lo(var+8)(a0)
 ; ILP32-NEXT:    fsw fa4, %lo(var+4)(a0)
 ; ILP32-NEXT:    fsw fa5, %lo(var)(a0)
 ; ILP32-NEXT:    ret
 ;
+; ILP32E-LABEL: callee:
+; ILP32E:       # %bb.0:
+; ILP32E-NEXT:    lui a0, %hi(var)
+; ILP32E-NEXT:    flw fa5, %lo(var)(a0)
+; ILP32E-NEXT:    flw fa4, %lo(var+4)(a0)
+; ILP32E-NEXT:    flw fa3, %lo(var+8)(a0)
+; ILP32E-NEXT:    flw fa2, %lo(var+12)(a0)
+; ILP32E-NEXT:    addi a1, a0, %lo(var)
+; ILP32E-NEXT:    flw fa1, 16(a1)
+; ILP32E-NEXT:    flw fa0, 20(a1)
+; ILP32E-NEXT:    flw ft0, 24(a1)
+; ILP32E-NEXT:    flw ft1, 28(a1)
+; ILP32E-NEXT:    flw ft2, 32(a1)
+; ILP32E-NEXT:    flw ft3, 36(a1)
+; ILP32E-NEXT:    flw ft4, 40(a1)
+; ILP32E-NEXT:    flw ft5, 44(a1)
+; ILP32E-NEXT:    flw ft6, 48(a1)
+; ILP32E-NEXT:    flw ft7, 52(a1)
+; ILP32E-NEXT:    flw fa6, 56(a1)
+; ILP32E-NEXT:    flw fa7, 60(a1)
+; ILP32E-NEXT:    flw ft8, 64(a1)
+; ILP32E-NEXT:    flw ft9, 68(a1)
+; ILP32E-NEXT:    flw ft10, 72(a1)
+; ILP32E-NEXT:    flw ft11, 76(a1)
+; ILP32E-NEXT:    flw fs0, 80(a1)
+; ILP32E-NEXT:    flw fs1, 84(a1)
+; ILP32E-NEXT:    flw fs2, 88(a1)
+; ILP32E-NEXT:    flw fs3, 92(a1)
+; ILP32E-NEXT:    flw fs4, 96(a1)
+; ILP32E-NEXT:    flw fs5, 100(a1)
+; ILP32E-NEXT:    flw fs6, 104(a1)
+; ILP32E-NEXT:    flw fs7, 108(a1)
+; ILP32E-NEXT:    flw fs8, 124(a1)
+; ILP32E-NEXT:    flw fs9, 120(a1)
+; ILP32E-NEXT:    flw fs10, 116(a1)
+; ILP32E-NEXT:    flw fs11, 112(a1)
+; ILP32E-NEXT:    fsw fs8, 124(a1)
+; ILP32E-NEXT:    fsw fs9, 120(a1)
+; ILP32E-NEXT:    fsw fs10, 116(a1)
+; ILP32E-NEXT:    fsw fs11, 112(a1)
+; ILP32E-NEXT:    fsw fs7, 108(a1)
+; ILP32E-NEXT:    fsw fs6, 104(a1)
+; ILP32E-NEXT:    fsw fs5, 100(a1)
+; ILP32E-NEXT:    fsw fs4, 96(a1)
+; ILP32E-NEXT:    fsw fs3, 92(a1)
+; ILP32E-NEXT:    fsw fs2, 88(a1)
+; ILP32E-NEXT:    fsw fs1, 84(a1)
+; ILP32E-NEXT:    fsw fs0, 80(a1)
+; ILP32E-NEXT:    fsw ft11, 76(a1)
+; ILP32E-NEXT:    fsw ft10, 72(a1)
+; ILP32E-NEXT:    fsw ft9, 68(a1)
+; ILP32E-NEXT:    fsw ft8, 64(a1)
+; ILP32E-NEXT:    fsw fa7, 60(a1)
+; ILP32E-NEXT:    fsw fa6, 56(a1)
+; ILP32E-NEXT:    fsw ft7, 52(a1)
+; ILP32E-NEXT:    fsw ft6, 48(a1)
+; ILP32E-NEXT:    fsw ft5, 44(a1)
+; ILP32E-NEXT:    fsw ft4, 40(a1)
+; ILP32E-NEXT:    fsw ft3, 36(a1)
+; ILP32E-NEXT:    fsw ft2, 32(a1)
+; ILP32E-NEXT:    fsw ft1, 28(a1)
+; ILP32E-NEXT:    fsw ft0, 24(a1)
+; ILP32E-NEXT:    fsw fa0, 20(a1)
+; ILP32E-NEXT:    fsw fa1, 16(a1)
+; ILP32E-NEXT:    fsw fa2, %lo(var+12)(a0)
+; ILP32E-NEXT:    fsw fa3, %lo(var+8)(a0)
+; ILP32E-NEXT:    fsw fa4, %lo(var+4)(a0)
+; ILP32E-NEXT:    fsw fa5, %lo(var)(a0)
+; ILP32E-NEXT:    ret
+;
 ; LP64-LABEL: callee:
 ; LP64:       # %bb.0:
 ; LP64-NEXT:    lui a0, %hi(var)
 ; LP64-NEXT:    flw fa5, %lo(var)(a0)
 ; LP64-NEXT:    flw fa4, %lo(var+4)(a0)
 ; LP64-NEXT:    flw fa3, %lo(var+8)(a0)
 ; LP64-NEXT:    flw fa2, %lo(var+12)(a0)
 ; LP64-NEXT:    addi a1, a0, %lo(var)

 ; LP64-NEXT:    fsw fa0, 20(a1)
 ; LP64-NEXT:    fsw fa1, 16(a1)
 ; LP64-NEXT:    fsw fa2, %lo(var+12)(a0)
 ; LP64-NEXT:    fsw fa3, %lo(var+8)(a0)
 ; LP64-NEXT:    fsw fa4, %lo(var+4)(a0)
 ; LP64-NEXT:    fsw fa5, %lo(var)(a0)
 ; LP64-NEXT:    ret
 ;
+; LP64E-LABEL: callee:
+; LP64E:       # %bb.0:
+; LP64E-NEXT:    lui a0, %hi(var)
+; LP64E-NEXT:    flw fa5, %lo(var)(a0)
+; LP64E-NEXT:    flw fa4, %lo(var+4)(a0)
+; LP64E-NEXT:    flw fa3, %lo(var+8)(a0)
+; LP64E-NEXT:    flw fa2, %lo(var+12)(a0)
+; LP64E-NEXT:    addi a1, a0, %lo(var)
+; LP64E-NEXT:    flw fa1, 16(a1)
+; LP64E-NEXT:    flw fa0, 20(a1)
+; LP64E-NEXT:    flw ft0, 24(a1)
+; LP64E-NEXT:    flw ft1, 28(a1)
+; LP64E-NEXT:    flw ft2, 32(a1)
+; LP64E-NEXT:    flw ft3, 36(a1)
+; LP64E-NEXT:    flw ft4, 40(a1)
+; LP64E-NEXT:    flw ft5, 44(a1)
+; LP64E-NEXT:    flw ft6, 48(a1)
+; LP64E-NEXT:    flw ft7, 52(a1)
+; LP64E-NEXT:    flw fa6, 56(a1)
+; LP64E-NEXT:    flw fa7, 60(a1)
+; LP64E-NEXT:    flw ft8, 64(a1)
+; LP64E-NEXT:    flw ft9, 68(a1)
+; LP64E-NEXT:    flw ft10, 72(a1)
+; LP64E-NEXT:    flw ft11, 76(a1)
+; LP64E-NEXT:    flw fs0, 80(a1)
+; LP64E-NEXT:    flw fs1, 84(a1)
+; LP64E-NEXT:    flw fs2, 88(a1)
+; LP64E-NEXT:    flw fs3, 92(a1)
+; LP64E-NEXT:    flw fs4, 96(a1)
+; LP64E-NEXT:    flw fs5, 100(a1)
+; LP64E-NEXT:    flw fs6, 104(a1)
+; LP64E-NEXT:    flw fs7, 108(a1)
+; LP64E-NEXT:    flw fs8, 124(a1)
+; LP64E-NEXT:    flw fs9, 120(a1)
+; LP64E-NEXT:    flw fs10, 116(a1)
+; LP64E-NEXT:    flw fs11, 112(a1)
+; LP64E-NEXT:    fsw fs8, 124(a1)
+; LP64E-NEXT:    fsw fs9, 120(a1)
+; LP64E-NEXT:    fsw fs10, 116(a1)
+; LP64E-NEXT:    fsw fs11, 112(a1)
+; LP64E-NEXT:    fsw fs7, 108(a1)
+; LP64E-NEXT:    fsw fs6, 104(a1)
+; LP64E-NEXT:    fsw fs5, 100(a1)
+; LP64E-NEXT:    fsw fs4, 96(a1)
+; LP64E-NEXT:    fsw fs3, 92(a1)
+; LP64E-NEXT:    fsw fs2, 88(a1)
+; LP64E-NEXT:    fsw fs1, 84(a1)
+; LP64E-NEXT:    fsw fs0, 80(a1)
+; LP64E-NEXT:    fsw ft11, 76(a1)
+; LP64E-NEXT:    fsw ft10, 72(a1)
+; LP64E-NEXT:    fsw ft9, 68(a1)
+; LP64E-NEXT:    fsw ft8, 64(a1)
+; LP64E-NEXT:    fsw fa7, 60(a1)
+; LP64E-NEXT:    fsw fa6, 56(a1)
+; LP64E-NEXT:    fsw ft7, 52(a1)
+; LP64E-NEXT:    fsw ft6, 48(a1)
+; LP64E-NEXT:    fsw ft5, 44(a1)
+; LP64E-NEXT:    fsw ft4, 40(a1)
+; LP64E-NEXT:    fsw ft3, 36(a1)
+; LP64E-NEXT:    fsw ft2, 32(a1)
+; LP64E-NEXT:    fsw ft1, 28(a1)
+; LP64E-NEXT:    fsw ft0, 24(a1)
+; LP64E-NEXT:    fsw fa0, 20(a1)
+; LP64E-NEXT:    fsw fa1, 16(a1)
+; LP64E-NEXT:    fsw fa2, %lo(var+12)(a0)
+; LP64E-NEXT:    fsw fa3, %lo(var+8)(a0)
+; LP64E-NEXT:    fsw fa4, %lo(var+4)(a0)
+; LP64E-NEXT:    fsw fa5, %lo(var)(a0)
+; LP64E-NEXT:    ret
+;
 ; ILP32F-LABEL: callee:
 ; ILP32F:       # %bb.0:
 ; ILP32F-NEXT:    addi sp, sp, -48
 ; ILP32F-NEXT:    fsw fs0, 44(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs1, 40(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs2, 36(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs3, 32(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs4, 28(sp) # 4-byte Folded Spill

 ; ILP32-NEXT:    flw fa5, 128(sp) # 4-byte Folded Reload
 ; ILP32-NEXT:    fsw fa5, %lo(var)(s0)
 ; ILP32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
 ; ILP32-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload
 ; ILP32-NEXT:    lw s1, 132(sp) # 4-byte Folded Reload
 ; ILP32-NEXT:    addi sp, sp, 144
 ; ILP32-NEXT:    ret
 ;
+; ILP32E-LABEL: caller:
+; ILP32E:       # %bb.0:
+; ILP32E-NEXT:    addi sp, sp, -140
+; ILP32E-NEXT:    sw ra, 136(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    sw s0, 132(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    sw s1, 128(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    lui s0, %hi(var)
+; ILP32E-NEXT:    flw fa5, %lo(var)(s0)
+; ILP32E-NEXT:    fsw fa5, 124(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, %lo(var+4)(s0)
+; ILP32E-NEXT:    fsw fa5, 120(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, %lo(var+8)(s0)
+; ILP32E-NEXT:    fsw fa5, 116(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, %lo(var+12)(s0)
+; ILP32E-NEXT:    fsw fa5, 112(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    addi s1, s0, %lo(var)
+; ILP32E-NEXT:    flw fa5, 16(s1)
+; ILP32E-NEXT:    fsw fa5, 108(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 20(s1)
+; ILP32E-NEXT:    fsw fa5, 104(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 24(s1)
+; ILP32E-NEXT:    fsw fa5, 100(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 28(s1)
+; ILP32E-NEXT:    fsw fa5, 96(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 32(s1)
+; ILP32E-NEXT:    fsw fa5, 92(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 36(s1)
+; ILP32E-NEXT:    fsw fa5, 88(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 40(s1)
+; ILP32E-NEXT:    fsw fa5, 84(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 44(s1)
+; ILP32E-NEXT:    fsw fa5, 80(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 48(s1)
+; ILP32E-NEXT:    fsw fa5, 76(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 52(s1)
+; ILP32E-NEXT:    fsw fa5, 72(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 56(s1)
+; ILP32E-NEXT:    fsw fa5, 68(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 60(s1)
+; ILP32E-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 64(s1)
+; ILP32E-NEXT:    fsw fa5, 60(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 68(s1)
+; ILP32E-NEXT:    fsw fa5, 56(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 72(s1)
+; ILP32E-NEXT:    fsw fa5, 52(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 76(s1)
+; ILP32E-NEXT:    fsw fa5, 48(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 80(s1)
+; ILP32E-NEXT:    fsw fa5, 44(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 84(s1)
+; ILP32E-NEXT:    fsw fa5, 40(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 88(s1)
+; ILP32E-NEXT:    fsw fa5, 36(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 92(s1)
+; ILP32E-NEXT:    fsw fa5, 32(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 96(s1)
+; ILP32E-NEXT:    fsw fa5, 28(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 100(s1)
+; ILP32E-NEXT:    fsw fa5, 24(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 104(s1)
+; ILP32E-NEXT:    fsw fa5, 20(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 108(s1)
+; ILP32E-NEXT:    fsw fa5, 16(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 112(s1)
+; ILP32E-NEXT:    fsw fa5, 12(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 116(s1)
+; ILP32E-NEXT:    fsw fa5, 8(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 120(s1)
+; ILP32E-NEXT:    fsw fa5, 4(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    flw fa5, 124(s1)
+; ILP32E-NEXT:    fsw fa5, 0(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    call callee
+; ILP32E-NEXT:    flw fa5, 0(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 124(s1)
+; ILP32E-NEXT:    flw fa5, 4(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 120(s1)
+; ILP32E-NEXT:    flw fa5, 8(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 116(s1)
+; ILP32E-NEXT:    flw fa5, 12(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 112(s1)
+; ILP32E-NEXT:    flw fa5, 16(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 108(s1)
+; ILP32E-NEXT:    flw fa5, 20(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 104(s1)
+; ILP32E-NEXT:    flw fa5, 24(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 100(s1)
+; ILP32E-NEXT:    flw fa5, 28(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 96(s1)
+; ILP32E-NEXT:    flw fa5, 32(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 92(s1)
+; ILP32E-NEXT:    flw fa5, 36(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 88(s1)
+; ILP32E-NEXT:    flw fa5, 40(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 84(s1)
+; ILP32E-NEXT:    flw fa5, 44(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 80(s1)
+; ILP32E-NEXT:    flw fa5, 48(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 76(s1)
+; ILP32E-NEXT:    flw fa5, 52(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 72(s1)
+; ILP32E-NEXT:    flw fa5, 56(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 68(s1)
+; ILP32E-NEXT:    flw fa5, 60(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 64(s1)
+; ILP32E-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 60(s1)
+; ILP32E-NEXT:    flw fa5, 68(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 56(s1)
+; ILP32E-NEXT:    flw fa5, 72(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 52(s1)
+; ILP32E-NEXT:    flw fa5, 76(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 48(s1)
+; ILP32E-NEXT:    flw fa5, 80(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 44(s1)
+; ILP32E-NEXT:    flw fa5, 84(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 40(s1)
+; ILP32E-NEXT:    flw fa5, 88(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 36(s1)
+; ILP32E-NEXT:    flw fa5, 92(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 32(s1)
+; ILP32E-NEXT:    flw fa5, 96(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 28(s1)
+; ILP32E-NEXT:    flw fa5, 100(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 24(s1)
+; ILP32E-NEXT:    flw fa5, 104(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 20(s1)
+; ILP32E-NEXT:    flw fa5, 108(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, 16(s1)
+; ILP32E-NEXT:    flw fa5, 112(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, %lo(var+12)(s0)
+; ILP32E-NEXT:    flw fa5, 116(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, %lo(var+8)(s0)
+; ILP32E-NEXT:    flw fa5, 120(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, %lo(var+4)(s0)
+; ILP32E-NEXT:    flw fa5, 124(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    fsw fa5, %lo(var)(s0)
+; ILP32E-NEXT:    lw ra, 136(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    lw s0, 132(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    lw s1, 128(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    addi sp, sp, 140
+; ILP32E-NEXT:    ret
+;
 ; LP64-LABEL: caller:
 ; LP64:       # %bb.0:
 ; LP64-NEXT:    addi sp, sp, -160
 ; LP64-NEXT:    sd ra, 152(sp) # 8-byte Folded Spill
 ; LP64-NEXT:    sd s0, 144(sp) # 8-byte Folded Spill
 ; LP64-NEXT:    sd s1, 136(sp) # 8-byte Folded Spill
 ; LP64-NEXT:    lui s0, %hi(var)
 ; LP64-NEXT:    flw fa5, %lo(var)(s0)

 ; LP64-NEXT:    flw fa5, 132(sp) # 4-byte Folded Reload
 ; LP64-NEXT:    fsw fa5, %lo(var)(s0)
 ; LP64-NEXT:    ld ra, 152(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    ld s0, 144(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    ld s1, 136(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    addi sp, sp, 160
 ; LP64-NEXT:    ret
 ;
+; LP64E-LABEL: caller:
+; LP64E:       # %bb.0:
+; LP64E-NEXT:    addi sp, sp, -152
+; LP64E-NEXT:    sd ra, 144(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    sd s0, 136(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    sd s1, 128(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    lui s0, %hi(var)
+; LP64E-NEXT:    flw fa5, %lo(var)(s0)
+; LP64E-NEXT:    fsw fa5, 124(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, %lo(var+4)(s0)
+; LP64E-NEXT:    fsw fa5, 120(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, %lo(var+8)(s0)
+; LP64E-NEXT:    fsw fa5, 116(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, %lo(var+12)(s0)
+; LP64E-NEXT:    fsw fa5, 112(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    addi s1, s0, %lo(var)
+; LP64E-NEXT:    flw fa5, 16(s1)
+; LP64E-NEXT:    fsw fa5, 108(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 20(s1)
+; LP64E-NEXT:    fsw fa5, 104(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 24(s1)
+; LP64E-NEXT:    fsw fa5, 100(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 28(s1)
+; LP64E-NEXT:    fsw fa5, 96(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 32(s1)
+; LP64E-NEXT:    fsw fa5, 92(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 36(s1)
+; LP64E-NEXT:    fsw fa5, 88(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 40(s1)
+; LP64E-NEXT:    fsw fa5, 84(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 44(s1)
+; LP64E-NEXT:    fsw fa5, 80(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 48(s1)
+; LP64E-NEXT:    fsw fa5, 76(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 52(s1)
+; LP64E-NEXT:    fsw fa5, 72(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 56(s1)
+; LP64E-NEXT:    fsw fa5, 68(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 60(s1)
+; LP64E-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 64(s1)
+; LP64E-NEXT:    fsw fa5, 60(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 68(s1)
+; LP64E-NEXT:    fsw fa5, 56(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 72(s1)
+; LP64E-NEXT:    fsw fa5, 52(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 76(s1)
+; LP64E-NEXT:    fsw fa5, 48(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 80(s1)
+; LP64E-NEXT:    fsw fa5, 44(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 84(s1)
+; LP64E-NEXT:    fsw fa5, 40(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 88(s1)
+; LP64E-NEXT:    fsw fa5, 36(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 92(s1)
+; LP64E-NEXT:    fsw fa5, 32(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 96(s1)
+; LP64E-NEXT:    fsw fa5, 28(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 100(s1)
+; LP64E-NEXT:    fsw fa5, 24(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 104(s1)
+; LP64E-NEXT:    fsw fa5, 20(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 108(s1)
+; LP64E-NEXT:    fsw fa5, 16(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 112(s1)
+; LP64E-NEXT:    fsw fa5, 12(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 116(s1)
+; LP64E-NEXT:    fsw fa5, 8(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 120(s1)
+; LP64E-NEXT:    fsw fa5, 4(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    flw fa5, 124(s1)
+; LP64E-NEXT:    fsw fa5, 0(sp) # 4-byte Folded Spill
+; LP64E-NEXT:    call callee
+; LP64E-NEXT:    flw fa5, 0(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 124(s1)
+; LP64E-NEXT:    flw fa5, 4(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 120(s1)
+; LP64E-NEXT:    flw fa5, 8(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 116(s1)
+; LP64E-NEXT:    flw fa5, 12(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 112(s1)
+; LP64E-NEXT:    flw fa5, 16(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 108(s1)
+; LP64E-NEXT:    flw fa5, 20(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 104(s1)
+; LP64E-NEXT:    flw fa5, 24(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 100(s1)
+; LP64E-NEXT:    flw fa5, 28(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 96(s1)
+; LP64E-NEXT:    flw fa5, 32(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 92(s1)
+; LP64E-NEXT:    flw fa5, 36(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 88(s1)
+; LP64E-NEXT:    flw fa5, 40(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 84(s1)
+; LP64E-NEXT:    flw fa5, 44(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 80(s1)
+; LP64E-NEXT:    flw fa5, 48(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 76(s1)
+; LP64E-NEXT:    flw fa5, 52(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 72(s1)
+; LP64E-NEXT:    flw fa5, 56(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 68(s1)
+; LP64E-NEXT:    flw fa5, 60(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 64(s1)
+; LP64E-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 60(s1)
+; LP64E-NEXT:    flw fa5, 68(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 56(s1)
+; LP64E-NEXT:    flw fa5, 72(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 52(s1)
+; LP64E-NEXT:    flw fa5, 76(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 48(s1)
+; LP64E-NEXT:    flw fa5, 80(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 44(s1)
+; LP64E-NEXT:    flw fa5, 84(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 40(s1)
+; LP64E-NEXT:    flw fa5, 88(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 36(s1)
+; LP64E-NEXT:    flw fa5, 92(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 32(s1)
+; LP64E-NEXT:    flw fa5, 96(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 28(s1)
+; LP64E-NEXT:    flw fa5, 100(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 24(s1)
+; LP64E-NEXT:    flw fa5, 104(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 20(s1)
+; LP64E-NEXT:    flw fa5, 108(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, 16(s1)
+; LP64E-NEXT:    flw fa5, 112(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, %lo(var+12)(s0)
+; LP64E-NEXT:    flw fa5, 116(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, %lo(var+8)(s0)
+; LP64E-NEXT:    flw fa5, 120(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, %lo(var+4)(s0)
+; LP64E-NEXT:    flw fa5, 124(sp) # 4-byte Folded Reload
+; LP64E-NEXT:    fsw fa5, %lo(var)(s0)
+; LP64E-NEXT:    ld ra, 144(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    ld s0, 136(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    ld s1, 128(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    addi sp, sp, 152
+; LP64E-NEXT:    ret
+;
 ; ILP32F-LABEL: caller:
 ; ILP32F:       # %bb.0:
 ; ILP32F-NEXT:    addi sp, sp, -144
 ; ILP32F-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    sw s1, 132(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs0, 128(sp) # 4-byte Folded Spill
 ; ILP32F-NEXT:    fsw fs1, 124(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs< %s \
 ; RUN:   | FileCheck %s -check-prefix=LP64
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64e -verify-machineinstrs< %s \
+; RUN:   | FileCheck %s -check-prefix=LP64E
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=ILP32D
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=LP64D
 
 @var = global [32 x double] zeroinitializer
 
-; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
+; All floating point registers are temporaries for the ilp32, lp64e and lp64 ABIs.
 ; fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.
 
 ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
 ; something appropriate.
 
 define void @callee() nounwind {
 ; ILP32-LABEL: callee:
 ; ILP32:       # %bb.0:

 ; LP64-NEXT:    fsd fa0, 40(a1)
 ; LP64-NEXT:    fsd fa1, 32(a1)
 ; LP64-NEXT:    fsd fa2, 24(a1)
 ; LP64-NEXT:    fsd fa3, 16(a1)
 ; LP64-NEXT:    fsd fa4, %lo(var+8)(a0)
 ; LP64-NEXT:    fsd fa5, %lo(var)(a0)
 ; LP64-NEXT:    ret
 ;
+; LP64E-LABEL: callee:
+; LP64E:       # %bb.0:
+; LP64E-NEXT:    lui a0, %hi(var)
+; LP64E-NEXT:    fld fa5, %lo(var)(a0)
+; LP64E-NEXT:    fld fa4, %lo(var+8)(a0)
+; LP64E-NEXT:    addi a1, a0, %lo(var)
+; LP64E-NEXT:    fld fa3, 16(a1)
+; LP64E-NEXT:    fld fa2, 24(a1)
+; LP64E-NEXT:    fld fa1, 32(a1)
+; LP64E-NEXT:    fld fa0, 40(a1)
+; LP64E-NEXT:    fld ft0, 48(a1)
+; LP64E-NEXT:    fld ft1, 56(a1)
+; LP64E-NEXT:    fld ft2, 64(a1)
+; LP64E-NEXT:    fld ft3, 72(a1)
+; LP64E-NEXT:    fld ft4, 80(a1)
+; LP64E-NEXT:    fld ft5, 88(a1)
+; LP64E-NEXT:    fld ft6, 96(a1)
+; LP64E-NEXT:    fld ft7, 104(a1)
+; LP64E-NEXT:    fld fa6, 112(a1)
+; LP64E-NEXT:    fld fa7, 120(a1)
+; LP64E-NEXT:    fld ft8, 128(a1)
+; LP64E-NEXT:    fld ft9, 136(a1)
+; LP64E-NEXT:    fld ft10, 144(a1)
+; LP64E-NEXT:    fld ft11, 152(a1)
+; LP64E-NEXT:    fld fs0, 160(a1)
+; LP64E-NEXT:    fld fs1, 168(a1)
+; LP64E-NEXT:    fld fs2, 176(a1)
+; LP64E-NEXT:    fld fs3, 184(a1)
+; LP64E-NEXT:    fld fs4, 192(a1)
+; LP64E-NEXT:    fld fs5, 200(a1)
+; LP64E-NEXT:    fld fs6, 208(a1)
+; LP64E-NEXT:    fld fs7, 216(a1)
+; LP64E-NEXT:    fld fs8, 248(a1)
+; LP64E-NEXT:    fld fs9, 240(a1)
+; LP64E-NEXT:    fld fs10, 232(a1)
+; LP64E-NEXT:    fld fs11, 224(a1)
+; LP64E-NEXT:    fsd fs8, 248(a1)
+; LP64E-NEXT:    fsd fs9, 240(a1)
+; LP64E-NEXT:    fsd fs10, 232(a1)
+; LP64E-NEXT:    fsd fs11, 224(a1)
+; LP64E-NEXT:    fsd fs7, 216(a1)
+; LP64E-NEXT:    fsd fs6, 208(a1)
+; LP64E-NEXT:    fsd fs5, 200(a1)
+; LP64E-NEXT:    fsd fs4, 192(a1)
+; LP64E-NEXT:    fsd fs3, 184(a1)
+; LP64E-NEXT:    fsd fs2, 176(a1)
+; LP64E-NEXT:    fsd fs1, 168(a1)
+; LP64E-NEXT:    fsd fs0, 160(a1)
+; LP64E-NEXT:    fsd ft11, 152(a1)
+; LP64E-NEXT:    fsd ft10, 144(a1)
+; LP64E-NEXT:    fsd ft9, 136(a1)
+; LP64E-NEXT:    fsd ft8, 128(a1)
+; LP64E-NEXT:    fsd fa7, 120(a1)
+; LP64E-NEXT:    fsd fa6, 112(a1)
+; LP64E-NEXT:    fsd ft7, 104(a1)
+; LP64E-NEXT:    fsd ft6, 96(a1)
+; LP64E-NEXT:    fsd ft5, 88(a1)
+; LP64E-NEXT:    fsd ft4, 80(a1)
+; LP64E-NEXT:    fsd ft3, 72(a1)
+; LP64E-NEXT:    fsd ft2, 64(a1)
+; LP64E-NEXT:    fsd ft1, 56(a1)
+; LP64E-NEXT:    fsd ft0, 48(a1)
+; LP64E-NEXT:    fsd fa0, 40(a1)
+; LP64E-NEXT:    fsd fa1, 32(a1)
+; LP64E-NEXT:    fsd fa2, 24(a1)
+; LP64E-NEXT:    fsd fa3, 16(a1)
+; LP64E-NEXT:    fsd fa4, %lo(var+8)(a0)
+; LP64E-NEXT:    fsd fa5, %lo(var)(a0)
+; LP64E-NEXT:    ret
+;
 ; ILP32D-LABEL: callee:
 ; ILP32D:       # %bb.0:
 ; ILP32D-NEXT:    addi sp, sp, -96
 ; ILP32D-NEXT:    fsd fs0, 88(sp) # 8-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs1, 80(sp) # 8-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs2, 72(sp) # 8-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs3, 64(sp) # 8-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs4, 56(sp) # 8-byte Folded Spill

 ; LP64-NEXT:    fld fa5, 256(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    fsd fa5, %lo(var)(s0)
 ; LP64-NEXT:    ld ra, 280(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    ld s0, 272(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    ld s1, 264(sp) # 8-byte Folded Reload
 ; LP64-NEXT:    addi sp, sp, 288
 ; LP64-NEXT:    ret
 ;
+; LP64E-LABEL: caller:
+; LP64E:       # %bb.0:
+; LP64E-NEXT:    addi sp, sp, -280
+; LP64E-NEXT:    sd ra, 272(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    sd s0, 264(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    sd s1, 256(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    lui s0, %hi(var)
+; LP64E-NEXT:    fld fa5, %lo(var)(s0)
+; LP64E-NEXT:    fsd fa5, 248(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, %lo(var+8)(s0)
+; LP64E-NEXT:    fsd fa5, 240(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    addi s1, s0, %lo(var)
+; LP64E-NEXT:    fld fa5, 16(s1)
+; LP64E-NEXT:    fsd fa5, 232(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 24(s1)
+; LP64E-NEXT:    fsd fa5, 224(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 32(s1)
+; LP64E-NEXT:    fsd fa5, 216(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 40(s1)
+; LP64E-NEXT:    fsd fa5, 208(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 48(s1)
+; LP64E-NEXT:    fsd fa5, 200(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 56(s1)
+; LP64E-NEXT:    fsd fa5, 192(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 64(s1)
+; LP64E-NEXT:    fsd fa5, 184(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 72(s1)
+; LP64E-NEXT:    fsd fa5, 176(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 80(s1)
+; LP64E-NEXT:    fsd fa5, 168(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 88(s1)
+; LP64E-NEXT:    fsd fa5, 160(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 96(s1)
+; LP64E-NEXT:    fsd fa5, 152(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 104(s1)
+; LP64E-NEXT:    fsd fa5, 144(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 112(s1)
+; LP64E-NEXT:    fsd fa5, 136(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 120(s1)
+; LP64E-NEXT:    fsd fa5, 128(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 128(s1)
+; LP64E-NEXT:    fsd fa5, 120(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 136(s1)
+; LP64E-NEXT:    fsd fa5, 112(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 144(s1)
+; LP64E-NEXT:    fsd fa5, 104(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 152(s1)
+; LP64E-NEXT:    fsd fa5, 96(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 160(s1)
+; LP64E-NEXT:    fsd fa5, 88(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 168(s1)
+; LP64E-NEXT:    fsd fa5, 80(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 176(s1)
+; LP64E-NEXT:    fsd fa5, 72(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 184(s1)
+; LP64E-NEXT:    fsd fa5, 64(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 192(s1)
+; LP64E-NEXT:    fsd fa5, 56(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 200(s1)
+; LP64E-NEXT:    fsd fa5, 48(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 208(s1)
+; LP64E-NEXT:    fsd fa5, 40(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 216(s1)
+; LP64E-NEXT:    fsd fa5, 32(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 224(s1)
+; LP64E-NEXT:    fsd fa5, 24(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 232(s1)
+; LP64E-NEXT:    fsd fa5, 16(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 240(s1)
+; LP64E-NEXT:    fsd fa5, 8(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    fld fa5, 248(s1)
+; LP64E-NEXT:    fsd fa5, 0(sp) # 8-byte Folded Spill
+; LP64E-NEXT:    call callee
+; LP64E-NEXT:    fld fa5, 0(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 248(s1)
+; LP64E-NEXT:    fld fa5, 8(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 240(s1)
+; LP64E-NEXT:    fld fa5, 16(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 232(s1)
+; LP64E-NEXT:    fld fa5, 24(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 224(s1)
+; LP64E-NEXT:    fld fa5, 32(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 216(s1)
+; LP64E-NEXT:    fld fa5, 40(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 208(s1)
+; LP64E-NEXT:    fld fa5, 48(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 200(s1)
+; LP64E-NEXT:    fld fa5, 56(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 192(s1)
+; LP64E-NEXT:    fld fa5, 64(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 184(s1)
+; LP64E-NEXT:    fld fa5, 72(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 176(s1)
+; LP64E-NEXT:    fld fa5, 80(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 168(s1)
+; LP64E-NEXT:    fld fa5, 88(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 160(s1)
+; LP64E-NEXT:    fld fa5, 96(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 152(s1)
+; LP64E-NEXT:    fld fa5, 104(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 144(s1)
+; LP64E-NEXT:    fld fa5, 112(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 136(s1)
+; LP64E-NEXT:    fld fa5, 120(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 128(s1)
+; LP64E-NEXT:    fld fa5, 128(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 120(s1)
+; LP64E-NEXT:    fld fa5, 136(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 112(s1)
+; LP64E-NEXT:    fld fa5, 144(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 104(s1)
+; LP64E-NEXT:    fld fa5, 152(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 96(s1)
+; LP64E-NEXT:    fld fa5, 160(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 88(s1)
+; LP64E-NEXT:    fld fa5, 168(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 80(s1)
+; LP64E-NEXT:    fld fa5, 176(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 72(s1)
+; LP64E-NEXT:    fld fa5, 184(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 64(s1)
+; LP64E-NEXT:    fld fa5, 192(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 56(s1)
+; LP64E-NEXT:    fld fa5, 200(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 48(s1)
+; LP64E-NEXT:    fld fa5, 208(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 40(s1)
+; LP64E-NEXT:    fld fa5, 216(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 32(s1)
+; LP64E-NEXT:    fld fa5, 224(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 24(s1)
+; LP64E-NEXT:    fld fa5, 232(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, 16(s1)
+; LP64E-NEXT:    fld fa5, 240(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, %lo(var+8)(s0)
+; LP64E-NEXT:    fld fa5, 248(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    fsd fa5, %lo(var)(s0)
+; LP64E-NEXT:    ld ra, 272(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    ld s0, 264(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    ld s1, 256(sp) # 8-byte Folded Reload
+; LP64E-NEXT:    addi sp, sp, 280
+; LP64E-NEXT:    ret
+;
 ; ILP32D-LABEL: caller:
 ; ILP32D:       # %bb.0:
 ; ILP32D-NEXT:    addi sp, sp, -272
 ; ILP32D-NEXT:    sw ra, 268(sp) # 4-byte Folded Spill
 ; ILP32D-NEXT:    sw s0, 264(sp) # 4-byte Folded Spill
 ; ILP32D-NEXT:    sw s1, 260(sp) # 4-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs0, 248(sp) # 8-byte Folded Spill
 ; ILP32D-NEXT:    fsd fs1, 240(sp) # 8-byte Folded Spill

llvm/test/CodeGen/RISCV/callee-saved-gprs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-ILP32E
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I-WITH-FP
 ; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs < %s \
 ; RUN: | FileCheck %s -check-prefixes=RV32IZCMP
 ; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs \
 ; RUN:  -frame-pointer=all < %s | FileCheck %s -check-prefixes=RV32IZCMP-WITH-FP
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-LP64E
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I-WITH-FP

 ; RV32I-NEXT:    lw s7, 44(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s8, 40(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s9, 36(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s10, 32(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s11, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 80
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: callee:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -48
+; RV32I-ILP32E-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lui a6, %hi(var)
+; RV32I-ILP32E-NEXT:    lw a0, %lo(var)(a6)
+; RV32I-ILP32E-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, %lo(var+4)(a6)
+; RV32I-ILP32E-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, %lo(var+8)(a6)
+; RV32I-ILP32E-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, %lo(var+12)(a6)
+; RV32I-ILP32E-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    addi a5, a6, %lo(var)
+; RV32I-ILP32E-NEXT:    lw a0, 16(a5)
+; RV32I-ILP32E-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 20(a5)
+; RV32I-ILP32E-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw t0, 24(a5)
+; RV32I-ILP32E-NEXT:    lw t1, 28(a5)
+; RV32I-ILP32E-NEXT:    lw t2, 32(a5)
+; RV32I-ILP32E-NEXT:    lw t3, 36(a5)
+; RV32I-ILP32E-NEXT:    lw t4, 40(a5)
+; RV32I-ILP32E-NEXT:    lw t5, 44(a5)
+; RV32I-ILP32E-NEXT:    lw t6, 48(a5)
+; RV32I-ILP32E-NEXT:    lw s2, 52(a5)
+; RV32I-ILP32E-NEXT:    lw s3, 56(a5)
+; RV32I-ILP32E-NEXT:    lw s4, 60(a5)
+; RV32I-ILP32E-NEXT:    lw s5, 64(a5)
+; RV32I-ILP32E-NEXT:    lw s6, 68(a5)
+; RV32I-ILP32E-NEXT:    lw s7, 72(a5)
+; RV32I-ILP32E-NEXT:    lw s8, 76(a5)
+; RV32I-ILP32E-NEXT:    lw s9, 80(a5)
+; RV32I-ILP32E-NEXT:    lw s10, 84(a5)
+; RV32I-ILP32E-NEXT:    lw s11, 88(a5)
+; RV32I-ILP32E-NEXT:    lw s0, 92(a5)
+; RV32I-ILP32E-NEXT:    lw s1, 96(a5)
+; RV32I-ILP32E-NEXT:    lw ra, 100(a5)
+; RV32I-ILP32E-NEXT:    lw a7, 104(a5)
+; RV32I-ILP32E-NEXT:    lw a4, 108(a5)
+; RV32I-ILP32E-NEXT:    lw a0, 124(a5)
+; RV32I-ILP32E-NEXT:    lw a1, 120(a5)
+; RV32I-ILP32E-NEXT:    lw a2, 116(a5)
+; RV32I-ILP32E-NEXT:    lw a3, 112(a5)
+; RV32I-ILP32E-NEXT:    sw a0, 124(a5)
+; RV32I-ILP32E-NEXT:    sw a1, 120(a5)
+; RV32I-ILP32E-NEXT:    sw a2, 116(a5)
+; RV32I-ILP32E-NEXT:    sw a3, 112(a5)
+; RV32I-ILP32E-NEXT:    sw a4, 108(a5)
+; RV32I-ILP32E-NEXT:    sw a7, 104(a5)
+; RV32I-ILP32E-NEXT:    sw ra, 100(a5)
+; RV32I-ILP32E-NEXT:    sw s1, 96(a5)
+; RV32I-ILP32E-NEXT:    sw s0, 92(a5)
+; RV32I-ILP32E-NEXT:    sw s11, 88(a5)
+; RV32I-ILP32E-NEXT:    sw s10, 84(a5)
+; RV32I-ILP32E-NEXT:    sw s9, 80(a5)
+; RV32I-ILP32E-NEXT:    sw s8, 76(a5)
+; RV32I-ILP32E-NEXT:    sw s7, 72(a5)
+; RV32I-ILP32E-NEXT:    sw s6, 68(a5)
+; RV32I-ILP32E-NEXT:    sw s5, 64(a5)
+; RV32I-ILP32E-NEXT:    sw s4, 60(a5)
+; RV32I-ILP32E-NEXT:    sw s3, 56(a5)
+; RV32I-ILP32E-NEXT:    sw s2, 52(a5)
+; RV32I-ILP32E-NEXT:    sw t6, 48(a5)
+; RV32I-ILP32E-NEXT:    sw t5, 44(a5)
+; RV32I-ILP32E-NEXT:    sw t4, 40(a5)
+; RV32I-ILP32E-NEXT:    sw t3, 36(a5)
+; RV32I-ILP32E-NEXT:    sw t2, 32(a5)
+; RV32I-ILP32E-NEXT:    sw t1, 28(a5)
+; RV32I-ILP32E-NEXT:    sw t0, 24(a5)
+; RV32I-ILP32E-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 20(a5)
+; RV32I-ILP32E-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 16(a5)
+; RV32I-ILP32E-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+12)(a6)
+; RV32I-ILP32E-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+8)(a6)
+; RV32I-ILP32E-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+4)(a6)
+; RV32I-ILP32E-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var)(a6)
+; RV32I-ILP32E-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 48
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV32I-WITH-FP-LABEL: callee:
 ; RV32I-WITH-FP:       # %bb.0:
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -80
 ; RV32I-WITH-FP-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s1, 68(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s2, 64(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s3, 60(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s7, 88(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s8, 80(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s9, 72(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s10, 64(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s11, 56(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 160
 ; RV64I-NEXT:    ret
 ;
+; RV64I-LP64E-LABEL: callee:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -80
+; RV64I-LP64E-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s1, 56(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lui a6, %hi(var)
+; RV64I-LP64E-NEXT:    lw a0, %lo(var)(a6)
+; RV64I-LP64E-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, %lo(var+4)(a6)
+; RV64I-LP64E-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, %lo(var+8)(a6)
+; RV64I-LP64E-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, %lo(var+12)(a6)
+; RV64I-LP64E-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    addi a5, a6, %lo(var)
+; RV64I-LP64E-NEXT:    lw a0, 16(a5)
+; RV64I-LP64E-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 20(a5)
+; RV64I-LP64E-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw t0, 24(a5)
+; RV64I-LP64E-NEXT:    lw t1, 28(a5)
+; RV64I-LP64E-NEXT:    lw t2, 32(a5)
+; RV64I-LP64E-NEXT:    lw t3, 36(a5)
+; RV64I-LP64E-NEXT:    lw t4, 40(a5)
+; RV64I-LP64E-NEXT:    lw t5, 44(a5)
+; RV64I-LP64E-NEXT:    lw t6, 48(a5)
+; RV64I-LP64E-NEXT:    lw s2, 52(a5)
+; RV64I-LP64E-NEXT:    lw s3, 56(a5)
+; RV64I-LP64E-NEXT:    lw s4, 60(a5)
+; RV64I-LP64E-NEXT:    lw s5, 64(a5)
+; RV64I-LP64E-NEXT:    lw s6, 68(a5)
+; RV64I-LP64E-NEXT:    lw s7, 72(a5)
+; RV64I-LP64E-NEXT:    lw s8, 76(a5)
+; RV64I-LP64E-NEXT:    lw s9, 80(a5)
+; RV64I-LP64E-NEXT:    lw s10, 84(a5)
+; RV64I-LP64E-NEXT:    lw s11, 88(a5)
+; RV64I-LP64E-NEXT:    lw s0, 92(a5)
+; RV64I-LP64E-NEXT:    lw s1, 96(a5)
+; RV64I-LP64E-NEXT:    lw ra, 100(a5)
+; RV64I-LP64E-NEXT:    lw a7, 104(a5)
+; RV64I-LP64E-NEXT:    lw a4, 108(a5)
+; RV64I-LP64E-NEXT:    lw a0, 124(a5)
+; RV64I-LP64E-NEXT:    lw a1, 120(a5)
+; RV64I-LP64E-NEXT:    lw a2, 116(a5)
+; RV64I-LP64E-NEXT:    lw a3, 112(a5)
+; RV64I-LP64E-NEXT:    sw a0, 124(a5)
+; RV64I-LP64E-NEXT:    sw a1, 120(a5)
+; RV64I-LP64E-NEXT:    sw a2, 116(a5)
+; RV64I-LP64E-NEXT:    sw a3, 112(a5)
+; RV64I-LP64E-NEXT:    sw a4, 108(a5)
+; RV64I-LP64E-NEXT:    sw a7, 104(a5)
+; RV64I-LP64E-NEXT:    sw ra, 100(a5)
+; RV64I-LP64E-NEXT:    sw s1, 96(a5)
+; RV64I-LP64E-NEXT:    sw s0, 92(a5)
+; RV64I-LP64E-NEXT:    sw s11, 88(a5)
+; RV64I-LP64E-NEXT:    sw s10, 84(a5)
+; RV64I-LP64E-NEXT:    sw s9, 80(a5)
+; RV64I-LP64E-NEXT:    sw s8, 76(a5)
+; RV64I-LP64E-NEXT:    sw s7, 72(a5)
+; RV64I-LP64E-NEXT:    sw s6, 68(a5)
+; RV64I-LP64E-NEXT:    sw s5, 64(a5)
+; RV64I-LP64E-NEXT:    sw s4, 60(a5)
+; RV64I-LP64E-NEXT:    sw s3, 56(a5)
+; RV64I-LP64E-NEXT:    sw s2, 52(a5)
+; RV64I-LP64E-NEXT:    sw t6, 48(a5)
+; RV64I-LP64E-NEXT:    sw t5, 44(a5)
+; RV64I-LP64E-NEXT:    sw t4, 40(a5)
+; RV64I-LP64E-NEXT:    sw t3, 36(a5)
+; RV64I-LP64E-NEXT:    sw t2, 32(a5)
+; RV64I-LP64E-NEXT:    sw t1, 28(a5)
+; RV64I-LP64E-NEXT:    sw t0, 24(a5)
+; RV64I-LP64E-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 20(a5)
+; RV64I-LP64E-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 16(a5)
+; RV64I-LP64E-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+12)(a6)
+; RV64I-LP64E-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+8)(a6)
+; RV64I-LP64E-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+4)(a6)
+; RV64I-LP64E-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var)(a6)
+; RV64I-LP64E-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s1, 56(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 80
+; RV64I-LP64E-NEXT:    ret
+;
 ; RV64I-WITH-FP-LABEL: callee:
 ; RV64I-WITH-FP:       # %bb.0:
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -160
 ; RV64I-WITH-FP-NEXT:    sd ra, 152(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s0, 144(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s1, 136(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s2, 128(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s3, 120(sp) # 8-byte Folded Spill

 ; RV32I-NEXT:    lw s7, 108(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s8, 104(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s9, 100(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s10, 96(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s11, 92(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 144
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -136
+; RV32I-ILP32E-NEXT:    sw ra, 132(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 128(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s1, 124(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lui a0, %hi(var)
+; RV32I-ILP32E-NEXT:    lw a1, %lo(var)(a0)
+; RV32I-ILP32E-NEXT:    sw a1, 120(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a1, %lo(var+4)(a0)
+; RV32I-ILP32E-NEXT:    sw a1, 116(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a1, %lo(var+8)(a0)
+; RV32I-ILP32E-NEXT:    sw a1, 112(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a1, %lo(var+12)(a0)
+; RV32I-ILP32E-NEXT:    sw a1, 108(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    addi s1, a0, %lo(var)
+; RV32I-ILP32E-NEXT:    lw a0, 16(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 104(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 20(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 100(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 24(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 96(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 28(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 92(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 32(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 88(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 36(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 40(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 44(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 48(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 72(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 52(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 68(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 56(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 64(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 60(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 60(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 64(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 68(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 52(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 72(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 76(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 80(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 40(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 84(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 36(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 88(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 92(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 96(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 100(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 104(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 108(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 112(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 116(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw a0, 120(s1)
+; RV32I-ILP32E-NEXT:    sw a0, 0(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    lw s0, 124(s1)
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    sw s0, 124(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 0(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 120(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 116(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 112(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 108(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 104(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 100(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 96(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 92(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 88(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 36(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 84(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 40(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 80(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 76(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 72(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 52(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 68(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 56(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 64(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 60(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 60(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 64(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 56(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 68(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 52(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 72(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 48(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 44(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 40(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 84(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 36(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 88(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 32(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 92(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 28(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 96(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 24(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 100(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 20(s1)
+; RV32I-ILP32E-NEXT:    lw a0, 104(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, 16(s1)
+; RV32I-ILP32E-NEXT:    lui a1, %hi(var)
+; RV32I-ILP32E-NEXT:    lw a0, 108(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+12)(a1)
+; RV32I-ILP32E-NEXT:    lw a0, 112(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+8)(a1)
+; RV32I-ILP32E-NEXT:    lw a0, 116(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var+4)(a1)
+; RV32I-ILP32E-NEXT:    lw a0, 120(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    sw a0, %lo(var)(a1)
+; RV32I-ILP32E-NEXT:    lw ra, 132(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 128(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s1, 124(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 136
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV32I-WITH-FP-LABEL: caller:
 ; RV32I-WITH-FP:       # %bb.0:
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -144
 ; RV32I-WITH-FP-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s1, 132(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s2, 128(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s3, 124(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s7, 216(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s8, 208(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s9, 200(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s10, 192(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s11, 184(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 288
 ; RV64I-NEXT:    ret
 ;
+; RV64I-LP64E-LABEL: caller:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -272
+; RV64I-LP64E-NEXT:    sd ra, 264(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 256(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s1, 248(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lui a0, %hi(var)
+; RV64I-LP64E-NEXT:    lw a1, %lo(var)(a0)
+; RV64I-LP64E-NEXT:    sd a1, 240(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a1, %lo(var+4)(a0)
+; RV64I-LP64E-NEXT:    sd a1, 232(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a1, %lo(var+8)(a0)
+; RV64I-LP64E-NEXT:    sd a1, 224(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a1, %lo(var+12)(a0)
+; RV64I-LP64E-NEXT:    sd a1, 216(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    addi s1, a0, %lo(var)
+; RV64I-LP64E-NEXT:    lw a0, 16(s1)
+; RV64I-LP64E-NEXT:    sd a0, 208(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 20(s1)
+; RV64I-LP64E-NEXT:    sd a0, 200(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 24(s1)
+; RV64I-LP64E-NEXT:    sd a0, 192(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 28(s1)
+; RV64I-LP64E-NEXT:    sd a0, 184(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 32(s1)
+; RV64I-LP64E-NEXT:    sd a0, 176(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 36(s1)
+; RV64I-LP64E-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 40(s1)
+; RV64I-LP64E-NEXT:    sd a0, 160(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 44(s1)
+; RV64I-LP64E-NEXT:    sd a0, 152(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 48(s1)
+; RV64I-LP64E-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 52(s1)
+; RV64I-LP64E-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 56(s1)
+; RV64I-LP64E-NEXT:    sd a0, 128(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 60(s1)
+; RV64I-LP64E-NEXT:    sd a0, 120(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 64(s1)
+; RV64I-LP64E-NEXT:    sd a0, 112(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 68(s1)
+; RV64I-LP64E-NEXT:    sd a0, 104(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 72(s1)
+; RV64I-LP64E-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 76(s1)
+; RV64I-LP64E-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 80(s1)
+; RV64I-LP64E-NEXT:    sd a0, 80(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 84(s1)
+; RV64I-LP64E-NEXT:    sd a0, 72(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 88(s1)
+; RV64I-LP64E-NEXT:    sd a0, 64(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 92(s1)
+; RV64I-LP64E-NEXT:    sd a0, 56(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 96(s1)
+; RV64I-LP64E-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 100(s1)
+; RV64I-LP64E-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 104(s1)
+; RV64I-LP64E-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 108(s1)
+; RV64I-LP64E-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 112(s1)
+; RV64I-LP64E-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 116(s1)
+; RV64I-LP64E-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw a0, 120(s1)
+; RV64I-LP64E-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    lw s0, 124(s1)
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    sw s0, 124(s1)
+; RV64I-LP64E-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 120(s1)
+; RV64I-LP64E-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 116(s1)
+; RV64I-LP64E-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 112(s1)
+; RV64I-LP64E-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 108(s1)
+; RV64I-LP64E-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 104(s1)
+; RV64I-LP64E-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 100(s1)
+; RV64I-LP64E-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 96(s1)
+; RV64I-LP64E-NEXT:    ld a0, 56(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 92(s1)
+; RV64I-LP64E-NEXT:    ld a0, 64(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 88(s1)
+; RV64I-LP64E-NEXT:    ld a0, 72(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 84(s1)
+; RV64I-LP64E-NEXT:    ld a0, 80(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 80(s1)
+; RV64I-LP64E-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 76(s1)
+; RV64I-LP64E-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 72(s1)
+; RV64I-LP64E-NEXT:    ld a0, 104(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 68(s1)
+; RV64I-LP64E-NEXT:    ld a0, 112(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 64(s1)
+; RV64I-LP64E-NEXT:    ld a0, 120(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 60(s1)
+; RV64I-LP64E-NEXT:    ld a0, 128(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 56(s1)
+; RV64I-LP64E-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 52(s1)
+; RV64I-LP64E-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 48(s1)
+; RV64I-LP64E-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 44(s1)
+; RV64I-LP64E-NEXT:    ld a0, 160(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 40(s1)
+; RV64I-LP64E-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 36(s1)
+; RV64I-LP64E-NEXT:    ld a0, 176(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 32(s1)
+; RV64I-LP64E-NEXT:    ld a0, 184(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 28(s1)
+; RV64I-LP64E-NEXT:    ld a0, 192(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 24(s1)
+; RV64I-LP64E-NEXT:    ld a0, 200(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 20(s1)
+; RV64I-LP64E-NEXT:    ld a0, 208(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, 16(s1)
+; RV64I-LP64E-NEXT:    lui a1, %hi(var)
+; RV64I-LP64E-NEXT:    ld a0, 216(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+12)(a1)
+; RV64I-LP64E-NEXT:    ld a0, 224(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+8)(a1)
+; RV64I-LP64E-NEXT:    ld a0, 232(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var+4)(a1)
+; RV64I-LP64E-NEXT:    ld a0, 240(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    sw a0, %lo(var)(a1)
+; RV64I-LP64E-NEXT:    ld ra, 264(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 256(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s1, 248(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 272
+; RV64I-LP64E-NEXT:    ret
+;
 ; RV64I-WITH-FP-LABEL: caller:
 ; RV64I-WITH-FP:       # %bb.0:
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -288
 ; RV64I-WITH-FP-NEXT:    sd ra, 280(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s0, 272(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s1, 264(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s2, 256(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s3, 248(sp) # 8-byte Folded Spill

 ; RV32I-NEXT:    .cfi_offset s4, -4
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    li s4, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    lw s4, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: foo:
+; RV32I-ILP32E:       # %bb.0: # %entry
+; RV32I-ILP32E-NEXT:    #APP
+; RV32I-ILP32E-NEXT:    li s4, 0
+; RV32I-ILP32E-NEXT:    #NO_APP
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV32I-WITH-FP-LABEL: foo:
 ; RV32I-WITH-FP:       # %bb.0: # %entry
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -16
 ; RV32I-WITH-FP-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-WITH-FP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s4, 4(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    .cfi_offset ra, -4

 ; RV64I-NEXT:    .cfi_offset s4, -8
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    li s4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld s4, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV64I-LP64E-LABEL: foo:
+; RV64I-LP64E:       # %bb.0: # %entry
+; RV64I-LP64E-NEXT:    #APP
+; RV64I-LP64E-NEXT:    li s4, 0
+; RV64I-LP64E-NEXT:    #NO_APP
+; RV64I-LP64E-NEXT:    ret
+;
 ; RV64I-WITH-FP-LABEL: foo:
 ; RV64I-WITH-FP:       # %bb.0: # %entry
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -32
 ; RV64I-WITH-FP-NEXT:    .cfi_def_cfa_offset 32
 ; RV64I-WITH-FP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s4, 8(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    .cfi_offset ra, -8

 ; RV32I-NEXT:    .cfi_offset s11, -4
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    li s11, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    lw s11, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: bar:
+; RV32I-ILP32E:       # %bb.0: # %entry
+; RV32I-ILP32E-NEXT:    #APP
+; RV32I-ILP32E-NEXT:    li s11, 0
+; RV32I-ILP32E-NEXT:    #NO_APP
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV32I-WITH-FP-LABEL: bar:
 ; RV32I-WITH-FP:       # %bb.0: # %entry
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -16
 ; RV32I-WITH-FP-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-WITH-FP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s11, 4(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    .cfi_offset ra, -4

 ; RV64I-NEXT:    .cfi_offset s11, -8
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    li s11, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld s11, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV64I-LP64E-LABEL: bar:
+; RV64I-LP64E:       # %bb.0: # %entry
+; RV64I-LP64E-NEXT:    #APP
+; RV64I-LP64E-NEXT:    li s11, 0
+; RV64I-LP64E-NEXT:    #NO_APP
+; RV64I-LP64E-NEXT:    ret
+;
 ; RV64I-WITH-FP-LABEL: bar:
 ; RV64I-WITH-FP:       # %bb.0: # %entry
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -32
 ; RV64I-WITH-FP-NEXT:    .cfi_def_cfa_offset 32
 ; RV64I-WITH-FP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s11, 8(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    .cfi_offset ra, -8

 ; RV32I-NEXT:    sw a2, 24(sp)
 ; RV32I-NEXT:    sw a1, 20(sp)
 ; RV32I-NEXT:    sw a0, 16(sp)
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 48
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: varargs:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -28
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 28
+; RV32I-ILP32E-NEXT:    sw ra, 0(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -28
+; RV32I-ILP32E-NEXT:    sw a5, 24(sp)
+; RV32I-ILP32E-NEXT:    sw a4, 20(sp)
+; RV32I-ILP32E-NEXT:    sw a3, 16(sp)
+; RV32I-ILP32E-NEXT:    sw a2, 12(sp)
+; RV32I-ILP32E-NEXT:    sw a1, 8(sp)
+; RV32I-ILP32E-NEXT:    sw a0, 4(sp)
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 0(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 28
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV32I-WITH-FP-LABEL: varargs:
 ; RV32I-WITH-FP:       # %bb.0:
 ; RV32I-WITH-FP-NEXT:    addi sp, sp, -48
 ; RV32I-WITH-FP-NEXT:    .cfi_def_cfa_offset 48
 ; RV32I-WITH-FP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITH-FP-NEXT:    .cfi_offset ra, -36
 ; RV32I-WITH-FP-NEXT:    .cfi_offset s0, -40

 ; RV64I-NEXT:    sd a2, 32(sp)
 ; RV64I-NEXT:    sd a1, 24(sp)
 ; RV64I-NEXT:    sd a0, 16(sp)
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 80
 ; RV64I-NEXT:    ret
 ;
+; RV64I-LP64E-LABEL: varargs:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -56
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 56
+; RV64I-LP64E-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -56
+; RV64I-LP64E-NEXT:    sd a5, 48(sp)
+; RV64I-LP64E-NEXT:    sd a4, 40(sp)
+; RV64I-LP64E-NEXT:    sd a3, 32(sp)
+; RV64I-LP64E-NEXT:    sd a2, 24(sp)
+; RV64I-LP64E-NEXT:    sd a1, 16(sp)
+; RV64I-LP64E-NEXT:    sd a0, 8(sp)
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 56
+; RV64I-LP64E-NEXT:    ret
+;
 ; RV64I-WITH-FP-LABEL: varargs:
 ; RV64I-WITH-FP:       # %bb.0:
 ; RV64I-WITH-FP-NEXT:    addi sp, sp, -80
 ; RV64I-WITH-FP-NEXT:    .cfi_def_cfa_offset 80
 ; RV64I-WITH-FP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64I-WITH-FP-NEXT:    .cfi_offset ra, -72
 ; RV64I-WITH-FP-NEXT:    .cfi_offset s0, -80

llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs -frame-pointer=all < %s \
+; RUN:   | FileCheck -check-prefix=RV64I-LP64E-WITHFP %s
+
+; This file contains tests that will have differing output for the lp64e ABIs.
+
+define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
+; RV64I-LP64E-FPELIM-LABEL: callee_float_in_regs:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    mv s0, a0
+; RV64I-LP64E-FPELIM-NEXT:    sext.w a0, a1
+; RV64I-LP64E-FPELIM-NEXT:    call __fixsfdi
+; RV64I-LP64E-FPELIM-NEXT:    add a0, s0, a0
+; RV64I-LP64E-FPELIM-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: callee_float_in_regs:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -24
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s1, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 24
+; RV64I-LP64E-WITHFP-NEXT:    mv s1, a0
+; RV64I-LP64E-WITHFP-NEXT:    sext.w a0, a1
+; RV64I-LP64E-WITHFP-NEXT:    call __fixsfdi
+; RV64I-LP64E-WITHFP-NEXT:    add a0, s1, a0
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s1, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 24
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  %b_fptosi = fptosi float %b to i64
+  %1 = add i64 %a, %b_fptosi
+  ret i64 %1
+}
+
+define i64 @caller_float_in_regs() nounwind {
+; RV64I-LP64E-FPELIM-LABEL: caller_float_in_regs:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -8
+; RV64I-LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    li a0, 1
+; RV64I-LP64E-FPELIM-NEXT:    lui a1, 262144
+; RV64I-LP64E-FPELIM-NEXT:    call callee_float_in_regs
+; RV64I-LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 8
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: caller_float_in_regs:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    li a0, 1
+; RV64I-LP64E-WITHFP-NEXT:    lui a1, 262144
+; RV64I-LP64E-WITHFP-NEXT:    call callee_float_in_regs
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  %1 = call i64 @callee_float_in_regs(i64 1, float 2.0)
+  ret i64 %1
+}
+
+define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind {
+; RV64I-LP64E-FPELIM-LABEL: callee_float_on_stack:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    addi s0, sp, 16
+; RV64I-LP64E-FPELIM-NEXT:    andi sp, sp, -16
+; RV64I-LP64E-FPELIM-NEXT:    lw a0, 16(s0)
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, s0, -16
+; RV64I-LP64E-FPELIM-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: callee_float_on_stack:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    andi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    lw a0, 16(s0)
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, s0, -16
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  %1 = trunc i128 %d to i64
+  %2 = bitcast float %e to i32
+  %3 = sext i32 %2 to i64
+  %4 = add i64 %1, %3
+  ret i64 %3
+}
+
+define i64 @caller_float_on_stack() nounwind {
+; RV64I-LP64E-FPELIM-LABEL: caller_float_on_stack:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -48
+; RV64I-LP64E-FPELIM-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    addi s0, sp, 48
+; RV64I-LP64E-FPELIM-NEXT:    andi sp, sp, -16
+; RV64I-LP64E-FPELIM-NEXT:    lui a0, 264704
+; RV64I-LP64E-FPELIM-NEXT:    sd a0, 16(sp)
+; RV64I-LP64E-FPELIM-NEXT:    sd zero, 8(sp)
+; RV64I-LP64E-FPELIM-NEXT:    li a1, 4
+; RV64I-LP64E-FPELIM-NEXT:    li a0, 1
+; RV64I-LP64E-FPELIM-NEXT:    li a2, 2
+; RV64I-LP64E-FPELIM-NEXT:    li a4, 3
+; RV64I-LP64E-FPELIM-NEXT:    sd a1, 0(sp)
+; RV64I-LP64E-FPELIM-NEXT:    li a1, 0
+; RV64I-LP64E-FPELIM-NEXT:    li a3, 0
+; RV64I-LP64E-FPELIM-NEXT:    li a5, 0
+; RV64I-LP64E-FPELIM-NEXT:    call callee_float_on_stack
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, s0, -48
+; RV64I-LP64E-FPELIM-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 48
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: caller_float_on_stack:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -48
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 48
+; RV64I-LP64E-WITHFP-NEXT:    andi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    lui a0, 264704
+; RV64I-LP64E-WITHFP-NEXT:    sd a0, 16(sp)
+; RV64I-LP64E-WITHFP-NEXT:    sd zero, 8(sp)
+; RV64I-LP64E-WITHFP-NEXT:    li a1, 4
+; RV64I-LP64E-WITHFP-NEXT:    li a0, 1
+; RV64I-LP64E-WITHFP-NEXT:    li a2, 2
+; RV64I-LP64E-WITHFP-NEXT:    li a4, 3
+; RV64I-LP64E-WITHFP-NEXT:    sd a1, 0(sp)
+; RV64I-LP64E-WITHFP-NEXT:    li a1, 0
+; RV64I-LP64E-WITHFP-NEXT:    li a3, 0
+; RV64I-LP64E-WITHFP-NEXT:    li a5, 0
+; RV64I-LP64E-WITHFP-NEXT:    call callee_float_on_stack
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, s0, -48
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 48
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  %1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
+  ret i64 %1
+}
+
+define float @callee_tiny_scalar_ret() nounwind {
+; RV64I-LP64E-FPELIM-LABEL: callee_tiny_scalar_ret:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    lui a0, 260096
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: callee_tiny_scalar_ret:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    lui a0, 260096
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  ret float 1.0
+}
+
+; The sign extension of the float return is necessary, as softened floats are
+; passed anyext.
+
+define i64 @caller_tiny_scalar_ret() nounwind {
+; RV64I-LP64E-FPELIM-LABEL: caller_tiny_scalar_ret:
+; RV64I-LP64E-FPELIM:       # %bb.0:
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, -8
+; RV64I-LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-FPELIM-NEXT:    call callee_tiny_scalar_ret
+; RV64I-LP64E-FPELIM-NEXT:    sext.w a0, a0
+; RV64I-LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-FPELIM-NEXT:    addi sp, sp, 8
+; RV64I-LP64E-FPELIM-NEXT:    ret
+;
+; RV64I-LP64E-WITHFP-LABEL: caller_tiny_scalar_ret:
+; RV64I-LP64E-WITHFP:       # %bb.0:
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    call callee_tiny_scalar_ret
+; RV64I-LP64E-WITHFP-NEXT:    sext.w a0, a0
+; RV64I-LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-WITHFP-NEXT:    ret
+  %1 = call float @callee_tiny_scalar_ret()
+  %2 = bitcast float %1 to i32
+  %3 = sext i32 %2 to i64
+  ret i64 %3
+}

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IF-ILP32E
+
+; Exercises the ILP32E calling convention code in the case that f32 is a legal
+; type. As well as testing that lowering is correct, these tests also aim to
+; check that floating point load/store or integer load/store is chosen
+; optimally when floats are passed on the stack.
+
+define float @onstack_f32_noop(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
+; RV32IF-ILP32E-LABEL: onstack_f32_noop:
+; RV32IF-ILP32E:       # %bb.0:
+; RV32IF-ILP32E-NEXT:    lw a0, 12(sp)
+; RV32IF-ILP32E-NEXT:    ret
+  ret float %f
+}
+
+define float @onstack_f32_fadd(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
+; RV32IF-ILP32E-LABEL: onstack_f32_fadd:
+; RV32IF-ILP32E:       # %bb.0:
+; RV32IF-ILP32E-NEXT:    flw fa5, 12(sp)
+; RV32IF-ILP32E-NEXT:    flw fa4, 8(sp)
+; RV32IF-ILP32E-NEXT:    fadd.s fa5, fa4, fa5
+; RV32IF-ILP32E-NEXT:    fmv.x.w a0, fa5
+; RV32IF-ILP32E-NEXT:    ret
+  %1 = fadd float %e, %f
+  ret float %1
+}
+
+define float @caller_onstack_f32_noop(float %a) nounwind {
+; RV32IF-ILP32E-LABEL: caller_onstack_f32_noop:
+; RV32IF-ILP32E:       # %bb.0:
+; RV32IF-ILP32E-NEXT:    addi sp, sp, -20
+; RV32IF-ILP32E-NEXT:    sw ra, 16(sp) # 4-byte Folded Spill
+; RV32IF-ILP32E-NEXT:    sw a0, 12(sp)
+; RV32IF-ILP32E-NEXT:    lui a0, 264704
+; RV32IF-ILP32E-NEXT:    sw a0, 8(sp)
+; RV32IF-ILP32E-NEXT:    sw zero, 4(sp)
+; RV32IF-ILP32E-NEXT:    li a1, 4
+; RV32IF-ILP32E-NEXT:    li a0, 1
+; RV32IF-ILP32E-NEXT:    li a2, 2
+; RV32IF-ILP32E-NEXT:    li a4, 3
+; RV32IF-ILP32E-NEXT:    sw a1, 0(sp)
+; RV32IF-ILP32E-NEXT:    li a1, 0
+; RV32IF-ILP32E-NEXT:    li a3, 0
+; RV32IF-ILP32E-NEXT:    li a5, 0
+; RV32IF-ILP32E-NEXT:    call onstack_f32_noop
+; RV32IF-ILP32E-NEXT:    lw ra, 16(sp) # 4-byte Folded Reload
+; RV32IF-ILP32E-NEXT:    addi sp, sp, 20
+; RV32IF-ILP32E-NEXT:    ret
+  %1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a)
+  ret float %1
+}
+
+define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
+; RV32IF-ILP32E-LABEL: caller_onstack_f32_fadd:
+; RV32IF-ILP32E:       # %bb.0:
+; RV32IF-ILP32E-NEXT:    addi sp, sp, -20
+; RV32IF-ILP32E-NEXT:    sw ra, 16(sp) # 4-byte Folded Spill
+; RV32IF-ILP32E-NEXT:    fmv.w.x fa5, a1
+; RV32IF-ILP32E-NEXT:    fmv.w.x fa4, a0
+; RV32IF-ILP32E-NEXT:    fadd.s fa3, fa4, fa5
+; RV32IF-ILP32E-NEXT:    fsub.s fa5, fa5, fa4
+; RV32IF-ILP32E-NEXT:    sw zero, 4(sp)
+; RV32IF-ILP32E-NEXT:    li a0, 4
+; RV32IF-ILP32E-NEXT:    sw a0, 0(sp)
+; RV32IF-ILP32E-NEXT:    fsw fa5, 12(sp)
+; RV32IF-ILP32E-NEXT:    li a0, 1
+; RV32IF-ILP32E-NEXT:    li a2, 2
+; RV32IF-ILP32E-NEXT:    li a4, 3
+; RV32IF-ILP32E-NEXT:    fsw fa3, 8(sp)
+; RV32IF-ILP32E-NEXT:    li a1, 0
+; RV32IF-ILP32E-NEXT:    li a3, 0
+; RV32IF-ILP32E-NEXT:    li a5, 0
+; RV32IF-ILP32E-NEXT:    call onstack_f32_noop
+; RV32IF-ILP32E-NEXT:    lw ra, 16(sp) # 4-byte Folded Reload
+; RV32IF-ILP32E-NEXT:    addi sp, sp, 20
+; RV32IF-ILP32E-NEXT:    ret
+  %1 = fadd float %a, %b
+  %2 = fsub float %b, %a
+  %3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2)
+  ret float %3
+}

llvm/test/CodeGen/RISCV/interrupt-attr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-F
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD
 ;
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+i -target-abi ilp32e -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV32I-ILP32E
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+e -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV32E
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+e,+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV32E-F
+;
 ; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
+;
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+i -target-abi lp64e -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV64I-LP64E
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+e -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV64E
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+e,+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV64E-F
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+e,+f,+d -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV64E-FD
 
 ;
 ; Checking for special return instructions (sret, mret).
 ;
 define void @foo_supervisor() #0 {
 ; CHECK-LABEL: foo_supervisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sret

 ; CHECK-RV32-FD-NEXT:    fld fs11, 32(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft8, 24(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft9, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft10, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft11, 0(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    addi sp, sp, 320
 ; CHECK-RV32-FD-NEXT:    mret
 ;
+; CHECK-RV32I-ILP32E-LABEL: foo_with_call:
+; CHECK-RV32I-ILP32E:       # %bb.0:
+; CHECK-RV32I-ILP32E-NEXT:    addi sp, sp, -104
+; CHECK-RV32I-ILP32E-NEXT:    sw ra, 100(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t0, 96(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t1, 92(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t2, 88(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    call otherfoo
+; CHECK-RV32I-ILP32E-NEXT:    lw ra, 100(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t0, 96(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t1, 92(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t2, 88(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    addi sp, sp, 104
+; CHECK-RV32I-ILP32E-NEXT:    mret
+;
+; CHECK-RV32E-LABEL: foo_with_call:
+; CHECK-RV32E:       # %bb.0:
+; CHECK-RV32E-NEXT:    addi sp, sp, -40
+; CHECK-RV32E-NEXT:    sw ra, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t0, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t1, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t2, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a1, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a2, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a3, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a4, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a5, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    call otherfoo
+; CHECK-RV32E-NEXT:    lw ra, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t0, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t1, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t2, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a1, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a2, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a3, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a4, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a5, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    addi sp, sp, 40
+; CHECK-RV32E-NEXT:    mret
+;
+; CHECK-RV32E-F-LABEL: foo_with_call:
+; CHECK-RV32E-F:       # %bb.0:
+; CHECK-RV32E-F-NEXT:    addi sp, sp, -168
+; CHECK-RV32E-F-NEXT:    sw ra, 164(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t0, 160(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t1, 156(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t2, 152(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a0, 148(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a1, 144(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a2, 140(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a3, 136(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a4, 132(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a5, 128(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft0, 124(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft1, 120(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft2, 116(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft3, 112(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft4, 108(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft5, 104(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft6, 100(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft7, 96(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs0, 92(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs1, 88(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft8, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft9, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft10, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft11, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    call otherfoo
+; CHECK-RV32E-F-NEXT:    lw ra, 164(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t0, 160(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t1, 156(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t2, 152(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a0, 148(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a1, 144(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a2, 140(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a3, 136(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a4, 132(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a5, 128(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft0, 124(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft1, 120(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft2, 116(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft3, 112(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft4, 108(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft5, 104(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft6, 100(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft7, 96(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs0, 92(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs1, 88(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft8, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft9, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft10, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft11, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    addi sp, sp, 168
+; CHECK-RV32E-F-NEXT:    mret
+;
 ; CHECK-RV64-LABEL: foo_with_call:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    addi sp, sp, -128
 ; CHECK-RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t0, 112(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t1, 104(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t2, 96(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    fld fs10, 40(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld fs11, 32(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft8, 24(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft9, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft10, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft11, 0(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    addi sp, sp, 384
 ; CHECK-RV64-FD-NEXT:    mret
+;
+; CHECK-RV64I-LP64E-LABEL: foo_with_call:
+; CHECK-RV64I-LP64E:       # %bb.0:
+; CHECK-RV64I-LP64E-NEXT:    addi sp, sp, -208
+; CHECK-RV64I-LP64E-NEXT:    sd ra, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t0, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t1, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t2, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a6, 120(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a7, 112(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s2, 104(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s3, 96(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s4, 88(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s5, 80(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s6, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s7, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s8, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s9, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s10, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s11, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    call otherfoo
+; CHECK-RV64I-LP64E-NEXT:    ld ra, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t0, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t1, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t2, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a6, 120(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a7, 112(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s2, 104(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s3, 96(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s4, 88(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s5, 80(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s6, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s7, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s8, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s9, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s10, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s11, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    addi sp, sp, 208
+; CHECK-RV64I-LP64E-NEXT:    mret
+;
+; CHECK-RV64E-LABEL: foo_with_call:
+; CHECK-RV64E:       # %bb.0:
+; CHECK-RV64E-NEXT:    addi sp, sp, -80
+; CHECK-RV64E-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t0, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t1, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t2, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a1, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a2, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a3, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a4, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a5, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    call otherfoo
+; CHECK-RV64E-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t0, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t1, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t2, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a1, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a2, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a3, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a4, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a5, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    addi sp, sp, 80
+; CHECK-RV64E-NEXT:    mret
+;
+; CHECK-RV64E-F-LABEL: foo_with_call:
+; CHECK-RV64E-F:       # %bb.0:
+; CHECK-RV64E-F-NEXT:    addi sp, sp, -208
+; CHECK-RV64E-F-NEXT:    sd ra, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t0, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t1, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t2, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft0, 124(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft1, 120(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft2, 116(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft3, 112(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft4, 108(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft5, 104(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft6, 100(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft7, 96(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs0, 92(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs1, 88(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft8, 12(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft9, 8(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft10, 4(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft11, 0(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    call otherfoo
+; CHECK-RV64E-F-NEXT:    ld ra, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t0, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t1, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t2, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft0, 124(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft1, 120(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft2, 116(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft3, 112(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft4, 108(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft5, 104(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft6, 100(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft7, 96(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs0, 92(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs1, 88(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft8, 12(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft9, 8(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft10, 4(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft11, 0(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    addi sp, sp, 208
+; CHECK-RV64E-F-NEXT:    mret
+;
+; CHECK-RV64E-FD-LABEL: foo_with_call:
+; CHECK-RV64E-FD:       # %bb.0:
+; CHECK-RV64E-FD-NEXT:    addi sp, sp, -464
+; CHECK-RV64E-FD-NEXT:    sd ra, 456(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t0, 448(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t1, 440(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t2, 432(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a0, 424(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a1, 416(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a2, 408(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a3, 400(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a4, 392(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a5, 384(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a6, 376(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a7, 368(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s2, 360(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s3, 352(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s4, 344(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s5, 336(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s6, 328(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s7, 320(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s8, 312(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s9, 304(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s10, 296(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s11, 288(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t3, 280(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t4, 272(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t5, 264(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t6, 256(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft0, 248(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft1, 240(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft2, 232(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft3, 224(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft4, 216(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft5, 208(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft6, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft7, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs0, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs1, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa6, 120(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa7, 112(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs2, 104(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs3, 96(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs4, 88(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs5, 80(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs6, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs7, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs8, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs9, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs10, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs11, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft8, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft9, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft10, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft11, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    call otherfoo
+; CHECK-RV64E-FD-NEXT:    ld ra, 456(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t0, 448(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t1, 440(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t2, 432(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a0, 424(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a1, 416(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a2, 408(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a3, 400(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a4, 392(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a5, 384(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a6, 376(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a7, 368(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s2, 360(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s3, 352(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s4, 344(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s5, 336(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s6, 328(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s7, 320(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s8, 312(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s9, 304(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s10, 296(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s11, 288(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t3, 280(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t4, 272(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t5, 264(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t6, 256(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft0, 248(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft1, 240(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft2, 232(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft3, 224(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft4, 216(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft5, 208(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft6, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft7, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs0, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs1, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa6, 120(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa7, 112(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs2, 104(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs3, 96(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs4, 88(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs5, 80(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs6, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs7, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs8, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs9, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs10, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs11, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft8, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft9, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft10, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft11, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    addi sp, sp, 464
+; CHECK-RV64E-FD-NEXT:    mret
   %call = call i32 @otherfoo()
   ret void
 }
 
 ;
 ; Additionally check frame pointer and return address are properly saved.
 ;
 define void @foo_fp_with_call() #2 {

 ; CHECK-RV32-FD-NEXT:    fld fs11, 40(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft8, 32(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft9, 24(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft10, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    fld ft11, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV32-FD-NEXT:    addi sp, sp, 336
 ; CHECK-RV32-FD-NEXT:    mret
 ;
+; CHECK-RV32I-ILP32E-LABEL: foo_fp_with_call:
+; CHECK-RV32I-ILP32E:       # %bb.0:
+; CHECK-RV32I-ILP32E-NEXT:    addi sp, sp, -108
+; CHECK-RV32I-ILP32E-NEXT:    sw ra, 104(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t0, 100(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t1, 96(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t2, 92(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s0, 88(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw a7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw s11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32I-ILP32E-NEXT:    addi s0, sp, 108
+; CHECK-RV32I-ILP32E-NEXT:    call otherfoo
+; CHECK-RV32I-ILP32E-NEXT:    lw ra, 104(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t0, 100(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t1, 96(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t2, 92(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s0, 88(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw a7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw s11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32I-ILP32E-NEXT:    addi sp, sp, 108
+; CHECK-RV32I-ILP32E-NEXT:    mret
+;
+; CHECK-RV32E-LABEL: foo_fp_with_call:
+; CHECK-RV32E:       # %bb.0:
+; CHECK-RV32E-NEXT:    addi sp, sp, -44
+; CHECK-RV32E-NEXT:    sw ra, 40(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t0, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t1, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw t2, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a1, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a2, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a3, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a4, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    sw a5, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32E-NEXT:    addi s0, sp, 44
+; CHECK-RV32E-NEXT:    call otherfoo
+; CHECK-RV32E-NEXT:    lw ra, 40(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t0, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t1, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw t2, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a1, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a2, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a3, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a4, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    lw a5, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32E-NEXT:    addi sp, sp, 44
+; CHECK-RV32E-NEXT:    mret
+;
+; CHECK-RV32E-F-LABEL: foo_fp_with_call:
+; CHECK-RV32E-F:       # %bb.0:
+; CHECK-RV32E-F-NEXT:    addi sp, sp, -172
+; CHECK-RV32E-F-NEXT:    sw ra, 168(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t0, 164(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t1, 160(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw t2, 156(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw s0, 152(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a0, 148(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a1, 144(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a2, 140(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a3, 136(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a4, 132(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    sw a5, 128(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft0, 124(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft1, 120(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft2, 116(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft3, 112(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft4, 108(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft5, 104(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft6, 100(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft7, 96(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs0, 92(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs1, 88(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fa7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw fs11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft8, 12(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft9, 8(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft10, 4(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    fsw ft11, 0(sp) # 4-byte Folded Spill
+; CHECK-RV32E-F-NEXT:    addi s0, sp, 172
+; CHECK-RV32E-F-NEXT:    call otherfoo
+; CHECK-RV32E-F-NEXT:    lw ra, 168(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t0, 164(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t1, 160(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw t2, 156(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw s0, 152(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a0, 148(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a1, 144(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a2, 140(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a3, 136(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a4, 132(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    lw a5, 128(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft0, 124(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft1, 120(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft2, 116(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft3, 112(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft4, 108(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft5, 104(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft6, 100(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft7, 96(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs0, 92(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs1, 88(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fa7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw fs11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft8, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft9, 8(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft10, 4(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    flw ft11, 0(sp) # 4-byte Folded Reload
+; CHECK-RV32E-F-NEXT:    addi sp, sp, 172
+; CHECK-RV32E-F-NEXT:    mret
+;
 ; CHECK-RV64-LABEL: foo_fp_with_call:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    addi sp, sp, -144
 ; CHECK-RV64-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t0, 128(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t1, 120(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd t2, 112(sp) # 8-byte Folded Spill
 ; CHECK-RV64-NEXT:    sd s0, 104(sp) # 8-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    fld fs10, 48(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld fs11, 40(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft8, 32(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft9, 24(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft10, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld ft11, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    addi sp, sp, 400
 ; CHECK-RV64-FD-NEXT:    mret
+;
+; CHECK-RV64I-LP64E-LABEL: foo_fp_with_call:
+; CHECK-RV64I-LP64E:       # %bb.0:
+; CHECK-RV64I-LP64E-NEXT:    addi sp, sp, -216
+; CHECK-RV64I-LP64E-NEXT:    sd ra, 208(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t0, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t1, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t2, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a6, 120(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd a7, 112(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s2, 104(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s3, 96(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s4, 88(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s5, 80(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s6, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s7, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s8, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s9, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s10, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd s11, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64I-LP64E-NEXT:    addi s0, sp, 216
+; CHECK-RV64I-LP64E-NEXT:    call otherfoo
+; CHECK-RV64I-LP64E-NEXT:    ld ra, 208(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t0, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t1, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t2, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a6, 120(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld a7, 112(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s2, 104(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s3, 96(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s4, 88(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s5, 80(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s6, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s7, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s8, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s9, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s10, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld s11, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64I-LP64E-NEXT:    addi sp, sp, 216
+; CHECK-RV64I-LP64E-NEXT:    mret
+;
+; CHECK-RV64E-LABEL: foo_fp_with_call:
+; CHECK-RV64E:       # %bb.0:
+; CHECK-RV64E-NEXT:    addi sp, sp, -88
+; CHECK-RV64E-NEXT:    sd ra, 80(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t0, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t1, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd t2, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a1, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a2, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a3, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a4, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    sd a5, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64E-NEXT:    addi s0, sp, 88
+; CHECK-RV64E-NEXT:    call otherfoo
+; CHECK-RV64E-NEXT:    ld ra, 80(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t0, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t1, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld t2, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a1, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a2, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a3, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a4, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    ld a5, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64E-NEXT:    addi sp, sp, 88
+; CHECK-RV64E-NEXT:    mret
+;
+; CHECK-RV64E-F-LABEL: foo_fp_with_call:
+; CHECK-RV64E-F:       # %bb.0:
+; CHECK-RV64E-F-NEXT:    addi sp, sp, -216
+; CHECK-RV64E-F-NEXT:    sd ra, 208(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t0, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t1, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd t2, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    sd a5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft0, 124(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft1, 120(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft2, 116(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft3, 112(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft4, 108(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft5, 104(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft6, 100(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft7, 96(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs0, 92(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs1, 88(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa0, 84(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa1, 80(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa2, 76(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa3, 72(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa4, 68(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa5, 64(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa6, 60(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fa7, 56(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs2, 52(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs3, 48(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs4, 44(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs5, 40(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs6, 36(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs7, 32(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs8, 28(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs9, 24(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs10, 20(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw fs11, 16(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft8, 12(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft9, 8(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft10, 4(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    fsw ft11, 0(sp) # 4-byte Folded Spill
+; CHECK-RV64E-F-NEXT:    addi s0, sp, 216
+; CHECK-RV64E-F-NEXT:    call otherfoo
+; CHECK-RV64E-F-NEXT:    ld ra, 208(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t0, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t1, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld t2, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    ld a5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft0, 124(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft1, 120(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft2, 116(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft3, 112(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft4, 108(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft5, 104(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft6, 100(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft7, 96(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs0, 92(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs1, 88(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa0, 84(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa1, 80(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa2, 76(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa3, 72(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa4, 68(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa5, 64(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa6, 60(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fa7, 56(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs2, 52(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs3, 48(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs4, 44(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs5, 40(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs6, 36(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs7, 32(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs8, 28(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs9, 24(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs10, 20(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw fs11, 16(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft8, 12(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft9, 8(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft10, 4(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    flw ft11, 0(sp) # 4-byte Folded Reload
+; CHECK-RV64E-F-NEXT:    addi sp, sp, 216
+; CHECK-RV64E-F-NEXT:    mret
+;
+; CHECK-RV64E-FD-LABEL: foo_fp_with_call:
+; CHECK-RV64E-FD:       # %bb.0:
+; CHECK-RV64E-FD-NEXT:    addi sp, sp, -472
+; CHECK-RV64E-FD-NEXT:    sd ra, 464(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t0, 456(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t1, 448(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t2, 440(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s0, 432(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a0, 424(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a1, 416(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a2, 408(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a3, 400(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a4, 392(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a5, 384(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a6, 376(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd a7, 368(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s2, 360(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s3, 352(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s4, 344(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s5, 336(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s6, 328(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s7, 320(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s8, 312(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s9, 304(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s10, 296(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd s11, 288(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t3, 280(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t4, 272(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t5, 264(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    sd t6, 256(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft0, 248(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft1, 240(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft2, 232(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft3, 224(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft4, 216(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft5, 208(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft6, 200(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft7, 192(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs0, 184(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs1, 176(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa0, 168(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa1, 160(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa2, 152(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa3, 144(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa4, 136(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa5, 128(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa6, 120(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fa7, 112(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs2, 104(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs3, 96(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs4, 88(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs5, 80(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs6, 72(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs7, 64(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs8, 56(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs9, 48(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs10, 40(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd fs11, 32(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft8, 24(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft9, 16(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft10, 8(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    fsd ft11, 0(sp) # 8-byte Folded Spill
+; CHECK-RV64E-FD-NEXT:    addi s0, sp, 472
+; CHECK-RV64E-FD-NEXT:    call otherfoo
+; CHECK-RV64E-FD-NEXT:    ld ra, 464(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t0, 456(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t1, 448(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t2, 440(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s0, 432(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a0, 424(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a1, 416(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a2, 408(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a3, 400(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a4, 392(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a5, 384(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a6, 376(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld a7, 368(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s2, 360(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s3, 352(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s4, 344(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s5, 336(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s6, 328(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s7, 320(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s8, 312(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s9, 304(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s10, 296(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld s11, 288(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t3, 280(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t4, 272(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t5, 264(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    ld t6, 256(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft0, 248(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft1, 240(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft2, 232(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft3, 224(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft4, 216(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft5, 208(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft6, 200(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft7, 192(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs0, 184(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs1, 176(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa0, 168(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa1, 160(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa2, 152(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa3, 144(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa4, 136(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa5, 128(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa6, 120(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fa7, 112(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs2, 104(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs3, 96(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs4, 88(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs5, 80(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs6, 72(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs7, 64(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs8, 56(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs9, 48(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs10, 40(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld fs11, 32(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft8, 24(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft9, 16(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft10, 8(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    fld ft11, 0(sp) # 8-byte Folded Reload
+; CHECK-RV64E-FD-NEXT:    addi sp, sp, 472
+; CHECK-RV64E-FD-NEXT:    mret
   %call = call i32 @otherfoo()
   ret void
 }
 
 attributes #0 = { nounwind "interrupt"="supervisor" }
 attributes #1 = { nounwind "interrupt"="machine" }
 attributes #2 = { nounwind "interrupt"="machine" "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/rv32e.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+; TODO: Add more tests.
+
+define i32 @exhausted(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
+; CHECK-LABEL: exhausted:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw t0, 0(sp)
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a3, a2
+; CHECK-NEXT:    add a0, a2, a0
+; CHECK-NEXT:    add a4, a5, a4
+; CHECK-NEXT:    add a0, a4, a0
+; CHECK-NEXT:    add a0, t0, a0
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = add i32 %c, %1
+  %3 = add i32 %d, %2
+  %4 = add i32 %e, %3
+  %5 = add i32 %f, %4
+  %6 = add i32 %g, %5
+  ret i32 %6
+}

llvm/test/CodeGen/RISCV/rv64e.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv64 -mattr=+e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+; TODO: Add more tests.
+
+define i64 @exhausted(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
+; CHECK-LABEL: exhausted:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld t0, 0(sp)
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a3, a2
+; CHECK-NEXT:    add a0, a2, a0
+; CHECK-NEXT:    add a4, a5, a4
+; CHECK-NEXT:    add a0, a4, a0
+; CHECK-NEXT:    add a0, t0, a0
+; CHECK-NEXT:    ret
+  %1 = add i64 %a, %b
+  %2 = add i64 %c, %1
+  %3 = add i64 %d, %2
+  %4 = add i64 %e, %3
+  %5 = add i64 %f, %4
+  %6 = add i64 %g, %5
+  ret i64 %6
+}

llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-ILP32E
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-LP64E
 
 declare void @callee(ptr, ptr)
 
 define void @caller(i32 %n) {
 ; RV32I-LABEL: caller:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -64
 ; RV32I-NEXT:    .cfi_def_cfa_offset 64

 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -64
 ; RV32I-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 52(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -64
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 64
+; RV32I-ILP32E-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s1, 52(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    .cfi_offset s1, -12
+; RV32I-ILP32E-NEXT:    addi s0, sp, 64
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -64
+; RV32I-ILP32E-NEXT:    mv s1, sp
+; RV32I-ILP32E-NEXT:    addi a0, a0, 3
+; RV32I-ILP32E-NEXT:    andi a0, a0, -4
+; RV32I-ILP32E-NEXT:    sub a0, sp, a0
+; RV32I-ILP32E-NEXT:    mv sp, a0
+; RV32I-ILP32E-NEXT:    mv a1, s1
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -64
+; RV32I-ILP32E-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s1, 52(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 64
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8

 ; RV64I-NEXT:    mv a1, s1
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -64
 ; RV64I-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -64
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 64
+; RV64I-LP64E-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s1, 40(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    .cfi_offset s1, -24
+; RV64I-LP64E-NEXT:    addi s0, sp, 64
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -64
+; RV64I-LP64E-NEXT:    mv s1, sp
+; RV64I-LP64E-NEXT:    slli a0, a0, 32
+; RV64I-LP64E-NEXT:    srli a0, a0, 32
+; RV64I-LP64E-NEXT:    addi a0, a0, 7
+; RV64I-LP64E-NEXT:    andi a0, a0, -8
+; RV64I-LP64E-NEXT:    sub a0, sp, a0
+; RV64I-LP64E-NEXT:    mv sp, a0
+; RV64I-LP64E-NEXT:    mv a1, s1
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -64
+; RV64I-LP64E-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s1, 40(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 64
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, i32 %n
   %2 = alloca i32, align 64
   call void @callee(ptr %1, ptr %2)
   ret void
 }

llvm/test/CodeGen/RISCV/stack-realignment.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-ILP32E
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-LP64E
 
 declare void @callee(ptr)
 
+define void @caller16() {
+; RV32I-LABEL: caller16:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    .cfi_def_cfa_offset 16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    .cfi_offset ra, -4
+; RV32I-NEXT:    mv a0, sp
+; RV32I-NEXT:    call callee
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV32I-ILP32E-LABEL: caller16:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -16
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 16
+; RV32I-ILP32E-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 16
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -16
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -16
+; RV32I-ILP32E-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 16
+; RV32I-ILP32E-NEXT:    ret
+;
+; RV64I-LABEL: caller16:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    .cfi_offset ra, -8
+; RV64I-NEXT:    mv a0, sp
+; RV64I-NEXT:    call callee
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller16:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -32
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 32
+; RV64I-LP64E-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 32
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -16
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -32
+; RV64I-LP64E-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 32
+; RV64I-LP64E-NEXT:    ret
+  %1 = alloca i8, align 16
+  call void @callee(i8* %1)
+  ret void
+}
+
+define void @caller_no_realign16() "no-realign-stack" {
+; RV32I-LABEL: caller_no_realign16:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    .cfi_def_cfa_offset 16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    .cfi_offset ra, -4
+; RV32I-NEXT:    mv a0, sp
+; RV32I-NEXT:    call callee
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV32I-ILP32E-LABEL: caller_no_realign16:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
+; RV64I-LABEL: caller_no_realign16:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    .cfi_offset ra, -8
+; RV64I-NEXT:    mv a0, sp
+; RV64I-NEXT:    call callee
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign16:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
+  %1 = alloca i8, align 16
+  call void @callee(i8* %1)
+  ret void
+}
+
 define void @caller32() {
 ; RV32I-LABEL: caller32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    .cfi_offset s0, -8
 ; RV32I-NEXT:    addi s0, sp, 32
 ; RV32I-NEXT:    .cfi_def_cfa s0, 0
 ; RV32I-NEXT:    andi sp, sp, -32
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -32
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller32:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -32
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 32
+; RV32I-ILP32E-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 32
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -32
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -32
+; RV32I-ILP32E-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 32
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    .cfi_def_cfa_offset 32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 32
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -32
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -32
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller32:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -32
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 32
+; RV64I-LP64E-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 32
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -32
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -32
+; RV64I-LP64E-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 32
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 32
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign32() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign32:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign32:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 32
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller64() {
 ; RV32I-LABEL: caller64:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -64
 ; RV32I-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller64:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -64
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 64
+; RV32I-ILP32E-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 64
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -64
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -64
+; RV32I-ILP32E-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 64
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 64
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -64
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -64
 ; RV64I-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller64:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -64
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 64
+; RV64I-LP64E-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 64
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -64
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -64
+; RV64I-LP64E-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 64
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 64
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign64() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign64:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign64:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 64
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller128() {
 ; RV32I-LABEL: caller128:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -128
 ; RV32I-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 128
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller128:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -128
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 128
+; RV32I-ILP32E-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 128
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -128
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -128
+; RV32I-ILP32E-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 128
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller128:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -128
 ; RV64I-NEXT:    .cfi_def_cfa_offset 128
 ; RV64I-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 128
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -128
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -128
 ; RV64I-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 128
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller128:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -128
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 128
+; RV64I-LP64E-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 128
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -128
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -128
+; RV64I-LP64E-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 128
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 128
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign128() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign128:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign128:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign128:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign128:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 128
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller256() {
 ; RV32I-LABEL: caller256:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -256
 ; RV32I-NEXT:    lw ra, 252(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 248(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 256
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller256:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -256
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 256
+; RV32I-ILP32E-NEXT:    sw ra, 252(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 248(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 256
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -256
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -256
+; RV32I-ILP32E-NEXT:    lw ra, 252(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 248(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 256
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller256:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -256
 ; RV64I-NEXT:    .cfi_def_cfa_offset 256
 ; RV64I-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 256
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -256
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -256
 ; RV64I-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 256
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller256:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -256
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 256
+; RV64I-LP64E-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 256
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -256
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -256
+; RV64I-LP64E-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 256
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign256() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign256:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign256:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign256:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign256:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller512() {
 ; RV32I-LABEL: caller512:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    addi a0, sp, 512
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -1024
 ; RV32I-NEXT:    lw ra, 1020(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 1016(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 1024
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller512:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -1024
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 1024
+; RV32I-ILP32E-NEXT:    sw ra, 1020(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 1016(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 1024
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    andi sp, sp, -512
+; RV32I-ILP32E-NEXT:    addi a0, sp, 512
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -1024
+; RV32I-ILP32E-NEXT:    lw ra, 1020(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 1016(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 1024
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller512:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -1024
 ; RV64I-NEXT:    .cfi_def_cfa_offset 1024
 ; RV64I-NEXT:    sd ra, 1016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 1008(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 1024
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -512
 ; RV64I-NEXT:    addi a0, sp, 512
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -1024
 ; RV64I-NEXT:    ld ra, 1016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 1008(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 1024
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller512:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -1024
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 1024
+; RV64I-LP64E-NEXT:    sd ra, 1016(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 1008(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 1024
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    andi sp, sp, -512
+; RV64I-LP64E-NEXT:    addi a0, sp, 512
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -1024
+; RV64I-LP64E-NEXT:    ld ra, 1016(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 1008(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 1024
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign512() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign512:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign512:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign512:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign512:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller1024() {
 ; RV32I-LABEL: caller1024:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    addi sp, s0, -2048
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller1024:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 2044
+; RV32I-ILP32E-NEXT:    sw ra, 2040(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 2036(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    addi sp, sp, -4
+; RV32I-ILP32E-NEXT:    andi sp, sp, -1024
+; RV32I-ILP32E-NEXT:    addi a0, sp, 1024
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    addi sp, s0, -2048
+; RV32I-ILP32E-NEXT:    addi sp, sp, 4
+; RV32I-ILP32E-NEXT:    lw ra, 2040(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 2036(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 2044
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    .cfi_def_cfa_offset 2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 2032
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    andi sp, sp, -1024
 ; RV64I-NEXT:    addi a0, sp, 1024
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    addi sp, s0, -2048
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller1024:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 2040
+; RV64I-LP64E-NEXT:    sd ra, 2032(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 2024(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    addi sp, sp, -8
+; RV64I-LP64E-NEXT:    andi sp, sp, -1024
+; RV64I-LP64E-NEXT:    addi a0, sp, 1024
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    addi sp, s0, -2048
+; RV64I-LP64E-NEXT:    addi sp, sp, 8
+; RV64I-LP64E-NEXT:    ld ra, 2032(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 2024(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 2040
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign1024() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign1024:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign1024:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign1024:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller2048() {
 ; RV32I-LABEL: caller2048:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller2048:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 2044
+; RV32I-ILP32E-NEXT:    sw ra, 2040(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 2036(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    addi sp, sp, -2048
+; RV32I-ILP32E-NEXT:    addi sp, sp, -4
+; RV32I-ILP32E-NEXT:    andi sp, sp, -2048
+; RV32I-ILP32E-NEXT:    addi a0, sp, 2047
+; RV32I-ILP32E-NEXT:    addi a0, a0, 1
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lui a0, 1
+; RV32I-ILP32E-NEXT:    sub sp, s0, a0
+; RV32I-ILP32E-NEXT:    addi sp, sp, 2044
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    lw ra, 2040(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 2036(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 2044
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    .cfi_def_cfa_offset 2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    addi s0, sp, 2032
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    addi sp, sp, -2048
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    addi a0, sp, 2047
 ; RV64I-NEXT:    addi a0, a0, 1
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller2048:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 2040
+; RV64I-LP64E-NEXT:    sd ra, 2032(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 2024(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    addi sp, sp, -2048
+; RV64I-LP64E-NEXT:    addi sp, sp, -8
+; RV64I-LP64E-NEXT:    andi sp, sp, -2048
+; RV64I-LP64E-NEXT:    addi a0, sp, 2047
+; RV64I-LP64E-NEXT:    addi a0, a0, 1
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    lui a0, 1
+; RV64I-LP64E-NEXT:    sub sp, s0, a0
+; RV64I-LP64E-NEXT:    addi sp, sp, 2040
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ld ra, 2032(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 2024(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 2040
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign2048() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign2048:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign2048:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller4096() {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller4096:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 2044
+; RV32I-ILP32E-NEXT:    sw ra, 2040(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    sw s0, 2036(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    .cfi_offset s0, -8
+; RV32I-ILP32E-NEXT:    addi s0, sp, 2044
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa s0, 0
+; RV32I-ILP32E-NEXT:    lui a0, 2
+; RV32I-ILP32E-NEXT:    addi a0, a0, -2044
+; RV32I-ILP32E-NEXT:    sub sp, sp, a0
+; RV32I-ILP32E-NEXT:    srli a0, sp, 12
+; RV32I-ILP32E-NEXT:    slli sp, a0, 12
+; RV32I-ILP32E-NEXT:    lui a0, 1
+; RV32I-ILP32E-NEXT:    add a0, sp, a0
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lui a0, 2
+; RV32I-ILP32E-NEXT:    sub sp, s0, a0
+; RV32I-ILP32E-NEXT:    addi a0, a0, -2044
+; RV32I-ILP32E-NEXT:    add sp, sp, a0
+; RV32I-ILP32E-NEXT:    lw ra, 2040(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    lw s0, 2036(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 2044
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    .cfi_def_cfa_offset 2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16

 ; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller4096:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 2040
+; RV64I-LP64E-NEXT:    sd ra, 2032(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    sd s0, 2024(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    .cfi_offset s0, -16
+; RV64I-LP64E-NEXT:    addi s0, sp, 2040
+; RV64I-LP64E-NEXT:    .cfi_def_cfa s0, 0
+; RV64I-LP64E-NEXT:    lui a0, 2
+; RV64I-LP64E-NEXT:    addiw a0, a0, -2040
+; RV64I-LP64E-NEXT:    sub sp, sp, a0
+; RV64I-LP64E-NEXT:    srli a0, sp, 12
+; RV64I-LP64E-NEXT:    slli sp, a0, 12
+; RV64I-LP64E-NEXT:    lui a0, 1
+; RV64I-LP64E-NEXT:    add a0, sp, a0
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    lui a0, 2
+; RV64I-LP64E-NEXT:    sub sp, s0, a0
+; RV64I-LP64E-NEXT:    addiw a0, a0, -2040
+; RV64I-LP64E-NEXT:    add sp, sp, a0
+; RV64I-LP64E-NEXT:    ld ra, 2032(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    ld s0, 2024(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 2040
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(ptr %1)
   ret void
 }
 
 define void @caller_no_realign4096() "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32I-ILP32E-LABEL: caller_no_realign4096:
+; RV32I-ILP32E:       # %bb.0:
+; RV32I-ILP32E-NEXT:    addi sp, sp, -8
+; RV32I-ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; RV32I-ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT:    .cfi_offset ra, -4
+; RV32I-ILP32E-NEXT:    mv a0, sp
+; RV32I-ILP32E-NEXT:    call callee
+; RV32I-ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT:    addi sp, sp, 8
+; RV32I-ILP32E-NEXT:    ret
+;
 ; RV64I-LABEL: caller_no_realign4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV64I-LP64E-LABEL: caller_no_realign4096:
+; RV64I-LP64E:       # %bb.0:
+; RV64I-LP64E-NEXT:    addi sp, sp, -16
+; RV64I-LP64E-NEXT:    .cfi_def_cfa_offset 16
+; RV64I-LP64E-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT:    .cfi_offset ra, -8
+; RV64I-LP64E-NEXT:    mv a0, sp
+; RV64I-LP64E-NEXT:    call callee
+; RV64I-LP64E-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT:    addi sp, sp, 16
+; RV64I-LP64E-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(ptr %1)
   ret void
 }

llvm/test/CodeGen/RISCV/target-abi-valid.ll

 ; RUN: llc -mtriple=riscv32 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64e < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=CHECK-IMP %s
 
 define void @nothing() nounwind {
 ; CHECK-IMP-LABEL: nothing:
 ; CHECK-IMP:       # %bb.0:
 ; CHECK-IMP-NEXT:    ret
   ret void
 }
-
-; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=CHECK-UNIMP %s
-
-; CHECK-UNIMP: LLVM ERROR: Don't know how to lower this ABI

llvm/test/CodeGen/RISCV/vararg-ilp32e.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=ILP32E %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -frame-pointer=all -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=ILP32E-WITHFP %s
+
+declare void @llvm.va_start(i8*)
+declare void @llvm.va_end(i8*)
+declare void @abort()
+
+define i32 @caller(i32 %a) {
+; ILP32E-LABEL: caller:
+; ILP32E:       # %bb.0: # %entry
+; ILP32E-NEXT:    addi sp, sp, -8
+; ILP32E-NEXT:    .cfi_def_cfa_offset 8
+; ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    sw s0, 0(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    .cfi_offset ra, -4
+; ILP32E-NEXT:    .cfi_offset s0, -8
+; ILP32E-NEXT:    mv s0, a0
+; ILP32E-NEXT:    li a0, 1
+; ILP32E-NEXT:    lui a2, 262144
+; ILP32E-NEXT:    li a1, 0
+; ILP32E-NEXT:    call va_double
+; ILP32E-NEXT:    mv a0, s0
+; ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    lw s0, 0(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    addi sp, sp, 8
+; ILP32E-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: caller:
+; ILP32E-WITHFP:       # %bb.0: # %entry
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -12
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa_offset 12
+; ILP32E-WITHFP-NEXT:    sw ra, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s1, 0(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    .cfi_offset ra, -4
+; ILP32E-WITHFP-NEXT:    .cfi_offset s0, -8
+; ILP32E-WITHFP-NEXT:    .cfi_offset s1, -12
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 12
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa s0, 0
+; ILP32E-WITHFP-NEXT:    mv s1, a0
+; ILP32E-WITHFP-NEXT:    li a0, 1
+; ILP32E-WITHFP-NEXT:    lui a2, 262144
+; ILP32E-WITHFP-NEXT:    li a1, 0
+; ILP32E-WITHFP-NEXT:    call va_double
+; ILP32E-WITHFP-NEXT:    mv a0, s1
+; ILP32E-WITHFP-NEXT:    lw ra, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s1, 0(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 12
+; ILP32E-WITHFP-NEXT:    ret
+entry:
+  call void (i32, ...) @va_double(i32 1, double 2.000000e+00)
+  ret i32 %a
+}
+
+define void @va_double(i32 %n, ...) {
+; ILP32E-LABEL: va_double:
+; ILP32E:       # %bb.0: # %entry
+; ILP32E-NEXT:    addi sp, sp, -32
+; ILP32E-NEXT:    .cfi_def_cfa_offset 32
+; ILP32E-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; ILP32E-NEXT:    .cfi_offset ra, -28
+; ILP32E-NEXT:    sw a5, 28(sp)
+; ILP32E-NEXT:    sw a4, 24(sp)
+; ILP32E-NEXT:    sw a3, 20(sp)
+; ILP32E-NEXT:    sw a2, 16(sp)
+; ILP32E-NEXT:    sw a1, 12(sp)
+; ILP32E-NEXT:    addi a0, sp, 12
+; ILP32E-NEXT:    sw a0, 0(sp)
+; ILP32E-NEXT:    addi a0, sp, 19
+; ILP32E-NEXT:    andi a1, a0, -8
+; ILP32E-NEXT:    addi a0, a1, 8
+; ILP32E-NEXT:    sw a0, 0(sp)
+; ILP32E-NEXT:    lw a0, 0(a1)
+; ILP32E-NEXT:    lw a1, 4(a1)
+; ILP32E-NEXT:    lui a3, 262144
+; ILP32E-NEXT:    li a2, 0
+; ILP32E-NEXT:    call __eqdf2
+; ILP32E-NEXT:    bnez a0, .LBB1_2
+; ILP32E-NEXT:  # %bb.1: # %if.end
+; ILP32E-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; ILP32E-NEXT:    addi sp, sp, 32
+; ILP32E-NEXT:    ret
+; ILP32E-NEXT:  .LBB1_2: # %if.then
+; ILP32E-NEXT:    call abort
+;
+; ILP32E-WITHFP-LABEL: va_double:
+; ILP32E-WITHFP:       # %bb.0: # %entry
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -36
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa_offset 36
+; ILP32E-WITHFP-NEXT:    sw ra, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    .cfi_offset ra, -28
+; ILP32E-WITHFP-NEXT:    .cfi_offset s0, -32
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 12
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa s0, 24
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 4
+; ILP32E-WITHFP-NEXT:    sw a0, -12(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 11
+; ILP32E-WITHFP-NEXT:    andi a1, a0, -8
+; ILP32E-WITHFP-NEXT:    addi a0, a1, 8
+; ILP32E-WITHFP-NEXT:    sw a0, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a0, 0(a1)
+; ILP32E-WITHFP-NEXT:    lw a1, 4(a1)
+; ILP32E-WITHFP-NEXT:    lui a3, 262144
+; ILP32E-WITHFP-NEXT:    li a2, 0
+; ILP32E-WITHFP-NEXT:    call __eqdf2
+; ILP32E-WITHFP-NEXT:    bnez a0, .LBB1_2
+; ILP32E-WITHFP-NEXT:  # %bb.1: # %if.end
+; ILP32E-WITHFP-NEXT:    lw ra, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 36
+; ILP32E-WITHFP-NEXT:    ret
+; ILP32E-WITHFP-NEXT:  .LBB1_2: # %if.then
+; ILP32E-WITHFP-NEXT:    call abort
+entry:
+  %args = alloca i8*, align 4
+  %args1 = bitcast i8** %args to i8*
+  call void @llvm.va_start(i8* %args1)
+  %argp.cur = load i8*, i8** %args, align 4
+  %0 = ptrtoint i8* %argp.cur to i32
+  %1 = add i32 %0, 7
+  %2 = and i32 %1, -8
+  %argp.cur.aligned = inttoptr i32 %2 to i8*
+  %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
+  store i8* %argp.next, i8** %args, align 4
+  %3 = bitcast i8* %argp.cur.aligned to double*
+  %4 = load double, double* %3, align 8
+  %cmp = fcmp une double %4, 2.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  call void @abort()
+  unreachable
+
+if.end:
+  %args2 = bitcast i8** %args to i8*
+  call void @llvm.va_end(i8* %args2)
+  ret void
+}

llvm/test/CodeGen/RISCV/vararg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \
 ; RUN:   | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \
 ; RUN:     -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
 ; RUN:     -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -target-abi ilp32e \
+; RUN:     -verify-machineinstrs \
+; RUN:   | FileCheck -check-prefix=ILP32E-FPELIM %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -target-abi ilp32e -frame-pointer=all \
+; RUN:     -verify-machineinstrs \
+; RUN:   | FileCheck -check-prefix=ILP32E-WITHFP %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64f \
 ; RUN:     -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \
 ; RUN:     -verify-machineinstrs \
 ; RUN:   | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all \
 ; RUN:   | FileCheck -check-prefix=LP64-LP64F-LP64D-WITHFP %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -target-abi lp64e \
+; RUN:     -verify-machineinstrs \
+; RUN:   | FileCheck -check-prefix=LP64E-FPELIM %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -target-abi lp64e -frame-pointer=all \
+; RUN:     -verify-machineinstrs \
+; RUN:   | FileCheck -check-prefix=LP64E-WITHFP %s
 
 ; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for
 ; lp64/lp64f/lp64d. Different CHECK lines are required for RV32D due to slight
 ; codegen differences due to the way the f64 load operations are lowered.
 ; The nounwind attribute is omitted for some of the tests, to check that CFI
 ; directives are correctly generated.
 
 declare void @llvm.va_start(ptr)

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 28(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a2, 24(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, sp, 24
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va1:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    .cfi_def_cfa_offset 32
+; ILP32E-FPELIM-NEXT:    mv a0, a1
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 16(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 12(sp)
+; ILP32E-FPELIM-NEXT:    addi a1, sp, 16
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va1:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -48
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa_offset 48
+; ILP32E-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    .cfi_offset ra, -28
+; ILP32E-WITHFP-NEXT:    .cfi_offset s0, -32
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 24
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa s0, 24
+; ILP32E-WITHFP-NEXT:    mv a0, a1
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a1, s0, 8
+; ILP32E-WITHFP-NEXT:    sw a1, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 48
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    .cfi_def_cfa_offset 80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a1, 24(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 72(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 64(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, sp, 28

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a5, 40(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a4, 32(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a3, 24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va1:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -64
+; LP64E-FPELIM-NEXT:    .cfi_def_cfa_offset 64
+; LP64E-FPELIM-NEXT:    sd a1, 24(sp)
+; LP64E-FPELIM-NEXT:    addi a0, sp, 28
+; LP64E-FPELIM-NEXT:    sd a0, 8(sp)
+; LP64E-FPELIM-NEXT:    lw a0, 24(sp)
+; LP64E-FPELIM-NEXT:    sd a5, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 32(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 64
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va1:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    .cfi_def_cfa_offset 80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    .cfi_offset ra, -56
+; LP64E-WITHFP-NEXT:    .cfi_offset s0, -64
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    .cfi_def_cfa s0, 48
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a0, s0, 12
+; LP64E-WITHFP-NEXT:    sd a0, -24(s0)
+; LP64E-WITHFP-NEXT:    lw a0, 8(s0)
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va, align 4
   %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
   store ptr %argp.next, ptr %va, align 4
   %1 = load i32, ptr %argp.cur, align 4
   call void @llvm.va_end(ptr %va)
   ret i32 %1

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 28(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a2, 24(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, sp, 24
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va1_va_arg:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    mv a0, a1
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 16(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 12(sp)
+; ILP32E-FPELIM-NEXT:    addi a1, sp, 16
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va1_va_arg:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -48
+; ILP32E-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 24
+; ILP32E-WITHFP-NEXT:    mv a0, a1
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a1, s0, 8
+; ILP32E-WITHFP-NEXT:    sw a1, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 48
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    mv a0, a1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 72(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 64(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 48(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va1_va_arg:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -64
+; LP64E-FPELIM-NEXT:    mv a0, a1
+; LP64E-FPELIM-NEXT:    sd a5, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 24(sp)
+; LP64E-FPELIM-NEXT:    addi a1, sp, 32
+; LP64E-FPELIM-NEXT:    sd a1, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 64
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va1_va_arg:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    mv a0, a1
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a1, s0, 16
+; LP64E-WITHFP-NEXT:    sd a1, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }
 
 ; Ensure the adjustment when restoring the stack pointer using the frame

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    mv a0, s1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, s0, -16
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va1_va_arg_alloca:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -40
+; ILP32E-FPELIM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    addi s0, sp, 16
+; ILP32E-FPELIM-NEXT:    mv s1, a1
+; ILP32E-FPELIM-NEXT:    sw a5, 20(s0)
+; ILP32E-FPELIM-NEXT:    sw a4, 16(s0)
+; ILP32E-FPELIM-NEXT:    sw a3, 12(s0)
+; ILP32E-FPELIM-NEXT:    sw a2, 8(s0)
+; ILP32E-FPELIM-NEXT:    sw a1, 4(s0)
+; ILP32E-FPELIM-NEXT:    addi a0, s0, 8
+; ILP32E-FPELIM-NEXT:    sw a0, -16(s0)
+; ILP32E-FPELIM-NEXT:    addi a0, a1, 3
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -4
+; ILP32E-FPELIM-NEXT:    sub a0, sp, a0
+; ILP32E-FPELIM-NEXT:    mv sp, a0
+; ILP32E-FPELIM-NEXT:    call notdead
+; ILP32E-FPELIM-NEXT:    mv a0, s1
+; ILP32E-FPELIM-NEXT:    addi sp, s0, -16
+; ILP32E-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 40
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va1_va_arg_alloca:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -40
+; ILP32E-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 16
+; ILP32E-WITHFP-NEXT:    mv s1, a1
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 8
+; ILP32E-WITHFP-NEXT:    sw a0, -16(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, a1, 3
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -4
+; ILP32E-WITHFP-NEXT:    sub a0, sp, a0
+; ILP32E-WITHFP-NEXT:    mv sp, a0
+; ILP32E-WITHFP-NEXT:    call notdead
+; ILP32E-WITHFP-NEXT:    mv a0, s1
+; ILP32E-WITHFP-NEXT:    addi sp, s0, -16
+; ILP32E-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 40
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg_alloca:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -96
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi s0, sp, 32
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    mv s1, a1

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call notdead
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    mv a0, s1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, s0, -32
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va1_va_arg_alloca:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -80
+; LP64E-FPELIM-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    addi s0, sp, 32
+; LP64E-FPELIM-NEXT:    mv s1, a1
+; LP64E-FPELIM-NEXT:    sd a5, 40(s0)
+; LP64E-FPELIM-NEXT:    sd a4, 32(s0)
+; LP64E-FPELIM-NEXT:    sd a3, 24(s0)
+; LP64E-FPELIM-NEXT:    sd a2, 16(s0)
+; LP64E-FPELIM-NEXT:    sd a1, 8(s0)
+; LP64E-FPELIM-NEXT:    addi a0, s0, 16
+; LP64E-FPELIM-NEXT:    sd a0, -32(s0)
+; LP64E-FPELIM-NEXT:    slli a0, a1, 32
+; LP64E-FPELIM-NEXT:    srli a0, a0, 32
+; LP64E-FPELIM-NEXT:    addi a0, a0, 7
+; LP64E-FPELIM-NEXT:    andi a0, a0, -8
+; LP64E-FPELIM-NEXT:    sub a0, sp, a0
+; LP64E-FPELIM-NEXT:    mv sp, a0
+; LP64E-FPELIM-NEXT:    call notdead
+; LP64E-FPELIM-NEXT:    mv a0, s1
+; LP64E-FPELIM-NEXT:    addi sp, s0, -32
+; LP64E-FPELIM-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 80
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va1_va_arg_alloca:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    mv s1, a1
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a0, s0, 16
+; LP64E-WITHFP-NEXT:    sd a0, -32(s0)
+; LP64E-WITHFP-NEXT:    slli a0, a1, 32
+; LP64E-WITHFP-NEXT:    srli a0, a0, 32
+; LP64E-WITHFP-NEXT:    addi a0, a0, 7
+; LP64E-WITHFP-NEXT:    andi a0, a0, -8
+; LP64E-WITHFP-NEXT:    sub a0, sp, a0
+; LP64E-WITHFP-NEXT:    mv sp, a0
+; LP64E-WITHFP-NEXT:    call notdead
+; LP64E-WITHFP-NEXT:    mv a0, s1
+; LP64E-WITHFP-NEXT:    addi sp, s0, -32
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   %2 = alloca i8, i32 %1
   call void @notdead(ptr %2)
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a3, 261888
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a4, 2
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a2, 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    call va1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va1_caller:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -4
+; ILP32E-FPELIM-NEXT:    sw ra, 0(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    lui a2, 261888
+; ILP32E-FPELIM-NEXT:    li a3, 2
+; ILP32E-FPELIM-NEXT:    li a1, 0
+; ILP32E-FPELIM-NEXT:    call va1
+; ILP32E-FPELIM-NEXT:    lw ra, 0(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 4
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va1_caller:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -8
+; ILP32E-WITHFP-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 0(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 8
+; ILP32E-WITHFP-NEXT:    lui a2, 261888
+; ILP32E-WITHFP-NEXT:    li a3, 2
+; ILP32E-WITHFP-NEXT:    li a1, 0
+; ILP32E-WITHFP-NEXT:    call va1
+; ILP32E-WITHFP-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 0(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 8
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a1, 1023
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a1, a1, 52
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a2, 2
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    call va1

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a1, 1023
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a1, a1, 52
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a2, 2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call va1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va1_caller:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -8
+; LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    li a1, 1023
+; LP64E-FPELIM-NEXT:    slli a1, a1, 52
+; LP64E-FPELIM-NEXT:    li a2, 2
+; LP64E-FPELIM-NEXT:    call va1
+; LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 8
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va1_caller:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; LP64E-WITHFP-NEXT:    li a1, 1023
+; LP64E-WITHFP-NEXT:    slli a1, a1, 52
+; LP64E-WITHFP-NEXT:    li a2, 2
+; LP64E-WITHFP-NEXT:    call va1
+; LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; LP64E-WITHFP-NEXT:    ret
   %1 = call i32 (ptr, ...) @va1(ptr undef, double 1.0, i32 2)
   ret void
 }
 
 ; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
 ; register pair (where the first register is even-numbered).
 
 define i64 @va2(ptr %fmt, ...) nounwind {

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    andi a0, a0, -8
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, sp, 35
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a1, 4(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 0(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va2:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 16(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 12(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 12
+; ILP32E-FPELIM-NEXT:    sw a0, 4(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 19
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -8
+; ILP32E-FPELIM-NEXT:    addi a1, sp, 27
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a1, 4(a0)
+; ILP32E-FPELIM-NEXT:    lw a0, 0(a0)
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va2:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -48
+; ILP32E-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 24
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 4
+; ILP32E-WITHFP-NEXT:    sw a0, -12(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 11
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -8
+; ILP32E-WITHFP-NEXT:    addi a1, s0, 19
+; ILP32E-WITHFP-NEXT:    sw a1, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a1, 4(a0)
+; ILP32E-WITHFP-NEXT:    lw a0, 0(a0)
+; ILP32E-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 48
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va2:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    mv a0, a1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 72(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 64(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 48(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 23
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va2:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -64
+; LP64E-FPELIM-NEXT:    mv a0, a1
+; LP64E-FPELIM-NEXT:    sd a5, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 24(sp)
+; LP64E-FPELIM-NEXT:    addi a1, sp, 39
+; LP64E-FPELIM-NEXT:    sd a1, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 64
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va2:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    mv a0, a1
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a1, s0, 23
+; LP64E-WITHFP-NEXT:    sd a1, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va
   %ptrint = ptrtoint ptr %argp.cur to iXLen
   %1 = add iXLen %ptrint, 7
   %2 = and iXLen %1, -8
   %argp.cur.aligned = inttoptr iXLen %1 to ptr
   %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    fld fa5, 0(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    fsd fa5, 0(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 0(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a1, 4(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va2_va_arg:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 16(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 12(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 19
+; ILP32E-FPELIM-NEXT:    andi a1, a0, -8
+; ILP32E-FPELIM-NEXT:    addi a0, a1, 4
+; ILP32E-FPELIM-NEXT:    sw a0, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a0, 0(a1)
+; ILP32E-FPELIM-NEXT:    addi a2, a1, 8
+; ILP32E-FPELIM-NEXT:    sw a2, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a1, 4(a1)
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va2_va_arg:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -48
+; ILP32E-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 24
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 11
+; ILP32E-WITHFP-NEXT:    andi a1, a0, -8
+; ILP32E-WITHFP-NEXT:    addi a0, a1, 4
+; ILP32E-WITHFP-NEXT:    sw a0, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a0, 0(a1)
+; ILP32E-WITHFP-NEXT:    addi a2, a1, 8
+; ILP32E-WITHFP-NEXT:    sw a2, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a1, 4(a1)
+; ILP32E-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 48
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va2_va_arg:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    mv a0, a1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 72(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 64(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 48(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va2_va_arg:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -64
+; LP64E-FPELIM-NEXT:    mv a0, a1
+; LP64E-FPELIM-NEXT:    sd a5, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 24(sp)
+; LP64E-FPELIM-NEXT:    addi a1, sp, 32
+; LP64E-FPELIM-NEXT:    sd a1, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 64
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va2_va_arg:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    mv a0, a1
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a1, s0, 16
+; LP64E-WITHFP-NEXT:    sd a1, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, double
   call void @llvm.va_end(ptr %va)
   %2 = bitcast double %1 to i64
   ret i64 %2
 }
 

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a3, 261888
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a2, 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    call va2
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va2_caller:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -4
+; ILP32E-FPELIM-NEXT:    sw ra, 0(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    lui a2, 261888
+; ILP32E-FPELIM-NEXT:    li a1, 0
+; ILP32E-FPELIM-NEXT:    call va2
+; ILP32E-FPELIM-NEXT:    lw ra, 0(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 4
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va2_caller:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -8
+; ILP32E-WITHFP-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 0(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 8
+; ILP32E-WITHFP-NEXT:    lui a2, 261888
+; ILP32E-WITHFP-NEXT:    li a1, 0
+; ILP32E-WITHFP-NEXT:    call va2
+; ILP32E-WITHFP-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 0(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 8
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a1, 1023
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a1, a1, 52
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    call va2
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-WITHFP-LABEL: va2_caller:
 ; LP64-LP64F-LP64D-WITHFP:       # %bb.0:
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, -16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi s0, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a1, 1023
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a1, a1, 52
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call va2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va2_caller:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -8
+; LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    li a1, 1023
+; LP64E-FPELIM-NEXT:    slli a1, a1, 52
+; LP64E-FPELIM-NEXT:    call va2
+; LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 8
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va2_caller:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; LP64E-WITHFP-NEXT:    li a1, 1023
+; LP64E-WITHFP-NEXT:    slli a1, a1, 52
+; LP64E-WITHFP-NEXT:    call va2
+; LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; LP64E-WITHFP-NEXT:    ret
  %1 = call i64 (ptr, ...) @va2(ptr undef, double 1.000000e+00)
  ret void
 }
 
 ; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
 ; vararg double is passed in a4 and a5 (rather than a3 and a4)
 
 define i64 @va3(i32 %a, i64 %b, ...) nounwind {

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 0(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a2, a2, a3
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sltu a1, a0, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a2, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va3:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 20
+; ILP32E-FPELIM-NEXT:    sw a0, 12(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 27
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -8
+; ILP32E-FPELIM-NEXT:    addi a3, sp, 35
+; ILP32E-FPELIM-NEXT:    sw a3, 12(sp)
+; ILP32E-FPELIM-NEXT:    lw a3, 4(a0)
+; ILP32E-FPELIM-NEXT:    lw a0, 0(a0)
+; ILP32E-FPELIM-NEXT:    add a2, a2, a3
+; ILP32E-FPELIM-NEXT:    add a0, a1, a0
+; ILP32E-FPELIM-NEXT:    sltu a1, a0, a1
+; ILP32E-FPELIM-NEXT:    add a1, a2, a1
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va3:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -32
+; ILP32E-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 16
+; ILP32E-WITHFP-NEXT:    sw a5, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 4
+; ILP32E-WITHFP-NEXT:    sw a0, -12(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 11
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -8
+; ILP32E-WITHFP-NEXT:    addi a3, s0, 19
+; ILP32E-WITHFP-NEXT:    sw a3, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a3, 4(a0)
+; ILP32E-WITHFP-NEXT:    lw a0, 0(a0)
+; ILP32E-WITHFP-NEXT:    add a2, a2, a3
+; ILP32E-WITHFP-NEXT:    add a0, a1, a0
+; ILP32E-WITHFP-NEXT:    sltu a1, a0, a1
+; ILP32E-WITHFP-NEXT:    add a1, a2, a1
+; ILP32E-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 32
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va3:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -64
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 48(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 40(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 32(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a3, 24(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a3, s0, 15
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a0, a1, a2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a3, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 80
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va3:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -48
+; LP64E-FPELIM-NEXT:    sd a5, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 24(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 16(sp)
+; LP64E-FPELIM-NEXT:    addi a3, sp, 31
+; LP64E-FPELIM-NEXT:    add a0, a1, a2
+; LP64E-FPELIM-NEXT:    sd a3, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 48
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va3:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -64
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    sd a5, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 8(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 0(s0)
+; LP64E-WITHFP-NEXT:    addi a3, s0, 15
+; LP64E-WITHFP-NEXT:    add a0, a1, a2
+; LP64E-WITHFP-NEXT:    sd a3, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 64
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va
   %ptrint = ptrtoint ptr %argp.cur to iXLen
   %1 = add iXLen %ptrint, 7
   %2 = and iXLen %1, -8
   %argp.cur.aligned = inttoptr iXLen %1 to ptr
   %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a3, 8(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a2, a2, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a3
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sltu a1, a0, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a2, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va3_va_arg:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 27
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -8
+; ILP32E-FPELIM-NEXT:    addi a3, a0, 4
+; ILP32E-FPELIM-NEXT:    sw a3, 12(sp)
+; ILP32E-FPELIM-NEXT:    lw a3, 0(a0)
+; ILP32E-FPELIM-NEXT:    addi a4, a0, 8
+; ILP32E-FPELIM-NEXT:    sw a4, 12(sp)
+; ILP32E-FPELIM-NEXT:    lw a4, 4(a0)
+; ILP32E-FPELIM-NEXT:    add a0, a1, a3
+; ILP32E-FPELIM-NEXT:    sltu a1, a0, a1
+; ILP32E-FPELIM-NEXT:    add a2, a2, a4
+; ILP32E-FPELIM-NEXT:    add a1, a2, a1
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va3_va_arg:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -32
+; ILP32E-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 16
+; ILP32E-WITHFP-NEXT:    sw a5, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 11
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -8
+; ILP32E-WITHFP-NEXT:    addi a3, a0, 4
+; ILP32E-WITHFP-NEXT:    sw a3, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a3, 0(a0)
+; ILP32E-WITHFP-NEXT:    addi a4, a0, 8
+; ILP32E-WITHFP-NEXT:    sw a4, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw a4, 4(a0)
+; ILP32E-WITHFP-NEXT:    add a0, a1, a3
+; ILP32E-WITHFP-NEXT:    sltu a1, a0, a1
+; ILP32E-WITHFP-NEXT:    add a2, a2, a4
+; ILP32E-WITHFP-NEXT:    add a1, a2, a1
+; ILP32E-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 32
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_va_arg:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -64
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 48(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 40(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 32(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a3, 24(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a3, s0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a0, a1, a2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a3, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 80
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va3_va_arg:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -48
+; LP64E-FPELIM-NEXT:    sd a5, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 24(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 16(sp)
+; LP64E-FPELIM-NEXT:    addi a3, sp, 24
+; LP64E-FPELIM-NEXT:    add a0, a1, a2
+; LP64E-FPELIM-NEXT:    sd a3, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 48
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va3_va_arg:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -64
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    sd a5, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 8(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 0(s0)
+; LP64E-WITHFP-NEXT:    addi a3, s0, 8
+; LP64E-WITHFP-NEXT:    add a0, a1, a2
+; LP64E-WITHFP-NEXT:    sd a3, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 64
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, double
   call void @llvm.va_end(ptr %va)
   %2 = bitcast double %1 to i64
   %3 = add i64 %b, %2
   ret i64 %3
 }

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a5, 262144
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a2, 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a4, 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    call va3
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va3_caller:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -4
+; ILP32E-FPELIM-NEXT:    sw ra, 0(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    li a0, 2
+; ILP32E-FPELIM-NEXT:    li a1, 1111
+; ILP32E-FPELIM-NEXT:    lui a4, 262144
+; ILP32E-FPELIM-NEXT:    li a2, 0
+; ILP32E-FPELIM-NEXT:    li a3, 0
+; ILP32E-FPELIM-NEXT:    call va3
+; ILP32E-FPELIM-NEXT:    lw ra, 0(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 4
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va3_caller:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -8
+; ILP32E-WITHFP-NEXT:    sw ra, 4(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 0(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 8
+; ILP32E-WITHFP-NEXT:    li a0, 2
+; ILP32E-WITHFP-NEXT:    li a1, 1111
+; ILP32E-WITHFP-NEXT:    lui a4, 262144
+; ILP32E-WITHFP-NEXT:    li a2, 0
+; ILP32E-WITHFP-NEXT:    li a3, 0
+; ILP32E-WITHFP-NEXT:    call va3
+; ILP32E-WITHFP-NEXT:    lw ra, 4(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 0(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 8
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a2, 1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a2, a2, 62
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a0, 2
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a1, 1111

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a2, a2, 62
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a0, 2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a1, 1111
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call va3
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va3_caller:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -8
+; LP64E-FPELIM-NEXT:    sd ra, 0(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    li a2, 1
+; LP64E-FPELIM-NEXT:    slli a2, a2, 62
+; LP64E-FPELIM-NEXT:    li a0, 2
+; LP64E-FPELIM-NEXT:    li a1, 1111
+; LP64E-FPELIM-NEXT:    call va3
+; LP64E-FPELIM-NEXT:    ld ra, 0(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 8
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va3_caller:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -16
+; LP64E-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 16
+; LP64E-WITHFP-NEXT:    li a2, 1
+; LP64E-WITHFP-NEXT:    slli a2, a2, 62
+; LP64E-WITHFP-NEXT:    li a0, 2
+; LP64E-WITHFP-NEXT:    li a1, 1111
+; LP64E-WITHFP-NEXT:    call va3
+; LP64E-WITHFP-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 16
+; LP64E-WITHFP-NEXT:    ret
  %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00)
  ret void
 }
 
 declare void @llvm.va_copy(ptr, ptr)
 
 define i32 @va4_va_copy(i32 %argno, ...) nounwind {
 ; ILP32-ILP32F-FPELIM-LABEL: va4_va_copy:

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a1, s0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a1, a2
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va4_va_copy:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -40
+; ILP32E-FPELIM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    mv s0, a1
+; ILP32E-FPELIM-NEXT:    sw a5, 36(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 32(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 20(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, sp, 24
+; ILP32E-FPELIM-NEXT:    sw a0, 4(sp)
+; ILP32E-FPELIM-NEXT:    sw a0, 0(sp)
+; ILP32E-FPELIM-NEXT:    call notdead
+; ILP32E-FPELIM-NEXT:    lw a0, 4(sp)
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 3
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -4
+; ILP32E-FPELIM-NEXT:    addi a1, a0, 4
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a1, 0(a0)
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 7
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -4
+; ILP32E-FPELIM-NEXT:    addi a2, a0, 4
+; ILP32E-FPELIM-NEXT:    sw a2, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a2, 0(a0)
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 7
+; ILP32E-FPELIM-NEXT:    andi a0, a0, -4
+; ILP32E-FPELIM-NEXT:    addi a3, a0, 4
+; ILP32E-FPELIM-NEXT:    sw a3, 4(sp)
+; ILP32E-FPELIM-NEXT:    lw a0, 0(a0)
+; ILP32E-FPELIM-NEXT:    add a1, a1, s0
+; ILP32E-FPELIM-NEXT:    add a1, a1, a2
+; ILP32E-FPELIM-NEXT:    add a0, a1, a0
+; ILP32E-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 40
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va4_va_copy:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -44
+; ILP32E-WITHFP-NEXT:    sw ra, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 20
+; ILP32E-WITHFP-NEXT:    mv s1, a1
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, s0, 8
+; ILP32E-WITHFP-NEXT:    sw a0, -16(s0)
+; ILP32E-WITHFP-NEXT:    sw a0, -20(s0)
+; ILP32E-WITHFP-NEXT:    call notdead
+; ILP32E-WITHFP-NEXT:    lw a0, -16(s0)
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 3
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -4
+; ILP32E-WITHFP-NEXT:    addi a1, a0, 4
+; ILP32E-WITHFP-NEXT:    sw a1, -16(s0)
+; ILP32E-WITHFP-NEXT:    lw a1, 0(a0)
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 7
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -4
+; ILP32E-WITHFP-NEXT:    addi a2, a0, 4
+; ILP32E-WITHFP-NEXT:    sw a2, -16(s0)
+; ILP32E-WITHFP-NEXT:    lw a2, 0(a0)
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 7
+; ILP32E-WITHFP-NEXT:    andi a0, a0, -4
+; ILP32E-WITHFP-NEXT:    addi a3, a0, 4
+; ILP32E-WITHFP-NEXT:    sw a3, -16(s0)
+; ILP32E-WITHFP-NEXT:    lw a0, 0(a0)
+; ILP32E-WITHFP-NEXT:    add a1, a1, s1
+; ILP32E-WITHFP-NEXT:    add a1, a1, a2
+; ILP32E-WITHFP-NEXT:    add a0, a1, a0
+; ILP32E-WITHFP-NEXT:    lw ra, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 44
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -96
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    mv s0, a1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 88(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 80(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a1, a1, s1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a1, a1, a2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a0, a1, a0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 112
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va4_va_copy:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -80
+; LP64E-FPELIM-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    mv s0, a1
+; LP64E-FPELIM-NEXT:    sd a5, 72(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 64(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 40(sp)
+; LP64E-FPELIM-NEXT:    addi a0, sp, 48
+; LP64E-FPELIM-NEXT:    sd a0, 8(sp)
+; LP64E-FPELIM-NEXT:    sd a0, 0(sp)
+; LP64E-FPELIM-NEXT:    call notdead
+; LP64E-FPELIM-NEXT:    ld a0, 8(sp)
+; LP64E-FPELIM-NEXT:    addi a0, a0, 3
+; LP64E-FPELIM-NEXT:    andi a0, a0, -4
+; LP64E-FPELIM-NEXT:    addi a1, a0, 8
+; LP64E-FPELIM-NEXT:    sd a1, 8(sp)
+; LP64E-FPELIM-NEXT:    ld a1, 0(a0)
+; LP64E-FPELIM-NEXT:    addi a0, a0, 11
+; LP64E-FPELIM-NEXT:    andi a0, a0, -4
+; LP64E-FPELIM-NEXT:    addi a2, a0, 8
+; LP64E-FPELIM-NEXT:    sd a2, 8(sp)
+; LP64E-FPELIM-NEXT:    ld a2, 0(a0)
+; LP64E-FPELIM-NEXT:    addi a0, a0, 11
+; LP64E-FPELIM-NEXT:    andi a0, a0, -4
+; LP64E-FPELIM-NEXT:    addi a3, a0, 8
+; LP64E-FPELIM-NEXT:    sd a3, 8(sp)
+; LP64E-FPELIM-NEXT:    ld a0, 0(a0)
+; LP64E-FPELIM-NEXT:    add a1, a1, s0
+; LP64E-FPELIM-NEXT:    add a1, a1, a2
+; LP64E-FPELIM-NEXT:    addw a0, a1, a0
+; LP64E-FPELIM-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 80
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va4_va_copy:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -88
+; LP64E-WITHFP-NEXT:    sd ra, 32(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s1, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 40
+; LP64E-WITHFP-NEXT:    mv s1, a1
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a0, s0, 16
+; LP64E-WITHFP-NEXT:    sd a0, -32(s0)
+; LP64E-WITHFP-NEXT:    sd a0, -40(s0)
+; LP64E-WITHFP-NEXT:    call notdead
+; LP64E-WITHFP-NEXT:    ld a0, -32(s0)
+; LP64E-WITHFP-NEXT:    addi a0, a0, 3
+; LP64E-WITHFP-NEXT:    andi a0, a0, -4
+; LP64E-WITHFP-NEXT:    addi a1, a0, 8
+; LP64E-WITHFP-NEXT:    sd a1, -32(s0)
+; LP64E-WITHFP-NEXT:    ld a1, 0(a0)
+; LP64E-WITHFP-NEXT:    addi a0, a0, 11
+; LP64E-WITHFP-NEXT:    andi a0, a0, -4
+; LP64E-WITHFP-NEXT:    addi a2, a0, 8
+; LP64E-WITHFP-NEXT:    sd a2, -32(s0)
+; LP64E-WITHFP-NEXT:    ld a2, 0(a0)
+; LP64E-WITHFP-NEXT:    addi a0, a0, 11
+; LP64E-WITHFP-NEXT:    andi a0, a0, -4
+; LP64E-WITHFP-NEXT:    addi a3, a0, 8
+; LP64E-WITHFP-NEXT:    sd a3, -32(s0)
+; LP64E-WITHFP-NEXT:    ld a0, 0(a0)
+; LP64E-WITHFP-NEXT:    add a1, a1, s1
+; LP64E-WITHFP-NEXT:    add a1, a1, a2
+; LP64E-WITHFP-NEXT:    addw a0, a1, a0
+; LP64E-WITHFP-NEXT:    ld ra, 32(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s1, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 88
+; LP64E-WITHFP-NEXT:    ret
   %vargs = alloca ptr
   %wargs = alloca ptr
   call void @llvm.va_start(ptr %vargs)
   %1 = va_arg ptr %vargs, i32
   call void @llvm.va_copy(ptr %wargs, ptr %vargs)
   %2 = load ptr, ptr %wargs, align 4
   call void @notdead(ptr %2)
   %3 = va_arg ptr %vargs, i32

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a4, 13
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    li a7, 4
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a5, 32(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    call va5_aligned_stack_callee
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 64
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va5_aligned_stack_caller:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -64
+; ILP32E-FPELIM-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
+; ILP32E-FPELIM-NEXT:    addi s0, sp, 64
+; ILP32E-FPELIM-NEXT:    andi sp, sp, -16
+; ILP32E-FPELIM-NEXT:    li a0, 17
+; ILP32E-FPELIM-NEXT:    sw a0, 24(sp)
+; ILP32E-FPELIM-NEXT:    li a0, 16
+; ILP32E-FPELIM-NEXT:    sw a0, 20(sp)
+; ILP32E-FPELIM-NEXT:    li a0, 15
+; ILP32E-FPELIM-NEXT:    sw a0, 16(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 262236
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 655
+; ILP32E-FPELIM-NEXT:    sw a0, 12(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 377487
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 1475
+; ILP32E-FPELIM-NEXT:    sw a0, 8(sp)
+; ILP32E-FPELIM-NEXT:    li a0, 14
+; ILP32E-FPELIM-NEXT:    sw a0, 4(sp)
+; ILP32E-FPELIM-NEXT:    li a0, 4
+; ILP32E-FPELIM-NEXT:    sw a0, 0(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 262153
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 491
+; ILP32E-FPELIM-NEXT:    sw a0, 44(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 545260
+; ILP32E-FPELIM-NEXT:    addi a0, a0, -1967
+; ILP32E-FPELIM-NEXT:    sw a0, 40(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 964690
+; ILP32E-FPELIM-NEXT:    addi a0, a0, -328
+; ILP32E-FPELIM-NEXT:    sw a0, 36(sp)
+; ILP32E-FPELIM-NEXT:    lui a0, 335544
+; ILP32E-FPELIM-NEXT:    addi a6, a0, 1311
+; ILP32E-FPELIM-NEXT:    lui a0, 688509
+; ILP32E-FPELIM-NEXT:    addi a5, a0, -2048
+; ILP32E-FPELIM-NEXT:    li a0, 1
+; ILP32E-FPELIM-NEXT:    li a1, 11
+; ILP32E-FPELIM-NEXT:    addi a2, sp, 32
+; ILP32E-FPELIM-NEXT:    li a3, 12
+; ILP32E-FPELIM-NEXT:    li a4, 13
+; ILP32E-FPELIM-NEXT:    sw a6, 32(sp)
+; ILP32E-FPELIM-NEXT:    call va5_aligned_stack_callee
+; ILP32E-FPELIM-NEXT:    addi sp, s0, -64
+; ILP32E-FPELIM-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 64
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va5_aligned_stack_caller:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -64
+; ILP32E-WITHFP-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 64
+; ILP32E-WITHFP-NEXT:    andi sp, sp, -16
+; ILP32E-WITHFP-NEXT:    li a0, 17
+; ILP32E-WITHFP-NEXT:    sw a0, 24(sp)
+; ILP32E-WITHFP-NEXT:    li a0, 16
+; ILP32E-WITHFP-NEXT:    sw a0, 20(sp)
+; ILP32E-WITHFP-NEXT:    li a0, 15
+; ILP32E-WITHFP-NEXT:    sw a0, 16(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 262236
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 655
+; ILP32E-WITHFP-NEXT:    sw a0, 12(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 377487
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 1475
+; ILP32E-WITHFP-NEXT:    sw a0, 8(sp)
+; ILP32E-WITHFP-NEXT:    li a0, 14
+; ILP32E-WITHFP-NEXT:    sw a0, 4(sp)
+; ILP32E-WITHFP-NEXT:    li a0, 4
+; ILP32E-WITHFP-NEXT:    sw a0, 0(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 262153
+; ILP32E-WITHFP-NEXT:    addi a0, a0, 491
+; ILP32E-WITHFP-NEXT:    sw a0, 44(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 545260
+; ILP32E-WITHFP-NEXT:    addi a0, a0, -1967
+; ILP32E-WITHFP-NEXT:    sw a0, 40(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 964690
+; ILP32E-WITHFP-NEXT:    addi a0, a0, -328
+; ILP32E-WITHFP-NEXT:    sw a0, 36(sp)
+; ILP32E-WITHFP-NEXT:    lui a0, 335544
+; ILP32E-WITHFP-NEXT:    addi a6, a0, 1311
+; ILP32E-WITHFP-NEXT:    lui a0, 688509
+; ILP32E-WITHFP-NEXT:    addi a5, a0, -2048
+; ILP32E-WITHFP-NEXT:    li a0, 1
+; ILP32E-WITHFP-NEXT:    li a1, 11
+; ILP32E-WITHFP-NEXT:    addi a2, sp, 32
+; ILP32E-WITHFP-NEXT:    li a3, 12
+; ILP32E-WITHFP-NEXT:    li a4, 13
+; ILP32E-WITHFP-NEXT:    sw a6, 32(sp)
+; ILP32E-WITHFP-NEXT:    call va5_aligned_stack_callee
+; ILP32E-WITHFP-NEXT:    addi sp, s0, -64
+; ILP32E-WITHFP-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 64
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -48
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a0, 17
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 24(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a0, 16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 16(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a5, 13
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a7, 14
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd t0, 0(sp)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call va5_aligned_stack_callee
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 48
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va5_aligned_stack_caller:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -56
+; LP64E-FPELIM-NEXT:    sd ra, 48(sp) # 8-byte Folded Spill
+; LP64E-FPELIM-NEXT:    li a0, 17
+; LP64E-FPELIM-NEXT:    sd a0, 40(sp)
+; LP64E-FPELIM-NEXT:    li a0, 16
+; LP64E-FPELIM-NEXT:    lui a1, %hi(.LCPI11_0)
+; LP64E-FPELIM-NEXT:    ld a1, %lo(.LCPI11_0)(a1)
+; LP64E-FPELIM-NEXT:    sd a0, 32(sp)
+; LP64E-FPELIM-NEXT:    li a0, 15
+; LP64E-FPELIM-NEXT:    sd a0, 24(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 16(sp)
+; LP64E-FPELIM-NEXT:    li a0, 14
+; LP64E-FPELIM-NEXT:    sd a0, 8(sp)
+; LP64E-FPELIM-NEXT:    lui a0, 2384
+; LP64E-FPELIM-NEXT:    addiw a0, a0, 761
+; LP64E-FPELIM-NEXT:    slli a6, a0, 11
+; LP64E-FPELIM-NEXT:    lui a0, %hi(.LCPI11_1)
+; LP64E-FPELIM-NEXT:    ld a2, %lo(.LCPI11_1)(a0)
+; LP64E-FPELIM-NEXT:    lui a0, %hi(.LCPI11_2)
+; LP64E-FPELIM-NEXT:    ld a3, %lo(.LCPI11_2)(a0)
+; LP64E-FPELIM-NEXT:    li a0, 1
+; LP64E-FPELIM-NEXT:    li a1, 11
+; LP64E-FPELIM-NEXT:    li a4, 12
+; LP64E-FPELIM-NEXT:    li a5, 13
+; LP64E-FPELIM-NEXT:    sd a6, 0(sp)
+; LP64E-FPELIM-NEXT:    call va5_aligned_stack_callee
+; LP64E-FPELIM-NEXT:    ld ra, 48(sp) # 8-byte Folded Reload
+; LP64E-FPELIM-NEXT:    addi sp, sp, 56
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va5_aligned_stack_caller:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -64
+; LP64E-WITHFP-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 64
+; LP64E-WITHFP-NEXT:    li a0, 17
+; LP64E-WITHFP-NEXT:    sd a0, 40(sp)
+; LP64E-WITHFP-NEXT:    li a0, 16
+; LP64E-WITHFP-NEXT:    lui a1, %hi(.LCPI11_0)
+; LP64E-WITHFP-NEXT:    ld a1, %lo(.LCPI11_0)(a1)
+; LP64E-WITHFP-NEXT:    sd a0, 32(sp)
+; LP64E-WITHFP-NEXT:    li a0, 15
+; LP64E-WITHFP-NEXT:    sd a0, 24(sp)
+; LP64E-WITHFP-NEXT:    sd a1, 16(sp)
+; LP64E-WITHFP-NEXT:    li a0, 14
+; LP64E-WITHFP-NEXT:    sd a0, 8(sp)
+; LP64E-WITHFP-NEXT:    lui a0, 2384
+; LP64E-WITHFP-NEXT:    addiw a0, a0, 761
+; LP64E-WITHFP-NEXT:    slli a6, a0, 11
+; LP64E-WITHFP-NEXT:    lui a0, %hi(.LCPI11_1)
+; LP64E-WITHFP-NEXT:    ld a2, %lo(.LCPI11_1)(a0)
+; LP64E-WITHFP-NEXT:    lui a0, %hi(.LCPI11_2)
+; LP64E-WITHFP-NEXT:    ld a3, %lo(.LCPI11_2)(a0)
+; LP64E-WITHFP-NEXT:    li a0, 1
+; LP64E-WITHFP-NEXT:    li a1, 11
+; LP64E-WITHFP-NEXT:    li a4, 12
+; LP64E-WITHFP-NEXT:    li a5, 13
+; LP64E-WITHFP-NEXT:    sd a6, 0(sp)
+; LP64E-WITHFP-NEXT:    call va5_aligned_stack_callee
+; LP64E-WITHFP-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 64
+; LP64E-WITHFP-NEXT:    ret
   %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
     i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
   ret void
 }
 
 ; A function with no fixed arguments is not valid C, but can be
 ; specified in LLVM IR. We must ensure the vararg save area is

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a2, 24(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 16(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, sp, 20
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va6_no_fixed_args:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32E-FPELIM-NEXT:    sw a5, 28(sp)
+; ILP32E-FPELIM-NEXT:    sw a4, 24(sp)
+; ILP32E-FPELIM-NEXT:    sw a3, 20(sp)
+; ILP32E-FPELIM-NEXT:    sw a2, 16(sp)
+; ILP32E-FPELIM-NEXT:    sw a1, 12(sp)
+; ILP32E-FPELIM-NEXT:    sw a0, 8(sp)
+; ILP32E-FPELIM-NEXT:    addi a1, sp, 12
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    addi sp, sp, 32
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va6_no_fixed_args:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -48
+; ILP32E-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 24
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    sw a0, 0(s0)
+; ILP32E-WITHFP-NEXT:    addi a1, s0, 4
+; ILP32E-WITHFP-NEXT:    sw a1, -12(s0)
+; ILP32E-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 48
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va6_no_fixed_args:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -80
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 72(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a6, 64(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a5, 56(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a4, 48(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a3, 40(sp)

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va6_no_fixed_args:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    addi sp, sp, -64
+; LP64E-FPELIM-NEXT:    sd a5, 56(sp)
+; LP64E-FPELIM-NEXT:    sd a4, 48(sp)
+; LP64E-FPELIM-NEXT:    sd a3, 40(sp)
+; LP64E-FPELIM-NEXT:    sd a2, 32(sp)
+; LP64E-FPELIM-NEXT:    sd a1, 24(sp)
+; LP64E-FPELIM-NEXT:    sd a0, 16(sp)
+; LP64E-FPELIM-NEXT:    addi a1, sp, 24
+; LP64E-FPELIM-NEXT:    sd a1, 8(sp)
+; LP64E-FPELIM-NEXT:    addi sp, sp, 64
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va6_no_fixed_args:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -80
+; LP64E-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    addi s0, sp, 32
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    sd a0, 0(s0)
+; LP64E-WITHFP-NEXT:    addi a1, s0, 8
+; LP64E-WITHFP-NEXT:    sd a1, -24(s0)
+; LP64E-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 80
+; LP64E-WITHFP-NEXT:    ret
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }
 
 ; TODO: improve constant materialization of stack addresses

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, a1, 280
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, sp, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a1, 24414
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, a1, 304
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add sp, sp, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
+; ILP32E-FPELIM-LABEL: va_large_stack:
+; ILP32E-FPELIM:       # %bb.0:
+; ILP32E-FPELIM-NEXT:    lui a0, 24414
+; ILP32E-FPELIM-NEXT:    addi a0, a0, 288
+; ILP32E-FPELIM-NEXT:    sub sp, sp, a0
+; ILP32E-FPELIM-NEXT:    .cfi_def_cfa_offset 100000032
+; ILP32E-FPELIM-NEXT:    mv a0, a1
+; ILP32E-FPELIM-NEXT:    lui a6, 24414
+; ILP32E-FPELIM-NEXT:    add a6, sp, a6
+; ILP32E-FPELIM-NEXT:    sw a5, 284(a6)
+; ILP32E-FPELIM-NEXT:    lui a5, 24414
+; ILP32E-FPELIM-NEXT:    add a5, sp, a5
+; ILP32E-FPELIM-NEXT:    sw a4, 280(a5)
+; ILP32E-FPELIM-NEXT:    lui a4, 24414
+; ILP32E-FPELIM-NEXT:    add a4, sp, a4
+; ILP32E-FPELIM-NEXT:    sw a3, 276(a4)
+; ILP32E-FPELIM-NEXT:    lui a3, 24414
+; ILP32E-FPELIM-NEXT:    add a3, sp, a3
+; ILP32E-FPELIM-NEXT:    sw a2, 272(a3)
+; ILP32E-FPELIM-NEXT:    lui a2, 24414
+; ILP32E-FPELIM-NEXT:    add a2, sp, a2
+; ILP32E-FPELIM-NEXT:    sw a1, 268(a2)
+; ILP32E-FPELIM-NEXT:    lui a1, 24414
+; ILP32E-FPELIM-NEXT:    addi a1, a1, 272
+; ILP32E-FPELIM-NEXT:    add a1, sp, a1
+; ILP32E-FPELIM-NEXT:    sw a1, 4(sp)
+; ILP32E-FPELIM-NEXT:    lui a1, 24414
+; ILP32E-FPELIM-NEXT:    addi a1, a1, 288
+; ILP32E-FPELIM-NEXT:    add sp, sp, a1
+; ILP32E-FPELIM-NEXT:    ret
+;
+; ILP32E-WITHFP-LABEL: va_large_stack:
+; ILP32E-WITHFP:       # %bb.0:
+; ILP32E-WITHFP-NEXT:    addi sp, sp, -2044
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa_offset 2044
+; ILP32E-WITHFP-NEXT:    sw ra, 2016(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    sw s0, 2012(sp) # 4-byte Folded Spill
+; ILP32E-WITHFP-NEXT:    .cfi_offset ra, -28
+; ILP32E-WITHFP-NEXT:    .cfi_offset s0, -32
+; ILP32E-WITHFP-NEXT:    addi s0, sp, 2020
+; ILP32E-WITHFP-NEXT:    .cfi_def_cfa s0, 24
+; ILP32E-WITHFP-NEXT:    lui a0, 24414
+; ILP32E-WITHFP-NEXT:    addi a0, a0, -1740
+; ILP32E-WITHFP-NEXT:    sub sp, sp, a0
+; ILP32E-WITHFP-NEXT:    mv a0, a1
+; ILP32E-WITHFP-NEXT:    sw a5, 20(s0)
+; ILP32E-WITHFP-NEXT:    sw a4, 16(s0)
+; ILP32E-WITHFP-NEXT:    sw a3, 12(s0)
+; ILP32E-WITHFP-NEXT:    sw a2, 8(s0)
+; ILP32E-WITHFP-NEXT:    sw a1, 4(s0)
+; ILP32E-WITHFP-NEXT:    addi a1, s0, 8
+; ILP32E-WITHFP-NEXT:    lui a2, 24414
+; ILP32E-WITHFP-NEXT:    sub a2, s0, a2
+; ILP32E-WITHFP-NEXT:    sw a1, -272(a2)
+; ILP32E-WITHFP-NEXT:    lui a1, 24414
+; ILP32E-WITHFP-NEXT:    addi a1, a1, -1740
+; ILP32E-WITHFP-NEXT:    add sp, sp, a1
+; ILP32E-WITHFP-NEXT:    lw ra, 2016(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    lw s0, 2012(sp) # 4-byte Folded Reload
+; ILP32E-WITHFP-NEXT:    addi sp, sp, 2044
+; ILP32E-WITHFP-NEXT:    ret
+;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 24414
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 336
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sub sp, sp, a0
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    .cfi_def_cfa_offset 100000080
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 24414
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    add a0, sp, a0

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a1, 24414
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a1, a1, -1680
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add sp, sp, a1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 1960(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 1952(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 2032
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
+;
+; LP64E-FPELIM-LABEL: va_large_stack:
+; LP64E-FPELIM:       # %bb.0:
+; LP64E-FPELIM-NEXT:    lui a0, 24414
+; LP64E-FPELIM-NEXT:    addiw a0, a0, 320
+; LP64E-FPELIM-NEXT:    sub sp, sp, a0
+; LP64E-FPELIM-NEXT:    .cfi_def_cfa_offset 100000064
+; LP64E-FPELIM-NEXT:    lui a0, 24414
+; LP64E-FPELIM-NEXT:    add a0, sp, a0
+; LP64E-FPELIM-NEXT:    sd a1, 280(a0)
+; LP64E-FPELIM-NEXT:    lui a0, 24414
+; LP64E-FPELIM-NEXT:    addiw a0, a0, 284
+; LP64E-FPELIM-NEXT:    add a0, sp, a0
+; LP64E-FPELIM-NEXT:    sd a0, 8(sp)
+; LP64E-FPELIM-NEXT:    lui a0, 24414
+; LP64E-FPELIM-NEXT:    add a0, sp, a0
+; LP64E-FPELIM-NEXT:    lw a0, 280(a0)
+; LP64E-FPELIM-NEXT:    lui a1, 24414
+; LP64E-FPELIM-NEXT:    add a1, sp, a1
+; LP64E-FPELIM-NEXT:    sd a5, 312(a1)
+; LP64E-FPELIM-NEXT:    lui a1, 24414
+; LP64E-FPELIM-NEXT:    add a1, sp, a1
+; LP64E-FPELIM-NEXT:    sd a4, 304(a1)
+; LP64E-FPELIM-NEXT:    lui a1, 24414
+; LP64E-FPELIM-NEXT:    add a1, sp, a1
+; LP64E-FPELIM-NEXT:    sd a3, 296(a1)
+; LP64E-FPELIM-NEXT:    lui a1, 24414
+; LP64E-FPELIM-NEXT:    add a1, sp, a1
+; LP64E-FPELIM-NEXT:    sd a2, 288(a1)
+; LP64E-FPELIM-NEXT:    lui a1, 24414
+; LP64E-FPELIM-NEXT:    addiw a1, a1, 320
+; LP64E-FPELIM-NEXT:    add sp, sp, a1
+; LP64E-FPELIM-NEXT:    ret
+;
+; LP64E-WITHFP-LABEL: va_large_stack:
+; LP64E-WITHFP:       # %bb.0:
+; LP64E-WITHFP-NEXT:    addi sp, sp, -2040
+; LP64E-WITHFP-NEXT:    .cfi_def_cfa_offset 2040
+; LP64E-WITHFP-NEXT:    sd ra, 1984(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    sd s0, 1976(sp) # 8-byte Folded Spill
+; LP64E-WITHFP-NEXT:    .cfi_offset ra, -56
+; LP64E-WITHFP-NEXT:    .cfi_offset s0, -64
+; LP64E-WITHFP-NEXT:    addi s0, sp, 1992
+; LP64E-WITHFP-NEXT:    .cfi_def_cfa s0, 48
+; LP64E-WITHFP-NEXT:    lui a0, 24414
+; LP64E-WITHFP-NEXT:    addiw a0, a0, -1704
+; LP64E-WITHFP-NEXT:    sub sp, sp, a0
+; LP64E-WITHFP-NEXT:    sd a1, 8(s0)
+; LP64E-WITHFP-NEXT:    addi a0, s0, 12
+; LP64E-WITHFP-NEXT:    lui a1, 24414
+; LP64E-WITHFP-NEXT:    sub a1, s0, a1
+; LP64E-WITHFP-NEXT:    sd a0, -288(a1)
+; LP64E-WITHFP-NEXT:    lw a0, 8(s0)
+; LP64E-WITHFP-NEXT:    sd a5, 40(s0)
+; LP64E-WITHFP-NEXT:    sd a4, 32(s0)
+; LP64E-WITHFP-NEXT:    sd a3, 24(s0)
+; LP64E-WITHFP-NEXT:    sd a2, 16(s0)
+; LP64E-WITHFP-NEXT:    lui a1, 24414
+; LP64E-WITHFP-NEXT:    addiw a1, a1, -1704
+; LP64E-WITHFP-NEXT:    add sp, sp, a1
+; LP64E-WITHFP-NEXT:    ld ra, 1984(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    ld s0, 1976(sp) # 8-byte Folded Reload
+; LP64E-WITHFP-NEXT:    addi sp, sp, 2040
+; LP64E-WITHFP-NEXT:    ret
   %large = alloca [ 100000000 x i8 ]
   %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va, align 4
   %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
   store ptr %argp.next, ptr %va, align 4
   %1 = load i32, ptr %argp.cur, align 4
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }

llvm/test/MC/RISCV/option-invalid.s

 .option arch, +f
 
 # CHECK: :[[#@LINE+1]]:13: error: expected newline
 .option rvc foo
 
 # CHECK: :[[#@LINE+1]]:12: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'arch', 'relax' or 'norelax'
 .option bar
 
-# CHECK: :[[#@LINE+1]]:16: error: unknown extension feature
-.option arch, -i
-
 # CHECK: :[[#@LINE+1]]:12: error: .option pop with no .option push
 .option pop
 
 # CHECK: :[[#@LINE+1]]:14: error: expected newline
 .option push 123
 
 # CHECK: :[[#@LINE+1]]:13: error: expected newline
 .option pop 123
 
 # CHECK: :[[#@LINE+1]]:15: error: bad arch string switching from rv32 to rv64
 .option arch, rv64gc

llvm/test/MC/RISCV/target-abi-invalid.s

 # RUN: llvm-mc -triple=riscv32 -mattr=+f -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32IF-LP64F %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32IFD-LP64D %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32E-LP64 %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EF-LP64F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
+# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EFD-LP64D %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32E-LP64E %s
 
 # RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32E-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32EF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32EFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32E-LP64E: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+# RV32EFD-LP64D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 
 # RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32I-ILP32F %s
 # RUN: llvm-mc -triple=riscv64 -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64I-LP64F %s
 
 # RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
 # RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)

 # RV32IF-ILP32D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
 # RV64I-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
 # RV64IF-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
 
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi ilp32 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EF-ILP32F %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi ilp32f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EF-ILP32F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32f < %s 2>&1 \
+# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EFD-ILP32F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
+# RUN: not --crash llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EFD-ILP32D %s
 
 # RV32E-ILP32: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EF-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EFD-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
+# RV32EFD-ILP32F: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 # RV32EFD-ILP32D: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
+# RV32EFD-ILP32D: LLVM ERROR: ILP32E cannot be used with the D ISA extension
 
 # RUN: llvm-mc -triple=riscv64 -mattr=+e -target-abi lp64 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64EF-LP64F %s
 # RUN: llvm-mc -triple=riscv64 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64EF-LP64F %s
 # RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64EFD-LP64F %s
 # RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64d < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64EFD-LP64D %s
 
 # RV64E-LP64: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
 # RV64EF-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
 # RV64EFD-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
 # RV64EFD-LP64D: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
 
 nop