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zixuan-wu (Zixuan Wu)
Alibaba T-HEAD LLVM Dev

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User Since
Aug 18 2020, 9:04 PM (135 w, 5 d)

Recent Activity

Mon, Mar 6

zixuan-wu added a comment to D140460: [RISCV][MC] Add FLI instruction support for the experimental zfa extension.

LGTM

Mon, Mar 6, 6:04 PM · Restricted Project, Restricted Project

Feb 21 2023

zixuan-wu added a comment to D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension.

With considering https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility I think we need make consensus to choose one option from following 2 options.

  1. Remove X86amx type in IR totally. (what I am doing now)
  2. Without removing X86amx type in IR, just upgrade the x86amx type to target extension and also upgrade bitcast llvm instruction to intrinsic(required). It also includes changing the testcase to target extension type.

I believe the right option is:

  1. Remove x86_amx type from the (in-memory) IR representation, but support an auto-upgrade for bitcode only.

We do need bitcode auto-upgrade support as a matter of policy, and we shouldn't support both type representation at the same time, that would defeat the point of the change.

I think target extension type is nice, if it is introduced 2 years ago I would vote for it. However my concern is the compatibility issue as I explained. We need to be compatible to the IR that built by previous compiler, and be compatible to the 3rd party software that based on the x86_amx type. I can't predict more risks for now if we replace an LLVM IR type, but I believe there is big risk hidden.

Due to bitcode auto-upgrade, compatibility with old IR is retained. As long as we avoid some of the API changes here, the impact on downstream code should be fairly minimal. (Though as already pointed out, downstream impact generally doesn't figure into LLVM design decisions anyway.)

Feb 21 2023, 6:54 PM · Restricted Project, Restricted Project, Restricted Project

Jan 18 2023

zixuan-wu accepted D141995: [CSKY] Fix errors caused by change of compressInst.
Jan 18 2023, 12:48 AM · Restricted Project, Restricted Project

Jan 17 2023

zixuan-wu added a comment to D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension.

With considering https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility I think we need make consensus to choose one option from following 2 options.

Jan 17 2023, 10:50 PM · Restricted Project, Restricted Project, Restricted Project
zixuan-wu updated the summary of D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension.
Jan 17 2023, 10:27 PM · Restricted Project, Restricted Project, Restricted Project
zixuan-wu added a comment to D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension.

@zixuan-wu, changing x86_amx would break our internal code. May I know the motivation to change the type?

Jan 17 2023, 10:04 PM · Restricted Project, Restricted Project, Restricted Project
zixuan-wu requested review of D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension.
Jan 17 2023, 12:13 AM · Restricted Project, Restricted Project, Restricted Project

Jan 15 2023

zixuan-wu added a comment to D139996: [RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic.

Gentle pin..

Jan 15 2023, 11:07 PM · Restricted Project, Restricted Project

Jan 11 2023

zixuan-wu added a comment to D135202: [IR] Add a target extension type to LLVM..

I'd like to enable the backend infra and propose draft later. To better demonstrate and enable backend target-independent code completely, I'd like to demonstrate with x86_amx that changing x86_amx type to target extension type and make all test passed, if nobody objects. @jcranmer-intel @LuoYuanke @craig.topper @pengfei

I have no objections to this; indeed, my original proposal for target extension types included x86_mmx and x86_amx as types that could be implemented as target extension types. However, I'm not involved with the x86 backend, so I must defer to the proper codeowners there as to whether or not to do this.

I think it's more appropriate to start with x86_fp80 and x86_mmx. I'd expect there will be a more general matrix representation for the AMX type, e.g., TLX, <8x8xi8> etc. rather than limit it to target extension type, though I'm not against to do prototype for it.

Aren't both x86_fp80 and x86_mmx recognized by InstCombine? They aren't truly opaque.

Jan 11 2023, 8:34 PM · Restricted Project, Restricted Project
zixuan-wu updated subscribers of D135202: [IR] Add a target extension type to LLVM..

I'd like to enable the backend infra and propose draft later. To better demonstrate and enable backend target-independent code completely, I'd like to demonstrate with x86_amx that changing x86_amx type to target extension type and make all test passed, if nobody objects. @jcranmer-intel @LuoYuanke @craig.topper @pengfei

I have no objections to this; indeed, my original proposal for target extension types included x86_mmx and x86_amx as types that could be implemented as target extension types. However, I'm not involved with the x86 backend, so I must defer to the proper codeowners there as to whether or not to do this.

I think it's more appropriate to start with x86_fp80 and x86_mmx. I'd expect there will be a more general matrix representation for the AMX type, e.g., TLX, <8x8xi8> etc. rather than limit it to target extension type, though I'm not against to do prototype for it.

Jan 11 2023, 8:15 PM · Restricted Project, Restricted Project

Jan 9 2023

zixuan-wu updated subscribers of D135202: [IR] Add a target extension type to LLVM..
Jan 9 2023, 11:16 PM · Restricted Project, Restricted Project
zixuan-wu updated subscribers of D135202: [IR] Add a target extension type to LLVM..
Jan 9 2023, 11:14 PM · Restricted Project, Restricted Project
zixuan-wu added a comment to D135202: [IR] Add a target extension type to LLVM..

I don't have an example backend that goes through GlobalISel or SelectionDAG yet; I've been focusing my effort on the production SPIR-V backend which translates to SPIR-V straight from LLVM IR.

There may need to be some additional work to map these types to appropriate MVT types in the codegen phases, but my knowledge of codegen infrastructure is somewhat shaky, and this is highly dependent on how different backends wish to translate these types.

Jan 9 2023, 11:07 PM · Restricted Project, Restricted Project
zixuan-wu added inline comments to D135202: [IR] Add a target extension type to LLVM..
Jan 9 2023, 10:59 PM · Restricted Project, Restricted Project

Jan 3 2023

zixuan-wu added a comment to D135202: [IR] Add a target extension type to LLVM..

hi, @jcranmer-intel , could you please propose a backend demo revision to demonstrate how to use targetext type of backend?

Jan 3 2023, 12:20 AM · Restricted Project, Restricted Project

Dec 30 2022

zixuan-wu added inline comments to D135202: [IR] Add a target extension type to LLVM..
Dec 30 2022, 1:49 AM · Restricted Project, Restricted Project

Dec 28 2022

zixuan-wu added inline comments to D137838: [Support] Move TargetParsers to new component.
Dec 28 2022, 12:07 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project

Dec 20 2022

zixuan-wu accepted D140364: [llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets.
Dec 20 2022, 8:00 PM · Restricted Project, Restricted Project
zixuan-wu edited reviewers for D140364: [llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets, added: zixuan-wu; removed: Zeson.
Dec 20 2022, 8:00 PM · Restricted Project, Restricted Project
zixuan-wu committed rG05f343fa8afe: [CSKY] Fix compiling error due to the interface change (authored by zixuan-wu).
[CSKY] Fix compiling error due to the interface change
Dec 20 2022, 7:59 PM · Restricted Project, Restricted Project

Dec 15 2022

zixuan-wu added a comment to D139996: [RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic.

(If the register is marked reserved with -ffixed-xN then you won't get the save/restore code here)

Dec 15 2022, 9:53 PM · Restricted Project, Restricted Project
zixuan-wu edited reviewers for D139996: [RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic, added: reames, craig.topper, kito-cheng, jrtc27; removed: lenary.
Dec 15 2022, 6:13 PM · Restricted Project, Restricted Project

Dec 13 2022

zixuan-wu requested review of D139996: [RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic.
Dec 13 2022, 11:19 PM · Restricted Project, Restricted Project

Dec 11 2022

zixuan-wu committed rG62c4dce5b4b9: [CSKY][NFC] Fix check-all error due to change of expected output (authored by zixuan-wu).
[CSKY][NFC] Fix check-all error due to change of expected output
Dec 11 2022, 7:32 PM · Restricted Project, Restricted Project

Nov 27 2022

zixuan-wu committed rGe52a41d0a2c1: [CSKY][NFC] Fix the compiling error of CSKYAsmPrinter.cpp (authored by zixuan-wu).
[CSKY][NFC] Fix the compiling error of CSKYAsmPrinter.cpp
Nov 27 2022, 9:49 PM · Restricted Project, Restricted Project

Nov 22 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

Ping.. Do we still prefer to specify target triple explicitly to make a check?

Nov 22 2022, 7:08 PM · Restricted Project, Restricted Project

Nov 20 2022

zixuan-wu committed rGf4d61cdf9cc3: [CSKY] Lower ISD::ConstantPool node to support getting the address of… (authored by zixuan-wu).
[CSKY] Lower ISD::ConstantPool node to support getting the address of…
Nov 20 2022, 6:42 PM · Restricted Project, Restricted Project

Nov 1 2022

zixuan-wu committed rG76fc5fe64a23: [CSKY] Fix the adjustFixupValue of fixup_csky_pcrel_uimm7_scale4 (authored by zixuan-wu).
[CSKY] Fix the adjustFixupValue of fixup_csky_pcrel_uimm7_scale4
Nov 1 2022, 11:19 PM · Restricted Project, Restricted Project
zixuan-wu committed rG9fbe16ee18a3: [CSKY] Fix .bss directive compling error created by --save-temps (authored by zixuan-wu).
[CSKY] Fix .bss directive compling error created by --save-temps
Nov 1 2022, 11:19 PM · Restricted Project, Restricted Project

Oct 19 2022

zixuan-wu committed rG55c2137939d8: [testcase][OpenMP] Fix the testcase error of check-all when… (authored by zixuan-wu).
[testcase][OpenMP] Fix the testcase error of check-all when…
Oct 19 2022, 7:20 PM · Restricted Project, Restricted Project
zixuan-wu closed D136239: [testcase] [OpenMP] Fix the testcase error of check-all when DCLANG_DEFAULT_OPENMP_RUNTIME is not libomp.
Oct 19 2022, 7:19 PM · Restricted Project, Restricted Project
zixuan-wu requested review of D136239: [testcase] [OpenMP] Fix the testcase error of check-all when DCLANG_DEFAULT_OPENMP_RUNTIME is not libomp.
Oct 19 2022, 3:15 AM · Restricted Project, Restricted Project

Oct 17 2022

zixuan-wu added inline comments to D70401: [RISCV] Complete RV32E/ilp32e implementation.
Oct 17 2022, 4:14 AM · Restricted Project, Restricted Project, Restricted Project

Oct 13 2022

zixuan-wu added a comment to D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string.

I'm seeing a regression on 401.bzip2 and possibly 471.astar. And I'm not seeing large improvements on 471.omnetpp or 483.xalancbmk.

Oct 13 2022, 10:50 PM · Restricted Project, Restricted Project, Restricted Project

Oct 10 2022

zixuan-wu added inline comments to D70401: [RISCV] Complete RV32E/ilp32e implementation.
Oct 10 2022, 2:22 AM · Restricted Project, Restricted Project, Restricted Project

Oct 7 2022

zixuan-wu added a comment to D134454: [Driver][Distro] Fix ArchLinux sysroot detection.

It's fine for CSKY to use config file. I only have 2 points.

Oct 7 2022, 9:19 PM · Restricted Project, Restricted Project
zixuan-wu added a comment to D121445: [Clang][CSKY] Add the CSKY target and compiler driver.

mips computed sysroot from GCCInstallation very early in 2013 rG08450bd55ccdc4aee4f5f73cde97e25b3c4ce5b9 and Android followed up in 2018 (D45291), but I am not sure this is the correct direction.
They are to support very special distributions. Hard coding the file hierarchy for every Linux distribution just does not scale.
I raised my concern on https://reviews.llvm.org/D134454#3824630 as well.

With https://reviews.llvm.org/D134337 (default configuration file) we should move the logic to use a default configuration file instead.

Oct 7 2022, 9:18 PM · Restricted Project, Restricted Project, Restricted Project

Sep 18 2022

zixuan-wu committed rGa42053a1fa81: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result (authored by zixuan-wu).
[llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result
Sep 18 2022, 11:24 PM · Restricted Project, Restricted Project
zixuan-wu closed D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.
Sep 18 2022, 11:23 PM · Restricted Project, Restricted Project

Sep 15 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

AFAIK, --target is clang-specific and transparent for compiler user in RV side. -m is also undefined or less used by RV user. It just uses -march to specify 32 or 64 mode and extensions.
Is the convention specified in RV Spec?

Sep 15 2022, 8:36 PM · Restricted Project, Restricted Project

Sep 14 2022

zixuan-wu added a comment to D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.

The chage looks good. However, the test must be improved.

Your test only checks the content of the write latency table. However, that is not enough to prove that this bug is fixed; you also need to show that the read advance entry for Read_D is associated with Write_B.

I suggest to modify the InstRW for Inst_C as follows:

def : InstRW<[Write_C, Read_D], (instrs Inst_C)>;

That way, Read_D will be associated to the first read operand of Inst_C.

Since Read_D is now explicitly used, a new MCReadAvanceEntry is added to table MyTargetReadAdvanceTable (see entry #1 below).

// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry MyTargetReadAdvanceTable[] = {
  {0,  0,  0}, // Invalid
  {0,  2,  1} // #1
}; // MyTargetReadAdvanceTable

In your test, you need to CHECK the presence of that {0, 2, 1} entry. That's the only way to know that there is a (at least one) SchedRead associated to Write_B (WriteResourceID = 2).
You should also check that Inst_C now uses that ReadAdvance. That's how we know that Read_D is effectively associated with Write_B.

In the .inc output, you should be able to check the last line of the table below:

// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
static const llvm::MCSchedClassDesc SchedModel_ASchedClasses[] = {
  {DBGFIELD("InvalidSchedClass")  8191, false, false, false, 0, 0,  0, 0,  0, 0},
  {DBGFIELD("Inst_A")             1, false, false, false,  0, 0,  1, 1,  0, 0}, // #1
  {DBGFIELD("Inst_B")             1, false, false, false,  0, 0,  1, 1,  0, 0}, // #2
  {DBGFIELD("Inst_C")             1, false, false, false,  0, 0,  1, 1,  1, 1}, // #3
}; // SchedModel_ASchedClasses

Based on that last descriptor, Inst_C declares a single read-advance entry (i.e. entry #1 in MyTargetReadAdvanceTable).
Entry #1 in MyTargetReadAdvanceTable declares a 1cy of read advance when associated with Write_B.

In conclusion, for completeness, you need to check also tables MyTargetReadAdvanceTable and SchedModel_ASchedClasses.

I hope it helps.

Sep 14 2022, 12:54 AM · Restricted Project, Restricted Project
zixuan-wu updated the diff for D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.
Sep 14 2022, 12:53 AM · Restricted Project, Restricted Project

Sep 13 2022

zixuan-wu committed rG955e6ac49912: [CSKY] Fix the Predicates of instruction selection (authored by zixuan-wu).
[CSKY] Fix the Predicates of instruction selection
Sep 13 2022, 12:03 AM · Restricted Project, Restricted Project

Sep 6 2022

zixuan-wu committed rG162131257ffb: [CSKY] Fix the compiling error about missing Log2 function with Log2_64 (authored by zixuan-wu).
[CSKY] Fix the compiling error about missing Log2 function with Log2_64
Sep 6 2022, 11:50 PM · Restricted Project, Restricted Project

Sep 5 2022

zixuan-wu added a comment to D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.

Does this fix PR57548?

Sep 5 2022, 7:22 PM · Restricted Project, Restricted Project

Sep 4 2022

zixuan-wu added reviewers for D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result: Paul-C-Anagnostopoulos, javed.absar, evgeny777, CoelacanthusHex, RKSimon.
Sep 4 2022, 7:06 PM · Restricted Project, Restricted Project

Aug 23 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

ping...

Aug 23 2022, 7:07 PM · Restricted Project, Restricted Project

Aug 19 2022

zixuan-wu updated the diff for D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.

Add testcase.

Aug 19 2022, 1:50 AM · Restricted Project, Restricted Project

Aug 18 2022

zixuan-wu requested review of D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result.
Aug 18 2022, 11:58 PM · Restricted Project, Restricted Project

Aug 8 2022

zixuan-wu added inline comments to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.
Aug 8 2022, 7:40 PM · Restricted Project, Restricted Project
zixuan-wu updated the summary of D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.
Aug 8 2022, 6:50 PM · Restricted Project, Restricted Project
zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

@zixuan-wu we discussed this a bit in the last community sync call. One aspect that makes this patch a little hard to review is the lack of a clear patch description summarising the behaviour before the patch, the behaviour after the patch, and the motivation for the change. I appreciate that the time isn't very convenient in all timezones, but if you were able to attend the next call (18th August, same time) to discuss, that might really help agree a path forwards on this change.

Aug 8 2022, 6:42 PM · Restricted Project, Restricted Project
zixuan-wu updated the summary of D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.
Aug 8 2022, 6:40 PM · Restricted Project, Restricted Project

Aug 7 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

Just realized the problem is trying to fixed the default value of -mabi=, currently clang -target riscv32-elf -march=rv64gc -mabi=lp64d/riscv32-elf-clang -march=rv64gc -mabi=lp64d is work, and match the behavior of GCC did, riscv32-elf-gcc -march=rv64gc -mabi=lp64d.

And this patch is trying to make following two command work: clang -target riscv32-elf -march=rv64gc/riscv32-elf-clang -march=rv64gc, specify -march and -target but no -mabi.

That is different story now, GCC isn't deduce the default abi from either target triple or abi, so if you invoke gcc with riscv32-elf-gcc -march=rv64gc or riscv64-elf-gcc -march=rv32gc, you will got error message like that: cc1: error: ABI requires '-march=rv32' or cc1: error: ABI requires '-march=rv64'.

So that's not compatible issue with GCC, that's sort of clang driver specify issue, and I don't have strong opinion on this.


As a GNU toolchain developer, I would say, we are not intend to change the behavior of default value of -mabi or -march, the consensus among RISC-V GNU toolchain maintainer is user should explicitly specify the -march and -mabi if you are not using default -march and -mabi.

Aug 7 2022, 7:11 PM · Restricted Project, Restricted Project

Aug 3 2022

Herald added a project to D63329: Allow static linking of libc++ on Linux, just like -static-libstdc++: Restricted Project.

Is this going to continue?
And also if we use libunwind to handle EH, then it uses dladdr function which need link libdl.

Aug 3 2022, 6:57 PM · Restricted Project, Restricted Project

Jul 31 2022

zixuan-wu added inline comments to D93138: Add initial support for multilibs in Baremetal toolchain..
Jul 31 2022, 6:59 PM · Restricted Project, Restricted Project

Jul 27 2022

zixuan-wu committed rG70b8b738c579: [CSKY] Fix the btsti16 instruction missing in generic processor (authored by zixuan-wu).
[CSKY] Fix the btsti16 instruction missing in generic processor
Jul 27 2022, 2:39 AM · Restricted Project, Restricted Project

Jul 26 2022

Herald added a project to D93138: Add initial support for multilibs in Baremetal toolchain.: Restricted Project.
Jul 26 2022, 8:45 PM · Restricted Project, Restricted Project

Jul 25 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

This was very briefly discussed at today's sync up call. We were running short on time, so we didn't get a chance to talk through it, but there did seem to be a consensus that discussion on the interface implications was needed. This should hopefully be on the agenda when we talk again in two weeks.

Jul 25 2022, 7:07 PM · Restricted Project, Restricted Project

Jul 21 2022

zixuan-wu added reviewers for D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way: craig.topper, kito-cheng.
Jul 21 2022, 7:11 PM · Restricted Project, Restricted Project
zixuan-wu committed rG08db089124a4: [CSKY] Fix the testcase error due to the verifyInstructionPredicates (authored by zixuan-wu).
[CSKY] Fix the testcase error due to the verifyInstructionPredicates
Jul 21 2022, 12:58 AM · Restricted Project, Restricted Project

Jul 19 2022

zixuan-wu added inline comments to D129975: [CodeGen] Add MachineFunction::estimateSizeInBytes().
Jul 19 2022, 7:02 PM · Restricted Project, Restricted Project

Jul 18 2022

zixuan-wu updated the diff for D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

Remove unnecessary include header.

Jul 18 2022, 9:08 PM · Restricted Project, Restricted Project
zixuan-wu added inline comments to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.
Jul 18 2022, 12:42 AM · Restricted Project, Restricted Project

Jul 14 2022

zixuan-wu added a comment to D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.

Does GCC allow this or not? Because this strikes me as a bad idea at first sight…

Jul 14 2022, 8:00 PM · Restricted Project, Restricted Project
Herald added a project to D54214: [RISCV] Set triple based on -march flag: Restricted Project.

Rebase.

@lenary Following the discussion regarding D69383, I think it's best for now to keep the logic just keeping -march directly, rather than using getRISCVArch. I think in the case of -target risc32-..... -mabi=lp64 I think it would confuse users if the tools suddenly changed to doing an rv64 compile. If we disable that, all that function would provide me is the same StringRef I'm already evaluating. I think adding any extra flag to indicate whether a rv32<->rv64 switch is acceptable would just make the code unnecessarily more messy. I think in the future if getRISCVArch evaluates more flags, then it might make sense to reconsider this.

Jul 14 2022, 7:35 PM · Restricted Project, Restricted Project
zixuan-wu requested review of D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way.
Jul 14 2022, 7:32 PM · Restricted Project, Restricted Project

Jul 13 2022

zixuan-wu committed rG033324db6f3b: [CSKY] Fix the br target operand type in td (authored by zixuan-wu).
[CSKY] Fix the br target operand type in td
Jul 13 2022, 8:36 PM · Restricted Project, Restricted Project

Jul 6 2022

zixuan-wu updated the diff for D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.

The logic of getIntMatCost and getInstSeqCost is correct to be called in different code place. But the logic is not clear.
So make it clear without still constructing 2 different version of getIntMatCost to reuse the for loop to calculate cost of each chunk.

Jul 6 2022, 2:37 AM · Restricted Project, Restricted Project

Jul 5 2022

zixuan-wu added a comment to D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.

I found it's no change in .ll test cases. I am wondering if there should be a cost model test case like llvm/test/Analysis/CostModel/ARM/immediates.ll, or make it as NFC patch.

Jul 5 2022, 6:49 PM · Restricted Project, Restricted Project
zixuan-wu updated the diff for D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.

Address comments.

Jul 5 2022, 6:47 PM · Restricted Project, Restricted Project

Jul 4 2022

Herald added a project to D45265: [PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler: Restricted Project.

I am curiosity about why Machine Scheduler is better than the List Scheduler after RA?
As I see substitutePass is already used in 3 targets( AArch64,PPC,AMD), should PostMachineSchedulerID going to be the default PostRA Scheduler? @nemanjai @echristo

Jul 4 2022, 11:10 PM · Restricted Project
zixuan-wu added inline comments to D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.
Jul 4 2022, 7:13 PM · Restricted Project, Restricted Project
zixuan-wu added a comment to D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.

I would like to ask a question, is this patch to reduce code size?

Jul 4 2022, 6:51 PM · Restricted Project, Restricted Project
zixuan-wu requested review of D129072: [NFC][RISCV] Make the cost calculation of getIntMatCost more clear.
Jul 4 2022, 3:55 AM · Restricted Project, Restricted Project

Jun 15 2022

zixuan-wu committed rZORGad28dc3775df: [CSKY] Add cmake build config parameters to not checkout clang_tools_extra… (authored by zixuan-wu).
[CSKY] Add cmake build config parameters to not checkout clang_tools_extra…
Jun 15 2022, 7:35 PM · Restricted Project

Jun 14 2022

zixuan-wu committed rG587573b9f9f7: [CSKY] Fix the assert in eliminateFrameIndex when the offset is negative (authored by zixuan-wu).
[CSKY] Fix the assert in eliminateFrameIndex when the offset is negative
Jun 14 2022, 6:56 PM · Restricted Project, Restricted Project

Jun 13 2022

zixuan-wu committed rZORG998344369ef5: [CSKY] Remove `'collapseRequests': False` because it's impossible to build for… (authored by zixuan-wu).
[CSKY] Remove `'collapseRequests': False` because it's impossible to build for…
Jun 13 2022, 10:48 PM · Restricted Project

Jun 12 2022

zixuan-wu committed rZORG8a4a05234a66: [CSKY] Fix the missing comma in extra_cmake_args config (authored by zixuan-wu).
[CSKY] Fix the missing comma in extra_cmake_args config
Jun 12 2022, 10:47 PM · Restricted Project

Jun 8 2022

zixuan-wu closed D127081: [CSKY] Add CSKY buildbot to enable monitoring CSKY related commits.
Jun 8 2022, 11:42 PM · Restricted Project
zixuan-wu committed rZORG01beacb31e7d: [CSKY] Add CSKY buildbot to enable monitoring CSKY related commits (authored by zixuan-wu).
[CSKY] Add CSKY buildbot to enable monitoring CSKY related commits
Jun 8 2022, 11:42 PM · Restricted Project
zixuan-wu committed rZORG3a1584150632: [NFC] cosmetic change to remove unnecessary whitespace (authored by zixuan-wu).
[NFC] cosmetic change to remove unnecessary whitespace
Jun 8 2022, 11:42 PM · Restricted Project
zixuan-wu updated the diff for D127081: [CSKY] Add CSKY buildbot to enable monitoring CSKY related commits.
Jun 8 2022, 12:00 AM · Restricted Project

Jun 7 2022

zixuan-wu added inline comments to D127081: [CSKY] Add CSKY buildbot to enable monitoring CSKY related commits.
Jun 7 2022, 11:36 PM · Restricted Project

Jun 6 2022

zixuan-wu added a comment to D126856: [test-suite] Disable ClamAV running on CSKY temporarily to not block constructing buildbot for CSKY.

Gentle pin...

Jun 6 2022, 10:40 PM · Restricted Project

Jun 5 2022

zixuan-wu requested review of D127081: [CSKY] Add CSKY buildbot to enable monitoring CSKY related commits.
Jun 5 2022, 8:30 PM · Restricted Project

Jun 2 2022

Herald added a project to D98002: [RISCV] Add scheduling resources for V: Restricted Project.

Adding those "sched" information into base RVV instructions seems redundant? The scheduler works on PseudoRVV instructions.

Not redundant, as some tools do use the information at this level, e.g., llvm-mca.

Moreover, this patch captures the resources in a way that it makes it easier to add latency information to specific targets later.

SchedReadWrite needs to consider pseudo instructions with LMUL? Their latency should be different.

And SEW. I'm working on this feature, of which this patch introduces the preliminary information.

Jun 2 2022, 1:08 AM · Restricted Project, Restricted Project

Jun 1 2022

zixuan-wu updated the summary of D126856: [test-suite] Disable ClamAV running on CSKY temporarily to not block constructing buildbot for CSKY.
Jun 1 2022, 11:40 PM · Restricted Project
zixuan-wu requested review of D126856: [test-suite] Disable ClamAV running on CSKY temporarily to not block constructing buildbot for CSKY.
Jun 1 2022, 11:39 PM · Restricted Project

May 31 2022

zixuan-wu committed rG80fd9f3e0a18: [CSKY] Fix error of underestimated function size by save/restore R15(LR) when… (authored by zixuan-wu).
[CSKY] Fix error of underestimated function size by save/restore R15(LR) when…
May 31 2022, 8:23 PM · Restricted Project, Restricted Project

May 30 2022

zixuan-wu committed rG563cc3fda9a2: [Clang][CSKY] Add support about CSKYABIInfo (authored by zixuan-wu).
[Clang][CSKY] Add support about CSKYABIInfo
May 30 2022, 7:56 PM · Restricted Project, Restricted Project
zixuan-wu closed D126451: [Clang][CSKY] Add support about CSKYABIInfo.
May 30 2022, 7:55 PM · Restricted Project, Restricted Project

May 29 2022

zixuan-wu updated the diff for D126451: [Clang][CSKY] Add support about CSKYABIInfo.
May 29 2022, 7:44 PM · Restricted Project, Restricted Project
zixuan-wu committed rTa67ae4972b54: [test-suite] Disable RSBench and XSBench running on CSKY (authored by zixuan-wu).
[test-suite] Disable RSBench and XSBench running on CSKY
May 29 2022, 7:32 PM · Restricted Project
zixuan-wu closed D126453: [test-suite] Disable RSBench and XSBench running on CSKY.
May 29 2022, 7:32 PM · Restricted Project

May 26 2022

zixuan-wu added a comment to D126451: [Clang][CSKY] Add support about CSKYABIInfo.

BTW, I have run llvm-test-suite, it passed.

May 26 2022, 7:33 PM · Restricted Project, Restricted Project
zixuan-wu added inline comments to D126451: [Clang][CSKY] Add support about CSKYABIInfo.
May 26 2022, 7:19 PM · Restricted Project, Restricted Project
zixuan-wu added a comment to D126451: [Clang][CSKY] Add support about CSKYABIInfo.

This looks good to me, but wait to make sure others see it, too.

My reasons are: it is largely similar to RISCV implementation, it seems to follow what I expected of the ABI (which is similar to other targets) and has a large corpus of tests.

I can't comment on the specifics of the ABI implementation (I haven't read the ABI document *that* thoroughly), but as David said, issues will be picked up by tests until the target reaches maturity.

May 26 2022, 7:16 PM · Restricted Project, Restricted Project
zixuan-wu committed rTf3a83077a501: [test-suite] Add C-SKY Support in benchmark (authored by zixuan-wu).
[test-suite] Add C-SKY Support in benchmark
May 26 2022, 7:03 PM · Restricted Project
zixuan-wu closed D100926: [test-suite] Add C-SKY Support in benchmark 1.3.0.
May 26 2022, 7:03 PM · Restricted Project