[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P

[melonedo]

Summary

Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the vendor specific extensions of CV32E40P that need LLVM intrinsics to implement Clang builtins.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Spec: https://github.com/openhwgroup/core-v-sw/blob/b69b8a487f8b0e4ab7e559d459cd0bbacab8adc9/specifications/corev-builtin-spec.md#listing-of-pulp-bit-manipulation-builtins-xcvbitmanip

[craig.topper]

Is there intended to be a header file that wraps the builtins? For other targets, builtins are considered an internal implementation detail and the real interface is the header file. I'm trying to get a C interface approved for Zb* and Zk* standard extenions https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

15

Use DefaultAttrsIntrinsic. Which I think includes IntrWillReturn

23

Use 2 space indentation

35

llvm.ctpop?

37

Can we use llvm.fshr like __builtin_rotateright32 does for this?

39

Can we use llvm.bitreverse?

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

147 ↗

(On Diff #548618)

Can we follow the established convention of having Pseudo at the beginning?

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

522

Why do we need these pseudos? Looks like it just to split up the immediate? Can't we do that with an SDNodeXForm in tablegen?

[melonedo]

• Use DefaultAttrsIntrinsic
• Implement LLVM intrinsics for ctpop/ctlz/cttz/ror/rol/bitreverse
• Replace pseudo instructions for SDNodeXForm

[melonedo]

In D157510#4573494, @craig.topper wrote:

Is there intended to be a header file that wraps the builtins? For other targets, builtins are considered an internal implementation detail and the real interface is the header file. I'm trying to get a C interface approved for Zb* and Zk* standard extenions https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Discussions for this question are being hosted under https://github.com/openhwgroup/corev-llvm-project/issues/74. Before we reach a conclusion, I will implement these intrinsics in both versions, i.e., both llvm.ctpop and llvm.riscv.cv.bitmanip.cnt.

llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

39

cv.bitreverse is a generalization of llvm.bitreverse, which allows specifying number of higher bits to be ignored and number of bits grouped togather. For example, cv.bitreverse t0, t0, 23, 2 can transform octal 001 010 011 to 01 010 001.

[craig.topper]

In D157510#4583629, @melonedo wrote:

In D157510#4573494, @craig.topper wrote:

Is there intended to be a header file that wraps the builtins? For other targets, builtins are considered an internal implementation detail and the real interface is the header file. I'm trying to get a C interface approved for Zb* and Zk* standard extenions https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Discussions for this question are being hosted under https://github.com/openhwgroup/corev-llvm-project/issues/74. Before we reach a conclusion, I will implement these intrinsics in both versions, i.e., both llvm.ctpop and llvm.riscv.cv.bitmanip.cnt.

We can have a builtin in the frontend that maps to a target independent intrinsic. We already do this for builtin_riscv_clz_32/64 and builtin_riscv_ctz_32/64.

[melonedo]

llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

39

...octal 001 010 011 to 011 010 001.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

509

I think you can drop Operand from these.

510

Space before :

523

Drop the space before <

[melonedo]

Fix formatting issues

[melonedo]

Remove CORE-V specific intrisics for cv.ff1/fl1/cnt/ror

[melonedo]

From discussions last week, a header file for the C API will be included later as a public interface, which is tracked by https://github.com/openhwgroup/corev-gcc/issues/48 and https://github.com/openhwgroup/corev-llvm-project/issues/74. For LLVM intrisics level, since target-specific builtins can map to target-independent intrisics, I will implement these with LLVM target independent intrinsics.

[melonedo]

Rebase to latest main

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   def int_riscv_vsm3c    : RISCVBinaryAAXUnMaskedZvk<IsVI=1>;
   def int_riscv_vsm3me   : RISCVBinaryAAXUnMasked;
 } // TargetPrefix = "riscv"
 
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 include "llvm/IR/IntrinsicsRISCVXTHead.td"
 include "llvm/IR/IntrinsicsRISCVXsf.td"
+include "llvm/IR/IntrinsicsRISCVXCV.td"

llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

+//===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the CORE-V vendor intrinsics for RISC-V.
+//
+//===----------------------------------------------------------------------===//
+
+class ScalarCoreVBitManipGprGprIntrinsic
+    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                            [IntrNoMem, IntrSpeculatable]>;
+
+class ScalarCoreVBitManipGprIntrinsic
+    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
+                            [IntrNoMem, IntrSpeculatable]>;
+
+let TargetPrefix = "riscv" in {
+  def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
+  def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
+  def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic;
+  def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic;
+
+  def int_riscv_cv_bitmanip_insert
+    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                            [IntrNoMem, IntrSpeculatable]>;
+
+  def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic;
+
+  def int_riscv_cv_bitmanip_bitrev
+    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                            [IntrNoMem, IntrWillReturn, IntrSpeculatable,
+                            ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
+} // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
     if (!RV64LegalI32 && Subtarget.is64Bit())
       setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
   } else if (Subtarget.hasVendorXTHeadBb()) {
     if (Subtarget.is64Bit())
       setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
     setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Custom);
+  } else if (Subtarget.hasVendorXCVbitmanip()) {
+    setOperationAction({ISD::ROTL}, XLenVT, Expand);
   } else {
     setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
     if (RV64LegalI32 && Subtarget.is64Bit())
       setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Expand);
   }
 
   // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
   // pattern match it directly in isel.
   setOperationAction(ISD::BSWAP, XLenVT,
                      (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
                       Subtarget.hasVendorXTHeadBb())
                          ? Legal
                          : Expand);
   if (RV64LegalI32 && Subtarget.is64Bit())
     setOperationAction(ISD::BSWAP, MVT::i32,
                        (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
                         Subtarget.hasVendorXTHeadBb())
                            ? Promote
                            : Expand);
 
+
+  if (Subtarget.hasVendorXCVbitmanip()) {
+    setOperationAction(ISD::BITREVERSE, XLenVT, Legal);
+  } else {
     // Zbkb can use rev8+brev8 to implement bitreverse.
     setOperationAction(ISD::BITREVERSE, XLenVT,
                        Subtarget.hasStdExtZbkb() ? Custom : Expand);
+  }
 
   if (Subtarget.hasStdExtZbb()) {
     setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT,
                        Legal);
     if (RV64LegalI32 && Subtarget.is64Bit())
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32,
                          Promote);
 
     if (Subtarget.is64Bit()) {
       if (RV64LegalI32)
         setOperationAction(ISD::CTTZ, MVT::i32, Legal);
       else
         setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
     }
-  } else {
+  } else if (!Subtarget.hasVendorXCVbitmanip()) {
     setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
     if (RV64LegalI32 && Subtarget.is64Bit())
       setOperationAction({ISD::CTTZ, ISD::CTPOP}, MVT::i32, Expand);
   }
 
-  if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb()) {
+  if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
+      Subtarget.hasVendorXCVbitmanip()) {
     // We need the custom lowering to make sure that the resulting sequence
     // for the 32bit case is efficient on 64bit targets.
     if (Subtarget.is64Bit()) {
       if (RV64LegalI32) {
         setOperationAction(ISD::CTLZ, MVT::i32,
                            Subtarget.hasStdExtZbb() ? Legal : Promote);
         if (!Subtarget.hasStdExtZbb())
           setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
   return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
 }
 
 bool RISCVTargetLowering::signExtendConstant(const ConstantInt *CI) const {
   return Subtarget.is64Bit() && CI->getType()->isIntegerTy(32);
 }
 
 bool RISCVTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
-  return Subtarget.hasStdExtZbb();
+  return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXCVbitmanip();
 }
 
 bool RISCVTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
-  return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb();
+  return Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
+         Subtarget.hasVendorXCVbitmanip();
 }
 
 bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
     const Instruction &AndI) const {
   // We expect to be able to match a bit extraction instruction if the Zbs
   // extension is supported and the mask is a power of two. However, we
   // conservatively return false if the mask would fit in an ANDI instruction,
   // on the basis that it's possible the sinking+duplication of the AND in

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
                           opcodestr, "$rd, $rs1, $is3, $is2">;
 
   class CVBitManipRR<bits<7> funct7, string opcodestr>
       : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
                 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVBitManipR<bits<7> funct7, string opcodestr>
       : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
-                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1"> {
+                (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
     let rs2 = 0b00000;
   }
 }
 
 let Predicates = [HasVendorXCVbitmanip, IsRV32],
     hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
   def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
   def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
   def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
         "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
 }
 
 def CVrrAsmOperand : AsmOperandClass {
   let Name = "RegReg";
   let ParserMethod = "parseRegReg";
   let DiagnosticType = "InvalidRegReg";
 }
 
 def CVrr : Operand<OtherVT> {
    let ParserMatchClass = CVrrAsmOperand;
    let EncoderMethod =  "getRegReg";
    let DecoderMethod = "decodeRegReg";
    let PrintMethod = "printRegReg";
 }
 
 class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
               opcodestr, "$rd, (${rs1}), ${imm12}"> {
   let Constraints = "$rs1_wb = $rs1";
   let DecoderNamespace = "XCVmem";
 }
 
 class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
               opcodestr, "$rd, (${rs1}), ${rs2}"> {
class CVLoad_ri<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
       (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
 
 let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
     mayLoad = 1, mayStore = 0 in {
   // Event load
   def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
 }
+
+def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
+def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
+def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
+
+def CV_LO5: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def CV_HI5: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+multiclass PatCoreVBitManip<Intrinsic intr> {
+  def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
+  def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
+            (!cast<RVInst>("CV_" # NAME) 
+             GPR:$rs1, (CV_HI5 cv_uimm10:$imm), (CV_LO5 cv_uimm10:$imm))>;
+}
+
+let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
+  defm EXTRACT : PatCoreVBitManip<int_riscv_cv_bitmanip_extract>;
+  defm EXTRACTU : PatCoreVBitManip<int_riscv_cv_bitmanip_extractu>;
+  defm BCLR : PatCoreVBitManip<int_riscv_cv_bitmanip_bclr>;
+  defm BSET : PatCoreVBitManip<int_riscv_cv_bitmanip_bset>;
+
+  def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, GPR:$rs2, GPR:$rd),
+            (CV_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+  def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, cv_uimm10:$imm, GPR:$rd),
+            (CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm), 
+                                          (CV_LO5 cv_uimm10:$imm))>;
+
+  def : PatGpr<cttz, CV_FF1>;
+  def : PatGpr<ctlz, CV_FL1>;
+  def : PatGpr<int_riscv_cv_bitmanip_clb, CV_CLB>;
+  def : PatGpr<ctpop, CV_CNT>;
+
+  def : PatGprGpr<rotr, CV_ROR>;
+
+  def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts, 
+             cv_tuimm2:$radix),
+            (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
+  def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
+}

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                   TTI::TargetCostKind CostKind) {
   // Prevent hoisting in unknown cases.
   return TTI::TCC_Free;
 }
 
 TargetTransformInfo::PopcntSupportKind
 RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) {
   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
-  return ST->hasStdExtZbb() ? TTI::PSK_FastHardware : TTI::PSK_Software;
+  return ST->hasStdExtZbb() || ST->hasVendorXCVbitmanip()
+             ? TTI::PSK_FastHardware
+             : TTI::PSK_Software;
 }
 
 bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
   // Currently, the ExpandReductions pass can't expand scalable-vector
   // reductions, but we still request expansion as RVV doesn't support certain
   // reductions and the SelectionDAG can't legalize them either.
   switch (II->getIntrinsicID()) {
   default:

llvm/test/CodeGen/RISCV/xcvbitmanip.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+xcvbitmanip -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-O0
+; RUN: llc -O3 -mtriple=riscv32 -mattr=+xcvbitmanip -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-O3
+
+declare i32 @llvm.riscv.cv.bitmanip.extract(i32, i32)
+
+define i32 @test.cv.extractr(i32 %a, i32 %b) {
+; CHECK-LABEL: test.cv.extractr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.extractr a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.extract(i32 %a, i32 %b)
+  ret i32 %1
+}
+
+define i32 @test.cv.extract(i32 %a) {
+; CHECK-LABEL: test.cv.extract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.extract a0, a0, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.extract(i32 %a, i32 65)
+  ret i32 %1
+}
+
+define i32 @test.cv.extract1023(i32 %a) {
+; CHECK-LABEL: test.cv.extract1023:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.extract a0, a0, 31, 31
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.extract(i32 %a, i32 1023)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.extractu(i32, i32)
+
+define i32 @test.cv.extractur(i32 %a, i32 %b) {
+; CHECK-LABEL: test.cv.extractur:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.extractur a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.extractu(i32 %a, i32 %b)
+  ret i32 %1
+}
+
+define i32 @test.cv.extractu(i32 %a) {
+; CHECK-LABEL: test.cv.extractu:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.extractu a0, a0, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.extractu(i32 %a, i32 65)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.insert(i32, i32, i32)
+
+define i32 @test.cv.insert(i32 %c, i32 %a) {
+; CHECK-LABEL: test.cv.insert:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.insert a0, a1, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.insert(i32 %a, i32 65, i32 %c)
+  ret i32 %1
+}
+
+define i32 @test.cv.insertr(i32 %c, i32 %b, i32 %a) {
+; CHECK-LABEL: test.cv.insertr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.insertr a0, a2, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.insert(i32 %a, i32 %b, i32 %c)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.bclr(i32, i32)
+
+define i32 @test.cv.bclrr(i32 %a, i32 %b) {
+; CHECK-LABEL: test.cv.bclrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bclrr a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.bclr(i32 %a, i32 %b)
+  ret i32 %1
+}
+
+define i32 @test.cv.bclr(i32 %a) {
+; CHECK-LABEL: test.cv.bclr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bclr a0, a0, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.bclr(i32 %a, i32 65)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.bset(i32, i32)
+
+define i32 @test.cv.bsetr(i32 %a, i32 %b) {
+; CHECK-LABEL: test.cv.bsetr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bsetr a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.bset(i32 %a, i32 %b)
+  ret i32 %1
+}
+
+define i32 @test.cv.bset(i32 %a) {
+; CHECK-LABEL: test.cv.bset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bset a0, a0, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.bset(i32 %a, i32 65)
+  ret i32 %1
+}
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define i32 @test.cv.ff1(i32 %a) {
+; CHECK-LABEL: test.cv.ff1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.ff1 a0, a0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.cttz.i32(i32 %a, i1 0)
+  ret i32 %1
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define i32 @test.cv.fl1(i32 %a) {
+; CHECK-LABEL: test.cv.fl1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.fl1 a0, a0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.clb(i32)
+
+define i32 @test.cv.clb(i32 %a) {
+; CHECK-LABEL: test.cv.clb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.clb a0, a0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.clb(i32 %a)
+  ret i32 %1
+}
+
+declare i32 @llvm.ctpop(i32)
+
+define i32 @test.cv.cnt(i32 %a) {
+; CHECK-LABEL: test.cv.cnt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.cnt a0, a0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.ctpop(i32 %a)
+  ret i32 %1
+}
+
+declare i32 @llvm.fshl.i32(i32, i32, i32)
+
+define i32 @test.llvm.fshl.imm(i32 %a) {
+; CHECK-LABEL: test.llvm.fshl.imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 30
+; CHECK-NEXT:    cv.ror a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 2)
+  ret i32 %1
+}
+
+define i32 @test.llvm.fshl.reg(i32 %a, i32 %b) {
+; CHECK-O0-LABEL: test.llvm.fshl.reg:
+; CHECK-O0:       # %bb.0:
+; CHECK-O0-NEXT:    mv a2, a1
+; CHECK-O0-NEXT:    li a1, 0
+; CHECK-O0-NEXT:    sub a1, a1, a2
+; CHECK-O0-NEXT:    cv.ror a0, a0, a1
+; CHECK-O0-NEXT:    ret
+;
+; CHECK-O3-LABEL: test.llvm.fshl.reg:
+; CHECK-O3:       # %bb.0:
+; CHECK-O3-NEXT:    neg a1, a1
+; CHECK-O3-NEXT:    cv.ror a0, a0, a1
+; CHECK-O3-NEXT:    ret
+  %1 = call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
+  ret i32 %1
+}
+
+declare i32 @llvm.fshr.i32(i32, i32, i32)
+
+define i32 @test.llvm.fshr.imm(i32 %a) {
+; CHECK-LABEL: test.llvm.fshr.imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    cv.ror a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 2)
+  ret i32 %1
+}
+
+define i32 @test.llvm.fshr.reg(i32 %a, i32 %b) {
+; CHECK-LABEL: test.llvm.fshr.reg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.ror a0, a0, a1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
+  ret i32 %1
+}
+
+declare i32 @llvm.riscv.cv.bitmanip.bitrev(i32, i32, i32)
+
+define i32 @test.cv.bitrev(i32 %a) {
+; CHECK-LABEL: test.cv.bitrev:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bitrev a0, a0, 2, 1
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.bitmanip.bitrev(i32 %a, i32 1, i32 2)
+  ret i32 %1
+}
+
+declare i32 @llvm.bitreverse(i32)
+
+define i32 @test.llvm.bitrev(i32 %a) {
+; CHECK-LABEL: test.llvm.bitrev:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.bitrev a0, a0, 0, 0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.bitreverse(i32 %a)
+  ret i32 %1
+}