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- User Since
- Jul 30 2013, 7:58 PM (390 w, 1 d)
Yesterday
Does this need earlyclobber? The spec says "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (speci fied by vs2), else an illegal instruction exception is raised."
LGTM
-Add tests for unused results on the masked intrinsic
-Make the masked intrinsic have "side effects"
-Use the default read/write memory property instead of IntrReadMem+IntrHasSideEffects which doesn't work correctly without tablegen changes.
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Revoking my approval
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Remove Zba changes that accidentally got merged in the previous rebase
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Remove side effects from READ_VL portion. Allowing it to be deleted.
Having just tripped over this bug again. I think we should fix this
LGTM
LGTM
LGTM
LGTM
Tue, Jan 19
LGTM to me with that one comment.
This is a very incomplete review, but I need to go eat dinner
LGTM
Rebase
Fix comment
Modify to use the same approach as rev8 and orc.b patch
Consistently use isCompressOnly = true
I'm not sure I understand what's special about vrgathere16 that needs this refactor. Can you provide an explanation?
LGTM with that one comment.
Mon, Jan 18
LGTM
LGTM
Check operands of zext.h in rv32zbb-valid.s
LGTM
-Rebase
-Add PseudoReadVL expansion. Remove string from Pseudo in .td.
I've committed a modified version of this patch that uses both results.
LGTM
Sun, Jan 17
Add test updates
I’m not against this, but do want to mention the help text is incorrect for x86-64. It lists CPUs that don’t support 64-bit. Using one of those CPUs will trigger a fatal error. A better list is fillValidCPUList from X86TargetParser.cpp in lib/Support. It takes a mode argument. That’s the interface clang uses.