- User Since
- Jul 30 2013, 7:58 PM (513 w, 4 d)
I think the vrgather.vv for reverse needs at most 2 sources for each VLEN piece. Is it likely hardware would optimize for that?
Rebase on D152039
Push WidenV constraint into class.
Finish using the EarlyClobber parameter I added to remove constraints.
I also dropped the ball on this. Will try to review for real after I sleep.
I still think replacing the 1 with a valid register for the mode is the better fix.
Thu, Jun 1
We pass SDValue by value all over the SelectionD
AG code. And it looks pretty easy for a compiler to see the unsigned field is unused. Does this change really make a difference?
Pretty sure the op is an SDValue not an SDUse.
Remove parentheses from RISCVISelDAGToDAG.cpp
Try to address review comments
Use Simon's suggestion.
Doesn't this make codegen worse on when those extensions aren't supported?
MS inline assembly is parsed twice, once by clang and once by the backend.
Wed, May 31
I think we can abandon this.
I think I already got this with https://reviews.llvm.org/D150996
The backend patch must go before the clang patch.
Tue, May 30
Do we need to enable these intrinsics for Zvfhmin?
What if the target doesn't natively support CTLZ/CTTZ and only has CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF will end up with a select followed by the AND? What if the target doesn't support CTTZ/CTLZ at all?
This patch is labeled as NFC but has new functionality.