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- Jul 30 2013, 7:58 PM (460 w, 3 d)
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There is an option to scale the LMUL returned to the vectorizer by TTI getRegisterBitWidth. Using that you can get LMUL>1 fixed vector loops. https://godbolt.org/z/34asbPcv7 should work for scalar too.
Rename variable. Cleanup comment slightly.
Thu, May 26
What is it isn't known to be null at compile time but gets optimized to it. Are we trying to make passing a null pointer defined behavior for these intrinsics?
I don't understand the motivation for this change. LLVM coding guidelines encourage using early returns.
Wed, May 25
Use DestReg as the source for the second operation.
Instead of dividing in half use a large immediate, either -2048 or (2048-stackalign),
to do a first adjustment. Then a smaller adjustment for the remainder.
Is it possible to test this?
Rebase. I used the wrong repo so it might have been older than I meant it to be.
Tue, May 24
The use of vscale came from the scalable vector autovectorizer. llvm.vscale is VLEN/RISCV::RVVBitsPerBlock. Which I guess is the right VLMAX for SEW=RISCV::RVVBitsPerBlock where RISCV::RVVBitPerBlock is 64.
Add a method to convert opcode to operand kind. All opcodes listed with an
unreachable default to make sure it always gets updated if new opcodes are used.
LGTM. Other than that last comment.
Mon, May 23