- User Since
- Jul 30 2013, 7:58 PM (302 w, 6 d)
Sun, May 19
Sat, May 18
Thu, May 16
Can we do this with 2 intrinsics with overloaded result types as I've done for lround/llround in D62026?
Wed, May 15
Tue, May 14
This logic was copied from canShiftBinOpWithConstantRHS in InstCombineShifts.cpp
Mon, May 13
LGTM to me with one minor
-Move into getAddressOperands.
-Emit the NEG machine directly as I'm not sure I trust accessing N at this point in the code to use insertDAGNode. N can be changed by CSEing and other DAG modifications that can occur during address matching.
-Add -pre-RA-sched=linearize to one test that would fail previously due to the dangling sub node getting left behind when LEA costing failed.
Sun, May 12
Sat, May 11
Fri, May 10
I've commited a modified version of my patch in r360475. I'll try to reduce a test case and commit that later tonight or tomorrow.
LGTM with that one remaining unused variable fixed.
@sammccall, can you try this patch
You’ll need to use llc to crash. But I can guess the issue now. SLH is expecting the memory address to have a virtual register as a base register, but we forced RSP on this access. We need to teach SLH about this case
@sammccall, any chance you’ve seen it with an asserts build? I think the debug output might say which registers it was trying to copy.
Wed, May 8
The X86 patterns are probably heavily hidden in tablegen classes, but they should be easily visible in X86GenDAGISel.inc. Does that file generate the same before and after this change?
Should we have a PowerPC test for ppcf128?
Tue, May 7
Moving back to Plan Changes because I still believe this is the wrong fix. I don't know what the right fix is.
Mon, May 6
Can you test lround.i32 with -mtriple=i686-unknown with and without -mattr=sse2.
Get rid of clang stuff.
Not sure. I'll fix it.
Sun, May 5