- User Since
- Jul 30 2013, 7:58 PM (233 w, 1 d)
I removed the srl/and reversing transform from X86 to see if we did any better. But end up with an and with 65024 in from of the shift.
I think we already have the encoding tests for the assembler and disassembler. The instructions were already present before this patch.
Unless I'm crazy the entirety of addcarry2.ll already passes on trunk. I think we hit regular isel patterns unless the carry out of the ADC/SBB is used.
You can have two instructions use the same encoding if you mark one with isAsmParserOnly = 1. See XACQUIRE_PREFIX and XRELEASE_PREFIX. isAsmParserOnly will hide from the disassembler that checks encoding collisions.
Rebase to fix the outdated trunc code. Add helper for splitting and extending v16i1 to v16i16/v16i8
Address review comments.
Fixed in r322724, but forgot to tag it in the commit.
Looking at clang's CGBuiltin.cpp we do have precedent for using Intrinsic::sqrt for builtins for AArch64, PowerPC, and SystemZ.
Add diffs for more v32i1 shuffle test case. I haven't commited the current versions of the tests to the repo yet, but you can see the before and after here.
Tue, Jan 16
While the v32i1 is technically a regression, its not a fair test of what happens with v32i1 shuffles. Previously we were getting lucky with type promotion working favorably with the types used for argument passing. I think a shuffle sandwiched between say an icmp and a select condition would be very different.
Should we be printing the DS_PREFIX as "notrack" like gcc?
With context this time.
Address Sanjay's comments.
I know smaller constants is meaningful to X86. But do other targets have different immediate sizes for And instructions. ARM encodes immediates with a shift amount applied to them I think? Not sure about others.
I wonder if we should do this in PreprocessISelDAG so the killing off of the AND when the mask is all 1s doesn't seem quite so weird. Right now when it happens the Select call ends up doing selection on the input to the AND.
Mon, Jan 15
Sun, Jan 14
bYeah there may be some crossover with lowerVectorShuffleByMerging128BitLanes. I'll see if I can generalize lowerVectorShuffleByMerging128BitLanes more.
Actually rebase the patch.
Rebase now that tets have been committed.
Sat, Jan 13
Rebase after improving vXi16/vXi8 select combines
Update with context
Fri, Jan 12
Remove the X86TargetTransformInfo.cpp changes and rebase.
This seems to cause a constant pool to be use for the second _mm_setzero_si64 call.
Remove 64-bit instructions from 32-bit mode tests
Commandeering so I can remove the 64-bit instructions from the 32-bit tests.
I'm not sure there's a functional change here. The instructions that are being modified don't have patterns defined.
Remove 64-bit mode only instructions from the 32-bit tests. Use movq mnemonic instead of movd for moves between 64-bit GPRs and MMX registers.
__builtin_cpu_init was added to clang between 5.0 and 6.0
Thu, Jan 11
Commandeering so I can rebase this patch
There are some VEX encoded instructions in the 64-bit test file. It probably can't be helped in the 32-bit file since you can't use xmm16-31
I don't know what platforms this needs to support. But __builtin_cpu_support only works when compiled with clang or gcc. And it requires compiler-rt or libgcc. I don't know if that's guaranteed to exist on Windows.
Wed, Jan 10
Can you show what code you expect for those cases and I'll see what I can do?
Add canExtendTo512DQ and canExtendTo512BW helper methods to encapsulate hasAVX512/hasBWI and prefer vector width check into one place.
Fix the calls in DAG combine and add test cases for it.
Remove unneeded line that snuck in during rebase.
Tue, Jan 9
Rebase and add the asserts Simon requested
Mon, Jan 8
Also block SETNE since that requires an XOR with all 1s to implement.
@hfinkel do you have any opinions on this?
Do you have any suggestions of how to do that? Not sure what features I could guarantee from the build bots.
I think the patch looks good now with the vector fix. Did you hear anything from @mzolotukhin about compile time?
Rebase on top of other recent changes.