Page MenuHomePhabricator

pcwang-thead (Wang Pengcheng)
User

Projects

User does not belong to any projects.

User Details

User Since
Oct 26 2021, 7:36 PM (66 w, 6 d)

Recent Activity

Yesterday

pcwang-thead added a comment to D131230: [RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values.

I have reverted it in 3df16e6f6e4d933f3839003e29b8a4b70e4c7ec8.
Please update CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c and reland this patch again.

Mon, Feb 6, 7:03 PM · Restricted Project, Restricted Project
pcwang-thead added a reverting change for rG28bd84f55fc0: [RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values: rG3df16e6f6e4d: Revert "[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting….
Mon, Feb 6, 7:01 PM · Restricted Project, Restricted Project
pcwang-thead committed rG3df16e6f6e4d: Revert "[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting… (authored by pcwang-thead).
Revert "[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting…
Mon, Feb 6, 7:01 PM · Restricted Project, Restricted Project
pcwang-thead added a reverting change for D131230: [RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values: rG3df16e6f6e4d: Revert "[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting….
Mon, Feb 6, 7:01 PM · Restricted Project, Restricted Project

Wed, Feb 1

pcwang-thead added inline comments to D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension.
Wed, Feb 1, 10:56 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D143029: [RISCV] Add vendor-defined XTHeadBa (address-generation) extension.
Wed, Feb 1, 10:54 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D143029: [RISCV] Add vendor-defined XTHeadBa (address-generation) extension.
Wed, Feb 1, 10:53 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D108961: [RISCV] MC relaxation for out-of-range conditional branch..

Vote +1 from my personal side.
We met some issues when porting Android/Rust to RISCV, and finally found it can be fixed by this patch.

Wed, Feb 1, 10:33 PM · Restricted Project, Restricted Project

Wed, Jan 18

pcwang-thead committed rGe4abfc4c3cf4: [CSKY] Fix errors caused by change of compressInst (authored by pcwang-thead).
[CSKY] Fix errors caused by change of compressInst
Wed, Jan 18, 1:01 AM · Restricted Project, Restricted Project
pcwang-thead closed D141995: [CSKY] Fix errors caused by change of compressInst.
Wed, Jan 18, 1:01 AM · Restricted Project, Restricted Project
pcwang-thead requested review of D141995: [CSKY] Fix errors caused by change of compressInst.
Wed, Jan 18, 12:09 AM · Restricted Project, Restricted Project

Tue, Jan 17

pcwang-thead added a comment to D141962: [RISCV] Use vfirst insead of vcpop for i1 reduce.and/or..

Is this early out really a feasible optimization for a microarchitecture?
All I can think about it is: for mask instruction vfirst.m, supposed that there are n = VLen / DataPath microinstructions issued (ideally, they are executed parallelly), then if the first k microinstructions find the 1, we may write the result of vfirst.m back before we get results of the last n-k microinstructions. But I don't see too much gains compared to the extra complexity.

Tue, Jan 17, 11:22 PM · Restricted Project, Restricted Project
pcwang-thead committed rG9bb7a38a6943: [RISCV][NFC] Use uncompressInst to relax instructions (authored by pcwang-thead).
[RISCV][NFC] Use uncompressInst to relax instructions
Tue, Jan 17, 10:35 PM · Restricted Project, Restricted Project
pcwang-thead committed rG3f703b071e43: [RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo (authored by pcwang-thead).
[RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo
Tue, Jan 17, 10:34 PM · Restricted Project, Restricted Project
pcwang-thead committed rGfcc2e5aa3942: [TableGen][NFC] Add postfix for validators of CompressPat (authored by pcwang-thead).
[TableGen][NFC] Add postfix for validators of CompressPat
Tue, Jan 17, 10:34 PM · Restricted Project, Restricted Project
pcwang-thead closed D141834: [RISCV][NFC] Use uncompressInst to relax instructions.
Tue, Jan 17, 10:34 PM · Restricted Project, Restricted Project
pcwang-thead closed D141897: [RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo.
Tue, Jan 17, 10:34 PM · Restricted Project, Restricted Project
pcwang-thead closed D141896: [TableGen][NFC] Add postfix for validators of CompressPat.
Tue, Jan 17, 10:34 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D141834: [RISCV][NFC] Use uncompressInst to relax instructions.

I've posted https://reviews.llvm.org/D141951 to removed the uncompressInst's dependency on MCRegisterInfo which should simplify this patch.

Tue, Jan 17, 10:01 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141834: [RISCV][NFC] Use uncompressInst to relax instructions.

Rebase.

Tue, Jan 17, 9:57 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141897: [RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo.

Rebase.

Tue, Jan 17, 9:56 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141896: [TableGen][NFC] Add postfix for validators of CompressPat.

Rebase

Tue, Jan 17, 9:55 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D141834: [RISCV][NFC] Use uncompressInst to relax instructions.

Can we do this in a way that doesn't replicate the uncompressInst function in two different cpp files.

Tue, Jan 17, 12:11 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141834: [RISCV][NFC] Use uncompressInst to relax instructions.

Address comments.

Tue, Jan 17, 12:05 AM · Restricted Project, Restricted Project
pcwang-thead requested review of D141897: [RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo.
Tue, Jan 17, 12:03 AM · Restricted Project, Restricted Project
pcwang-thead requested review of D141896: [TableGen][NFC] Add postfix for validators of CompressPat.
Tue, Jan 17, 12:01 AM · Restricted Project, Restricted Project

Mon, Jan 16

pcwang-thead updated the diff for D141834: [RISCV][NFC] Use uncompressInst to relax instructions.

Address comment.

Mon, Jan 16, 7:11 PM · Restricted Project, Restricted Project
pcwang-thead requested review of D141834: [RISCV][NFC] Use uncompressInst to relax instructions.
Mon, Jan 16, 2:28 AM · Restricted Project, Restricted Project

Sun, Jan 15

pcwang-thead committed rG4954c3c7b690: [RISCV] Generate march string from target features (authored by pcwang-thead).
[RISCV] Generate march string from target features
Sun, Jan 15, 8:05 PM · Restricted Project, Restricted Project
pcwang-thead closed D141479: [RISCV] Generate march string from target features.
Sun, Jan 15, 8:04 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141479: [RISCV] Generate march string from target features.
  • Rebase.
  • Add spec version.
Sun, Jan 15, 7:07 PM · Restricted Project, Restricted Project

Fri, Jan 13

pcwang-thead added inline comments to D141479: [RISCV] Generate march string from target features.
Fri, Jan 13, 2:04 AM · Restricted Project, Restricted Project
pcwang-thead updated the summary of D141479: [RISCV] Generate march string from target features.
Fri, Jan 13, 2:02 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141479: [RISCV] Generate march string from target features.
  • Add reference to RISCV spec.
  • Address comments.
Fri, Jan 13, 1:50 AM · Restricted Project, Restricted Project

Wed, Jan 11

pcwang-thead added inline comments to D141479: [RISCV] Generate march string from target features.
Wed, Jan 11, 8:19 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141479: [RISCV] Generate march string from target features.

Fix errors caused by destroyed string.

Wed, Jan 11, 8:12 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141479: [RISCV] Generate march string from target features.

Reduce constructions of std::string.

Wed, Jan 11, 7:26 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D141479: [RISCV] Generate march string from target features.

Address comments.

Wed, Jan 11, 7:19 PM · Restricted Project, Restricted Project
pcwang-thead requested review of D141479: [RISCV] Generate march string from target features.
Wed, Jan 11, 4:16 AM · Restricted Project, Restricted Project

Sun, Jan 8

pcwang-thead added inline comments to D141032: [Clang][RISCV] Expose vlenb to user.
Sun, Jan 8, 11:55 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D141032: [Clang][RISCV] Expose vlenb to user.
Sun, Jan 8, 9:53 PM · Restricted Project, Restricted Project
pcwang-thead accepted D141032: [Clang][RISCV] Expose vlenb to user.

The code is OK to me, except that a few small comments.

Sun, Jan 8, 8:26 PM · Restricted Project, Restricted Project

Jan 5 2023

pcwang-thead added inline comments to D141032: [Clang][RISCV] Expose vlenb to user.
Jan 5 2023, 1:01 AM · Restricted Project, Restricted Project

Jan 4 2023

pcwang-thead added inline comments to D141032: [Clang][RISCV] Expose vlenb to user.
Jan 4 2023, 11:48 PM · Restricted Project, Restricted Project

Jan 3 2023

pcwang-thead added inline comments to D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen..
Jan 3 2023, 7:35 PM · Restricted Project, Restricted Project, Restricted Project

Jan 2 2023

pcwang-thead committed rGc570287fbf4d: [RISCV][NFC] Move RISCVISAInfo back to Support (authored by pcwang-thead).
[RISCV][NFC] Move RISCVISAInfo back to Support
Jan 2 2023, 9:56 PM · Restricted Project, Restricted Project
pcwang-thead closed D140529: [RISCV][NFC] Move RISCVISAInfo back to Support.
Jan 2 2023, 9:56 PM · Restricted Project, Restricted Project

Dec 28 2022

pcwang-thead added inline comments to D137838: [Support] Move TargetParsers to new component.
Dec 28 2022, 12:48 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project

Dec 22 2022

pcwang-thead added a comment to D140529: [RISCV][NFC] Move RISCVISAInfo back to Support.

@craig.topper Thanks!

Dec 22 2022, 11:29 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen..

@pcwang-thead, may I ask you to own these further optimisations of the generative process, and submit a patch for it after the current patch lands? I'd happily review it!

The reason I am asking this is because the current patch is mostly dealing with making sure we can build clang/llvm after removing the def file. People are discussing dependencies and modules (for example, last update I did was to make the patch work for modules with -DLLVM_ENABLE_MODULES=On), and this is already taking quite a number of comments.
There is value in the discussion on how to build march out of the features, I'd rather keep it in a separate submission so that the threads do not get lost among the other comments for this patch.

Francesco

Dec 22 2022, 4:33 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead added a comment to D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen..

@pcwang-thead, I addressed some of your comments.

The value of EnumFeatures is now computed dynamicaly from the
Features field of the Processor class.

Thanks! That sounds great to me!

As for generating MArch out of the Features field, @craig.topper
pointed me at
https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11. From
the reading of it, it seems that the alphabetical order is enough to
build the string that carries MArch. Am I missing something?

Currently, I think the alphabetical order is OK. If we relax the checking of arch string someday, there is no doubt that we should change the implementation here too.

The currently accepted order isn’t alphabetical. The single letter extensions have a specific order. The z extensions are ordered by looking up the second letter in the single letter order. If we alphabetize here i don’t think it will be accepted by the frontend.

Dec 22 2022, 12:11 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead requested review of D140529: [RISCV][NFC] Move RISCVISAInfo back to Support.
Dec 22 2022, 12:09 AM · Restricted Project, Restricted Project

Dec 21 2022

pcwang-thead added a comment to D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen..

@pcwang-thead, I addressed some of your comments.

The value of EnumFeatures is now computed dynamicaly from the
Features field of the Processor class.

Dec 21 2022, 7:50 PM · Restricted Project, Restricted Project, Restricted Project

Dec 19 2022

pcwang-thead added inline comments to D139386: [RISCV] Implement assembler support for XTHeadVdot.
Dec 19 2022, 12:00 AM · Restricted Project, Restricted Project

Dec 18 2022

pcwang-thead added a comment to D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Hi,

Is there any update about this ?

Dec 18 2022, 6:45 PM · Restricted Project, Restricted Project, Restricted Project, Restricted Project

Dec 14 2022

pcwang-thead added inline comments to D139386: [RISCV] Implement assembler support for XTHeadVdot.
Dec 14 2022, 6:56 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D139386: [RISCV] Implement assembler support for XTHeadVdot.

It seems we have split Clang changes off, but this patch still mix MC and CodeGen changes.
I think we can do further splitting to make it easier to review (separate MC and CodeGen). :-)

Dec 14 2022, 6:54 PM · Restricted Project, Restricted Project

Dec 13 2022

pcwang-thead abandoned D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.

I think there is no left changes.
Thanks. @reames

Dec 13 2022, 6:45 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D139386: [RISCV] Implement assembler support for XTHeadVdot.

I am confused about the failures of CI testing and checked that is AddressSanitizer-Unit of x86,
it looks there is no relation between AddressSanitizer and this patch,
could anyone give me some hints for the failures ? thanks :)

Dec 13 2022, 6:14 PM · Restricted Project, Restricted Project

Dec 12 2022

pcwang-thead accepted D139747: [RISCV] Allow fractional LMUL for reduction start value.

LGTM

Dec 12 2022, 1:07 AM · Restricted Project, Restricted Project
pcwang-thead accepted D139648: [RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable.

LGTM
@craig.topper Any other thoughts?

Dec 12 2022, 1:02 AM · Restricted Project, Restricted Project

Dec 11 2022

pcwang-thead committed rGf02e37827565: [RISCV][NFC] Define variables for vector VT list of different LMUL (authored by pcwang-thead).
[RISCV][NFC] Define variables for vector VT list of different LMUL
Dec 11 2022, 6:47 PM · Restricted Project, Restricted Project
pcwang-thead closed D139690: [RISCV][NFC] Define variables for vector VT list of different LMUL.
Dec 11 2022, 6:47 PM · Restricted Project, Restricted Project

Dec 9 2022

pcwang-thead updated the summary of D139699: [RISCV][WIP] Add register class for instructions that ignore register groups.
Dec 9 2022, 2:24 AM · Restricted Project, Restricted Project
pcwang-thead requested review of D139699: [RISCV][WIP] Add register class for instructions that ignore register groups.
Dec 9 2022, 2:21 AM · Restricted Project, Restricted Project

Dec 8 2022

pcwang-thead updated the diff for D139690: [RISCV][NFC] Define variables for vector VT list of different LMUL.

Reuse defined VMaskVTs in VR/VRNoV0.

Dec 8 2022, 10:55 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D139690: [RISCV][NFC] Define variables for vector VT list of different LMUL.
Dec 8 2022, 10:46 PM · Restricted Project, Restricted Project
pcwang-thead requested review of D139690: [RISCV][NFC] Define variables for vector VT list of different LMUL.
Dec 8 2022, 10:24 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D139656: [RISCV] Reuse VL (if non-zero) when building single element vector for start of reduction chain.

Talked to Craig because I hadn't followed his last comment.

The issue that we have is that vmv.x.s is modeled badly. We model it as if it had an LMUL8 variant, but if you read the actual instruction manual you'll see that it ignores register groups and only writes to a single register. This isn't a correctness concern, but it does mean that this patch over constrains the register allocator (by using a lmul8 reg class), which could result in poor codegen. This is only an issue for this call site as the previous callsite (earlier change in stack), already had this issue and was likely going to write to the full LMUL8 register group in the following instruction anyways. The reduction instruction also only writes to a single vector register.

Dec 8 2022, 8:16 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D139648: [RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable.
Dec 8 2022, 7:10 PM · Restricted Project, Restricted Project

Dec 7 2022

pcwang-thead added a comment to D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.

I'm looking at your test changes - not the code - and it really seems like the sole benefit of this here is vsetvli insertion.

Dec 7 2022, 8:11 PM · Restricted Project, Restricted Project

Nov 30 2022

pcwang-thead added inline comments to D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.
Nov 30 2022, 10:23 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.
  • Address comments.
  • Fix incorrect EVT when combining to reductions.
Nov 30 2022, 10:20 PM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D137426: [RISCV][Codegen] Account for LMUL in Vector floating-point instructions.
Nov 30 2022, 12:19 AM · Restricted Project, Restricted Project
pcwang-thead committed rG2b6910e12aeb: [RISCV] Remove lmuls argument in Sched class (authored by pcwang-thead).
[RISCV] Remove lmuls argument in Sched class
Nov 30 2022, 12:17 AM · Restricted Project, Restricted Project
pcwang-thead closed D138640: [RISCV] Remove lmuls argument in Sched class.
Nov 30 2022, 12:16 AM · Restricted Project, Restricted Project

Nov 29 2022

pcwang-thead added a comment to D138640: [RISCV] Remove lmuls argument in Sched class.

There may be some more changes (of the same kind) required depending when this lands because of the following patches:

https://reviews.llvm.org/D137342 (already landed)
https://reviews.llvm.org/D137426

Nov 29 2022, 10:08 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D138640: [RISCV] Remove lmuls argument in Sched class.

Rebase

Nov 29 2022, 10:05 PM · Restricted Project, Restricted Project

Nov 28 2022

pcwang-thead added a comment to D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.

Gentle ping. :-)

Nov 28 2022, 7:01 PM · Restricted Project, Restricted Project

Nov 24 2022

pcwang-thead added a comment to D70401: [RISCV] Complete RV32E/ilp32e implementation.

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when RV32E/ilp32e is ratified.

  1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
  2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

RV32E/ilp32e has been ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan to proceed with this patch? :)

Nov 24 2022, 4:16 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead requested review of D138640: [RISCV] Remove lmuls argument in Sched class.
Nov 24 2022, 12:37 AM · Restricted Project, Restricted Project

Nov 23 2022

pcwang-thead committed rG241accea2a9d: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat) (authored by pcwang-thead).
[RISCV] Lower unmasked zero-stride vector load to (scalar load + splat)
Nov 23 2022, 7:13 PM · Restricted Project, Restricted Project
pcwang-thead closed D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).
Nov 23 2022, 7:12 PM · Restricted Project, Restricted Project
pcwang-thead committed rG25b51b7924e7: [RISCV] Precommit test for D138101 (authored by pcwang-thead).
[RISCV] Precommit test for D138101
Nov 23 2022, 7:08 PM · Restricted Project, Restricted Project
pcwang-thead closed D138543: [RISCV] Precommit test for D138101.
Nov 23 2022, 7:08 PM · Restricted Project, Restricted Project
pcwang-thead accepted D138543: [RISCV] Precommit test for D138101.

I will commit this patch since it has been approved in D138101.

Nov 23 2022, 6:33 PM · Restricted Project, Restricted Project

Nov 22 2022

pcwang-thead updated the diff for D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).

Rebase on separate test.

Nov 22 2022, 11:20 PM · Restricted Project, Restricted Project
pcwang-thead requested review of D138543: [RISCV] Precommit test for D138101.
Nov 22 2022, 11:14 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D137044: [ClangFE] Add support for option -mno-pic-data-is-text-relative.

The test clang/test/Driver/pic.c failed when we compiled Clang/LLVM with -DCLANG_DEFAULT_PIE_ON_LINUX=False.

Nov 22 2022, 12:01 AM · Restricted Project, Restricted Project, Restricted Project

Nov 21 2022

pcwang-thead added inline comments to D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).
Nov 21 2022, 6:31 PM · Restricted Project, Restricted Project

Nov 20 2022

pcwang-thead added a comment to D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions.

Ping :-)

Nov 20 2022, 6:44 PM · Restricted Project, Restricted Project

Nov 16 2022

pcwang-thead updated the diff for D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).

Update tests.

Nov 16 2022, 6:53 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).

Fix test.

Nov 16 2022, 2:30 AM · Restricted Project, Restricted Project
pcwang-thead added inline comments to D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized.
Nov 16 2022, 12:35 AM · Restricted Project, Restricted Project
pcwang-thead requested review of D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat).
Nov 16 2022, 12:30 AM · Restricted Project, Restricted Project

Nov 15 2022

pcwang-thead committed rGa214c521f876: [RISCV] Don't use zero-stride vector load for gather if not optimized (authored by pcwang-thead).
[RISCV] Don't use zero-stride vector load for gather if not optimized
Nov 15 2022, 6:44 PM · Restricted Project, Restricted Project
pcwang-thead closed D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized.
Nov 15 2022, 6:44 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized.

This isn't correct. The strided load can be masked. For the case where all lanes are masked off, executing the scalar load is unsound and could introduce a fault.

You could allow any mask where you can prove at least one lane active, or make the scalar store conditional, but there's a bunch of complexity there. As a starting point, I suggest you restrict your transformation to when the instruction is unmasked.

Nov 15 2022, 12:11 AM · Restricted Project, Restricted Project

Nov 14 2022

pcwang-thead updated the summary of D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized.
Nov 14 2022, 11:58 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized.

Restrict this to unmasked loads only.

Nov 14 2022, 11:58 PM · Restricted Project, Restricted Project