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pcwang-thead (Wang Pengcheng)
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User Since
Oct 26 2021, 7:36 PM (12 w, 2 d)

Recent Activity

Today

pcwang-thead updated the diff for D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.
  • Rebase.
  • Revert to the original version.
Thu, Jan 20, 9:37 PM · Restricted Project
pcwang-thead added inline comments to D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.
Thu, Jan 20, 7:01 PM · Restricted Project
pcwang-thead updated the diff for D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.

Set CostPerUse for floating point registers.

Thu, Jan 20, 4:52 AM · Restricted Project
pcwang-thead added a comment to D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.

I have one question: Should we set CostPerUse for floating point registers? If so, we may need to unroll the register definitions for F&D manually.

Thu, Jan 20, 1:21 AM · Restricted Project

Yesterday

pcwang-thead added a comment to D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.

This scheme seems rather inflexible. We can get away with it currently since the default behaviour of zero-filling CostPerUse elements out to the maximum list size works in every case, but I could see there being issues in future where you end up needing to be extremely verbose to avoid such behaviour.

Wed, Jan 19, 11:11 PM · Restricted Project
pcwang-thead updated the diff for D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.

Address comments.

Wed, Jan 19, 9:06 PM · Restricted Project
pcwang-thead requested review of D117741: [RISCV] Set CostPerUse to 1 iff RVC is enabled.
Wed, Jan 19, 8:34 PM · Restricted Project

Mon, Jan 17

pcwang-thead added inline comments to D70401: [RISCV] Complete RV32E/ilp32e implementation.
Mon, Jan 17, 10:04 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D70401: [RISCV] Complete RV32E/ilp32e implementation.

Gentle ping.

Mon, Jan 17, 7:08 PM · Restricted Project, Restricted Project

Tue, Jan 11

pcwang-thead committed rGc6430fade344: [RISCV] Generate 32 bits jumptable entries when code model is small (authored by pcwang-thead).
[RISCV] Generate 32 bits jumptable entries when code model is small
Tue, Jan 11, 2:22 AM
pcwang-thead closed D116435: [RISCV] Generate 32 bits jumptable entries when code model is small.
Tue, Jan 11, 2:22 AM · Restricted Project
pcwang-thead added a comment to D116435: [RISCV] Generate 32 bits jumptable entries when code model is small.

AArch64 does even better and has a PC-relative jump table lowering whose element size depends on how big your switch is, not the code model in use. Ideally this would be made target-independent, or at least copied to RISC-V. That'd let you have small entries even for medany RV64.

Thanks for your advice!

It seems that AArch64 has a pass called AArch64CompressJumpTables to do this, I may add it to RISCV later (or make it a target-independent pass).

Tue, Jan 11, 1:32 AM · Restricted Project
pcwang-thead updated the diff for D116435: [RISCV] Generate 32 bits jumptable entries when code model is small.

Address comment.

Tue, Jan 11, 1:28 AM · Restricted Project

Mon, Jan 10

pcwang-thead committed rG98d51c2542dc: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT (authored by pcwang-thead).
[RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT
Mon, Jan 10, 11:55 PM
pcwang-thead closed D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.
Mon, Jan 10, 11:55 PM · Restricted Project

Sun, Jan 9

pcwang-thead added a comment to D108447: [RISCV] Implement BuildSDIVPow2, use cmov to lower sdiv pow2..

What a coincidence.😁

Sun, Jan 9, 7:21 PM · Restricted Project

Thu, Jan 6

pcwang-thead committed rG91cf2a9b6c3c: [RISCV][NFC] Use sub operator to generate register list (authored by pcwang-thead).
[RISCV][NFC] Use sub operator to generate register list
Thu, Jan 6, 8:31 PM
pcwang-thead closed D116729: [RISCV][NFC] Use sub operator to generate register list.
Thu, Jan 6, 8:31 PM · Restricted Project
pcwang-thead added a comment to D116435: [RISCV] Generate 32 bits jumptable entries when code model is small.

AArch64 does even better and has a PC-relative jump table lowering whose element size depends on how big your switch is, not the code model in use. Ideally this would be made target-independent, or at least copied to RISC-V. That'd let you have small entries even for medany RV64.

Thu, Jan 6, 7:11 PM · Restricted Project
pcwang-thead requested review of D116729: [RISCV][NFC] Use sub operator to generate register list.
Thu, Jan 6, 1:42 AM · Restricted Project

Fri, Dec 31

pcwang-thead requested review of D116435: [RISCV] Generate 32 bits jumptable entries when code model is small.
Fri, Dec 31, 12:20 AM · Restricted Project

Thu, Dec 30

pcwang-thead committed rG41454ab25645: [RISCV] Use constant pool for large integers (authored by pcwang-thead).
[RISCV] Use constant pool for large integers
Thu, Dec 30, 10:49 PM
pcwang-thead closed D114950: [RISCV] Use constant pool for large integers.
Thu, Dec 30, 10:49 PM · Restricted Project
pcwang-thead updated the diff for D114950: [RISCV] Use constant pool for large integers.
  • Rebase.
  • Update CodeGen/RISCV/div-by-constant.ll.
Thu, Dec 30, 9:56 PM · Restricted Project
pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

Thanks!

Thu, Dec 30, 6:55 PM · Restricted Project

Tue, Dec 28

pcwang-thead updated the diff for D70401: [RISCV] Complete RV32E/ilp32e implementation.

Update tests.

Tue, Dec 28, 2:48 AM · Restricted Project, Restricted Project

Mon, Dec 27

pcwang-thead added a comment to D70401: [RISCV] Complete RV32E/ilp32e implementation.

ping.

Mon, Dec 27, 10:15 PM · Restricted Project, Restricted Project
pcwang-thead retitled D70401: [RISCV] Complete RV32E/ilp32e implementation from [WIP][RISCV] Complete RV32E/ilp32e implementation to [RISCV] Complete RV32E/ilp32e implementation.
Mon, Dec 27, 10:10 PM · Restricted Project, Restricted Project

Dec 19 2021

pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

GCC will merge constant pool entries with the same value in the whole compilation unit, can LLVM do this too?
It seems that ConstantPool is owned by MachineFunction and can't be shared with other MachineFunctions.
Are there something I missed? Is it possible for LLVM to create module-scoped constant pool that can be used by all functions?

I found this related bug https://bugs.llvm.org/show_bug.cgi?id=16711

Dec 19 2021, 7:16 PM · Restricted Project

Dec 16 2021

pcwang-thead updated the diff for D70401: [RISCV] Complete RV32E/ilp32e implementation.
  • Fix tests.
Dec 16 2021, 9:43 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D70401: [RISCV] Complete RV32E/ilp32e implementation.
  • Update tests.
Dec 16 2021, 8:10 PM · Restricted Project, Restricted Project
pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

GCC will merge constant pool entries with the same value in the whole compilation unit, can LLVM do this too?
It seems that ConstantPool is owned by MachineFunction and can't be shared with other MachineFunctions.
Are there something I missed? Is it possible for LLVM to create module-scoped constant pool that can be used by all functions?

Dec 16 2021, 7:03 PM · Restricted Project
pcwang-thead updated the summary of D70401: [RISCV] Complete RV32E/ilp32e implementation.
Dec 16 2021, 1:31 AM · Restricted Project, Restricted Project
pcwang-thead updated the summary of D70401: [RISCV] Complete RV32E/ilp32e implementation.
Dec 16 2021, 1:30 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D70401: [RISCV] Complete RV32E/ilp32e implementation.
  • Add macro __riscv_32e.
Dec 16 2021, 1:15 AM · Restricted Project, Restricted Project
pcwang-thead retitled D70401: [RISCV] Complete RV32E/ilp32e implementation from [WIP][RISCV] Implement ilp32e ABI to [WIP][RISCV] Complete RV32E/ilp32e implementation.
Dec 16 2021, 12:18 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D70401: [RISCV] Complete RV32E/ilp32e implementation.
  • Rebase.
  • Reserve x16-x31 when using RV32E.
  • Make ilp32e incompatible with D extension.
  • Update/Add tests.
Dec 16 2021, 12:09 AM · Restricted Project, Restricted Project

Dec 15 2021

pcwang-thead commandeered D70401: [RISCV] Complete RV32E/ilp32e implementation.
Dec 15 2021, 11:46 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D114361: [MachineCSE] Add an option to enable global CSE.
  • Rebase.
  • Address comment.
Dec 15 2021, 10:30 PM · Restricted Project
pcwang-thead added a comment to D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.

From the LLVM Code-Review Policy and Practices (https://llvm.org/docs/CodeReview.html):

If it is urgent, provide reasons why it is important to you to get this patch landed and ping it every couple of days. If it is not urgent, the common courtesy ping rate is one week. Remember that you’re asking for valuable time from other professional developers.

It's only been 3 days for this and other patches you've just pinged

Dec 15 2021, 6:53 PM · Restricted Project
pcwang-thead added a comment to D114361: [MachineCSE] Add an option to enable global CSE.

ping

Dec 15 2021, 6:33 PM · Restricted Project
pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

ping

Dec 15 2021, 6:33 PM · Restricted Project
pcwang-thead added a comment to D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.

ping

Dec 15 2021, 6:32 PM · Restricted Project

Dec 14 2021

pcwang-thead updated pcwang-thead.
Dec 14 2021, 3:05 AM
pcwang-thead updated the summary of D114950: [RISCV] Use constant pool for large integers.
Dec 14 2021, 12:30 AM · Restricted Project
pcwang-thead retitled D114950: [RISCV] Use constant pool for large integers from [RISCV] Using constant pool for large integers to [RISCV] Use constant pool for large integers.
Dec 14 2021, 12:23 AM · Restricted Project
pcwang-thead retitled D114950: [RISCV] Use constant pool for large integers from [RISCV] Promote large integers to constant pool to [RISCV] Using constant pool for large integers.
Dec 14 2021, 12:20 AM · Restricted Project
pcwang-thead updated the diff for D114950: [RISCV] Use constant pool for large integers.

Address comments.

Dec 14 2021, 12:15 AM · Restricted Project

Dec 13 2021

pcwang-thead updated the diff for D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.
  • Address comments.
Dec 13 2021, 10:36 PM · Restricted Project
pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

Do we have a test case that shows the bug @asb found with "zero" previously? I skimmed the tests but I might have missed it.

Dec 13 2021, 6:44 PM · Restricted Project
pcwang-thead added a comment to D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.

Some of the i32 ones look like they might not be profitable on RV64 unless you have a wide out-of-order processor; 50% more instructions in some cases

Dec 13 2021, 6:32 AM · Restricted Project
pcwang-thead updated the diff for D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.
  • Address comments.
  • Only apply to divisors whose absolute value is less than 2^12.
Dec 13 2021, 5:59 AM · Restricted Project
pcwang-thead added a comment to D114950: [RISCV] Use constant pool for large integers.

There's a question of what to do about some of the imm.ll test cases. Perhaps it makes sense to add an option to either change the threshold or disable the constant pool, then some of these tests can still usefully check the materialisation logic and it's easier for people to experiment with different thresholds if their microarch might benefit? I'd be open to counter-arguments that it's not worth the hassle though.

Dec 13 2021, 1:42 AM · Restricted Project
pcwang-thead updated the diff for D114950: [RISCV] Use constant pool for large integers.
  • Rebase.
  • Address comments.
  • Add options to disable promotion and set threshold.
Dec 13 2021, 1:32 AM · Restricted Project

Dec 2 2021

pcwang-thead updated the diff for D114950: [RISCV] Use constant pool for large integers.

Address comments.

Dec 2 2021, 11:31 PM · Restricted Project
pcwang-thead requested review of D114950: [RISCV] Use constant pool for large integers.
Dec 2 2021, 5:57 AM · Restricted Project

Dec 1 2021

pcwang-thead requested review of D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT.
Dec 1 2021, 1:49 AM · Restricted Project

Nov 26 2021

pcwang-thead added a comment to D114361: [MachineCSE] Add an option to enable global CSE.

OK, that's a good start. I was expected something among the lines of "I have tested RISCV on the llvm test suite or some other large codebase under Oz and it reduced the total codesize by 0.16%".

My experiments on ARM and AArch64 are not as great. This seems to increase codesize more than it reduces it, especially on ARM. The AArch64 numbers were dominated by one large increase, with some of the smaller cases being smaller. I would be interested in what the tests in-tree showed too.

You might want to check X86 as it's easy to run. If I was making target independent changed like this I would expect to test at least a couple of architecture combos (say, X86 with Arm and AArch64 for 32bit and 64bit variants), and potentially add target overrides where needed. In this case the default should maybe be kept as before, unless we have some evidence this is beneficial across most architectures.

Nov 26 2021, 3:44 AM · Restricted Project
pcwang-thead updated the diff for D114361: [MachineCSE] Add an option to enable global CSE.
  • Address comments.
  • Only apply aggressive CSE to Heuristics 1.
  • Make enableAggressiveMachineCSE return false by default.
  • Remove RISCV MIR test.
Nov 26 2021, 1:59 AM · Restricted Project

Nov 23 2021

pcwang-thead added a comment to D114361: [MachineCSE] Add an option to enable global CSE.

Thanks. What targets have you tested with this? And what kind of codesize differences have you observed?

Nov 23 2021, 2:35 AM · Restricted Project
pcwang-thead updated the summary of D114361: [MachineCSE] Add an option to enable global CSE.
Nov 23 2021, 12:16 AM · Restricted Project
pcwang-thead updated the diff for D114361: [MachineCSE] Add an option to enable global CSE.
  • Change global to aggressive.
  • Return true immediately if aggressive MachineCSE is enabled.
  • Change test case to MIR test.
Nov 23 2021, 12:14 AM · Restricted Project

Nov 22 2021

pcwang-thead added a comment to D114361: [MachineCSE] Add an option to enable global CSE.

Global is not a good name here. MachineCSE is working on the whole function, which is global in compiler's terminology, by walking through the DominatorTree.

Nov 22 2021, 5:51 AM · Restricted Project
pcwang-thead added a reviewer for D114361: [MachineCSE] Add an option to enable global CSE: lebedev.ri.
Nov 22 2021, 4:37 AM · Restricted Project
pcwang-thead added reviewers for D114361: [MachineCSE] Add an option to enable global CSE: lkail, anton-afanasyev.
Nov 22 2021, 4:36 AM · Restricted Project
pcwang-thead updated the diff for D114361: [MachineCSE] Add an option to enable global CSE.

Do not modify global variable EnableGlobalCSE.

Nov 22 2021, 4:31 AM · Restricted Project
pcwang-thead updated the summary of D114361: [MachineCSE] Add an option to enable global CSE.
Nov 22 2021, 4:21 AM · Restricted Project
pcwang-thead updated the diff for D114361: [MachineCSE] Add an option to enable global CSE.

Amend commit message.

Nov 22 2021, 4:17 AM · Restricted Project
pcwang-thead requested review of D114361: [MachineCSE] Add an option to enable global CSE.
Nov 22 2021, 4:15 AM · Restricted Project

Nov 21 2021

pcwang-thead committed rGaf0ecfccae82: [RISCV] Generate pseudo instruction li (authored by pcwang-thead).
[RISCV] Generate pseudo instruction li
Nov 21 2021, 10:04 PM
pcwang-thead closed D112692: [RISCV] Generate pseudo instruction li.
Nov 21 2021, 10:04 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.

Rebase.

Nov 21 2021, 9:16 PM · Restricted Project, Restricted Project

Nov 15 2021

pcwang-thead updated the diff for D113885: [MachineCSE] Use isAsCheapAsAMove in TargetInstrInfo.

Format code.

Nov 15 2021, 5:09 AM · Restricted Project
pcwang-thead added a comment to D113885: [MachineCSE] Use isAsCheapAsAMove in TargetInstrInfo.

IIUC, this shouldn't be an NFC change, please provide test cases.

Nov 15 2021, 4:49 AM · Restricted Project
pcwang-thead updated the summary of D113885: [MachineCSE] Use isAsCheapAsAMove in TargetInstrInfo.
Nov 15 2021, 4:22 AM · Restricted Project
pcwang-thead requested review of D113885: [MachineCSE] Use isAsCheapAsAMove in TargetInstrInfo.
Nov 15 2021, 4:14 AM · Restricted Project

Nov 2 2021

pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Adds ADDITIONAL_COMPILE_FLAGS and guard macros to:

  • libcxx\test\std\language.support\support.dynamic\new.delete\new.delete.single\sized_delete14.pass.cpp
  • libcxx\test\std\language.support\support.dynamic\new.delete\new.delete.array\sized_delete_array14.pass.cpp
Nov 2 2021, 10:48 PM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead added a comment to D112692: [RISCV] Generate pseudo instruction li.

Oh, I see, Alex's suggestion. I'm not convinced by that, if you're maintaining a significant downstream fork and you don't know how to batch-update tests then I don't know what to say other than you shouldn't be maintaining a significant downstream fork.

Nov 2 2021, 9:49 PM · Restricted Project, Restricted Project
pcwang-thead updated the summary of D112692: [RISCV] Generate pseudo instruction li.
Nov 2 2021, 9:17 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.
  • Reverts sanitizer changes.
  • Adds a note about how to update tests to commit message.
Nov 2 2021, 9:14 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Makes required changes

Nov 2 2021, 7:09 AM · Restricted Project, Restricted Project, Restricted Project

Nov 1 2021

pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.
  • Regenerate clang\test\AST\ast-dump-stmt-json.cpp and clang\test\AST\ast-dump-expr-json.cpp.
  • Format code.
Nov 1 2021, 11:20 PM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Removes unnecessary -fno-sized-deallocation and some comments.

Nov 1 2021, 10:24 PM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.
  • Changes to Args.AddLastArg(CmdArgs, ...)
  • Adds a note to clang/docs/ReleaseNotes.rst
  • Fixs clangd test failure.
Nov 1 2021, 8:27 PM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Add -fno-sized-allocation to:

  • clang\test\AST\ast-dump-expr-json.cpp
  • clang\test\AST\ast-dump-stmt-json.cpp
  • clang\test\CodeGenCXX\dllimport.cpp
  • clang\test\SemaCXX\MicrosoftExtensions.cpp
  • clang-tools-extra/clangd/unittests/FindTargetTests.cpp
Nov 1 2021, 6:12 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead added a comment to D112692: [RISCV] Generate pseudo instruction li.

Change addi/mv zero in compiler-rt to li

This is a completely separate thing, it does not belong here (and I don't agree that it's better, it's just different, they're both idiomatic)

Nov 1 2021, 5:56 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112921: [clang] Enable sized deallocation by default in C++14 onwards.

Fix errors in clang-tools-extra\test\clang-tidy\checkers\misc-new-delete-overloads.cpp

Nov 1 2021, 5:12 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead added a reviewer for D112921: [clang] Enable sized deallocation by default in C++14 onwards: rnk.
Nov 1 2021, 4:13 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead requested review of D112921: [clang] Enable sized deallocation by default in C++14 onwards.
Nov 1 2021, 4:12 AM · Restricted Project, Restricted Project, Restricted Project
pcwang-thead added a comment to D112692: [RISCV] Generate pseudo instruction li.

I have no idea why some tests about sanitizer failed.

Nov 1 2021, 3:43 AM · Restricted Project, Restricted Project
pcwang-thead added a comment to D112692: [RISCV] Generate pseudo instruction li.
Nov 1 2021, 3:42 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.

Change addi/mv zero in compiler-rt to li

Nov 1 2021, 1:54 AM · Restricted Project, Restricted Project

Oct 28 2021

pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.

Removed spaces.

Oct 28 2021, 8:21 PM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.

Fix errors in llvm\test\MC\RISCV\rv64zbs-aliases-valid.s and llvm\test\MC\RISCV\rv64zba-aliases-valid.s

Oct 28 2021, 2:37 AM · Restricted Project, Restricted Project
pcwang-thead updated the diff for D112692: [RISCV] Generate pseudo instruction li.

Updating D112692: [RISCV] Generate pseudo instruction li

Oct 28 2021, 1:09 AM · Restricted Project, Restricted Project

Oct 27 2021

pcwang-thead added a reviewer for D112692: [RISCV] Generate pseudo instruction li: asb.
Oct 27 2021, 11:57 PM · Restricted Project, Restricted Project
pcwang-thead requested review of D112692: [RISCV] Generate pseudo instruction li.
Oct 27 2021, 11:45 PM · Restricted Project, Restricted Project
pcwang-thead updated pcwang-thead.
Oct 27 2021, 10:01 PM