User Details
- User Since
- Jul 4 2022, 12:40 AM (74 w, 4 d)
Aug 24 2023
From discussions last week, a header file for the C API will be included later as a public interface, which is tracked by https://github.com/openhwgroup/corev-gcc/issues/48 and https://github.com/openhwgroup/corev-llvm-project/issues/74. For LLVM intrisics level, since target-specific builtins can map to target-independent intrisics, I will implement these with LLVM target independent intrinsics.
Aug 20 2023
Remove CORE-V specific intrisics for cv.ff1/fl1/cnt/ror
Aug 14 2023
Fix formatting issues
Aug 13 2023
- Use DefaultAttrsIntrinsic
- Implement LLVM intrinsics for ctpop/ctlz/cttz/ror/rol/bitreverse
- Replace pseudo instructions for SDNodeXForm
Aug 9 2023
Jul 28 2023
Jul 24 2023
Amend RISCVUsage.rst
Adjust opcode field and rebase to main
Edit RISCVUsage.rst
Jul 21 2023
Switch cv.and/or/xor to signed according to spec to allow 0xffff-like patterns
Jul 18 2023
Add tests for +xcvbi option; add extension to RISCVISAInfo; fix spelling
Fix capitalization of FeatureVendorXCVsimd
Various corrections based on D155283
Jul 11 2023
RV->CV; update version; add "CORE-V" to feature description
Change version of spec to 1.0.0
Jul 4 2023
Adopt suggestions
Rename RVInst* to CVInst*
Fix type
Jul 3 2023
Update immediate type of cv.avgu/srl/sra/sll
Jun 25 2023
Rebase to main
Jun 19 2023
Jun 16 2023
Reuse RVInstI/R and enable test for disassembler
Jun 15 2023
Add contributor
Jun 14 2023
Switch to one file per vendor
[RISCV] Add support for XCVbitmanip extension in CV32E40P
Remove excessive test header
Fix typo
Add usage, merge tests and ensure 80-char limit
Nov 9 2022
Oct 27 2022
Specify -filetype=null
Revise comments
Also use opaque pointers in ghccc-nest.ll
Use opaque pointers
Use ptr for opaque pointers
Sep 7 2022
Rebase and upload changes again
Aug 18 2022
Adopt suggestions
Jul 5 2022
Rebase the commit on master.