Please can you LAHF/SAHF tests to the resources-x86_64.s llvm-mca test files

Is there any llvm side fast isel tests for these?

Would it be better to implement m_APInt_or_Undef and m_APFloat_or_Undef - explaining that the undef is only for vectors (and naturally must still contain at least one APInt).

@asb What's the plan for this patch?

Can anyone recommend the best shuffle costs to put here for the 32/64 cases?

@spatel Should this wait for D48236 or can I commit it now?

Thanks

I haven't had a chance to go through this yet, but it'd be useful to be able to call these through ArrayRef<int> style shuffle masks (see the TODO I added for SLP to D48023)

In D48252#1134779, @lebedev.ri wrote:

In D48252#1134776, @RKSimon wrote:

LGTM thanks

Thank you for the review.

Note that i don't fully understand the pattern here.
I followed the basic idea that for every instruction, the last (destination) register should always be the same,
the highest used register (i.e. if there is an instruction taking 3 registers, it would be %rcx).
All others start from 0/a always. And the memory operand is always 64-bit.

LGTM thanks

LGTM as well

Should there be some AVX512VL tests? We don't have any scheduler that can test XOP instructions AFAICT (unless we want to cheat and use SandyBridge in its role as the generic model).

Abandon this? D47763 took this patch's idea for a UnsupportedWriteResPair multiclass but kept the unsupported classes in target's scheduler td file.

@courbet What's the plan for this phab?

@niravd This is failing on EXPENSIVE_CHECKS builds - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/10278

Simplified SK_Select pattern matching

Thanks @dtemirbulatov

@kparzysz This is failing when EXPENSIVE_CHECKS is enabled:

*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function:    _amdgpu_cs_main
- v. register: %44

LGTM

LGTM - thank @courbet

rebase

Refreshed with tests for RHS Identity shuffles

In D47986#1128533, @spatel wrote:

We should fold these in InstSimplify, so assigning a zero cost seems appropriate, but that raises the question: who's creating these? Couldn't they call llvm::SimplifyShuffleVectorInst() and short-circuit the problem?

@craig.topper What do you want to do for the avx512 equivalents in X86IntrinsicsInfo.h

Thanks - this fixes PR37759

LGTM with a few final minor corrections.

Nice! A couple of minors - but almost there I reckon.

The tests probably need committing with trunk's current codegen, so this patch then shows the diff.

LGTM - thanks.

In D45806#1109593, @RKSimon wrote:

@zvi Any movement on this? I can commandeer if you're still busy.

We're going to need more codegen tests on the llvm side - test coverage (fast-isel and intrinsics) isn't great. But LGTM on the clang side.

LGTM @efriedma any more comments?

LGTM (as long as you don't forget about the lost AVX1 improvements and the AVX2 slt_zero_fp_select regression!)

In D47766#1124959, @avt77 wrote:

9>>! In D47766#1124708, @RKSimon wrote:

I really don't like the idea of a separate file - I think the models need to stay self contained. @courbet 's approach in D47763 seems a lot tidier

As I remember there was a discussion about a possibility to use some "common" possibility to mark unsupported/default features w/o necessity to repeat those unsupported features in all models. The idea was to put such things in some place and to "inherit" or "redefine" them. I tried to implement this behaviour in this patch: we should not repeat description of unsupported features inside every model; we should simply include some file(s) with common description of those features.

On the other hand I see now X86WriteResUnsupported/X86WriteResPairUnsupported in D47763 and I like it for unsupported resources. Because of that I'm going to close this review.

LGTM with one minor - thanks.

@evandro Does AArch64SchedExynosM1.td and AArch64SchedThunderX2T99.td look correct now please?