Please can you add tests for the intel-syntax acquire/release as well?

Thanks for reducing this, LGTM with one minor. Also, as this is just a refactor at this point (make sure you rephrase the commit summary accordingly btw) you can probably drop the test case as its not doing anything any more.

Since its the only other AMD model, please can you add the SSE4A values?

I don't have time to finish this off, but this further reduced version of the test case appears to still show the same issue - please can you confirm (and possibly see if you further reduce it)?

define amdgpu_ps void @main() local_unnamed_addr {
.entry:
  br i1 undef, label %bb12, label %bb

LGTM

LGTM

Given its limited use I don't see why we shouldn't just update the existing isFPExtFree to take Opcode, SrcVT and DstVT - all of which may be useful.

Adding people from D36711

Also, again the tests looks more complex than they should need to be for slpvectorizer

Please can you commit reorder.ll to trunk now with the current trunk codegen, and update the patch so it shows the delta?

In D36581#839584, @dbabokin wrote:

In D36581#838767, @niravd wrote:

I also have a patch that more aggressively causes invalidation-based assertions where latent bugs may lie; I think it'll catch the lion share of the latent bugs.

Let me know if you need to run assertion patch through random testing (which finds all this cases I'm filing as bugs).

No more comments from me

LGTM too

Please don't forget to include llvm-commits as a subscriber

LGTM

LGTM

LGTM

LGTM with a couple of minors

We also need to support matching horizontal binops from target shuffles in order to convert the final operation to HADD.

LGTM - one minor

Thanks for the new tests - a few minor remarks.

In D36645#839910, @craig.topper wrote:

Looks like it fixes PR33229. Probably will fix PR24943, PR22571 as well.

Is this PR33229?

@jbhateja Sorry for the delay - I highly recommend that you request commit rights yourself

In D36638#839669, @craig.topper wrote:

I also wonder if this interface shouldn't take the source type as input. In case some other target has multiple legal vector sizes but can't extract a quarter of vector like x86 can.

@niravd Anything stopping this going in?

@niravd Anything stopping this going in?

LGTM, thanks

LGTM

As discussed offline, the test cases need to be much simpler

Do you think we should make SUBV_BROADCAST a memory intrinsic? Maybe BROADCAST as well, although that has reg implementations and splitting it into two may be awkward.

LGTM - thanks

@dorit I've implemented most of the x86 single source shuffle costs at rL310632, please can you see if this has improved things for you?

LGTM. The duplication between this and FoldConstantVectorArithmetic suggests that a merging is overdue - add a TODO comment?

Thanks, LGTM

LGTM, with one minor.

Test cases?

I think its almost there now, my only concern is that we're not discriminating between signed/unsigned in getMinMaxReductionCost calls - e.g. SSE is very inconsistent with support for these.

@dim What effect does this patch have on PR34080? The changes in pr34080.ll aren't looking hopeful

Is there a suitable repro test from PR34073 that you can add?

Updated with second test that simplifies the mask based on both shuffle inputs (note: further improvements are possible on this shuffle in future patches).

LGTM

In D35846#833693, @coby wrote:

In D35846#827607, @craig.topper wrote:

Is this consistent with GNU assembler behavior? Or does GNU assembler accept both versions?

Both, as do we, via this change