FWICT from the discussion on D57888, doesn't that mean the problem is really in the commutation code and we should be fixing that?

The patch has rotted and needs rewriting, but putting in an assert causes hits in these tests:

Failing Tests (16):
    LLVM :: CodeGen/AMDGPU/copy-illegal-type.ll
    LLVM :: CodeGen/AMDGPU/cvt_f32_ubyte.ll
    LLVM :: CodeGen/AMDGPU/flat_atomics_i64.ll
    LLVM :: CodeGen/AMDGPU/global_atomics_i64.ll
    LLVM :: CodeGen/AMDGPU/load-constant-i1.ll
    LLVM :: CodeGen/AMDGPU/load-constant-i16.ll
    LLVM :: CodeGen/AMDGPU/load-global-i1.ll
    LLVM :: CodeGen/AMDGPU/load-global-i16.ll
    LLVM :: CodeGen/AMDGPU/load-local-i1.ll
    LLVM :: CodeGen/AMDGPU/load-local-i16.ll
    LLVM :: CodeGen/AMDGPU/max.i16.ll
    LLVM :: CodeGen/AMDGPU/min.ll
    LLVM :: CodeGen/AMDGPU/select.f16.ll
    LLVM :: CodeGen/AMDGPU/selectcc.ll
    LLVM :: CodeGen/AMDGPU/v_madak_f16.ll
    LLVM :: CodeGen/X86/vector-intrinsics.ll

If possible please can you use one of these to show a codegen change? I tried the x86 test but didn't find anything.

LGTM

Here you're making more use of the domain pass to reduce isel patterns, but in rL354511 you added isel patterns to avoid the load folding pass - what's the difference?

LGTM

LGTM, cheers

@deadalnix Please can you rebase this?

LGTM

@kparzysz Do we still need this? Does the IR funnel shift work that @spatel did last year make this redundant?

@dlj @sammccall I think I've fixed the root issue now (rL354358) - please reply on this ticket if there are any more issues. Cheers!

@craig.topper Any comments?

LGTM once D57825 lands

ping?

cheers - I tried that but it had stayed red - I don't know what it is about that bot but it acts up a lot......

LGTM - cheers

@craig.topper This appears to breaking some buildbots:

Missing context.

LGTM - cheers.

In D58181#1399533, @spatel wrote:

Better to stage this in 2 parts?
I can add a check for fast-variable-shuffle, so we get the clear improvements. Then, a follow-up can remove that check and see if that results in any real-world fallout.

@hfinkel @MatzeB Any comments?

LGTM with one minor

@jkorous This is failing on windows buildbots - do you have a fix or shall I revert?

Intel targets tend to only accept vector shifts on Port0, while vector logic can use Port0/1/5 - not sure how much of an issue that would be @craig.topper ? Some AMD targets are almost as bad while others (Jaguar) can issue vector immediate shifts to any vector integer pipe.

LGTM with a couple of minors

Thanks @sammccall I've been able to repro it now.

Adding @nikic as there's crossover with D58006

Let's try this again....

I hate Mondays - closing this again as its the wrong patch........

Reopening as it was reverted at rL353699 due to a rather weird regression.....

LGTM

In D57317#1390578, @deadalnix wrote:

@RKSimon This can go now, but has no effect in isolation in any of the test cases I have, mainly because DAGCombine is fairly powerless when faced with addcarry as most of the work involve 'deep' patterns. Do you think I should land anyways ?