RKSimon (Simon Pilgrim)
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User Since
May 5 2014, 7:26 AM (232 w, 1 d)

Recent Activity

Today

RKSimon committed rL344602: [LegalizeDAG] ExpandLegalINT_TO_FP - cleanup UINT_TO_FP i64 -> f64 expansion..
[LegalizeDAG] ExpandLegalINT_TO_FP - cleanup UINT_TO_FP i64 -> f64 expansion.
Tue, Oct 16, 3:08 AM
RKSimon committed rL344600: [X86] Fix Skylake ReadAfterLd for PADDrm etc..
[X86] Fix Skylake ReadAfterLd for PADDrm etc.
Tue, Oct 16, 2:52 AM
RKSimon committed rC344598: Fix buildbots - update clang-interpreter to use Legacy ORC classes introduced….
Fix buildbots - update clang-interpreter to use Legacy ORC classes introduced…
Tue, Oct 16, 2:24 AM
RKSimon committed rL344598: Fix buildbots - update clang-interpreter to use Legacy ORC classes introduced….
Fix buildbots - update clang-interpreter to use Legacy ORC classes introduced…
Tue, Oct 16, 2:23 AM

Yesterday

RKSimon committed rL344554: [AARCH64] Improve vector popcnt lowering with ADDLP.
[AARCH64] Improve vector popcnt lowering with ADDLP
Mon, Oct 15, 2:18 PM
RKSimon closed D53259: [AARCH64] Improve vector popcnt lowering with ADDLP.
Mon, Oct 15, 2:18 PM
RKSimon added inline comments to D53258: [LegalizeDAG] Add generic vector CTPOP expansion (PR32655) (WIP).
Mon, Oct 15, 2:15 PM
RKSimon committed rL344512: [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281).
[ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)
Mon, Oct 15, 6:22 AM
RKSimon closed D53257: [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281).
Mon, Oct 15, 6:22 AM
RKSimon added inline comments to D53257: [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281).
Mon, Oct 15, 4:10 AM

Sun, Oct 14

RKSimon committed rL344484: [InstCombine] Add PR27343 test cases.
[InstCombine] Add PR27343 test cases
Sun, Oct 14, 1:16 PM
RKSimon created D53259: [AARCH64] Improve vector popcnt lowering with ADDLP.
Sun, Oct 14, 11:49 AM
RKSimon updated the diff for D53257: [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281).

Turns out the CTTZ custom lowering was already using this pattern.

Sun, Oct 14, 11:13 AM
RKSimon committed rL344481: [X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8….
[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8…
Sun, Oct 14, 10:36 AM
RKSimon committed rL344479: [ARM] Regenerate cttz tests.
[ARM] Regenerate cttz tests
Sun, Oct 14, 9:51 AM
RKSimon created D53258: [LegalizeDAG] Add generic vector CTPOP expansion (PR32655) (WIP).
Sun, Oct 14, 9:17 AM
RKSimon committed rL344477: [LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP. .
[LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP.
Sun, Oct 14, 8:58 AM
RKSimon created D53257: [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281).
Sun, Oct 14, 8:47 AM
RKSimon added a reviewer for D52779: AMD BdVer2 (Piledriver) Initial Scheduler model: GGanesh.

Adding Ganesh at AMD who might have some insights.

Sun, Oct 14, 4:25 AM

Sat, Oct 13

RKSimon accepted D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine.

LGTM with one minor query - cheers

Sat, Oct 13, 3:18 PM
RKSimon committed rL344466: [AARCH64] Regenerate popcnt tests.
[AARCH64] Regenerate popcnt tests
Sat, Oct 13, 2:52 PM
RKSimon committed rL344465: [ARM] Regenerate popcnt tests.
[ARM] Regenerate popcnt tests
Sat, Oct 13, 2:34 PM
RKSimon added a comment to D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine.

The only issue I can see is the PANDN -> XOR+PSRL change from allbits/comparison results - is this something we want to fix before/after this patch?

Sat, Oct 13, 12:47 PM
RKSimon accepted D53173: [X86] Type legalize v2f32 stores by widening to v4f32, casting to v2f64, extracting f64 and storing..

LGTM - cheers

Sat, Oct 13, 11:56 AM
RKSimon committed rL344461: Pull out repeated variables from SelectionDAGLegalize::ExpandBitCount..
Pull out repeated variables from SelectionDAGLegalize::ExpandBitCount.
Sat, Oct 13, 11:43 AM
RKSimon committed rL344457: [X86][SSE] Remove most of vector CTTZ custom lowering and use LegalizeDAG….
[X86][SSE] Remove most of vector CTTZ custom lowering and use LegalizeDAG…
Sat, Oct 13, 9:13 AM
RKSimon committed rL344453: [X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG….
[X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG…
Sat, Oct 13, 8:19 AM
RKSimon committed rL344452: [X86][SSE] combineIncDecVector - use isConstantSplat.
[X86][SSE] combineIncDecVector - use isConstantSplat
Sat, Oct 13, 7:49 AM
RKSimon committed rL344451: [X86] Pull out target constant splat helper function. NFCI..
[X86] Pull out target constant splat helper function. NFCI.
Sat, Oct 13, 7:31 AM
RKSimon committed rL344450: Pull out repeated getOperand(). NFCI..
Pull out repeated getOperand(). NFCI.
Sat, Oct 13, 6:36 AM
RKSimon committed rL344449: Remove unused variable. NFCI..
Remove unused variable. NFCI.
Sat, Oct 13, 6:32 AM
RKSimon committed rL344448: [X86][SSE] Improve CTTZ lowering when CTLZ is legal.
[X86][SSE] Improve CTTZ lowering when CTLZ is legal
Sat, Oct 13, 6:07 AM
RKSimon committed rL344447: [X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1)).
[X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1))
Sat, Oct 13, 5:14 AM
RKSimon closed D53214: [X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1)).
Sat, Oct 13, 5:14 AM
RKSimon added inline comments to D53173: [X86] Type legalize v2f32 stores by widening to v4f32, casting to v2f64, extracting f64 and storing..
Sat, Oct 13, 5:08 AM
RKSimon accepted D53232: [LegalizeTypes] Prevent an assertion from PromoteIntRes_BSWAP and PromoteIntRes_BITREVERSE if the shift amount is too large for the VT returned by getShiftAmountTy.

LGTM

Sat, Oct 13, 5:01 AM
RKSimon committed rL344446: [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles….
[X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles…
Sat, Oct 13, 4:41 AM
RKSimon closed D53148: [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (PR39161).
Sat, Oct 13, 4:41 AM

Fri, Oct 12

RKSimon updated the diff for D53148: [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (PR39161).

Fixed SmallVector<> LaneMask

Fri, Oct 12, 1:29 PM
RKSimon added inline comments to D53148: [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (PR39161).
Fri, Oct 12, 1:29 PM
RKSimon created D53214: [X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1)).
Fri, Oct 12, 1:11 PM
RKSimon added a comment to rL344365: [tests] Readd Python binding tests to check-all.

Do you have any clue how to solve this? Or should I just if() the tests out of Windows?

Fri, Oct 12, 12:59 PM
RKSimon updated subscribers of rL344365: [tests] Readd Python binding tests to check-all.

@mgorny I'm sorry but I had to revert this to try and get the windows buildbots green :

Fri, Oct 12, 12:50 PM
RKSimon committed rC344408: Revert rL344365: [tests] Readd Python binding tests to check-all.
Revert rL344365: [tests] Readd Python binding tests to check-all
Fri, Oct 12, 12:48 PM
RKSimon committed rL344408: Revert rL344365: [tests] Readd Python binding tests to check-all.
Revert rL344365: [tests] Readd Python binding tests to check-all
Fri, Oct 12, 12:48 PM
RKSimon added a reverting commit for rL344365: [tests] Readd Python binding tests to check-all: rL344408: Revert rL344365: [tests] Readd Python binding tests to check-all.
Fri, Oct 12, 12:48 PM
RKSimon committed rL344402: Fix Wdocumentation warning. NFCI..
Fix Wdocumentation warning. NFCI.
Fri, Oct 12, 12:32 PM
RKSimon committed rL344400: Fix a clang::driver::ArgStringList usage I missed in rL344398. NFCI..
Fix a clang::driver::ArgStringList usage I missed in rL344398. NFCI.
Fri, Oct 12, 12:16 PM
RKSimon committed rC344400: Fix a clang::driver::ArgStringList usage I missed in rL344398. NFCI..
Fix a clang::driver::ArgStringList usage I missed in rL344398. NFCI.
Fri, Oct 12, 12:16 PM
RKSimon added a comment to D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine.

Entirely getting rid of the BITCASTs around logic ops (including X86ISD::ANDNP) would be wonderful - we miss a bit of reassociation later on because of this as well.

Fri, Oct 12, 12:10 PM
RKSimon committed rL344399: Regenerate test. NFCI..
Regenerate test. NFCI.
Fri, Oct 12, 12:05 PM
RKSimon committed rL344398: Consistently make llvm::opt::ArgStringList usage explicit to try and appease….
Consistently make llvm::opt::ArgStringList usage explicit to try and appease…
Fri, Oct 12, 11:57 AM
RKSimon committed rC344398: Consistently make llvm::opt::ArgStringList usage explicit to try and appease….
Consistently make llvm::opt::ArgStringList usage explicit to try and appease…
Fri, Oct 12, 11:57 AM
RKSimon committed rL344390: Fix MCBTF string array initialization so its MSVC friendly. NFCI..
Fix MCBTF string array initialization so its MSVC friendly. NFCI.
Fri, Oct 12, 11:12 AM
RKSimon accepted D53037: [InstCombine] combine a shuffle and an extract subvector shuffle .

LGTM - cheers

Fri, Oct 12, 10:33 AM
RKSimon committed rL344355: Pull out repeated value types. NFCI..
Pull out repeated value types. NFCI.
Fri, Oct 12, 8:51 AM
RKSimon committed rL344354: Pull out repeated value types. NFCI..
Pull out repeated value types. NFCI.
Fri, Oct 12, 8:50 AM
RKSimon committed rL344352: Fix MSVC 2015 ambiguous symbol warning introduced by rL344337. NFCI..
Fix MSVC 2015 ambiguous symbol warning introduced by rL344337. NFCI.
Fri, Oct 12, 8:18 AM
RKSimon committed rC344352: Fix MSVC 2015 ambiguous symbol warning introduced by rL344337. NFCI..
Fix MSVC 2015 ambiguous symbol warning introduced by rL344337. NFCI.
Fri, Oct 12, 8:18 AM
RKSimon committed rL344349: [SelectionDAG] Move VectorLegalizer::ExpandCTLZ codegen into….
[SelectionDAG] Move VectorLegalizer::ExpandCTLZ codegen into…
Fri, Oct 12, 7:48 AM
RKSimon committed rL344348: [X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage. .
[X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage.
Fri, Oct 12, 7:20 AM
RKSimon committed rL344341: [X86][AVX] Regenerate tzcnt tests.
[X86][AVX] Regenerate tzcnt tests
Fri, Oct 12, 6:26 AM
RKSimon committed rL344336: [X86][SSE] Add extract_subvector(PSHUFB) -> PSHUFB(extract_subvector()) combine.
[X86][SSE] Add extract_subvector(PSHUFB) -> PSHUFB(extract_subvector()) combine
Fri, Oct 12, 5:12 AM
RKSimon committed rC344333: Fix Wdocumentation warning. NFCI..
Fix Wdocumentation warning. NFCI.
Fri, Oct 12, 3:36 AM
RKSimon committed rL344333: Fix Wdocumentation warning. NFCI..
Fix Wdocumentation warning. NFCI.
Fri, Oct 12, 3:36 AM
RKSimon accepted D52912: [SelectionDAG] allow FP binops in SimplifyDemandedVectorElts.

LGTM although may need to be rebased after D53095 lands

Fri, Oct 12, 3:33 AM
RKSimon committed rL344332: [X86][AVX] Add examples of shuffles that can be reduced to a cross-lane shuffle….
[X86][AVX] Add examples of shuffles that can be reduced to a cross-lane shuffle…
Fri, Oct 12, 3:29 AM
RKSimon committed rL344331: [X86] Ignore float/double non-temporal loads (PR39256).
[X86] Ignore float/double non-temporal loads (PR39256)
Fri, Oct 12, 3:22 AM

Thu, Oct 11

RKSimon added a comment to D52293: [TLI][X86][AArch64] Generalize isDesirableToCommuteWithShift() hook and enable for X86.

Abandon this?

Thu, Oct 11, 2:04 PM
RKSimon accepted D53134: [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen..

LGTM - apart from 2 different names for the same thing and @mattd's minors

Thu, Oct 11, 11:43 AM
RKSimon created D53148: [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (PR39161).
Thu, Oct 11, 10:24 AM
RKSimon added inline comments to D53134: [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen..
Thu, Oct 11, 10:11 AM
RKSimon resigned from D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
Thu, Oct 11, 8:56 AM
RKSimon accepted D53095: [x86] add and use fast horizontal vector math subtarget feature.

LGTM too

Thu, Oct 11, 8:55 AM
RKSimon accepted D52528: [X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector..

LGTM as long as all the regressions are documented somewhere so we don't lose track

Thu, Oct 11, 4:19 AM
RKSimon updated subscribers of rL344211: [WebAssembly][NFC] Use intrinsic dag nodes directly.

@tlively This is failing on EXPENSIVE_CHECKS builds please can you take a look:

Thu, Oct 11, 3:47 AM
RKSimon accepted D53126: [X86] Restore X86ISelDAGToDAG::matchBEXTRFromAnd. Teach address matching to create a BEXTR pattern from a (shl (and X, mask >> C1) if C1 can be folded into addressing mode..

LGTM

Thu, Oct 11, 2:25 AM

Wed, Oct 10

RKSimon added a comment to D53022: [SelectionDAG] Enable iX SimplifyDemandedBits to vXi1 SimplifyDemandedVectorElts simplification.

I haven't looked into this yet but I'm hoping this can be fixed by reusing the isTypePromotionOfi1ZeroUpBits code somehow.

Wed, Oct 10, 8:42 AM
RKSimon accepted D52426: [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering.

LGTM - thanks

Wed, Oct 10, 8:12 AM
RKSimon committed rL344138: [TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI..
[TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI.
Wed, Oct 10, 6:03 AM
RKSimon added a comment to D52426: [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering.

I'm a bit worried about these test changes - I thought this patch was about moving the existing code, not altering the pattern matching features.

Wed, Oct 10, 5:44 AM
RKSimon committed rL344136: [TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI..
[TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI.
Wed, Oct 10, 5:34 AM
RKSimon added inline comments to D52426: [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering.
Wed, Oct 10, 4:33 AM
RKSimon added a reviewer for D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor: arsenm.
Wed, Oct 10, 4:01 AM
RKSimon resigned from D52967: Extend shelf-life by 70 years.

Sorry I'm not the right person to review this - adding some other potentials

Wed, Oct 10, 3:50 AM
RKSimon committed rL344132: [TargetLowering] Add root node back to work list after successful….
[TargetLowering] Add root node back to work list after successful…
Wed, Oct 10, 3:46 AM
RKSimon closed D53026: [TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts.
Wed, Oct 10, 3:46 AM

Tue, Oct 9

RKSimon accepted D52997: [x86] allow single source horizontal op matching (PR39195).

LGTM - thanks

Tue, Oct 9, 10:04 AM
RKSimon created D53026: [TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts.
Tue, Oct 9, 10:04 AM
RKSimon added inline comments to D49200: [DAGCombine] Improve Load-Store Forwarding.
Tue, Oct 9, 9:12 AM
RKSimon accepted D52747: [InstCombine] reverse 'trunc X to <N x i1>' canonicalization.

LGTM - thanks

Tue, Oct 9, 8:02 AM
RKSimon created D53022: [SelectionDAG] Enable iX SimplifyDemandedBits to vXi1 SimplifyDemandedVectorElts simplification.
Tue, Oct 9, 7:16 AM
RKSimon added a comment to D52747: [InstCombine] reverse 'trunc X to <N x i1>' canonicalization.

Now that D52964 has landed - is there anything stopping this?

Tue, Oct 9, 7:11 AM
RKSimon committed rL344043: [SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to….
[SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to…
Tue, Oct 9, 6:15 AM
RKSimon accepted D52964: [x86] use demanded bits to simplify masked store codegen.

LGTM - the AVX1 regression needs SIGN_EXTEND_VECTOR_INREG support adding to SimplifyDemandedBits which I intend to do as a follow up patch

Tue, Oct 9, 5:27 AM
RKSimon added a comment to D52997: [x86] allow single source horizontal op matching (PR39195).

So 2 options for moving forward:

  1. Allow this transform as shown here because it is mostly just restoring the behavior of last week. Follow that up with a subtarget feature to prevent the transform (not ideal, but the alternative 'undo' is much harder).
  2. Limit this transform to 'optsize' right now because it's a size win in all cases.
Tue, Oct 9, 5:26 AM
RKSimon added a comment to D52964: [x86] use demanded bits to simplify masked store codegen.

Also, I confirmed that the combination of this patch + D52980 will remove the extra AVX1 shift from masked_store_bool_mask_demand_trunc_sext().

Tue, Oct 9, 12:54 AM
RKSimon committed rL344019: [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors.
[X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors
Tue, Oct 9, 12:45 AM
RKSimon closed D52980: [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors.
Tue, Oct 9, 12:44 AM

Mon, Oct 8

RKSimon added a reviewer for D52997: [x86] allow single source horizontal op matching (PR39195): andreadb.
Mon, Oct 8, 2:42 PM