♟ RKSimon

[X86][SSE] Add SSE vector imm/var shift support to…

[X86][SSE] Fix all remaining modulo vector rotation amounts (PR38243)

[X86][SSE] Fix modulo rotation amounts for v8i16/v16i16/v4i32 (PR38243)

[X86][SSE] Merge the vXi16/vXi32 vector rotation expansion cases. NFCI.

[X86][BWI] Don't custom lower vXi8 rotations.

[DAGCombine] Moved X86 rotate_amount % bitwidth == 0 early out to DAGCombiner

[TargetLowering] Add ISD::ROTL/ROTR vector expansion

[X86] Added missing constant pool checks. NFCI.

Fix Wdocumentation warning. NFCI.

[X86] Added missing constant pool checks. NFCI.

[SelectionDAG] Add a generic isSplatValue function

Thanks - this approach makes more sense to me. @craig.topper @MatzeB Any other comments?

Addressed @andreadb's comments

I've generalized https://bugs.llvm.org/show_bug.cgi?id=34232 to cover all possible cases where we should/could use MULX

[TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts

Regenerate knownbits test. NFCI.

In D55414#1327263, @craig.topper wrote:

How should we proceed here? Can we commit this patch and file a bug for AMD improvements?

What do you want to do about the tests (I think just psubus.ll and avx512-regcall-NoMask.ll) that show an increase in moves?

[TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBits

Fix "not all control paths return a value" MSVC warnings. NFCI.

Cheers - @andreadb @craig.topper do you have any comments?

[TargetLowering] Add UNDEF folding to SimplifyDemandedVectorElts

[DAGCombiner] Remove unnecessary recursive DAGCombiner::visitINSERT_SUBVECTOR…

In D54278#1325013, @craig.topper wrote:

I'm happy to abandon this.

[X86] Extend pfm counter coverage for llvm-exegesis

In D54278#1303494, @craig.topper wrote:

Removing any of the constant folding code in X86 requires committing D54276 first so that we can still see constant MULH inputs as build_vectors and DAG combine them that way. With MULH lowering happening during DAG legalization we don't get a chance to constant fold until they have been turned into constant pool entries and that requires target specific constant folding.

In D38028#1324542, @thakis wrote:

In D38028#1324522, @craig.topper wrote:

You're correct, nothing sets it. I'm nervous about ever using the autogenerated table by default. I've used it a while back to copy entries into the manual tables. But I had to add more waivers and adjustments to fix bugs in the autogenerated table in the process. I don't think they are still a perfect match. I worry that if we switch to the autogenerated table and as we add new instructions in the future we can silently introduce bugs because the new table entries weren't reviewed.

Should we remove the autogenerated table again then?

Fix unused variable warning. NFCI.

[X86] Replace instregex with instrs list. NFCI.

[llvm-mca][x86] Add RDSEED instruction resource tests for GLM

[llvm-mca][x86] Add missing AES instruction resource tests

[llvm-mca][x86] Add RDRAND/RDSEED instruction resource tests

[X86] Improve pfm counter coverage for llvm-exegesis

In D55432#1323115, @lebedev.ri wrote:

The plan is to only add these mappings, and encourage people to come up with new sched profiles,
or is the auto-sched-profile-generation upcoming?

Use getConstantOperandVal where possible

Fix gcc7.3 -Wparentheses warning. NFCI.

@Higuoxing I'm seeing build failures because ELFYAML::VersionNeedSection is not defined - please revert and recommit with the missing definition.

[X86] Add ivybridge to llvm-exegesis PFM counter mappings

[SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR

LGTM - thanks. If you have concerns that the isel pattern is still used anywhere, I'm fine with it staying with a suitable FIXME comment.

Fix Wdocumentation warning. NFCI.

LGTM - I'll commit shortly but please make sure you've requested commit access

[X86] Refactored IsSplatVector to use switch. NFCI.

DAGCombiner::visitINSERT_VECTOR_ELT - pull out repeated VT.getVectorNumElements…

This looks ok, but I know very little about this pass - @MatzeB @craig.topper any comments?

Fix -Wcovered-switch-default warning. NFCI.

This addresses a FIXME and avoids depending on an isel pattern match I think.

[X86][SSE] Fix a copy+paste typo that was folding the sext/zext of partial…

Also, its probably worth doing the initial simplifyConcatVectors refactor as a NFC

[X86][SSE] Begun adding modulo rotate support to LowerRotate

[TargetLowering] Remove ISD::ANY_EXTEND/ANY_EXTEND_VECTOR_INREG opcodes from…

[DAG] Add fshl/fshr tblgen opcodes

[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)

Remove superfluous comments. NFCI.

[TargetLowering] SimplifyDemandedVectorElts - don't alter DemandedElts mask

[X86][SSE] Add SimplifyDemandedBitsForTargetNode handling for MOVMSK

Maybe call the test file combine-concatvectors.ll ? That matches the other filenames we have.

[X86][SSE] Add MOVMSK demandedbits/elts tests

Add common check prefix. NFCI.

@dtemirbulatov Any movement on this? It'd be great to get this in for the 8.0 release!

RKSimon (Simon Pilgrim)
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