♟ RKSimon

[LegalizeDAG] ExpandLegalINT_TO_FP - cleanup UINT_TO_FP i64 -> f64 expansion.

[X86] Fix Skylake ReadAfterLd for PADDrm etc.

Fix buildbots - update clang-interpreter to use Legacy ORC classes introduced…

[AARCH64] Improve vector popcnt lowering with ADDLP

[ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)

[InstCombine] Add PR27343 test cases

Turns out the CTTZ custom lowering was already using this pattern.

[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8…

[ARM] Regenerate cttz tests

[LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP.

Adding Ganesh at AMD who might have some insights.

LGTM with one minor query - cheers

[AARCH64] Regenerate popcnt tests

[ARM] Regenerate popcnt tests

The only issue I can see is the PANDN -> XOR+PSRL change from allbits/comparison results - is this something we want to fix before/after this patch?

Pull out repeated variables from SelectionDAGLegalize::ExpandBitCount.

[X86][SSE] Remove most of vector CTTZ custom lowering and use LegalizeDAG…

[X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG…

[X86][SSE] combineIncDecVector - use isConstantSplat

[X86] Pull out target constant splat helper function. NFCI.

Pull out repeated getOperand(). NFCI.

Remove unused variable. NFCI.

[X86][SSE] Improve CTTZ lowering when CTLZ is legal

[X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1))

[X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles…

Fixed SmallVector<> LaneMask

In rL344365#292490, @mgorny wrote:

Do you have any clue how to solve this? Or should I just if() the tests out of Windows?

@mgorny I'm sorry but I had to revert this to try and get the windows buildbots green :

Revert rL344365: [tests] Readd Python binding tests to check-all

Fix Wdocumentation warning. NFCI.

Fix a clang::driver::ArgStringList usage I missed in rL344398. NFCI.

Entirely getting rid of the BITCASTs around logic ops (including X86ISD::ANDNP) would be wonderful - we miss a bit of reassociation later on because of this as well.

Regenerate test. NFCI.

Consistently make llvm::opt::ArgStringList usage explicit to try and appease…

Fix MCBTF string array initialization so its MSVC friendly. NFCI.

Pull out repeated value types. NFCI.

Fix MSVC 2015 ambiguous symbol warning introduced by rL344337. NFCI.

[SelectionDAG] Move VectorLegalizer::ExpandCTLZ codegen into…

[X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage.

[X86][AVX] Regenerate tzcnt tests

[X86][SSE] Add extract_subvector(PSHUFB) -> PSHUFB(extract_subvector()) combine

Fix Wdocumentation warning. NFCI.

LGTM although may need to be rebased after D53095 lands

[X86][AVX] Add examples of shuffles that can be reduced to a cross-lane shuffle…

[X86] Ignore float/double non-temporal loads (PR39256)

LGTM - apart from 2 different names for the same thing and @mattd's minors

LGTM as long as all the regressions are documented somewhere so we don't lose track

@tlively This is failing on EXPENSIVE_CHECKS builds please can you take a look:

I haven't looked into this yet but I'm hoping this can be fixed by reusing the isTypePromotionOfi1ZeroUpBits code somehow.

[TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI.

I'm a bit worried about these test changes - I thought this patch was about moving the existing code, not altering the pattern matching features.

[TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI.

Sorry I'm not the right person to review this - adding some other potentials

[TargetLowering] Add root node back to work list after successful…

Now that D52964 has landed - is there anything stopping this?

[SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to…

LGTM - the AVX1 regression needs SIGN_EXTEND_VECTOR_INREG support adding to SimplifyDemandedBits which I intend to do as a follow up patch

In D52997#1258717, @spatel wrote:

So 2 options for moving forward:

Allow this transform as shown here because it is mostly just restoring the behavior of last week. Follow that up with a subtarget feature to prevent the transform (not ideal, but the alternative 'undo' is much harder).

Limit this transform to 'optsize' right now because it's a size win in all cases.

In D52964#1257755, @spatel wrote:

Also, I confirmed that the combination of this patch + D52980 will remove the extra AVX1 shift from masked_store_bool_mask_demand_trunc_sext().

[X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors

RKSimon (Simon Pilgrim)
User

Projects

User Details

Recent Activity
View All

Today

Yesterday

Sun, Oct 14

Sat, Oct 13

Fri, Oct 12

Thu, Oct 11

Wed, Oct 10

Tue, Oct 9

Mon, Oct 8

RKSimon (Simon Pilgrim)User