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- May 5 2014, 7:26 AM (215 w, 14 h)
Please can you LAHF/SAHF tests to the resources-x86_64.s llvm-mca test files
Is there any llvm side fast isel tests for these?
Would it be better to implement m_APInt_or_Undef and m_APFloat_or_Undef - explaining that the undef is only for vectors (and naturally must still contain at least one APInt).
@asb What's the plan for this patch?
Can anyone recommend the best shuffle costs to put here for the 32/64 cases?
I haven't had a chance to go through this yet, but it'd be useful to be able to call these through ArrayRef<int> style shuffle masks (see the TODO I added for SLP to D48023)
Fri, Jun 15
LGTM as well
Should there be some AVX512VL tests? We don't have any scheduler that can test XOP instructions AFAICT (unless we want to cheat and use SandyBridge in its role as the generic model).
Abandon this? D47763 took this patch's idea for a UnsupportedWriteResPair multiclass but kept the unsupported classes in target's scheduler td file.
@courbet What's the plan for this phab?
@niravd This is failing on EXPENSIVE_CHECKS builds - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/10278
Thu, Jun 14
Simplified SK_Select pattern matching
Wed, Jun 13
@kparzysz This is failing when EXPENSIVE_CHECKS is enabled:
*** Bad machine code: Virtual register defs don't dominate all uses. *** - function: _amdgpu_cs_main - v. register: %44
LGTM - thank @courbet
Tue, Jun 12
Refreshed with tests for RHS Identity shuffles
Mon, Jun 11
@craig.topper What do you want to do for the avx512 equivalents in X86IntrinsicsInfo.h
Thanks - this fixes PR37759
LGTM with a few final minor corrections.
Nice! A couple of minors - but almost there I reckon.
The tests probably need committing with trunk's current codegen, so this patch then shows the diff.
LGTM - thanks.
Sun, Jun 10
Sat, Jun 9
We're going to need more codegen tests on the llvm side - test coverage (fast-isel and intrinsics) isn't great. But LGTM on the clang side.
Fri, Jun 8
LGTM @efriedma any more comments?
LGTM (as long as you don't forget about the lost AVX1 improvements and the AVX2 slt_zero_fp_select regression!)
LGTM with one minor - thanks.
@evandro Does AArch64SchedExynosM1.td and AArch64SchedThunderX2T99.td look correct now please?