In D46179#1203852, @jgorbe wrote:

I think this change is breaking one of our builds. The attached reduced test case fails with the current trunk revision if built with "clang -x c -O2 -mavx -c crash.ii".

Fri, Aug 17, 4:25 AM

RKSimon committed rL340010: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding.

[DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding

Fri, Aug 17, 3:53 AM

RKSimon closed D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding.

Fri, Aug 17, 3:53 AM

RKSimon committed rCTE340009: Fix clangd tests on older compilers.

Fix clangd tests on older compilers

Fri, Aug 17, 3:40 AM

RKSimon committed rL340009: Fix clangd tests on older compilers.

Fix clangd tests on older compilers

Fri, Aug 17, 3:40 AM

RKSimon committed rL340006: Fix "control reaches end of non-void function" -Wreturn-type warning. NFCI..

Fix "control reaches end of non-void function" -Wreturn-type warning. NFCI.

Fri, Aug 17, 2:55 AM

Thu, Aug 16

RKSimon added a comment to D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding.

In D35722#1202997, @spatel wrote:

LGTM. I notice we don't fold the non-splat case of this pattern in IR. Do you think it's worth adding there too, or backend is good enough?

Thu, Aug 16, 12:45 PM

RKSimon committed rL339908: [TargetLowering] Add support for non-uniform vectors to BuildSDIV.

[TargetLowering] Add support for non-uniform vectors to BuildSDIV

Thu, Aug 16, 10:45 AM

RKSimon closed D50765: [TargetLowering] Add support for non-uniform vectors to BuildSDIV.

Thu, Aug 16, 10:45 AM

RKSimon added inline comments to D50765: [TargetLowering] Add support for non-uniform vectors to BuildSDIV.

Thu, Aug 16, 10:27 AM

RKSimon added inline comments to D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding.

Thu, Aug 16, 10:24 AM

RKSimon updated the diff for D50781: [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLW.

Remove unnecessary hasBWI()

Thu, Aug 16, 10:22 AM

RKSimon added inline comments to D50781: [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLW.

Thu, Aug 16, 10:21 AM

RKSimon committed rL339901: [X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and all….

[X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and all…

Thu, Aug 16, 10:08 AM

RKSimon updated the diff for D50765: [TargetLowering] Add support for non-uniform vectors to BuildSDIV.

rebased

Thu, Aug 16, 10:02 AM

RKSimon committed rL339898: [TargetLowering] Refactor BuildSDIV in preparation for D50765. NFCI..

[TargetLowering] Refactor BuildSDIV in preparation for D50765. NFCI.

Thu, Aug 16, 9:54 AM

RKSimon committed rL339890: [TableGen] TypeSetByHwMode::operator== optimization.

[TableGen] TypeSetByHwMode::operator== optimization

Thu, Aug 16, 9:17 AM

RKSimon closed D50841: [TableGen] TypeSetByHwMode::operator== optimization.

Thu, Aug 16, 9:17 AM

RKSimon committed rL339888: [TableGen] Avoid self getPredicates() != comparison. NFCI..

[TableGen] Avoid self getPredicates() != comparison. NFCI.

Thu, Aug 16, 9:04 AM

RKSimon committed rL339884: [TableGen] Return ValueTypeByHwMode by const reference from….

[TableGen] Return ValueTypeByHwMode by const reference from…

Thu, Aug 16, 8:30 AM

RKSimon added a reviewer for D50840: [InstCombine] Extend collectShuffleElements to support extract/zext/insert patterns: RKSimon.

Thu, Aug 16, 7:44 AM

RKSimon added a reviewer for D50840: [InstCombine] Extend collectShuffleElements to support extract/zext/insert patterns: ABataev.

It could be the kind of thing we should do in slp @ABataev what do you think?

Thu, Aug 16, 7:43 AM

RKSimon created D50841: [TableGen] TypeSetByHwMode::operator== optimization.

Thu, Aug 16, 7:11 AM

RKSimon committed rL339879: Fixed unused variable warning. NFCI..

Fixed unused variable warning. NFCI.

Thu, Aug 16, 6:56 AM

RKSimon committed rCTE339879: Fixed unused variable warning. NFCI..

Fixed unused variable warning. NFCI.

Thu, Aug 16, 6:56 AM

RKSimon closed D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

Committed at rL339818 (typo in commit message prevented phab from catching it)

Thu, Aug 16, 6:00 AM

RKSimon committed rCTE339866: Attempt to fix clangd tests on older compilers.

Attempt to fix clangd tests on older compilers

Thu, Aug 16, 4:43 AM

RKSimon committed rL339866: Attempt to fix clangd tests on older compilers.

Attempt to fix clangd tests on older compilers

Thu, Aug 16, 4:42 AM

RKSimon committed rL339863: [ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX.

[ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX

Thu, Aug 16, 4:09 AM

RKSimon closed D50777: [ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX.

Thu, Aug 16, 4:09 AM

RKSimon added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

We're seeing tlbgen warnings after this patch:

Thu, Aug 16, 3:27 AM

Wed, Aug 15

RKSimon accepted D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

LGTM - I'll continue investigating how to combine VSELECT with target shuffles to fix that prefer-avx256-mask-shuffle.ll regression.

Wed, Aug 15, 2:05 PM

RKSimon committed rL339812: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode ->….

[TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode ->…

Wed, Aug 15, 1:42 PM

RKSimon closed D50789: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize.

Wed, Aug 15, 1:42 PM

RKSimon added inline comments to D50781: [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLW.

Wed, Aug 15, 11:00 AM

RKSimon added a reviewer for D50789: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize: fhahn.

Wed, Aug 15, 10:19 AM

RKSimon created D50789: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize.

Wed, Aug 15, 10:16 AM

RKSimon accepted D50777: [ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX.

LGTM - thanks

Wed, Aug 15, 8:01 AM

RKSimon created D50781: [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLW.

Wed, Aug 15, 7:46 AM

RKSimon committed rL339767: Remove lambda default argument to fix gcc pedantic warning..

Remove lambda default argument to fix gcc pedantic warning.

Wed, Aug 15, 5:32 AM

RKSimon created D50765: [TargetLowering] Add support for non-uniform vectors to BuildSDIV.

Wed, Aug 15, 4:41 AM

RKSimon committed rL339763: [TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI..

[TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI.

Wed, Aug 15, 4:11 AM

RKSimon committed rL339761: [X86][SSE] Add sdiv by nonuniform constant vector tests.

[X86][SSE] Add sdiv by nonuniform constant vector tests

Wed, Aug 15, 4:00 AM

RKSimon committed rL339758: [TargetLowering] Minor refactor to TargetLowering::BuildUDIV to merge….

[TargetLowering] Minor refactor to TargetLowering::BuildUDIV to merge…

Wed, Aug 15, 3:11 AM

RKSimon committed rL339757: [DagCombiner] Don't bother adding to the work list if TLI.BuildSDIVPow2 failed..

[DagCombiner] Don't bother adding to the work list if TLI.BuildSDIVPow2 failed.

Wed, Aug 15, 3:03 AM

RKSimon committed rL339756: [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV.

[TargetLowering] Add support for non-uniform vectors to BuildExactSDIV

Wed, Aug 15, 2:36 AM

RKSimon closed D50392: [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV.

Wed, Aug 15, 2:35 AM

RKSimon added a comment to D50636: [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds..

@jonpa @pftbest Any more comments?

Wed, Aug 15, 1:48 AM

Tue, Aug 14

RKSimon added inline comments to D50392: [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV.

Tue, Aug 14, 1:05 PM

RKSimon added inline comments to D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

Tue, Aug 14, 12:58 PM

RKSimon added a comment to D50392: [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV.

ping?

Tue, Aug 14, 12:40 PM

RKSimon committed rL339696: [X86][SSE] Avoid duplicate shuffle input sources in….

[X86][SSE] Avoid duplicate shuffle input sources in…

Tue, Aug 14, 10:23 AM

RKSimon added a reviewer for D48193: [LoopVectorizer] Use an interleave count of 1 when using a vector library call: RKSimon.

Tue, Aug 14, 10:06 AM

RKSimon committed rL339686: [X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB) style patterns..

[X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB) style patterns.

Tue, Aug 14, 9:00 AM

RKSimon committed rL339684: [X86][SSE] Add shuffle combine tests for OR(PSHUFB,PSHUFB) style patterns..

[X86][SSE] Add shuffle combine tests for OR(PSHUFB,PSHUFB) style patterns.

Tue, Aug 14, 8:22 AM

RKSimon committed rL339679: [X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any vXi8….

[X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any vXi8…

Tue, Aug 14, 7:00 AM

RKSimon updated the diff for D46276: [CostModel][X86] Derive TTI costs from complete scheduling models (PR36550) (RFC).

Rebased - this patch is still waiting on a fix to MCSubtargetInfo::resolveVariantSchedClass that will return the default class when an MCInst is not available (== NULL) - @andreadb is investigating.

Tue, Aug 14, 6:09 AM

RKSimon added a comment to D50314: M680x0 codegen target.

@m4yers You really need to have this discussed on the llvm-dev mailing list first - adding a new target is not a small matter.

Tue, Aug 14, 5:36 AM

RKSimon committed rL339670: [TableGen] Pass string/vector types by const reference (PR37666). NFCI.

[TableGen] Pass string/vector types by const reference (PR37666). NFCI

Tue, Aug 14, 4:18 AM

RKSimon committed rL339666: Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI..

Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI.

Tue, Aug 14, 3:05 AM

RKSimon added a comment to D50636: [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds..

I'm happy to apply the test changes beforehand once everybody is happy with the patch - but I'll keep them in the diff for now to make its effects clear.

Tue, Aug 14, 1:00 AM

Mon, Aug 13

RKSimon accepted D49574: [CodeGen] Fix ICE in SelectionDAG::computeKnownBits.

LGTM - cheers

Mon, Aug 13, 10:23 AM

RKSimon added inline comments to D50636: [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds..

Mon, Aug 13, 10:07 AM

RKSimon committed rL339584: [InstCombine] Limit simplifyAllocaArraySize constant folding to values that fit….

[InstCombine] Limit simplifyAllocaArraySize constant folding to values that fit…

Mon, Aug 13, 9:51 AM

RKSimon updated subscribers of rL339428: Add Windows support for the GNUstep Objective-C ABI V2..

@theraven We're seeing a test failure in CodeGenObjC/2007-04-03-ObjcEH.m which seems to be from this commit:

Mon, Aug 13, 9:47 AM

RKSimon added a comment to D50636: [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds..

In D50636#1197251, @jonpa wrote:

Not sure if I'm doing something wrong (I use git and tried first patch -p0, and then also with dos2unix, but then that didn't work so I had to write the patch manually although just a few lines...)

Mon, Aug 13, 8:29 AM

RKSimon added a comment to rL339562: [X86] Add tests showing missing div/rem 0, X -> 0 combines.

In rL339562#282787, @xbolva00 wrote:

is this related to https://bugs.llvm.org/show_bug.cgi?id=38479 ?

also maybe..
fold (mul 0, x) -> 0
fold (shifts 0, x) -> 0

Mon, Aug 13, 7:23 AM

RKSimon created D50636: [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds..

Mon, Aug 13, 7:20 AM

RKSimon committed rL339562: [X86] Add tests showing missing div/rem 0, X -> 0 combines.

[X86] Add tests showing missing div/rem 0, X -> 0 combines

Mon, Aug 13, 6:30 AM

RKSimon updated subscribers of rL339551: [Sparc] Add support for the cycle counter available in GR740.

@dcederman @jyknight, this is breaking EXPENSIVE_CHECKS builds. Please can you take a look?

Mon, Aug 13, 6:25 AM

RKSimon committed rL339561: [DAGCombiner] simplifyDivRem - add comment describing divide by undef/zero….

[DAGCombiner] simplifyDivRem - add comment describing divide by undef/zero…

Mon, Aug 13, 6:13 AM

RKSimon committed rCTE339557: Fix MSVC 'std::min: no matching overloaded function found' error..

Fix MSVC 'std::min: no matching overloaded function found' error.

Mon, Aug 13, 5:25 AM

RKSimon committed rL339557: Fix MSVC 'std::min: no matching overloaded function found' error..

Fix MSVC 'std::min: no matching overloaded function found' error.

Mon, Aug 13, 5:25 AM

RKSimon committed rL339556: [CGP] Fix GEP issue with out of range APInt constant values not fitting in….

[CGP] Fix GEP issue with out of range APInt constant values not fitting in…

Mon, Aug 13, 5:10 AM

RKSimon committed rL339549: Remove extra semicolon (fixes -Wpedantic warning). NFCI..

Remove extra semicolon (fixes -Wpedantic warning). NFCI.

Mon, Aug 13, 3:06 AM

Sun, Aug 12

RKSimon added inline comments to D50402: [SelectionDAG][X86] Reorder the operands the MaskedStoreSDNode to put the value first..

Sun, Aug 12, 6:44 AM

RKSimon accepted D50553: [X86] Add constant folding for AVX512 versions of scalar floating point to integer conversion intrinsics..

LGTM

Sun, Aug 12, 6:38 AM

Fri, Aug 10

RKSimon committed rL339425: [X86][SSE] Pull out repeated shift getOpcode() calls. NFCI..

[X86][SSE] Pull out repeated shift getOpcode() calls. NFCI.

Fri, Aug 10, 4:43 AM

RKSimon committed rL339422: Fix -Wimplicit-fallthrough warning introduced in rL339397..

Fix -Wimplicit-fallthrough warning introduced in rL339397.

Fri, Aug 10, 4:03 AM

RKSimon updated subscribers of rL339078: AMDGPU: cvt_pk_rtz_f16 canonicalizes.

Fri, Aug 10, 3:47 AM

RKSimon updated the diff for D35722: [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) folding.

Resurrecting this old patch, refactored to correctly handle overflows of the sum of shifts.

Fri, Aug 10, 3:02 AM

Thu, Aug 9

RKSimon added a reviewer for D41436: [X86][AVX512] Enable variable shuffle combining by default on AVX512 targets: pcordes.

Adding @pcordes who had some comments about SLOW/FAST variable shuffle mask operation for KNL on D50074

Thu, Aug 9, 7:52 AM

RKSimon updated the diff for D50392: [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV.

I've refactored the approach slightly to demonstrate ISD::matchUnaryPredicate being used to iterate over a scalar or the elements of a vector. - this could be used in TargetLowering::BuildUDIV as well to make the equivalent code easier to understand.

Thu, Aug 9, 7:22 AM

RKSimon committed rL339346: [TargetLowering] Add BuildSDIVPattern helper to BuildExactSDIV (NFCI)..

[TargetLowering] Add BuildSDIVPattern helper to BuildExactSDIV (NFCI).

Thu, Aug 9, 6:56 AM

RKSimon added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.

Thu, Aug 9, 6:09 AM