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spatel (Sanjay Patel)
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May 22 2014, 1:24 PM (282 w, 5 d)

Recent Activity

Yesterday

spatel added inline comments to D61917: [IR] allow fast-math-flags on select of FP values.
Tue, Oct 22, 6:01 AM · Restricted Project

Sat, Oct 19

spatel accepted D68930: [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595).

Ignoring the -O3 issue, i'm not really confident AggressiceInstCombine is a great fit for these problems.
The thing is, these folds are not one-off "folds - yay, no fold - shrug".
There isn't much interest in this fold happening in itself.
The really important part is that it will pave the road for other folds to happen.
In particular, this fold will allow e.g. rL373964 to happen.
The situation is likely similar with all other "aggressive" folds i'we added.

Yes, I understand this patch alone doesn't look like a big change.

To recap, the main problem is not that they use InstSimplify,
but that SimplifyAssociativeBinOp() uses recursive reasoning, correct?

Sat, Oct 19, 1:50 PM · Restricted Project
spatel committed rGa298964d22a2: [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold… (authored by spatel).
[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold…
Sat, Oct 19, 9:56 AM
spatel closed D69116: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (1/2).
Sat, Oct 19, 9:56 AM · Restricted Project
spatel committed rL375347: [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold….
[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold…
Sat, Oct 19, 9:56 AM
spatel committed rG0a15981a84b9: [MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC (authored by spatel).
[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Sat, Oct 19, 9:28 AM
spatel closed D69099: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests).
Sat, Oct 19, 9:28 AM · Restricted Project
spatel committed rL375345: [MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC.
[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Sat, Oct 19, 9:28 AM
spatel added a comment to D68930: [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595).

Ignoring the -O3 issue, i'm not really confident AggressiceInstCombine is a great fit for these problems.
The thing is, these folds are not one-off "folds - yay, no fold - shrug".
There isn't much interest in this fold happening in itself.
The really important part is that it will pave the road for other folds to happen.
In particular, this fold will allow e.g. rL373964 to happen.
The situation is likely similar with all other "aggressive" folds i'we added.

Sat, Oct 19, 9:01 AM · Restricted Project
spatel added a comment to D69127: [DAGCombiner] widen zext of popcount based on target support.

This patch would already have hoisted the zext ahead of the i32 ctpop in that basic example, but if we had started with this i32 code, then we'd widen to i64 ctpop because we assume it's no more expensive than i32 ctpop+zext. For the PPC examples, the zext becomes a mask op, so we eliminate that instruction.

Sat, Oct 19, 8:26 AM · Restricted Project
spatel added a comment to D69127: [DAGCombiner] widen zext of popcount based on target support.

So the assumption here is that the popcnt we choose here is the same performance as any smaller popcnt that LegalizeDAG would pick through promotion. Or near enough that its better than having 2 zexts?

Sat, Oct 19, 8:22 AM · Restricted Project

Fri, Oct 18

spatel added a comment to D68930: [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595).

sadly i'm still seeing regressions (although smaller!) in target benchmark, and analysis of IR points to *this* missing pattern

But does this or base pattern shows up somewhere else (test suite/clang/chromium) than in your benchmark?

It's not "'your benchmark'", that is a real code. I'm not pulling it out of a thin air.

Fri, Oct 18, 2:32 PM · Restricted Project
spatel added a comment to D69127: [DAGCombiner] widen zext of popcount based on target support.

LGTM. Thanks.
Do we want to consider any_extend as well?

Fri, Oct 18, 2:05 PM · Restricted Project
spatel accepted D69116: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (1/2).

LGTM - see inline for a minor improvement.

Fri, Oct 18, 12:21 PM · Restricted Project
spatel added a comment to D69044: [X86] Allow up to 4 loads per inline memcmp().

Can we make the x86 change to combineVectorSizedSetCCEquality() independently and before the change to TargetLowering?

Given that the previous attempt was reverted because of perf only it would be good to show some perf data here in the proposal. Micro-benchmark or more substantial. cc'ing @courbet in case there's already a test harness in place for that.

I haven't looked at this in a while, so I wonder if we now have the infrastructure within memcmp expansion to create the partial vector code with 'ptest' shown here:
https://bugs.llvm.org/show_bug.cgi?id=33914

Hi @spatel,

Thanks for the feedback and yes we can separate the changes. A few thoughts:

  1. The inlined memcmp is much smarter than the Glibc memcmp code these days, at least for pure equality comparisons. In particular, the compiler's overlapping load optimization is really nice (see D55263).
  2. This change proposal intentionally sidesteps more complex memcmps where the return result is tristate (greater, lesser, or equal), not binary (equal versus not). The tristate memcmp is what regressed in PR33914.
  3. It would be easy to contrive a microbenchmark that makes any libc memcmp look very bad and the inlined memcmp look very good. This would be fun, but not informative or actionable.
  4. If I were to design a somewhat interesting and quasi-realistic micro-benchmark, I might create a carefully crafted test that hammers on a llvm::StringSwitch where the cases need more than two load pairs to be inlined.

    This all being said, and if I might be totally honest, I'd like to observe two things:
  5. The size of inlined memcmps tend to have a log-normal distribution with a small mean/median/variance. In other words, the vast majority of inlined memcmps (especially on AVX or AVX512 CPUs) don't need more than two load pairs.
  6. That being said, the specialization that a higher max load pair count allows matters more on simpler CPUs with smaller vectors (if at all) and fewer micro-architectural tricks to mask the cost of libc's dynamic dispatch.

    Therefore, I would argue that the max load pair count should be derived, not fixed. For example, I think the following psuedo-code would yield reasonable results across the semi-recent history of Intel's product line: 2 * CACHELINE_SIZE / PREFERRED_VECTOR_SIZE

    I'd further argue that the compiler shouldn't assume that "max load pairs per block" being less than "max load pairs" is predictable by the branch predictor, but that's a separate discussion.

    Your thoughts would be appreciated. Thanks!
Fri, Oct 18, 10:58 AM · Restricted Project
spatel added a comment to D68930: [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595).

Any thoughts on this?

Fri, Oct 18, 9:52 AM · Restricted Project
spatel added a comment to D69161: [IR] Allow fast math flags on calls with floating point array type..

I think this patch is also allowing the following constructs, but not testing for them.

Are there any existing tests for fast math flags on select or phi, that I could extend? I didn't even know they were allowed because they weren't mentioned in this part of the docs (https://llvm.org/docs/LangRef.html#fast-math-flags) and they aren't explicitly listed in the implementation of FPMathOperator::classof.

Fri, Oct 18, 9:34 AM · Restricted Project
spatel accepted D69175: [X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops.

LGTM

Fri, Oct 18, 9:15 AM · Restricted Project
spatel accepted D69176: [IR] Reimplement FPMathOperator::classof as a whitelist..

LGTM

Fri, Oct 18, 9:07 AM · Restricted Project
spatel added a comment to D69161: [IR] Allow fast math flags on calls with floating point array type..

The LangRef needs edits for this change.
I think this patch is also allowing the following constructs, but not testing for them.

Fri, Oct 18, 6:35 AM · Restricted Project
spatel added a comment to D69044: [X86] Allow up to 4 loads per inline memcmp().

Also worth mentioning: one of the suspects for the regression in PR33914 was a trailing cmov. That's gone now*, so we might want to implement the simpler fix (expand everything to 4) and re-check perf.

Fri, Oct 18, 5:25 AM · Restricted Project
spatel updated subscribers of D69044: [X86] Allow up to 4 loads per inline memcmp().

Can we make the x86 change to combineVectorSizedSetCCEquality() independently and before the change to TargetLowering?

Fri, Oct 18, 5:19 AM · Restricted Project
spatel accepted D68740: [NFC][CVP] Count all the no-wraps we prooved.

LGTM

Fri, Oct 18, 4:47 AM · Restricted Project

Thu, Oct 17

spatel added inline comments to D69116: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (1/2).
Thu, Oct 17, 12:45 PM · Restricted Project
spatel committed rGe3905dee0044: [x86] add test for setcc to shift transform; NFC (authored by spatel).
[x86] add test for setcc to shift transform; NFC
Thu, Oct 17, 12:36 PM
spatel committed rL375158: [x86] add test for setcc to shift transform; NFC.
[x86] add test for setcc to shift transform; NFC
Thu, Oct 17, 12:35 PM
spatel added reviewers for D69116: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (1/2): asl, dylanmckay.
Thu, Oct 17, 11:40 AM · Restricted Project
spatel created D69127: [DAGCombiner] widen zext of popcount based on target support.
Thu, Oct 17, 11:30 AM · Restricted Project
spatel committed rG990c43380b35: [PowerPC] add tests for popcount with zext; NFC (authored by spatel).
[PowerPC] add tests for popcount with zext; NFC
Thu, Oct 17, 10:43 AM
spatel committed rL375142: [PowerPC] add tests for popcount with zext; NFC.
[PowerPC] add tests for popcount with zext; NFC
Thu, Oct 17, 10:42 AM
spatel accepted D69099: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests).

LGTM

Thu, Oct 17, 7:12 AM · Restricted Project
spatel added inline comments to D69099: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests).
Thu, Oct 17, 5:07 AM · Restricted Project

Wed, Oct 16

spatel accepted D69038: [InstCombine] Fix miscompile bug in canEvaluateShuffled.

LGTM with minor fixes as suggested.

Wed, Oct 16, 11:33 AM · Restricted Project
spatel committed rG8cc6d42e8d6c: [SLP] avoid reduction transform on patterns that the backend can load-combine… (authored by spatel).
[SLP] avoid reduction transform on patterns that the backend can load-combine…
Wed, Oct 16, 11:06 AM
spatel committed rL375025: [SLP] avoid reduction transform on patterns that the backend can load-combine….
[SLP] avoid reduction transform on patterns that the backend can load-combine…
Wed, Oct 16, 11:05 AM
spatel closed D67841: [SLP] avoid reduction transform on patterns that the backend can load-combine.
Wed, Oct 16, 11:05 AM · Restricted Project
spatel added a comment to D68982: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine.

You need to work on svn trunk.

Wed, Oct 16, 7:59 AM · Restricted Project
spatel added inline comments to D69038: [InstCombine] Fix miscompile bug in canEvaluateShuffled.
Wed, Oct 16, 7:50 AM · Restricted Project
spatel updated the diff for D67841: [SLP] avoid reduction transform on patterns that the backend can load-combine.

Patch updated:
Change implementation to a pure SLP bailout based on pattern-matching of a load-combine-reduction opportunity. Same test results.

Wed, Oct 16, 5:03 AM · Restricted Project
spatel added inline comments to D67841: [SLP] avoid reduction transform on patterns that the backend can load-combine.
Wed, Oct 16, 4:49 AM · Restricted Project

Tue, Oct 15

spatel added a comment to D68128: [InstCombine] Fold PHIs with equal incoming pointers.

I didn't step through the entire patch/tests, but the first few examples are flattened/simplified by -simplifycfg. Would it be better to look there to add the missing functionality? Is there a test in this patch that shows a case that simplifycfg can't already flatten?

Tue, Oct 15, 10:01 AM · Restricted Project
spatel updated subscribers of D68982: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine.

Also, I have no knowledge of MSP430, and I don't see a code owner for this target. cc @asl @krisb based on D54623.

Tue, Oct 15, 8:56 AM · Restricted Project
spatel added reviewers for D68982: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine: efriedma, hfinkel, mehdi_amini, lebedev.ri, craig.topper.

I understand the direction, and I think there's general agreement on it (adding some more potential reviewers based on the bug report and llvm-dev thread), but:

  1. Add the tests in the patch description to a file in test/CodeGen/MSP430 as an NFC commit *before* applying this patch. Generate baseline test assertions for current asm using utils/update_llc_test_checks.py.
  2. Split this patch up. In the 1st step, we can add the TLI hook and 1-2 usages of that hook that show a test diff for MSP430. Ideally, we can add small tests for each proposed usage of the TLI hook.
Tue, Oct 15, 8:38 AM · Restricted Project
spatel committed rGd545c9056e00: [DAGCombiner] fold select-of-constants based on sign-bit test (authored by spatel).
[DAGCombiner] fold select-of-constants based on sign-bit test
Tue, Oct 15, 8:28 AM
spatel committed rL374902: [DAGCombiner] fold select-of-constants based on sign-bit test.
[DAGCombiner] fold select-of-constants based on sign-bit test
Tue, Oct 15, 8:28 AM
spatel closed D68949: [DAGCombiner] fold select-of-constants based on sign-bit test.
Tue, Oct 15, 8:28 AM · Restricted Project
spatel committed rG455ce7816ce4: [InstCombine] fold a shifted bool zext to a select (2nd try) (authored by spatel).
[InstCombine] fold a shifted bool zext to a select (2nd try)
Tue, Oct 15, 6:15 AM
spatel closed D63382: [InstCombine] fold a shifted zext to a select.
Tue, Oct 15, 6:15 AM · Restricted Project
spatel committed rL374886: [InstCombine] fold a shifted bool zext to a select (2nd try).
[InstCombine] fold a shifted bool zext to a select (2nd try)
Tue, Oct 15, 6:10 AM

Mon, Oct 14

spatel added inline comments to D63382: [InstCombine] fold a shifted zext to a select.
Mon, Oct 14, 5:37 PM · Restricted Project
spatel committed rG4335d8f0e834: Revert [InstCombine] fold a shifted bool zext to a select (authored by spatel).
Revert [InstCombine] fold a shifted bool zext to a select
Mon, Oct 14, 5:00 PM
spatel committed rL374851: Revert [InstCombine] fold a shifted bool zext to a select.
Revert [InstCombine] fold a shifted bool zext to a select
Mon, Oct 14, 5:00 PM
spatel reopened D63382: [InstCombine] fold a shifted zext to a select.

Reverted at rL374851 - appears to cause a test-suite failure and stage 2 failure.

Mon, Oct 14, 5:00 PM · Restricted Project
spatel committed rG1f40f15d54aa: [InstCombine] fold a shifted bool zext to a select (authored by spatel).
[InstCombine] fold a shifted bool zext to a select
Mon, Oct 14, 3:00 PM
spatel closed D63382: [InstCombine] fold a shifted zext to a select.
Mon, Oct 14, 3:00 PM · Restricted Project
spatel committed rL374828: [InstCombine] fold a shifted bool zext to a select.
[InstCombine] fold a shifted bool zext to a select
Mon, Oct 14, 3:00 PM
spatel added reviewers for D63382: [InstCombine] fold a shifted zext to a select: lebedev.ri, xbolva00, joanlluch.
Mon, Oct 14, 2:31 PM · Restricted Project
spatel updated the diff for D63382: [InstCombine] fold a shifted zext to a select.

Patch updated:
Rebased after committing baseline tests and cosmetic changes to the code.

Mon, Oct 14, 2:21 PM · Restricted Project
spatel commandeered D63382: [InstCombine] fold a shifted zext to a select.

Commandeering to rebase.

Mon, Oct 14, 2:21 PM · Restricted Project
spatel committed rGbfaa1082e126: [InstCombine] add tests for select/shift transforms; NFC (authored by spatel).
[InstCombine] add tests for select/shift transforms; NFC
Mon, Oct 14, 1:35 PM
spatel committed rL374818: [InstCombine] add tests for select/shift transforms; NFC.
[InstCombine] add tests for select/shift transforms; NFC
Mon, Oct 14, 1:25 PM
spatel updated the diff for D68949: [DAGCombiner] fold select-of-constants based on sign-bit test.

Patch updated:
Added code comment about the inverted/commuted variations of these patterns.

Mon, Oct 14, 1:15 PM · Restricted Project
spatel added inline comments to D68949: [DAGCombiner] fold select-of-constants based on sign-bit test.
Mon, Oct 14, 10:43 AM · Restricted Project
spatel created D68949: [DAGCombiner] fold select-of-constants based on sign-bit test.
Mon, Oct 14, 10:15 AM · Restricted Project
spatel committed rGee86804cf1bc: [x86] adjust select to sra tests; NFC (authored by spatel).
[x86] adjust select to sra tests; NFC
Mon, Oct 14, 9:02 AM
spatel committed rL374783: [x86] adjust select to sra tests; NFC.
[x86] adjust select to sra tests; NFC
Mon, Oct 14, 8:52 AM
spatel committed rG03462bbe7d54: [x86] add tests for possible select to sra transforms; NFC (authored by spatel).
[x86] add tests for possible select to sra transforms; NFC
Mon, Oct 14, 7:48 AM
spatel committed rL374779: [x86] add tests for possible select to sra transforms; NFC.
[x86] add tests for possible select to sra transforms; NFC
Mon, Oct 14, 7:48 AM

Sun, Oct 13

spatel committed rGb32e4664a715: [ConstantFold] fix inconsistent handling of extractelement with undef index… (authored by spatel).
[ConstantFold] fix inconsistent handling of extractelement with undef index…
Sun, Oct 13, 10:38 AM
spatel committed rL374729: [ConstantFold] fix inconsistent handling of extractelement with undef index….
[ConstantFold] fix inconsistent handling of extractelement with undef index…
Sun, Oct 13, 10:37 AM
spatel committed rGf90728c3227d: [InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non… (authored by spatel).
[InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non…
Sun, Oct 13, 10:20 AM
spatel closed D68706: [InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non-default address space.
Sun, Oct 13, 10:19 AM · Restricted Project
spatel committed rL374728: [InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non….
[InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non…
Sun, Oct 13, 10:19 AM

Sat, Oct 12

spatel added a comment to D63382: [InstCombine] fold a shifted zext to a select.

I haven't tested this on trunk, but I added the DAGCombiner reversals:
rL374397
rL374555
...so this should be good to go. Should I commandeer?

Sat, Oct 12, 7:42 AM · Restricted Project
spatel updated subscribers of D63382: [InstCombine] fold a shifted zext to a select.

@joanlluch - this is a case where we could transform incoming shift to select and benefit small targets as you've noted.

Sat, Oct 12, 7:42 AM · Restricted Project
spatel created D68911: [AArch64] enable (v)select to math TLI hook (WIP).
Sat, Oct 12, 7:26 AM · Restricted Project

Fri, Oct 11

spatel committed rG781c49de9c76: [AArch64] add tests for (v)select-of-constants; NFC (authored by spatel).
[AArch64] add tests for (v)select-of-constants; NFC
Fri, Oct 11, 9:10 AM
spatel committed rL374568: [AArch64] add tests for (v)select-of-constants; NFC.
[AArch64] add tests for (v)select-of-constants; NFC
Fri, Oct 11, 9:10 AM
spatel added a comment to D67841: [SLP] avoid reduction transform on patterns that the backend can load-combine.

There seems to be general agreement that this is a temporary (stopgap) solution until we can do limited load combining in IR. So it's a question of whether we're ok with a cost model hack to overcome the motivating bugs while we figure out how to add a new pass.

Fri, Oct 11, 8:51 AM · Restricted Project
spatel committed rG3b581ac80f72: [DAGCombiner] fold vselect-of-constants to shift (authored by spatel).
[DAGCombiner] fold vselect-of-constants to shift
Fri, Oct 11, 7:18 AM
spatel committed rL374555: [DAGCombiner] fold vselect-of-constants to shift.
[DAGCombiner] fold vselect-of-constants to shift
Fri, Oct 11, 7:18 AM

Thu, Oct 10

spatel committed rG8dd16ed0c8d7: [x86] reduce duplicate test assertions; NFC (authored by spatel).
[x86] reduce duplicate test assertions; NFC
Thu, Oct 10, 12:57 PM
spatel committed rL374436: [x86] reduce duplicate test assertions; NFC.
[x86] reduce duplicate test assertions; NFC
Thu, Oct 10, 12:57 PM
spatel committed rG7b904ce7246b: [DAGCombiner] fold select-of-constants to shift (authored by spatel).
[DAGCombiner] fold select-of-constants to shift
Thu, Oct 10, 10:53 AM
spatel committed rL374397: [DAGCombiner] fold select-of-constants to shift.
[DAGCombiner] fold select-of-constants to shift
Thu, Oct 10, 10:53 AM
spatel committed rG7f0e7c0b1ca2: [DAGCombiner] reduce code duplication; NFC (authored by spatel).
[DAGCombiner] reduce code duplication; NFC
Thu, Oct 10, 8:41 AM
spatel committed rL374370: [DAGCombiner] reduce code duplication; NFC.
[DAGCombiner] reduce code duplication; NFC
Thu, Oct 10, 8:40 AM
spatel committed rG3370d4d2b766: [AArch64][x86] add tests for (v)select bit magic; NFC (authored by spatel).
[AArch64][x86] add tests for (v)select bit magic; NFC
Thu, Oct 10, 6:00 AM
spatel committed rL374334: [AArch64][x86] add tests for (v)select bit magic; NFC.
[AArch64][x86] add tests for (v)select bit magic; NFC
Thu, Oct 10, 5:51 AM
spatel updated subscribers of D68748: Add FMF to vector ops for phi.

Note that @reames suggested that we should publicize the previous patch to make sure there were no known unintended consequences from this change, so:
http://lists.llvm.org/pipermail/llvm-dev/2019-September/135444.html

Thu, Oct 10, 5:22 AM · Restricted Project

Wed, Oct 9

spatel committed rG232b9dc46a30: [ConstProp] add tests for extractelement with undef index; NFC (authored by spatel).
[ConstProp] add tests for extractelement with undef index; NFC
Wed, Oct 9, 1:19 PM
spatel committed rL374210: [ConstProp] add tests for extractelement with undef index; NFC.
[ConstProp] add tests for extractelement with undef index; NFC
Wed, Oct 9, 1:12 PM
spatel accepted D68250: [DAGCombine] Match more patterns for half word bswap.

LGTM - I applied the patch locally and ran 'make check' and don't see failures now.

Wed, Oct 9, 11:55 AM · Restricted Project
spatel added a comment to D68706: [InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non-default address space.

Can you add the test I provided as well?

Wed, Oct 9, 11:45 AM · Restricted Project
spatel updated the diff for D68706: [InstCombine] don't assume 'inbounds' for bitcast deref or null pointer in non-default address space.

Patch updated:
No diffs in this patch itself, but rebased after adding test at rL374190.
I don't have much experience with addrspaces or inbounds, so let me know if I should change anything else.

Wed, Oct 9, 11:26 AM · Restricted Project
spatel committed rG0845ac7331e1: [InstCombine] add another test for gep inbounds; NFC (authored by spatel).
[InstCombine] add another test for gep inbounds; NFC
Wed, Oct 9, 10:58 AM
spatel committed rL374190: [InstCombine] add another test for gep inbounds; NFC.
[InstCombine] add another test for gep inbounds; NFC
Wed, Oct 9, 10:57 AM
spatel accepted D68713: [FPEnv] Change test to conform to strictfp attribute rules.

LGTM - you may want to annotate the title with 'NFC' when committing to indicate this patch doesn't actually change code.

Wed, Oct 9, 10:09 AM · Restricted Project
spatel committed rGdf14bd315db9: [SLP] respect target register width for GEP vectorization (PR43578) (authored by spatel).
[SLP] respect target register width for GEP vectorization (PR43578)
Wed, Oct 9, 9:41 AM
spatel closed D68667: [SLP] respect target register width for GEP vectorization (PR43578).
Wed, Oct 9, 9:41 AM · Restricted Project