- User Since
- May 22 2014, 1:24 PM (230 w, 14 h)
Tue, Oct 16
Mon, Oct 15
Is the motivating case integer or FP?
I'm asking because we have a canonicalization for integer cmp+sel for the IR in these tests, but we're missing the corresponding FP transform.
If we add the FP canonicalization in IR, would there still be a need for this backend patch? Ie, is something generating this select code in the DAG itself?
I think this is the right way to go. It's a blob of patterns, but they're stamped out in a regular form.
When the logic ops are promoted, we might have to deal with them separately as noted in D51553.
Sun, Oct 14
Sat, Oct 13
I suspect that none of these changes are actually 'NFC'.
- Add "LegalTypes" as the first predicate for trying this transform to make it less likely that any weird types invalidate the later assumptions.
- Add an assert that the scalar bitwidth is a multiple of the vector element bitwidth (scalar_to_vector size must be a multiple, and bitcast can't change size).
- Add a test that at least starts with a weird type in IR.
Fri, Oct 12
Thu, Oct 11
Wed, Oct 10
LGTM - see inline for a couple of nits.
Added an assert to (hopefully) make this transform clearer.
Tue, Oct 9
Nit: it would be nicer to check in the PPC tests with baseline asm as a preliminary step. That way, we'd just see the asm diff there too.
How about enabling the hook for PPC before adding to the generic DAG combine...
Right now, you'll get something horrible for normal fabs (and fneg?) without this patch, right?
Mon, Oct 8
Removed unnecessary depth param (copy-paste remnant).
Sun, Oct 7
I'm trying to improve vector-demanded-elements folds in D52912 which means we need to do better at recognizing patterns with undefs.
This patch is not 'NFC'. I added a test that should show an improvement at rL343936.
Fixed whitespace diff.
Sat, Oct 6
Fri, Oct 5
Patch updated - once again, no code changes, but rebased after:
...so now we don't have any more sched test diffs.
I was completely missing the point of those tests (to check both reg-reg and reg-mem variants of the opcodes).
Patch updated - no code changes, but:
Rebased after rL343858, so less noise from the SSE1/2 sched tests.