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khchen (Kuan Hsu Chen (Zakk))
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User Since
Oct 23 2013, 8:22 AM (361 w, 1 d)

Recent Activity

Jul 15 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address @lenary's comment, good catch! thanks a lot!!

Jul 15 2020, 8:17 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address @asb's comment. thanks.

Jul 15 2020, 1:42 AM · Restricted Project, Restricted Project

Jul 14 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

Hi @lenary
This is normal behavior in current clang implementation,
-mcpu=? flag does not interact with any flags, it just print out the all of ProcessorModel registered in backend.
https://github.com/llvm/llvm-project/blob/master/clang/tools/driver/cc1_main.cpp#L213-L215

Jul 14 2020, 6:46 PM · Restricted Project, Restricted Project

Jul 11 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

@asb @lenary I thought this path is ready to land?

Jul 11 2020, 7:41 PM · Restricted Project, Restricted Project

Jul 10 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

avoid to check compiler version in testcase

Jul 10 2020, 9:06 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

fix typo

Jul 10 2020, 8:00 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

addess @asb 's comment.

Jul 10 2020, 1:48 AM · Restricted Project, Restricted Project

Jul 9 2020

khchen planned changes to D71124: [RISCV] support clang driver to select cpu.

BTW, this patch depends on D77030, which aim to avoid the forcing of any ProcessorModel to have FeatureRVCHints feature.
But if we decide to keep the FeatureRVCHints, I need to change implementation a little.

Jul 9 2020, 6:40 AM · Restricted Project, Restricted Project

May 6 2020

khchen updated the diff for D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.

update testcases

May 6 2020, 2:39 AM · Restricted Project, Restricted Project

May 3 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address kito's comment

May 3 2020, 11:57 PM · Restricted Project, Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

s/ld/lld/

May 3 2020, 8:41 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

address @MaskRay's review feedback

May 3 2020, 10:37 AM · Restricted Project
khchen updated the summary of D78988: [LTO] Suppress emission of empty combined module by default.
May 3 2020, 10:37 AM · Restricted Project

May 2 2020

khchen retitled D78988: [LTO] Suppress emission of empty combined module by default from [LTO] Suppress emission of the empty object file to [LTO] Suppress emission of empty combined module by default.
May 2 2020, 7:55 AM · Restricted Project

Apr 30 2020

khchen updated the diff for D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.

rebase on master

Apr 30 2020, 4:43 AM · Restricted Project
khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

Another proposal for -mcpu and -mtune:

Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and -mtune for micro-arch/pipeline model, they accept different option set.

e.g.
-mcpu=sifive-e24 # Imply -march=rv32imafc -mtune=sifive-2-series
-mtune=sifive-2-series # no effect on arch
-mtune=rocket # no effect on arch

So -mcpu=rocket is invalid, since it's micro-arch/pipeline model only,
and -mtune=sifive-e24 is invalid too, because it's CPU not a micro-arch.

Apr 30 2020, 3:21 AM · Restricted Project, Restricted Project
khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

This is looking good.

I remember we discussed this on the LLVM call a few weeks ago - there was a discussion as to whether we should be prioritising -march or -mcpu - do you recall the outcome of that discussion?

Apr 30 2020, 3:01 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address @lenary's review feedback

Apr 30 2020, 3:01 AM · Restricted Project, Restricted Project

Apr 29 2020

khchen added a comment to D78988: [LTO] Suppress emission of empty combined module by default.

@MaskRay Thanks for your suggestion and reminder.

Apr 29 2020, 11:59 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.
  1. Rebase on master branch.
  2. update lld testcases
Apr 29 2020, 11:58 PM · Restricted Project
khchen updated the diff for D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.

rebase on D78988

Apr 29 2020, 11:13 PM · Restricted Project, Restricted Project
khchen added inline comments to D78988: [LTO] Suppress emission of empty combined module by default.
Apr 29 2020, 9:37 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.
  1. Add empty combined module checking before call backend()
  2. Appling new approach, some testcasess need to updated and deleted. In checking module empty approach, it can suppress emitting optimzed empty combined module, but in new approach, it still emit combined module. I thought new approach behavior is acceptable. This case happend in linker-script-symbols-assign.ll.
  3. Delete llvm/test/ThinLTO/X86/empty-object.ll. I misunderstood -thinlto-distributed-indexes option meaning. I add this case just becasue becuase I modified llvm-lto2. I think testing in empty-module.ll is enough. This patch focus on empty combined module, I think we don't need to comfirm "empty ThinLTO module" still be emitted.
Apr 29 2020, 9:37 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

rebase master

Apr 29 2020, 10:11 AM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

address @tejohnson's comments

Apr 29 2020, 4:47 AM · Restricted Project
khchen added inline comments to D78988: [LTO] Suppress emission of empty combined module by default.
Apr 29 2020, 4:47 AM · Restricted Project

Apr 28 2020

khchen added a comment to D78988: [LTO] Suppress emission of empty combined module by default.

Hi @tejohnson
I'm very appreciate your help and comment,
because I'm not LTO expert, so if you have any good idea and concern in implementation
Please don't hesitate to correct me, thanks.

Apr 28 2020, 10:06 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

fixed linker-script-symbols-assign.ll, now lto would not generate empty module (%t2.lto.o)
fixed typo and format.

Apr 28 2020, 11:16 AM · Restricted Project
khchen planned changes to D78988: [LTO] Suppress emission of empty combined module by default.

sorry, my fault, there are two failing tests I need to fix first.

Apr 28 2020, 7:29 AM · Restricted Project
khchen created D78988: [LTO] Suppress emission of empty combined module by default.
Apr 28 2020, 3:11 AM · Restricted Project

Apr 19 2020

khchen planned changes to D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.

I plan to suppress to emit empty module or avoid ld to link empty module's object file.

Apr 19 2020, 8:49 PM · Restricted Project, Restricted Project

Apr 16 2020

khchen added a comment to D78021: [RISCV]: Adjust riscv64 GCC detector to also check for existence of crtbegin.o in the default multilib dir, like most other ports..

Could you add a testcase? It will helpful to see what issue fixed in this patch. thanks.

Apr 16 2020, 8:54 AM

Apr 14 2020

khchen added inline comments to D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.
Apr 14 2020, 7:35 PM · Restricted Project, Restricted Project
khchen added inline comments to D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.
Apr 14 2020, 2:05 AM · Restricted Project, Restricted Project

Apr 13 2020

Herald added a reviewer for D72624: [WIP] TargetMachine Hook for Module Metadata: herhut.

Hi @lenary, I added a PoC patch D78035 to complete ThinLTO based on this patch.

Apr 13 2020, 10:12 AM · Restricted Project, Restricted Project, Restricted Project
khchen created D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.
Apr 13 2020, 10:12 AM · Restricted Project, Restricted Project

Apr 9 2020

khchen added a comment to D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.

I agree negative features is not intuitive, but HINT instruction default is legal and supported, in other words, it mean the disabling HINT instruction is a feature, right?
There were also negative features in other backend. (grep FeatureNo) so we are not first support it.
For sure, I won’t insist on doing this, I feel it's just a friendly trade-off between user and developer.
Thanks. :P

Apr 9 2020, 7:36 PM · Restricted Project
khchen added a comment to D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.
In D77030#1971795, @asb wrote:

I can see the argument for changing the default of EnableRVCHintInstrs. Might we be better just doing that, and keeping it as "rvc-hints" to avoid adding negative features?

Apr 9 2020, 8:07 AM · Restricted Project

Apr 6 2020

khchen updated the summary of D71124: [RISCV] support clang driver to select cpu.
Apr 6 2020, 10:51 AM · Restricted Project, Restricted Project
khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

@lenary (Sorry for the very late reply...)

Apr 6 2020, 10:50 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

update implementation and handle -mcpu with explicitly specified -march.
If -mcpu has default march, explicitly -march will overwrite it.

Apr 6 2020, 10:18 AM · Restricted Project, Restricted Project

Mar 29 2020

khchen created D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.
Mar 29 2020, 9:24 PM · Restricted Project

Mar 26 2020

Zakk Chen <zakk.chen@sifive.com> committed rG64fe84185602: Fix typo, targetFeature should be lowercase. (authored by khchen).
Fix typo, targetFeature should be lowercase.
Mar 26 2020, 8:08 PM
khchen closed D76757: Fix typo, targetFeature should be lowercase..
Mar 26 2020, 8:08 PM · Restricted Project, Restricted Project
khchen changed the repository for D76757: Fix typo, targetFeature should be lowercase. from rZORG LLVM Github Zorg to rG LLVM Github Monorepo.
Mar 26 2020, 8:38 AM · Restricted Project, Restricted Project

Mar 25 2020

khchen added reviewers for D76757: Fix typo, targetFeature should be lowercase.: ziangwan, kongyi.
Mar 25 2020, 12:30 AM · Restricted Project, Restricted Project

Mar 24 2020

khchen created D76757: Fix typo, targetFeature should be lowercase..
Mar 24 2020, 11:57 PM · Restricted Project, Restricted Project

Jan 16 2020

khchen updated the diff for D70837: [RISCV] Support ABI checking with per function target-features.

I fixed bug here, but I'm not sure this small fixed should be another commit or not.
@lenary, do you have any suggestion?

Jan 16 2020, 7:03 PM · Restricted Project
khchen reopened D70837: [RISCV] Support ABI checking with per function target-features.
Jan 16 2020, 7:03 PM · Restricted Project
khchen requested review of D70837: [RISCV] Support ABI checking with per function target-features.
Jan 16 2020, 7:03 PM · Restricted Project
khchen added a comment to D70837: [RISCV] Support ABI checking with per function target-features.

@khchen We have a load of EXPENSIVE_CHECKS RISCV MC + asm failures, a lot of which appear to be related to these changes to RISCVAsmParser please can you take a look?

First appeared:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/21599/

Current:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/21630/steps/test-check-all/logs/stdio

Jan 16 2020, 6:15 PM · Restricted Project

Jan 15 2020

khchen added a comment to D72755: [RISCV] Pass target-abi via module flag metadata.

Please can you also add code for ensuring that the target-abi module flag matches the -target-abi command line flag in llvm?

Jan 15 2020, 7:07 AM · Restricted Project
khchen created D72768: [RISCV] Check the target-abi module flag matches the -target-abi option.
Jan 15 2020, 7:00 AM · Restricted Project
khchen created D72755: [RISCV] Pass target-abi via module flag metadata.
Jan 15 2020, 2:01 AM · Restricted Project

Jan 14 2020

khchen added inline comments to D70837: [RISCV] Support ABI checking with per function target-features.
Jan 14 2020, 7:51 PM · Restricted Project
khchen added a comment to D72624: [WIP] TargetMachine Hook for Module Metadata.

I think putting the resetTargetDefaultOptions after instance of TargetMachine is too late.
for example:
ppc and mips compute the TargetABI in XXXXTargetMachine constructor. In addition , mips compute the DataLayout with target ABI in TargetMachine constructor.

Jan 14 2020, 5:07 AM · Restricted Project, Restricted Project, Restricted Project
khchen added a comment to D70837: [RISCV] Support ABI checking with per function target-features.

Hi @lenary,
This patch is necessary for enabling LTO
backend does this mismatch checking before getSubtargetImpl which reads the target-feature info from IR function attribute, and it will reset the target-abi if mismatching happen.
because I don't want to break this mismatch checking feature, so I move this checking later than getSubtargetImpl execution.

Jan 14 2020, 1:13 AM · Restricted Project
khchen updated the summary of D70837: [RISCV] Support ABI checking with per function target-features.
Jan 14 2020, 12:26 AM · Restricted Project

Jan 13 2020

khchen added a comment to D72624: [WIP] TargetMachine Hook for Module Metadata.

I think putting the resetTargetDefaultOptions after instance of TargetMachine is too late.
for example:
ppc and mips compute the TargetABI in XXXXTargetMachine constructor. In addition , mips compute the DataLayout with target ABI in TargetMachine constructor.

Jan 13 2020, 7:27 PM · Restricted Project, Restricted Project, Restricted Project

Jan 12 2020

khchen updated subscribers of D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.

Hi @efriedma
Could you please guide me and review this PoC?
or take a look at this [[ take a look at | maillist ]] thread?
Thank you!

Jan 12 2020, 5:46 PM · Restricted Project, Restricted Project

Jan 9 2020

khchen added inline comments to D71124: [RISCV] support clang driver to select cpu.
Jan 9 2020, 10:10 PM · Restricted Project, Restricted Project
khchen updated the diff for D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.

remote LTO related code.
this PoC include D70837 patch for generate correct code.

Jan 9 2020, 9:45 AM · Restricted Project, Restricted Project
khchen updated the diff for D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Jan 9 2020, 8:02 AM · Restricted Project, Restricted Project

Jan 6 2020

khchen added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

I'd like to discuss what is good way to pass target-abi in maillist after I had a try to encoding ABI info into LLVM IR via module flag.
any suggestions are welcome, thanks.

Jan 6 2020, 1:21 AM · Restricted Project

Jan 5 2020

khchen created D72246: [PoC][RISCV][LTO] Pass target-abi via module flag metadata (solution 2 ).
Jan 5 2020, 10:04 PM · Restricted Project
khchen updated the diff for D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Jan 5 2020, 9:55 PM · Restricted Project, Restricted Project
khchen created D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Jan 5 2020, 9:46 PM · Restricted Project, Restricted Project

Dec 19 2019

khchen planned changes to D71124: [RISCV] support clang driver to select cpu.

The problem is how -mcpu interact with explicitly specified -march (or target features).

Dec 19 2019, 10:34 PM · Restricted Project, Restricted Project
khchen added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

But in RISCV clang emits the same IR for different ABI (-mabi),

This is not true. For simple cases, it does, yes, but there are some weird edge cases for functions with many arguments.

Dec 19 2019, 6:43 PM · Restricted Project

Dec 17 2019

khchen planned changes to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

I asked @kito-cheng about the GCC LTO behavior,
GCC LTO encodes the ABI info in elf and the behavior in above examples match to @efriedma 's responses.
So I think maybe encode ABI in module metadata flag is a good ideal.

Dec 17 2019, 11:12 PM · Restricted Project
khchen added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

Unfortunately on RISCV, the ABI info is only derived from -mabi option and the target triple does not encode ABI info (same to gcc).

How does gcc decide the default ABI for a target? Do you explicitly specify it at configure time?

Dec 17 2019, 10:12 PM · Restricted Project
khchen added inline comments to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.
Dec 17 2019, 9:07 AM · Restricted Project
khchen added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

My primary concern with this is that I'm not sure you should be passing this information separately, as opposed to encoding it into the bitcode.

On ARM, the ABI for a file is generally derived from the target triple. For example, "arm-eabi" is soft-float, "arm-eabihf" is hard-float. This makes the intended target clear, provides some protection against accidentally using LTO with files compiled for different ABIs, and matches up well with our existing configuration flags to set a default target for a compiler.

Dec 17 2019, 9:04 AM · Restricted Project

Dec 11 2019

khchen updated the diff for D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

update missed code..

Dec 11 2019, 11:12 PM · Restricted Project
khchen created D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.
Dec 11 2019, 8:46 PM · Restricted Project

Dec 10 2019

khchen added inline comments to D71124: [RISCV] support clang driver to select cpu.
Dec 10 2019, 6:57 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.
Dec 10 2019, 6:51 AM · Restricted Project, Restricted Project

Dec 6 2019

khchen added a comment to D68685: [RISCV] Scheduler description for Rocket Core.

BTW, I used this patch and D71124 to run the CoreMark on HiFive unleashed with -O3 -mllvm -enable-misched -mllvm -enable-post-misched -mcpu=rocket-rv64,
the result is better than -O3 -mllvm -enable-misched -mllvm -enable-post-misched and get the performance 3.5% speedup (use ld.bfd and libgcc).

Dec 6 2019, 9:07 AM · Restricted Project
khchen created D71124: [RISCV] support clang driver to select cpu.
Dec 6 2019, 8:48 AM · Restricted Project, Restricted Project

Dec 3 2019

khchen added inline comments to D70116: [RISCV] add subtargets initialized with target feature.
Dec 3 2019, 6:18 PM · Restricted Project

Nov 29 2019

khchen updated the diff for D70837: [RISCV] Support ABI checking with per function target-features.

update summary.

Nov 29 2019, 8:29 AM · Restricted Project
khchen updated the diff for D70837: [RISCV] Support ABI checking with per function target-features.
Nov 29 2019, 6:50 AM · Restricted Project
khchen updated the diff for D70837: [RISCV] Support ABI checking with per function target-features.
Nov 29 2019, 2:43 AM · Restricted Project
khchen added a comment to D70837: [RISCV] Support ABI checking with per function target-features.
Nov 29 2019, 2:33 AM · Restricted Project

Nov 28 2019

khchen updated the summary of D70837: [RISCV] Support ABI checking with per function target-features.
Nov 28 2019, 10:13 PM · Restricted Project
khchen created D70837: [RISCV] Support ABI checking with per function target-features.
Nov 28 2019, 8:06 PM · Restricted Project
khchen updated the diff for D70116: [RISCV] add subtargets initialized with target feature.

add expected failed case, it fixed in https://reviews.llvm.org/D70837.

Nov 28 2019, 7:55 PM · Restricted Project

Nov 27 2019

khchen added a comment to D70116: [RISCV] add subtargets initialized with target feature.

So am I right in thinking that neither foo nor foo2 will trigger the ABI_Unknown issue, and the issue is only coming from hand-written assembly files?

Actually, you may need to specify -target-abi in the top of the subtarget-features-std-ext.ll file.

Sorry I didn't explain clearly,
The problem is caused by when I try to enable LTO and it need to pass mabi to LTO code generator (mabi is not encoded in bitcode)
like we compile below case with llc example.c -mtriple=riscv32 -mabi=ilp32f.

define float @foo(i32 %a) nounwind #0 {
  %conv = sitofp i32 %a to float
  ret float %conv
}

define float @foo2(i32 %a) nounwind #1{
  %conv = sitofp i32 %a to float
  ret float %conv
}

attributes #0 = { "target-features"="+f"}
attributes #1 = { "target-features"="+f"}

and they will show two error messages Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension.
so there is no any issue in subtarget-features-std-ext.ll without -target-abi.

when I started to fix this error, I found backend shares the ABI parsing/checking function (computeTargetABI) in codegen and MC layer when instance RISCVAsmBackend (note: IR function is not available at this point)
ref. https://github.com/llvm/llvm-project/commit/fea4957177315f83746dca90cb4c9013eb465c46

so this patch is workable, but it's not useful for LTO, not useful enough to support per function feature in backend, and then I'm not sure it's worth to upstream this patch.

This patch seems to solve the issue of working out the correct Subtarget on a per-function basis? This would suggest it is useful.

Yes. Okay, agree with you.

Presumably the next steps are to work out how to pass -target-abi through to the LTO backend via attributes? I was trying to see how other backends did this, but I'm not sure. I think the right way may be to have a feature per ABI, like ARM does here: https://github.com/llvm/llvm-project/blob/2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77/clang/lib/Driver/ToolChains/Arch/ARM.cpp#L313-L319

It might be worth sending an email to llvm-dev, asking for guidance.

Nov 27 2019, 10:27 AM · Restricted Project
khchen added a comment to D70116: [RISCV] add subtargets initialized with target feature.

So am I right in thinking that neither foo nor foo2 will trigger the ABI_Unknown issue, and the issue is only coming from hand-written assembly files?

Actually, you may need to specify -target-abi in the top of the subtarget-features-std-ext.ll file.

Nov 27 2019, 4:20 AM · Restricted Project

Nov 26 2019

khchen requested review of D70116: [RISCV] add subtargets initialized with target feature.

I found RISCVABI::computeTargetABI will check ABI with target feature,
so when I apply this patch and enabling lto, the checking get failed and set ABI to ABI_Unknown.
It's not easy to fix it because target-features is per-function basis but ABI is not.

Nov 26 2019, 6:07 PM · Restricted Project

Nov 21 2019

khchen added a comment to D67508: [RISCV] support mutilib in baremetal environment.

Re-applied with test fix in https://reviews.llvm.org/rG4fccd383d571865321b4723b81c3042d2c15fd80

Nov 21 2019, 11:46 PM · Restricted Project
Zakk Chen <zakk.chen@sifive.com> committed rG4fccd383d571: [RISCV] Support mutilib in baremetal environment (authored by khchen).
[RISCV] Support mutilib in baremetal environment
Nov 21 2019, 8:06 PM
khchen updated subscribers of rGdf876a026981: [RISCV] Support mutilib in baremetal environment.

@lenary failed again,
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/483/steps/test-check-clang/logs/FAIL%3A%20Clang%3A%3Ariscv32-toolchain.c
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/483/steps/test-check-clang/logs/FAIL%3A%20Clang%3A%3Ariscv64-toolchain.c
I will setup windows platform to figure out what's going on.

Nov 21 2019, 6:17 AM
Zakk Chen <zakk.chen@sifive.com> committed rGdf876a026981: [RISCV] Support mutilib in baremetal environment (authored by khchen).
[RISCV] Support mutilib in baremetal environment
Nov 21 2019, 1:18 AM

Nov 19 2019

khchen updated subscribers of rGb6d7bbfa0043: [RISCV] Support mutilib in baremetal environment.
Nov 19 2019, 6:05 PM
Zakk Chen <zakk.chen@sifive.com> committed rGb6d7bbfa0043: [RISCV] Support mutilib in baremetal environment (authored by khchen).
[RISCV] Support mutilib in baremetal environment
Nov 19 2019, 2:19 AM
khchen closed D67508: [RISCV] support mutilib in baremetal environment.
Nov 19 2019, 2:19 AM · Restricted Project

Nov 18 2019

khchen updated the diff for D67508: [RISCV] support mutilib in baremetal environment.

rebase and fix failed testcases

Nov 18 2019, 8:26 PM · Restricted Project

Nov 15 2019

khchen updated the diff for D67508: [RISCV] support mutilib in baremetal environment.

rebase

Nov 15 2019, 4:47 AM · Restricted Project

Nov 14 2019

khchen planned changes to D70116: [RISCV] add subtargets initialized with target feature.

I found RISCVABI::computeTargetABI will check ABI with target feature,
so when I apply this patch and enabling lto, the checking get failed and set ABI to ABI_Unknown.
It's not easy to fix it because target-features is per-function basis but ABI is not.

Nov 14 2019, 5:58 AM · Restricted Project