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khchen (Zakk Chen)
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User Since
Oct 23 2013, 8:22 AM (377 w, 3 d)

Recent Activity
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Today

khchen added inline comments to D94589: [RISCV] Add intrinsics for vector AMO instructions.
Sat, Jan 16, 6:37 AM · Restricted Project

Yesterday

khchen added a comment to D94566: [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF..

LGTM!

Fri, Jan 15, 7:12 AM · Restricted Project
khchen added inline comments to D94589: [RISCV] Add intrinsics for vector AMO instructions.
Fri, Jan 15, 7:10 AM · Restricted Project

Wed, Jan 13

khchen added inline comments to D94589: [RISCV] Add intrinsics for vector AMO instructions.
Wed, Jan 13, 7:46 AM · Restricted Project

Tue, Dec 29

khchen committed rG6da00336248c: [RISCV] Define vsext/vzext intrinsics. (authored by khchen).
[RISCV] Define vsext/vzext intrinsics.
Tue, Dec 29, 5:03 PM
khchen closed D93893: [RISCV] Define vsext/vzext intrinsics..
Tue, Dec 29, 5:02 PM · Restricted Project
khchen updated the diff for D93893: [RISCV] Define vsext/vzext intrinsics..

Replace NoVReg with VR and add comment to indicate which is NoVReg.

Tue, Dec 29, 5:11 AM · Restricted Project
khchen requested review of D93893: [RISCV] Define vsext/vzext intrinsics..
Tue, Dec 29, 2:21 AM · Restricted Project

Mon, Dec 28

khchen accepted D93878: [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source.

thanks for fixup, LGTM.

Mon, Dec 28, 10:54 PM · Restricted Project
khchen accepted D93867: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions.
Mon, Dec 28, 8:36 PM · Restricted Project
khchen added a comment to D93867: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions.

LGTM, thanks for fixup!

Mon, Dec 28, 8:36 PM · Restricted Project
khchen added inline comments to D93878: [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source.
Mon, Dec 28, 8:30 PM · Restricted Project
khchen committed rGf3f9ce3b7948: [RISCV] Define vmclr.m/vmset.m intrinsics. (authored by khchen).
[RISCV] Define vmclr.m/vmset.m intrinsics.
Mon, Dec 28, 6:57 PM
khchen closed D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..
Mon, Dec 28, 6:57 PM · Restricted Project
khchen added a comment to D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..

Those different chooses reason are interesting to learn, I really appreciate your information.

Mon, Dec 28, 4:52 PM · Restricted Project
khchen committed rGe673d4019947: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics. (authored by khchen).
[RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics.
Mon, Dec 28, 6:16 AM
khchen closed D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..
Mon, Dec 28, 6:16 AM · Restricted Project
khchen updated the diff for D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..

Address frasercrmck's comments, thanks!

Mon, Dec 28, 1:27 AM · Restricted Project

Sun, Dec 27

khchen updated the diff for D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..
  1. Address craig.topper's comments.
  2. Set BaseInstr as corresponding v-inst, so we only need to define one pseudo instruction.
Sun, Dec 27, 11:04 PM · Restricted Project
khchen updated the diff for D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..

Change back VPseudoUnaryNoMask argument and add a comment

Sun, Dec 27, 7:59 PM · Restricted Project
khchen updated the diff for D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..
  1. remove HasDummyMask = 1 in mask pseudo class
  2. chagne DAGOperand to VReg in VPseudoUnaryNoMask
Sun, Dec 27, 7:40 PM · Restricted Project
khchen updated the diff for D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..

update ceudoinstructions comments

Sun, Dec 27, 7:20 PM · Restricted Project
khchen requested review of D93849: [RISCV] Define vmclr.m/vmset.m intrinsics..
Sun, Dec 27, 7:18 PM · Restricted Project
khchen updated the diff for D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..

make consistent for td class naming.

Sun, Dec 27, 7:05 PM · Restricted Project
khchen updated the diff for D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..

address @HsiangKai's comments, thanks!!

Sun, Dec 27, 6:49 PM · Restricted Project

Sat, Dec 26

khchen requested review of D93823: [RISCV] Define vmsbf.m/vmsif.m/vmsof.m/viota.m/vid.v intrinsics..
Sat, Dec 26, 9:00 AM · Restricted Project

Thu, Dec 24

khchen committed rGda4a637e9917: [RISCV] Define vpopc/vfirst intrinsics. (authored by khchen).
[RISCV] Define vpopc/vfirst intrinsics.
Thu, Dec 24, 7:50 PM
khchen closed D93795: [RISCV] Define vpopc/vfirst intrinsics..
Thu, Dec 24, 7:50 PM · Restricted Project
khchen committed rG351c216f36af: [RISCV] Define vector mask-register logical intrinsics. (authored by khchen).
[RISCV] Define vector mask-register logical intrinsics.
Thu, Dec 24, 7:17 PM
khchen closed D93705: [RISCV] Define vector mask-register logical intrinsics..
Thu, Dec 24, 7:17 PM · Restricted Project
khchen updated the diff for D93705: [RISCV] Define vector mask-register logical intrinsics..

rebase

Thu, Dec 24, 6:16 PM · Restricted Project
khchen requested review of D93795: [RISCV] Define vpopc/vfirst intrinsics..
Thu, Dec 24, 12:28 AM · Restricted Project

Wed, Dec 23

khchen updated the diff for D93705: [RISCV] Define vector mask-register logical intrinsics..

address @HsiangKai's comments.

Wed, Dec 23, 7:58 PM · Restricted Project
khchen added inline comments to D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Wed, Dec 23, 6:45 PM · Restricted Project
khchen accepted D93672: [RISCV] Add intrinsics for vfmv.v.f.

LGTM

Wed, Dec 23, 8:19 AM · Restricted Project
khchen added inline comments to D93705: [RISCV] Define vector mask-register logical intrinsics..
Wed, Dec 23, 8:09 AM · Restricted Project
khchen updated the diff for D93705: [RISCV] Define vector mask-register logical intrinsics..

remove vmmv and vmnot tests.

Wed, Dec 23, 2:18 AM · Restricted Project
khchen committed rG032600b9aef9: [RISCV] Define vmerge/vfmerge intrinsics. (authored by khchen).
[RISCV] Define vmerge/vfmerge intrinsics.
Wed, Dec 23, 12:08 AM
khchen closed D93674: [RISCV] Define vmerge/vfmerge intrinsics..
Wed, Dec 23, 12:07 AM · Restricted Project

Tue, Dec 22

khchen added a comment to D93705: [RISCV] Define vector mask-register logical intrinsics..

address @craig.topper 's comment.
thanks!

Tue, Dec 22, 11:09 PM · Restricted Project
khchen updated the diff for D93705: [RISCV] Define vector mask-register logical intrinsics..
  1. remove vmmv and vmnot.
  2. add tests for v16i1/v32i1/v64i1
  3. add and use AAA intrinsic pattern
Tue, Dec 22, 11:08 PM · Restricted Project
khchen updated the diff for D93674: [RISCV] Define vmerge/vfmerge intrinsics..

address @craig.topper's comment.

Tue, Dec 22, 6:23 PM · Restricted Project
khchen requested review of D93705: [RISCV] Define vector mask-register logical intrinsics..
Tue, Dec 22, 7:18 AM · Restricted Project

Mon, Dec 21

khchen updated the diff for D93674: [RISCV] Define vmerge/vfmerge intrinsics..

update typo

Mon, Dec 21, 10:06 PM · Restricted Project
khchen committed rG7a2c8be641de: [RISCV] Define vleff intrinsics. (authored by khchen).
[RISCV] Define vleff intrinsics.
Mon, Dec 21, 10:06 PM
khchen closed D93516: [RISCV] Define vleff intrinsics..
Mon, Dec 21, 10:05 PM · Restricted Project
khchen requested review of D93674: [RISCV] Define vmerge/vfmerge intrinsics..
Mon, Dec 21, 9:34 PM · Restricted Project

Sat, Dec 19

khchen added inline comments to D93446: [RISCV] Add vadd with mask and without mask builtin..
Sat, Dec 19, 7:03 AM · Restricted Project
khchen committed rG9cf3b1b66650: [RISCV] Define vlxe/vsxe/vsuxe intrinsics. (authored by khchen).
[RISCV] Define vlxe/vsxe/vsuxe intrinsics.
Sat, Dec 19, 6:52 AM
khchen closed D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics..
Sat, Dec 19, 6:52 AM · Restricted Project
khchen updated the diff for D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics..

fix typo

Sat, Dec 19, 6:51 AM · Restricted Project
khchen updated the diff for D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics..

fixed, thanks again!

Sat, Dec 19, 6:28 AM · Restricted Project

Fri, Dec 18

khchen updated the diff for D93516: [RISCV] Define vleff intrinsics..

rebase main

Fri, Dec 18, 12:15 AM · Restricted Project

Thu, Dec 17

khchen requested review of D93516: [RISCV] Define vleff intrinsics..
Thu, Dec 17, 11:50 PM · Restricted Project

Dec 17 2020

khchen accepted D93514: [RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i.

Sorry, I saw D93487 already has negative constant tests, it's enough.

Dec 17 2020, 11:04 PM · Restricted Project
khchen requested changes to D93514: [RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i.
Dec 17 2020, 10:47 PM · Restricted Project
khchen accepted D93514: [RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i.
Dec 17 2020, 10:46 PM · Restricted Project
khchen updated the diff for D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics..

address @craig.topper's comments. thanks!

Dec 17 2020, 7:29 PM · Restricted Project
khchen committed rG4b07c515ef40: [RISCV] Define vlse/vsse intrinsics. (authored by khchen).
[RISCV] Define vlse/vsse intrinsics.
Dec 17 2020, 5:00 PM
khchen closed D93445: [RISCV] Define vlse/vsse intrinsics..
Dec 17 2020, 5:00 PM · Restricted Project
khchen requested review of D93471: [RISCV] Define vlxe/vsxe/vsuxe intrinsics..
Dec 17 2020, 10:25 AM · Restricted Project
khchen updated the diff for D93445: [RISCV] Define vlse/vsse intrinsics..

address @craig.topper comment and update tests.

Dec 17 2020, 10:08 AM · Restricted Project

Dec 16 2020

khchen requested review of D93445: [RISCV] Define vlse/vsse intrinsics..
Dec 16 2020, 10:40 PM · Restricted Project
khchen accepted D93409: [RISCV] Infer mask type for vector intrinsics from the data type.
Dec 16 2020, 7:36 PM · Restricted Project
khchen committed rGc1d6d461aa77: [RISCV] Define vle/vse intrinsics. (authored by khchen).
[RISCV] Define vle/vse intrinsics.
Dec 16 2020, 6:08 PM
khchen added a comment to D93409: [RISCV] Infer mask type for vector intrinsics from the data type.

LGTM.

Dec 16 2020, 6:08 PM · Restricted Project
khchen closed D93359: [RISCV] Define vle/vse intrinsics..
Dec 16 2020, 6:08 PM · Restricted Project
khchen added inline comments to D93359: [RISCV] Define vle/vse intrinsics..
Dec 16 2020, 5:47 AM · Restricted Project
khchen updated the diff for D93359: [RISCV] Define vle/vse intrinsics..

address @craig.topper's comment

Dec 16 2020, 5:27 AM · Restricted Project

Dec 15 2020

khchen requested review of D93359: [RISCV] Define vle/vse intrinsics..
Dec 15 2020, 7:01 PM · Restricted Project
khchen committed rG15ce0ab7ac46: [RISCV] Refine vector load/store tablegen pattern, NFC. (authored by khchen).
[RISCV] Refine vector load/store tablegen pattern, NFC.
Dec 15 2020, 6:58 PM
khchen closed D93284: [RISCV] Refine vector load/store tablegen pattern, NFC..
Dec 15 2020, 6:58 PM · Restricted Project
khchen updated the diff for D93284: [RISCV] Refine vector load/store tablegen pattern, NFC..

Fix wrong index

Dec 15 2020, 8:06 AM · Restricted Project
khchen updated khchen.
Dec 15 2020, 12:34 AM
khchen requested review of D93284: [RISCV] Refine vector load/store tablegen pattern, NFC..
Dec 15 2020, 12:13 AM · Restricted Project

Dec 11 2020

khchen added a comment to D93080: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter.

Maybe we should use tail undisturbed for instructions that have something like "let Constraints = "$rd = $rs3"?

Dec 11 2020, 5:52 AM · Restricted Project

Dec 10 2020

khchen added a comment to D93080: [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter.

Hi @craig.topper
I think maybe default tail undisturbed would be more friendly and intuitive for programmer or vectorizer in reduction case.
please see below example:

Dec 10 2020, 5:57 PM · Restricted Project

Dec 7 2020

khchen added inline comments to D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 7:32 PM · Restricted Project

Nov 29 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

How does the CLI options correspond with the back-end capabilities?

Nov 29 2020, 5:48 AM · Restricted Project, Restricted Project

Nov 25 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.
In D71124#2415424, @oceanfish81 wrote:

I tried to build the following:

https://gist.github.com/advancedwebdeveloper/09033869445a09a2e297a73387d46c41/raw/bf7dac33e256621c445f9e61f88a832e50d901a3/llvm_cpu_features_investigation.cpp

but it didn't show me any CPU features, on https://fedoraproject.org/wiki/Architectures/RISC-V/Installing#Boot_under_QEMU

Nov 25 2020, 6:43 PM · Restricted Project, Restricted Project

Nov 24 2020

Herald added a reviewer for D47769: [SVE][TableGen] LLT support for scalable vectors: efriedma.
Nov 24 2020, 11:24 PM

Oct 15 2020

khchen added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

FYI: LLVM-RVV CodeGen RFC slide.

Oct 15 2020, 7:44 AM · Restricted Project

Oct 12 2020

khchen added a comment to D89025: [RISCV] Add -mtune support.

RISCV supports -mcpu with default empty arch to align gcc's -mtune behavior since clang didn't support -mtune before. But now clang has -mtune, is it a good idea to remove those options? (ex. rocket-rv32/rv64, sifive-7-rv32/64)

Oct 12 2020, 1:54 AM · Restricted Project, Restricted Project

Oct 6 2020

Herald added a reviewer for D53613: RFC: Explicit Vector Length Intrinsics and Attributes: jdoerfert.
Oct 6 2020, 12:00 AM · Restricted Project

Oct 4 2020

khchen accepted D88759: [RISCV] Add SiFive cores to the CPU option.

LGTM.

Oct 4 2020, 7:20 PM · Restricted Project, Restricted Project

Jul 15 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address @lenary's comment, good catch! thanks a lot!!

Jul 15 2020, 8:17 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address @asb's comment. thanks.

Jul 15 2020, 1:42 AM · Restricted Project, Restricted Project

Jul 14 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

Hi @lenary
This is normal behavior in current clang implementation,
-mcpu=? flag does not interact with any flags, it just print out the all of ProcessorModel registered in backend.
https://github.com/llvm/llvm-project/blob/master/clang/tools/driver/cc1_main.cpp#L213-L215

Jul 14 2020, 6:46 PM · Restricted Project, Restricted Project

Jul 11 2020

khchen added a comment to D71124: [RISCV] support clang driver to select cpu.

@asb @lenary I thought this path is ready to land?

Jul 11 2020, 7:41 PM · Restricted Project, Restricted Project

Jul 10 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

avoid to check compiler version in testcase

Jul 10 2020, 9:06 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

fix typo

Jul 10 2020, 8:00 AM · Restricted Project, Restricted Project
khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

addess @asb 's comment.

Jul 10 2020, 1:48 AM · Restricted Project, Restricted Project

Jul 9 2020

khchen planned changes to D71124: [RISCV] support clang driver to select cpu.

BTW, this patch depends on D77030, which aim to avoid the forcing of any ProcessorModel to have FeatureRVCHints feature.
But if we decide to keep the FeatureRVCHints, I need to change implementation a little.

Jul 9 2020, 6:40 AM · Restricted Project, Restricted Project

May 6 2020

khchen updated the diff for D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV.

update testcases

May 6 2020, 2:39 AM · Restricted Project, Restricted Project

May 3 2020

khchen updated the diff for D71124: [RISCV] support clang driver to select cpu.

address kito's comment

May 3 2020, 11:57 PM · Restricted Project, Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

s/ld/lld/

May 3 2020, 8:41 PM · Restricted Project
khchen updated the diff for D78988: [LTO] Suppress emission of empty combined module by default.

address @MaskRay's review feedback

May 3 2020, 10:37 AM · Restricted Project
khchen updated the summary of D78988: [LTO] Suppress emission of empty combined module by default.
May 3 2020, 10:37 AM · Restricted Project

May 2 2020

khchen retitled D78988: [LTO] Suppress emission of empty combined module by default from [LTO] Suppress emission of the empty object file to [LTO] Suppress emission of empty combined module by default.
May 2 2020, 7:55 AM · Restricted Project

Apr 30 2020

khchen updated the diff for D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.

rebase on master

Apr 30 2020, 4:43 AM · Restricted Project