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efriedma (Eli Friedman)
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Aug 10 2016, 1:07 PM (179 w, 3 d)

Recent Activity

Yesterday

efriedma added a comment to D72961: In early-ifconversion check that the operands of a PHI share a common regclass with the destination regclass..

My initial reaction was that the PHI was invalid, but according to @qcolombet it's ok to have different register banks on the operands

Fri, Jan 17, 5:05 PM · Restricted Project
efriedma added a comment to D72646: [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory.

It looks like the build isn't passing the new flag to cmake. Does the buildbot need to be restarted?

Fri, Jan 17, 4:55 PM
efriedma created D72968: [lld][ELF] Don't apply --fix-cortex-a53-843419 to relocatable links..
Fri, Jan 17, 4:46 PM · Restricted Project
efriedma added inline comments to D29014: [SelDag][MIR] Add FREEZE.
Fri, Jan 17, 4:27 PM · Restricted Project
efriedma accepted D72762: [ARM][TargetParser] Improve handling of dependencies between target features.

LGTM

Fri, Jan 17, 3:58 PM · Restricted Project
efriedma added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

I don't like fiddling with the ABI based on CPU features; it's common to mix code with different CPU features enabled (particularly for desktop/mobile CPUs; less so on microcontrollers, but it can still happen). If we want to support some other ABI for performance reasons, we should make the user request it explicitly.

Fri, Jan 17, 3:58 PM
efriedma added a comment to D72961: In early-ifconversion check that the operands of a PHI share a common regclass with the destination regclass..

What is the restriction on the register classes of PHI operands, if they don't have to have to be same register class as the result? I don't see any relevant documentation, or checks in MachineVerifier::checkPHIOps().

Fri, Jan 17, 3:30 PM · Restricted Project
efriedma accepted D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

LGTM

Fri, Jan 17, 1:17 PM · Restricted Project
efriedma committed rG447dcef79001: Revert "[SVE] Pass Scalable argument to VectorType::get in Bitcode Reader" (authored by efriedma).
Revert "[SVE] Pass Scalable argument to VectorType::get in Bitcode Reader"
Fri, Jan 17, 12:18 PM
efriedma added a reverting change for rG5df53a225927: [SVE] Pass Scalable argument to VectorType::get in Bitcode Reader: rG447dcef79001: Revert "[SVE] Pass Scalable argument to VectorType::get in Bitcode Reader".
Fri, Jan 17, 12:18 PM

Thu, Jan 16

efriedma added a comment to D72869: Add __warn_memset_zero_len builtin as a workaround for glibc issue.

We currently don't have any mechanism for restricting builtins to specific operating systems. I guess we could add one, but this change doesn't seem like a compelling argument to add that capability.

Thu, Jan 16, 4:42 PM · Restricted Project
efriedma added a comment to D72315: [NFC] Simplifying the condition which kind of MCFragment doesn't need to handle fixup.

Did you audit the other uses of dyn_cast<MCEncodedFragment>

Thu, Jan 16, 3:53 PM · Restricted Project
efriedma added a comment to D71469: [AArch64] Add sq(r)dmulh_lane(q) LLVM IR intrinsics.

This makes it impossible to do a neat trick when using NEON intrinsics: one can load a number of constants using a single vector load, which are then repeatedly used to multiply whole vectors by one of the constants. This trick is used for a nice performance upside (2.5% to 4% on one microbenchmark) in libjpeg-turbo.

Thu, Jan 16, 3:43 PM · Restricted Project, Restricted Project
efriedma added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

It is not redundant with respect to -mfloat-abi=soft, as it leaves the door open to passing integer vector arguments via the so-called "FP registers".

So then "-mfloat-abi=hard -mfpu=none" means "pass floating-point values in registers, but don't use any other floating-point operations"?

No, it does not mean that, at least not yet, and it's not immediately obvious if that would be of any advantage. But it does affect integer vectors.

Thu, Jan 16, 3:03 PM
efriedma accepted D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates.
Thu, Jan 16, 2:43 PM · Restricted Project
efriedma added inline comments to D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
Thu, Jan 16, 2:34 PM · Restricted Project
efriedma accepted D72869: Add __warn_memset_zero_len builtin as a workaround for glibc issue.

LGTM

Thu, Jan 16, 2:15 PM · Restricted Project
efriedma added a comment to D65653: [AArch64] Change location of frame-record within callee-save area..

So I believe that after this change, we are no longer guaranteed that FP + 16 = SP at exit, correct?

Thu, Jan 16, 2:15 PM · Restricted Project
efriedma added a comment to D70072: [ARM] Improve codegen of volatile load/store of i64.

Apparently the ARM-mode LDRD is a bit more strange than I realized. From the ARM manual: if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;. I guess we're managed to avoid running into this in the past by never generating the register form of ldrd.

Thu, Jan 16, 1:45 PM · Restricted Project
efriedma added a comment to D72869: Add __warn_memset_zero_len builtin as a workaround for glibc issue.

This is very hacky, but it might be the least-bad alternative. I mean, we could change D71082 so it doesn't allow system headers to define memset, but that seems worse.

Thu, Jan 16, 1:16 PM · Restricted Project

Wed, Jan 15

efriedma added inline comments to D72753: [ARM] Fixup FP16 bitcasts.
Wed, Jan 15, 3:44 PM · Restricted Project
efriedma added inline comments to D72758: Add OffsetIsScalable to getMemOperandWithOffset.
Wed, Jan 15, 3:20 PM · Restricted Project
efriedma added inline comments to D72753: [ARM] Fixup FP16 bitcasts.
Wed, Jan 15, 2:46 PM · Restricted Project
efriedma accepted D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates.

LGTM with one question

Wed, Jan 15, 1:40 PM · Restricted Project
efriedma added a comment to D71710: [instrinsics] Add @llvm.memcpy.inline instrinsics.

It would be nice to do a bit more work so various optimizations handle llvm.memcpy.inline in a way that isn't completely conservative (for example, in alias analysis), but I guess that doesn't need to be in the initial patch.

I'm not too familiar with AA but my understanding is that the definition in llvm/include/llvm/IR/Intrinsics.td already describes the arguments with enough precision to be helpful for the AA pass.

def int_memcpy_inline
    : Intrinsic<[],
      [ llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i1_ty ],
      [ IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>,
      ImmArg<2>, ImmArg<3> ]>;

Did you have something specific in mind? Or am I missing something completely?

Wed, Jan 15, 1:38 PM · Restricted Project
efriedma added a comment to D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

Can we also also add mul patterns for targets that have SVE, but not SVE2?

That instruction is restricted to SVE2. Do we have unpredicated vector mul instructions for SVE targets as well?

Wed, Jan 15, 1:30 PM · Restricted Project
efriedma added a comment to D71992: [ARM] Unrestrict Armv8 IT blocks.

I'm not really tracking performance for 32-bit armv8-a at the moment... but I would be fine with changing the default with appropriate testing. I don't think we should have core-specific heuristics unless there's evidence some core is actually different in a meaningful way.

Wed, Jan 15, 1:29 PM · Restricted Project
efriedma added a comment to D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions.

Can we also also add mul patterns for targets that have SVE, but not SVE2?

Wed, Jan 15, 12:24 PM · Restricted Project
efriedma added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

It is not redundant with respect to -mfloat-abi=soft, as it leaves the door open to passing integer vector arguments via the so-called "FP registers".

Wed, Jan 15, 12:05 PM
efriedma added inline comments to D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
Wed, Jan 15, 11:37 AM · Restricted Project
efriedma added a comment to D72792: [SVE] Pass Scalable argument to VectorType::get in Bitcode Reader.

Please add a testcase to make sure we can round-trip from .ll->.bc->.ll.

Wed, Jan 15, 11:18 AM · Restricted Project

Tue, Jan 14

efriedma committed rZORG6ad01600c4e2: [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory (authored by efriedma).
[zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory
Tue, Jan 14, 6:11 PM
efriedma closed D72646: [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory.
Tue, Jan 14, 6:11 PM
efriedma added a comment to D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

This makes sense.

Tue, Jan 14, 5:22 PM · Restricted Project
efriedma accepted D67678: PR17164: Change clang's default behavior from -flax-vector-conversions=all to -flax-vector-conversions=integer..

LGTM

Tue, Jan 14, 5:21 PM · Restricted Project
efriedma added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

Okay. Please let me know if you want me to review anything.

Tue, Jan 14, 5:08 PM · Restricted Project
efriedma accepted D72728: [LegalizeTypes] Remove untested code from ExpandIntOp_UINT_TO_FP.

check is false for most combinations for int and fp types except maybe i32 and f64

Tue, Jan 14, 12:30 PM · Restricted Project
efriedma added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

In terms of the user-visible behavior, I guess my question is whether it would make sense to add "-mfpu=mve"/"-mfpu=mve.fp", and make "-mfpu=none" mean "no FP registers". I'm not sure why a user would specify "-mfpu=none" if they didn't want to disable the floating-point registers altogether.

Tue, Jan 14, 12:12 PM
efriedma accepted D72654: [SVE] Add patterns for MUL immediate instruction..

LGTM

Tue, Jan 14, 11:33 AM · Restricted Project
efriedma accepted D72398: [AArch64][SVE] Add ptest intrinsics.

LGTM

Tue, Jan 14, 11:13 AM · Restricted Project
efriedma added a comment to D68203: Add support for (expressing) vscale..

LGTM.

Tue, Jan 14, 11:03 AM · Restricted Project

Mon, Jan 13

efriedma updated the diff for D72467: Remove "mask" operand from shufflevector..

Fixed one more issue. While I'm at it, get rid of the old overload of ConstantExpr::getShuffleVector, which only had a few remaining uses.

Mon, Jan 13, 6:32 PM · Restricted Project, Restricted Project
efriedma updated the diff for D72467: Remove "mask" operand from shufflevector..

Rebase. Address review comment. More work on bitcode.

Mon, Jan 13, 5:45 PM · Restricted Project, Restricted Project
efriedma committed rGe68e4cbcc50b: [GlobalISel] Change representation of shuffle masks in MachineOperand. (authored by efriedma).
[GlobalISel] Change representation of shuffle masks in MachineOperand.
Mon, Jan 13, 4:59 PM
efriedma closed D72663: [GlobalISel] Change representation of shuffle masks in MachineOperand..
Mon, Jan 13, 4:59 PM · Restricted Project
efriedma added a comment to D72666: [IR] ArgMemOnly functions with WriteOnly ptr args do not read memory..

I'd prefer to just add writeonly markings in places where they're missing. For llvm.memset in particular, can we mark it IntrWriteMem?

Mon, Jan 13, 4:50 PM · Restricted Project
efriedma added inline comments to D72663: [GlobalISel] Change representation of shuffle masks in MachineOperand..
Mon, Jan 13, 4:32 PM · Restricted Project
efriedma created D72663: [GlobalISel] Change representation of shuffle masks in MachineOperand..
Mon, Jan 13, 3:54 PM · Restricted Project
efriedma added inline comments to D72467: Remove "mask" operand from shufflevector..
Mon, Jan 13, 3:08 PM · Restricted Project, Restricted Project
efriedma accepted D72652: [NFC][IndVarSimplify] remove duplicate code in widenWithVariantLoadUseCodegen.

LGTM. Do you have commit access?

Mon, Jan 13, 3:08 PM · Restricted Project
efriedma added a comment to D72654: [SVE] Add patterns for MUL immediate instruction..

Do we have any negative tests, for immediates that are outside the range of the sve mul immediate instruction?

Mon, Jan 13, 2:59 PM · Restricted Project
efriedma added a comment to D71992: [ARM] Unrestrict Armv8 IT blocks.

Are there any cores where we don't want FeatureDontRestrictIT ? I mean, multi-instruction it blocks were formally deprecated, but I'm not sure anyone actually took advantage of that.

Mon, Jan 13, 2:58 PM · Restricted Project
efriedma created D72646: [zorg] Pass "-DLLVM_POLLY_LINK_INTO_TOOLS=ON" in getPollyBuildFactory.
Mon, Jan 13, 2:02 PM
efriedma accepted D71216: [AArch64] Implement passing SVE vectors by ref for AAPCS..

Please add a comment explaining each isScalableVector(), to make it clear why we're excluding them. Otherwise LGTM

Mon, Jan 13, 1:24 PM · Restricted Project
efriedma edited reviewers for D69372: [X86][VARARG] Avoid spilling xmm vararg arguments., added: rnk; removed: efriedma.

Target-independent changes look fine.

Mon, Jan 13, 1:15 PM · Restricted Project
efriedma added a comment to D68203: Add support for (expressing) vscale..

The new IR intrinsic makes more sense.

Mon, Jan 13, 1:05 PM · Restricted Project
efriedma added a comment to D72579: Evaluate __{c11_,}atomic_is_lock_free to 0 (avoid libcall) if larger than MaxAtomicPromoteWidth.

Eagerly evaluating based on MaxAtomicPromoteWidth seems fine... assuming we're actually setting MaxAtomicPromoteWidth to something appropriate. The value on PowerPC looks wrong.

Mon, Jan 13, 12:56 PM · Restricted Project
efriedma added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

Probably if I was designing these flags from scratch, I wouldn't choose the semantics of "-mfpu=none is *very* similar to -mfloat-abi=soft, only that it should not disable MVE-I.", but I guess we're following gcc here?

Mon, Jan 13, 12:37 PM
efriedma added inline comments to D72612: [AArch64][SVE] Add ImmArg property to intrinsics with immediates.
Mon, Jan 13, 12:27 PM · Restricted Project
efriedma accepted D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP.

LGTM

Mon, Jan 13, 12:09 PM · Restricted Project

Fri, Jan 10

efriedma accepted D72398: [AArch64][SVE] Add ptest intrinsics.

LGTM with one minor request.

Fri, Jan 10, 6:18 PM · Restricted Project
efriedma added a comment to D68203: Add support for (expressing) vscale..

Does it make sense to have a special case for vscale * 1 or vscale * -1? Not that it's likely to come up in most cases, but it would look pretty silly to generate a madd that multiplies by 1.

Fri, Jan 10, 6:09 PM · Restricted Project
efriedma accepted D72536: [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from RunttimeLibcalls.def and all associated usages.

LGTM

Fri, Jan 10, 5:47 PM · Restricted Project
efriedma added a comment to D72519: [LoopInfo] Support multi edge in getLoopLatch().

My concern with this is that there there might be some places where we're assuming the backedge of a loop latch is exactly one edge, and you might not have found them. There are a lot of places that call getLoopLatch or isLoopSimplifyForm, we don't really have much regression test coverage for this sort of construct, and the C/C++ tests most people run probably have few switches like this.

Fri, Jan 10, 5:38 PM · Restricted Project
efriedma updated the diff for D72467: Remove "mask" operand from shufflevector..

Figured out the changes necessary to get bitcode reading/writing working. ninja check now passes.

Fri, Jan 10, 5:11 PM · Restricted Project, Restricted Project
efriedma added inline comments to D72467: Remove "mask" operand from shufflevector..
Fri, Jan 10, 5:02 PM · Restricted Project, Restricted Project
efriedma updated the diff for D72467: Remove "mask" operand from shufflevector..

Add more comments, fixed the GlobalISel representation of shuffles, misc other cleanups. Still haven't addressed the bitcode reader/writer issues.

Fri, Jan 10, 3:59 PM · Restricted Project, Restricted Project
efriedma added a comment to D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.

I'd like to see a few more testcases here, to cover the new functionality

Fri, Jan 10, 9:33 AM · Restricted Project

Thu, Jan 9

efriedma added inline comments to D72420: [LoopRotate] Add support for rotating loops with switch exit.
Thu, Jan 9, 5:58 PM · Restricted Project
efriedma added a comment to D71636: [AArch64][SVE][WIP] Add support for vscale constants (?).
My current thinking for shuffles is that we shouldn't represent the shuffle mask of shufflevector as a Constant at all.

If shuffle masks are no longer IR entities, this means ruling out computed shuffle masks in the future, which are available on some targets (X86). Whether we want computed shuffle masks at all is a different question.

Thu, Jan 9, 3:17 PM · Restricted Project
efriedma accepted D71082: Allow system header to provide their own implementation of some builtin.

LGTM

Thu, Jan 9, 3:06 PM · Restricted Project
efriedma accepted D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP.

LGTM

Thu, Jan 9, 2:56 PM · Restricted Project
efriedma added a comment to D71978: [RISCV] Fix evalutePCRelLo for symbols at the end of a fragment.

Instead of returning a symbol difference from evaluatePCRelLo and folding it MCAssembler, can just fold the symbol difference to a constant in evaluatePCRelLo itself? MCExpr::evaluateAsRelocatableImpl does something like that in EvaluateSymbolicAdd.

Thu, Jan 9, 2:47 PM · Restricted Project
efriedma accepted D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

LGTM

Thu, Jan 9, 1:50 PM · Restricted Project
efriedma updated the diff for D72467: Remove "mask" operand from shufflevector..

(Reupload with context.)

Thu, Jan 9, 10:42 AM · Restricted Project, Restricted Project
efriedma created D72467: Remove "mask" operand from shufflevector..
Thu, Jan 9, 10:33 AM · Restricted Project, Restricted Project

Wed, Jan 8

efriedma added inline comments to D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP.
Wed, Jan 8, 1:18 PM · Restricted Project
efriedma added inline comments to D71698: [AArch64][SVE] Add intrinsic for non-faulting loads.
Wed, Jan 8, 12:41 PM · Restricted Project
efriedma added a comment to D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM.

It might be possible to rearrange Low Overhead Loops to run before ConstantIslands, but you'd probably need to do more to make it work properly. I don't think ConstantIslands knows how to handle the branches generated by LowOverheadLoop. If you think it's necessary, please split it into a separate patch with proper tests.

Wed, Jan 8, 12:32 PM · Restricted Project, Restricted Project

Tue, Jan 7

efriedma accepted D71978: [RISCV] Fix evalutePCRelLo for symbols at the end of a fragment.

the approach that's here has proved sufficient in all the cases we can come up with

Tue, Jan 7, 5:32 PM · Restricted Project
efriedma added a comment to D71978: [RISCV] Fix evalutePCRelLo for symbols at the end of a fragment.

it requires . and .Ltmp0 be in the same fragment [...] This is checked earlier by ensuring findAssociatedFragment() matches for each.

Tue, Jan 7, 4:21 PM · Restricted Project
efriedma added a comment to D71978: [RISCV] Fix evalutePCRelLo for symbols at the end of a fragment.

I think ultimately, the problem here is that the relocation is marked FKF_IsPCRel. That has a specific meaning that doesn't apply here: the ultimate value encoded into the addi is based on the distance between two symbols: the symbol in the pcrel_lo, and the symbol in the corresponding pcrel_hi. The address of the addi itself isn't relevant.

Tue, Jan 7, 1:46 PM · Restricted Project
efriedma added a comment to D71978: [RISCV] Fix evalutePCRelLo for symbols at the end of a fragment.

I don't understand what you're doing here.

Tue, Jan 7, 1:36 PM · Restricted Project
efriedma added inline comments to D72299: [DSE] Improve mayThrowBetween for 2 instructions in the same BB..
Tue, Jan 7, 12:58 PM · Restricted Project
efriedma added a comment to D61446: Generalize the pass registration mechanism used by Polly to any third-party tool.

http://lab.llvm.org:8011/builders/aosp-O3-polly-before-vectorizer-unprofitable is currently broken, I think due to this patch. It looks like polly isn't getting linked into clang by default anymore?

Tue, Jan 7, 12:20 PM · Restricted Project, Restricted Project

Mon, Jan 6

efriedma added a comment to D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

better reflect the difference in the semantics of the corresponding instructions

Mon, Jan 6, 3:03 PM · Restricted Project
efriedma added inline comments to D72299: [DSE] Improve mayThrowBetween for 2 instructions in the same BB..
Mon, Jan 6, 2:25 PM · Restricted Project
efriedma added inline comments to D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP.
Mon, Jan 6, 1:57 PM · Restricted Project
efriedma added a comment to D71710: [instrinsics] Add @llvm.memcpy.inline instrinsics.

Needs a LangRef update.

Mon, Jan 6, 12:42 PM · Restricted Project
efriedma added a comment to D71828: [InstCombine] Convert vector store to scalar store if only one element updated.

I think you need to check the elements are byte-sized?

Mon, Jan 6, 12:24 PM · Restricted Project
efriedma added inline comments to D72224: [LegalizeVectorOps] Improve handling of multi-result operations..
Mon, Jan 6, 12:14 PM · Restricted Project

Sun, Dec 29

efriedma added a comment to D60031: Split tailcallelim into tailcallmark and tailcallelim.

What happened to this patch?

Sun, Dec 29, 10:06 PM · Restricted Project
efriedma added inline comments to D71861: [LegalizeVectorOps] Pass the post-UpdateNodeOperands version of the Node to the LowerOperation/PromoteNode/ExpandNode calls.
Sun, Dec 29, 10:00 PM · Restricted Project

Mon, Dec 23

efriedma added a comment to D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

Wong SMAX; you're referring to VECREDUCE_SMAX, which isn't relevant here. There is no IR intrinsic for ISD::SMAX; it's pattern-matched from select instructions.

Mon, Dec 23, 9:25 AM · Restricted Project

Fri, Dec 20

efriedma added a comment to D71714: [Sema] Fix -Warray-bounds false negative when casting an out-of-bounds array item.

and it seems to involve a lot of AST traversal

Fri, Dec 20, 2:30 PM · Restricted Project
efriedma added inline comments to D71698: [AArch64][SVE] Add intrinsic for non-faulting loads.
Fri, Dec 20, 2:08 PM · Restricted Project
efriedma added a comment to D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions.

Do we actually need an intrinsic for this, as opposed to adding patterns for ISD::SMAX etc.?

Fri, Dec 20, 1:58 PM · Restricted Project
efriedma accepted D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

Would it make sense to merge int_aarch64_sve_ld1_gather and int_aarch64_sve_ld1_gather_imm into one intrinsic? They're sort of similar... maybe not worth messing with it, though.

Fri, Dec 20, 1:58 PM · Restricted Project
efriedma added a comment to D71742: Added intrinsics for access to FP environment.

It is expected that targets will implement custom lowering to proper machine instructions for better performance.

Fri, Dec 20, 1:47 PM · Restricted Project
efriedma added a comment to D71636: [AArch64][SVE][WIP] Add support for vscale constants (?).

Can we guarantee "sizeof(<vscale x 1 x i8>) == vscale" for all future targets?

Fri, Dec 20, 1:37 PM · Restricted Project