dsanders (Daniel Sanders)
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Aug 19 2013, 3:30 PM (230 w, 1 d)

Recent Activity

Today

dsanders added a comment to rL322086: [CodeGen] Don't print register classes in -debug output.

Hmm this change is not equivalent. Take a random example of a testcase here:

%2:gpr = SMULBB %1, %1, pred:14, pred:%noreg; GPR:%2,%1,%1

now becomes:

%2:gpr = SMULBB %1, %1, pred:14, pred:%noreg

the register class of %1 is no longer visible.

While it is fine to only print the regclass for definitions when printing a whole .mir file, when we only print a single instruction we need the register class on use operands as well!

I agree. Although I would like to get rid of the "; GPR..." syntax.

How about:

%2:gpr = SMULBB %1:gpr, %1:gpr, 14, %noreg

This would allow us to still have valid MIR.

Tue, Jan 16, 10:07 AM
dsanders added a comment to rL322086: [CodeGen] Don't print register classes in -debug output.

I agree, we need the classes when printing single/few instructions. I also think this generally makes it harder to debug things which is contradictory to the purpose of -debug.

Tue, Jan 16, 10:04 AM

Fri, Jan 12

dsanders accepted D42012: [GlobalISel][TableGen] Add support for SDNodeXForm.

LGTM with some nits fixed

Fri, Jan 12, 5:50 PM

Tue, Jan 2

dsanders added inline comments to D41373: [GISel][RFC]: GlobalISel Combiner prototype.
Tue, Jan 2, 6:05 PM
dsanders added a comment to D41373: [GISel][RFC]: GlobalISel Combiner prototype.

GICombinerHelper - this contains transformations that are common to all targets. Targets can pick and choose which transformations (at function/opcode granularity) each pass uses via configuring a GICombinerInfo.

Tue, Jan 2, 5:08 PM

Thu, Dec 21

dsanders added a comment to D41362: [AArch64][GlobalISel] Enable GlobalISel at -O0 by default.

How about checking for EnableGlobalISelAbort.getNumOccurences() > 0 to check for an command line override, otherwise doing what the target wants via the isGlobalISelAbortEnabled() override?

That's what I meant :). (Instead of adding a == 3 case for the option.)

Thu, Dec 21, 3:23 AM

Wed, Dec 20

dsanders committed rL321176: [globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector….
[globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector…
Wed, Dec 20, 6:42 AM

Mon, Dec 18

dsanders added inline comments to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.
Mon, Dec 18, 11:51 AM

Dec 11 2017

dsanders added inline comments to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.
Dec 11 2017, 2:58 PM
dsanders accepted D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.

LGTM. We need to follow up with the refactor to eliminate clearImplicitMap() though. We ought to follow up with the simplification of PredicateListMatcher too. The templating isn’t very useful anymore now that predicates have a common base class

Dec 11 2017, 2:07 PM

Dec 4 2017

dsanders committed rL319739: Revert r319691: [globalisel][tablegen] Split atomic load/store into separate….
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate…
Dec 4 2017, 9:52 PM
dsanders committed rL319701: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..
Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC.
Dec 4 2017, 1:41 PM
dsanders closed D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..
Dec 4 2017, 1:41 PM
dsanders committed rL319698: [globalisel][tablegen] Tests for r319691.
[globalisel][tablegen] Tests for r319691
Dec 4 2017, 1:15 PM
dsanders committed rL319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable….
[globalisel][tablegen] Split atomic load/store into separate opcode and enable…
Dec 4 2017, 12:40 PM
dsanders added inline comments to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.
Dec 4 2017, 10:17 AM

Dec 1 2017

dsanders added inline comments to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.
Dec 1 2017, 5:27 PM

Nov 30 2017

dsanders committed rL319475: [globalisel][tablegen] Add support for relative AtomicOrderings.
[globalisel][tablegen] Add support for relative AtomicOrderings
Nov 30 2017, 1:06 PM
dsanders committed rL319466: [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*.
[aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*
Nov 30 2017, 12:12 PM
dsanders accepted D39823: GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES.

LGTM

Nov 30 2017, 11:30 AM
dsanders committed rL319457: [globalisel][tablegen] Add support for specific immediates in the match pattern.
[globalisel][tablegen] Add support for specific immediates in the match pattern
Nov 30 2017, 10:49 AM
dsanders accepted D40604: [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads and stores.

LGTM

Nov 30 2017, 9:54 AM

Nov 29 2017

dsanders added a comment to D40074: [GISel] Canonicalize constants to RHS for commutative operations.

I see why ARM is different from AArch64. ARM only sees one pattern being emitted because TableGen has some code that prevents commutativity being considered when one of the children of a
commutative operator is either the imm operator or a plain integer (see OnlyOnRHSOfCommutative() which is used in canPatternMatch()). Meanwhile, AArch64's case is using a ComplexPattern so both cases get emitted.

So it appears that TableGen considers commutative pattern but chooses to ignore the second pattern because it knows theres some canonicalization taking place.

Yes, the canonicalization takes place in the target-independent part of the SelectionDAG code (SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags).

I guess one advantage that DAGISel has over GlobalISel is that the getNode helpers are used throughout instruction selection. If we wanted the same kind of behaviour for GlobalISel, we'd have to put this canonicalization in the MachineInstrBuilder, but that would affect the whole backend.

I think for now it's better to keep this in the IRTranslator since it's the least disruptive thing to do, and any subsequent passes (e.g. combiners and whatnot) can benefit from having a canonical form to work with most of the time. An alternative would be to move these things into their own canonicalization pass that we can then schedule whenever we see fit, but that might be a bit overkill since adding canonicalizations isn't really a priority at this point.

Nov 29 2017, 1:23 PM
dsanders added inline comments to D39823: GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES.
Nov 29 2017, 10:48 AM
dsanders added inline comments to D40604: [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads and stores.
Nov 29 2017, 9:41 AM
dsanders added inline comments to D40604: [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads and stores.
Nov 29 2017, 8:38 AM

Nov 28 2017

dsanders committed rL319252: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match….
[globalisel][tablegen] Fix PR35375 by sign-extending the table value to match…
Nov 28 2017, 3:19 PM
dsanders closed D40532: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal().
Nov 28 2017, 3:19 PM
dsanders updated the summary of D40532: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal().
Nov 28 2017, 3:18 PM
dsanders added a comment to D40532: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal().

I think GIM_CheckLiteralInt might have the same issue but I don't think there's any existing rules that would detect the problem. As far as I know X86 is the only user and only uses 0 and 1. We should probably change it to match GIM_CheckConstantInt if only for consistency. Do you agree?

Nov 28 2017, 2:56 PM
dsanders committed rL319232: [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG….
[globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG…
Nov 28 2017, 2:07 PM
dsanders committed rL319220: [aarch64][globalisel] Add missing tests from r319216.
[aarch64][globalisel] Add missing tests from r319216
Nov 28 2017, 12:28 PM
dsanders committed rL319216: [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them….
[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them…
Nov 28 2017, 12:21 PM
dsanders added a comment to D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together..

Thanks

Nov 28 2017, 10:57 AM
dsanders committed rL319202: [mir] Print/Parse both MOLoad and MOStore when they occur together..
[mir] Print/Parse both MOLoad and MOStore when they occur together.
Nov 28 2017, 10:57 AM
dsanders closed D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together..
Nov 28 2017, 10:57 AM

Nov 27 2017

dsanders added a comment to D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg.

ping

Nov 27 2017, 5:40 PM
dsanders added a comment to D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..

ping

Nov 27 2017, 5:40 PM
dsanders added a comment to D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together..

ping

Nov 27 2017, 5:39 PM
dsanders created D40532: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal().
Nov 27 2017, 5:17 PM
dsanders committed rL319093: Add release note about TargetRegistry change from r318352.
Add release note about TargetRegistry change from r318352
Nov 27 2017, 1:13 PM

Nov 17 2017

dsanders committed rL318574: [globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN..
[globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN.
Nov 17 2017, 4:17 PM
dsanders added dependencies for D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg: D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together., D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..
Nov 17 2017, 9:01 AM
dsanders added a dependent revision for D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC.: D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg.
Nov 17 2017, 9:01 AM
dsanders added a dependent revision for D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together.: D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg.
Nov 17 2017, 9:01 AM
dsanders updated the diff for D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg.

Rename G_ATOMIC_CMPXCHG to G_ATOMIC_CMPXCHG_WITH_SUCCESS. There is a gap between
the LLVM-IR cmpxchg instruction and the SDNode that is usable in SelectionDAG
patterns. IRTranslate into a LLVM-IR-like representation. We'll then bridge the
gap in the legalizer.

Nov 17 2017, 9:01 AM

Nov 16 2017

dsanders updated the diff for D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together..

Include the CHECK lines in the patch.

Nov 16 2017, 4:30 PM
dsanders created D40157: [mir] Print/Parse both MOLoad and MOStore when they occur together..
Nov 16 2017, 4:27 PM
dsanders added a comment to D39742: Add backend name to Target to enable runtime info to be fed back into TableGen.

Hi,

Build for ARC fails, fix TargetInfo for this target please.

Nov 16 2017, 11:17 AM
dsanders committed rL318443: [arc] Fix ambiguous overloaded operator error.
[arc] Fix ambiguous overloaded operator error
Nov 16 2017, 11:17 AM
dsanders committed rL318441: [arc] Update TargetInfo to include the new backend name argument.
[arc] Update TargetInfo to include the new backend name argument
Nov 16 2017, 11:10 AM

Nov 15 2017

dsanders committed rL318356: [globalisel][tablegen] Generate rule coverage and use it to identify untested….
[globalisel][tablegen] Generate rule coverage and use it to identify untested…
Nov 15 2017, 4:46 PM
dsanders closed D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.
Nov 15 2017, 4:46 PM
dsanders committed rL318352: Add backend name to Target to enable runtime info to be fed back into TableGen.
Add backend name to Target to enable runtime info to be fed back into TableGen
Nov 15 2017, 3:56 PM
dsanders closed D39742: Add backend name to Target to enable runtime info to be fed back into TableGen.
Nov 15 2017, 3:55 PM
dsanders updated the summary of D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..
Nov 15 2017, 12:58 PM
dsanders created D40096: Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC..
Nov 15 2017, 12:48 PM
dsanders added a comment to D40074: [GISel] Canonicalize constants to RHS for commutative operations.

I see why ARM is different from AArch64. ARM only sees one pattern being emitted because TableGen has some code that prevents commutativity being considered when one of the children of a commutative operator is either the imm operator or a plain integer (see OnlyOnRHSOfCommutative() which is used in canPatternMatch()). Meanwhile, AArch64's case is using a ComplexPattern so both cases get emitted.

Nov 15 2017, 11:48 AM
dsanders added a comment to D40074: [GISel] Canonicalize constants to RHS for commutative operations.

Hi Diana,

Nov 15 2017, 11:35 AM
dsanders created D40092: [globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg.
Nov 15 2017, 10:51 AM

Nov 13 2017

dsanders added a comment to D39742: Add backend name to Target to enable runtime info to be fed back into TableGen.

ping

Nov 13 2017, 3:05 PM
dsanders committed rL318102: [tablegen] Handle atomic predicates for ordering inside tablegen. NFC..
[tablegen] Handle atomic predicates for ordering inside tablegen. NFC.
Nov 13 2017, 3:05 PM
dsanders committed rL318095: [tablegen] Handle atomic predicates for memory type inside tablegen. NFC..
[tablegen] Handle atomic predicates for memory type inside tablegen. NFC.
Nov 13 2017, 2:26 PM
dsanders committed rL318068: [globalisel][tablegen] Add support for extload..
[globalisel][tablegen] Add support for extload.
Nov 13 2017, 10:30 AM

Nov 10 2017

dsanders committed rL317971: [globalisel][tablegen] Import signextload and zeroextload..
[globalisel][tablegen] Import signextload and zeroextload.
Nov 10 2017, 7:24 PM

Nov 9 2017

dsanders added inline comments to D39823: GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES.
Nov 9 2017, 4:19 PM

Nov 8 2017

dsanders updated the diff for D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.

Fix covered() -> setCovered() change that was somehow missed, and the other nits.

Nov 8 2017, 1:23 PM
dsanders added a comment to D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.

Awesome, I could use something like this. LGTM with a few nits.

Is the long-term intention to try and drive this coverage to 100% via in-tree tests, or rather via the test-suite? I'm asking because I was actually considering removing some of the arm-instruction-selector.mir tests which cover the same kind of pattern - e.g. ADD, SUB, AND, OR etc are all derived from an AsI1_bin_irs, so it should be enough to test one of them. We already have tests for the TableGen emitter, so each backend should only have acceptance tests, to make sure TableGen does the right thing for each kind of pattern that it's interested in. Having one test for each rule would just explode the number of tests to the point where they can only be managed automatically, which would really reduce my confidence in them (mostly because TableGen is quirky and I would expect whatever edge cases are handled incorrectly in the emitter to also be handled incorrectly in whatever automatic test generator we'd derive with TableGen).

Nov 8 2017, 1:21 PM

Nov 7 2017

dsanders updated the diff for D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.

CodeGenCoverage::covered() -> setCovered()
Use SmartMutex and SmartScopedLock
Add missing docstring

Nov 7 2017, 11:27 AM
dsanders added inline comments to D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.
Nov 7 2017, 11:17 AM
dsanders created D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.
Nov 7 2017, 10:21 AM
dsanders added a dependent revision for D39742: Add backend name to Target to enable runtime info to be fed back into TableGen: D39747: [globalisel][tablegen] Generate rule coverage and use it to identify untested rules.
Nov 7 2017, 10:21 AM
dsanders created D39742: Add backend name to Target to enable runtime info to be fed back into TableGen.
Nov 7 2017, 10:00 AM

Nov 2 2017

dsanders added a comment to D39554: [globalisel][tablegen] Skip src child predicates.

LGTM. This must have been missed because they're genuinely operands. A lot of the predicates (particularly those on imm and fpimm) are on operators even though they look like operands.

Nov 2 2017, 11:04 AM

Nov 1 2017

dsanders committed rL317132: [globalisel][regbank] Warn about MIR ambiguities when register bank/class names….
[globalisel][regbank] Warn about MIR ambiguities when register bank/class names…
Nov 1 2017, 3:13 PM
dsanders committed rL317117: [globalisel][tablegen] Add support for multi-insn emission.
[globalisel][tablegen] Add support for multi-insn emission
Nov 1 2017, 12:58 PM

Oct 31 2017

dsanders committed rL317057: [globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC.
[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC
Oct 31 2017, 5:30 PM
dsanders committed rL317049: Re-commit: [globalisel][tablegen] Keep track of the insertion point while….
Re-commit: [globalisel][tablegen] Keep track of the insertion point while…
Oct 31 2017, 4:04 PM
dsanders committed rL317042: Revert r317040: [globalisel][tablegen] Keep track of the insertion point while….
Revert r317040: [globalisel][tablegen] Keep track of the insertion point while…
Oct 31 2017, 2:55 PM
dsanders committed rL317040: Re-commit: [globalisel][tablegen] Keep track of the insertion point while….
Re-commit: [globalisel][tablegen] Keep track of the insertion point while…
Oct 31 2017, 2:35 PM
dsanders committed rL317033: Revert r317029: [globalisel][tablegen] Keep track of the insertion point while….
Revert r317029: [globalisel][tablegen] Keep track of the insertion point while…
Oct 31 2017, 1:30 PM
dsanders committed rL317029: [globalisel][tablegen] Keep track of the insertion point while adding….
[globalisel][tablegen] Keep track of the insertion point while adding…
Oct 31 2017, 12:54 PM
dsanders committed rL317025: [globalisel][tablegen] Factor out implicit def/use renderers from….
[globalisel][tablegen] Factor out implicit def/use renderers from…
Oct 31 2017, 12:10 PM
dsanders committed rL317022: [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to….
[globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to…
Oct 31 2017, 11:50 AM
dsanders committed rL317017: [globalisel][tablegen] Allow any comment in DebugCommentAction. NFC.
[globalisel][tablegen] Allow any comment in DebugCommentAction. NFC
Oct 31 2017, 11:07 AM
dsanders added a comment to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.

For this, I was thinking there would be two kinds of partitioner. Those that deal with structure (number of operands, opcodes?*, nested instructions, etc.) and those that deal with predicates.

I would rather avoid the partitioners to be kind of "semantic-aware". If at all possible I would rather stick to simple concept like put "actions" that are identical together. On a different topic, the same apply for the matcher. Right now, we do the distinction between capturing, matching and so on, but all in all, this is just actions.

What I am saying is the design is more complicated than I would have thought and I wonder if on the long run it won't get in the way of modifying it... Unless it is well documented, in particular the intent :).

Oct 31 2017, 9:35 AM

Oct 24 2017

dsanders added a comment to D39034: [WIP][GlobalISel][TableGen] Optimize MatchTable for faster instruction selection.

There are a lot of changes in this patch so I haven't gone through the detail but this seems to be heading in the general direction I had in mind for when we got to optimizing the rules.

Oct 24 2017, 12:34 PM
dsanders committed rL316480: [globalisel][tablegen] Fix future undefined behaviour in r316463..
[globalisel][tablegen] Fix future undefined behaviour in r316463.
Oct 24 2017, 11:12 AM
dsanders committed rL316463: [globalisel][tablegen] Multi-insn emission requires that BuildMIAction support….
[globalisel][tablegen] Multi-insn emission requires that BuildMIAction support…
Oct 24 2017, 10:09 AM
dsanders abandoned D32744: [globalisel] Improve legalizer DEBUG_ONLY output..

Tracing the legalizer is still something we need to improve on but this patch isn't suitable given that we aren't restricting the insertion point.

Oct 24 2017, 9:47 AM

Oct 23 2017

dsanders committed rL316407: [globalisel][tablegen] Remove unused InstructionMatcher's. NFC.
[globalisel][tablegen] Remove unused InstructionMatcher's. NFC
Oct 23 2017, 6:49 PM
dsanders updated the diff for D39150: [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero..

Reduce patch to just the bit about applying this to GPR32/GPR64/GPR32all/
GPR64all. I found a way to constrain the original to just the relevant stores.

Oct 23 2017, 12:24 PM
dsanders committed rL316360: [globalisel][tablegen] Import stores and allow GISel to automatically….
[globalisel][tablegen] Import stores and allow GISel to automatically…
Oct 23 2017, 11:22 AM
dsanders committed rL316350: [globalisel] Add very brief docs summarizing the ISel part of the LLVMDev….
[globalisel] Add very brief docs summarizing the ISel part of the LLVMDev…
Oct 23 2017, 10:19 AM

Oct 20 2017

dsanders added a comment to D39150: [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero..

There's two patches in one here and I'm going to try and extract the stores portion of the patch and commit that separately if I can find a reasonable way to do so without causing regressions. The main purpose of this review is to determine whether we agree it's safe to allow the new GIZeroRegister on GPR32/GPR64/GPR32all/GPR64all. I think it's probably ok, but I don't feel I have sufficient knowledge of AArch64 to make such a sweeping change without someone more familiar with it giving it the go ahead.

Oct 20 2017, 4:51 PM
dsanders created D39150: [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero..
Oct 20 2017, 4:46 PM
dsanders committed rL316237: [globalisel][tablegen] Fix small spelling nits. NFC.
[globalisel][tablegen] Fix small spelling nits. NFC
Oct 20 2017, 1:55 PM

Oct 17 2017

dsanders committed rL316047: [aarch64][globalisel] Register banks and classes should have distinct names..
[aarch64][globalisel] Register banks and classes should have distinct names.
Oct 17 2017, 5:13 PM

Oct 16 2017

dsanders committed rL315972: [globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and….
[globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and…
Oct 16 2017, 10:24 PM

Oct 15 2017

dsanders committed rL315890: [aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by….
[aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by…
Oct 15 2017, 10:39 PM