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shiva0217 (Shiva Chen)
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Dec 25 2016, 5:14 PM (120 w, 4 d)

Recent Activity

Wed, Apr 10

shiva0217 committed rG7cc03bd06487: [RISCV] Put data smaller than eight bytes to small data section (authored by shiva0217).
[RISCV] Put data smaller than eight bytes to small data section
Wed, Apr 10, 9:58 PM
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Update patch to address Alex's comments.
Hi Alex, thanks for the review.

Wed, Apr 10, 6:51 PM · Restricted Project

Sun, Mar 31

shiva0217 accepted D59686: [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation).

Thanks for the update, LGTM.

Sun, Mar 31, 7:19 PM · Restricted Project

Fri, Mar 29

shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Update patch to address the comments from Eli and Ana.

Fri, Mar 29, 2:39 AM · Restricted Project
shiva0217 added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Fri, Mar 29, 2:34 AM · Restricted Project

Thu, Mar 28

shiva0217 added inline comments to D57497: [RISCV] Passing small data limitation value to RISCV backend.
Thu, Mar 28, 6:39 AM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Add warning message for -msmall-data-limit with -fpic or RV64 with -mcmodel=large

Thu, Mar 28, 5:53 AM · Restricted Project

Fri, Mar 22

shiva0217 added a comment to D59686: [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation).

Could you add a case in option-relax.s after .option norelax to indicate the relocation type for local symbol will leave once the relaxation has been enabled?

Fri, Mar 22, 7:34 AM · Restricted Project

Wed, Mar 20

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update patch to address Ana's comments.

  1. Ignoring -G when -msmall-data-limit= in the command line and show the warning message
  2. Removing LTO plugin invoking which should introduce in another patch
Wed, Mar 20, 11:49 PM · Restricted Project
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Remove riscv-ssection-threshold flag because front end will pass the threshold by module flag.

Wed, Mar 20, 11:42 PM · Restricted Project
shiva0217 added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Wed, Mar 20, 11:32 PM · Restricted Project

Mar 14 2019

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Passing small data limitation by module flag.

Mar 14 2019, 4:09 AM · Restricted Project
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Add getModuleMetadata() to read SmallDataLimit Module flag.

Mar 14 2019, 4:09 AM · Restricted Project

Feb 19 2019

shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Did you mean declare as a target feature in RISCV.td or I misunderstanding something?

That's sort of the right idea, but I don't think it works in this context because we aren't trying to change the generated code for a function; we actually need to stick the global into a specific section. Maybe worth sending an email to llvmdev to discuss the right way to represent this in IR?

Hi Eli,
I have sent the email to llvmdev http://lists.llvm.org/pipermail/llvm-dev/2019-February/130222.html. It seems that there're not much consensus on how to represent in IR. I incline to implement passing through -plugin-opt= as the first version. We could create an incremental patch when we have more consensus on IR approach. What do you think?

Feb 19 2019, 6:41 PM · Restricted Project

Feb 17 2019

shiva0217 committed rGe3aaeabb6da6: [RISCV] Default enable RISCV linker relaxation (authored by shiva0217).
[RISCV] Default enable RISCV linker relaxation
Feb 17 2019, 8:06 AM
shiva0217 updated the diff for D47127: [RISCV] Default enable RISCV linker relaxation.

Update patch to address Alex's comment.

Feb 17 2019, 7:44 AM · Restricted Project

Feb 11 2019

shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

If this is a target flag in GCC, shouldn't we make it a LLVM Target feature and pass it as -mattr, just like done for mrelax?

Feb 11 2019, 6:21 PM · Restricted Project

Feb 5 2019

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.
  1. Remove passing path for LTO because Eli raised the concern that whether it would appropriate to assign the same limitation for all files when LTO enabled.
  2. Add -msmall-data-limitation= as James pointed out it's the main setting flag for RISCV GCC
Feb 5 2019, 11:33 PM · Restricted Project

Feb 3 2019

shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

I don't see -plugin-opt=-riscv-ssection-threshold=.. being passed.
tools::gnutools::Linker::ConstructJob is being invoked with target riscv32-unknown-linux-gnu
It has to work for riscv32-unknown-linux-gnu and riscv32-unknown-elf

Feb 3 2019, 6:52 PM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Support passing small data limitation for target riscv32-unknown-linux-gnu with LTO enabled.

Feb 3 2019, 6:44 PM · Restricted Project
shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Hi Shiva, I think you need to check for and pass along the -G option to the linker (gnutools::Linker and RISCV::Linker) and will be available for LTO. Check Hexagon, it passes the threshold value to the assembler (via -gpsize) and linker (via -G).

Feb 3 2019, 1:59 AM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.
  1. Setting small data limitation to zero for PIC and RV64 with large code model.
  2. Support passing small data limitation with LTO enabled.
Feb 3 2019, 1:39 AM · Restricted Project
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Remove guard condition for large code model which will implement in clang.

Feb 3 2019, 1:31 AM · Restricted Project

Feb 2 2019

shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Add testing for large code model.

Feb 2 2019, 5:45 PM · Restricted Project

Feb 1 2019

shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Correct the default small data limitation to 8 bytes for RV32 and RV64.
Setting the limitation to 0 for PIC.
The test case didn' add the testing line for PIC because we don't support pic yet, it will trigger "Unable to lowerGlobalAddress" error message.

Feb 1 2019, 9:40 PM · Restricted Project
shiva0217 added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Feb 1 2019, 5:37 PM · Restricted Project
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Fix the issue for -G0 as Ana pointed out.

Feb 1 2019, 5:33 PM · Restricted Project

Jan 31 2019

Herald added a project to D57497: [RISCV] Passing small data limitation value to RISCV backend: Restricted Project.

As this mllvm option only affects the creation of ELF objects, do we also need to add a similar option for the LTO case, as the -G value would have no effect otherwise?

Jan 31 2019, 7:28 PM · Restricted Project

Jan 30 2019

shiva0217 added a child revision for D57493: [RISCV] Put data smaller than eight bytes to small data section: D57497: [RISCV] Passing small data limitation value to RISCV backend.
Jan 30 2019, 9:51 PM · Restricted Project
shiva0217 added a parent revision for D57497: [RISCV] Passing small data limitation value to RISCV backend: D57493: [RISCV] Put data smaller than eight bytes to small data section.
Jan 30 2019, 9:51 PM · Restricted Project
shiva0217 created D57497: [RISCV] Passing small data limitation value to RISCV backend.
Jan 30 2019, 9:48 PM · Restricted Project
shiva0217 created D57493: [RISCV] Put data smaller than eight bytes to small data section.
Jan 30 2019, 6:30 PM · Restricted Project

Jan 18 2019

shiva0217 closed D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Hi Eli, Thanks for the review.

Jan 18 2019, 12:55 AM

Jan 17 2019

shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Hi @asb, I got your point, we could guard the target hook with AF.hasEmitNops(), so the behavior of .align 4, 1 will be the same as gnu assembler. What do you think?

Jan 17 2019, 10:48 PM

Jan 11 2019

shiva0217 added a comment to D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.
In D47755#1352910, @asb wrote:

Hi Alex, I have added a constant pool test case at the end of align.s to verify the padding behavior for constant pool. Once D45961 landing and changing the behavior, we should be able to aware. It seems that GCC will insert Nops for padding constant pool. Could you illustrate more about "use .align with a value to fill with"? I could test on GCC.

I meant that .align/.p2align in GNU as accept a padding value https://sourceware.org/binutils/docs/as/Align.html#Align. It seems that for RISC-V, it accepts and uses this padding value even when relaxation is enabled, but won't emit the R_RISCV_RELAX in that case (which I suppose makes sense, as the linker wouldn't respect the padding value). I'm not saying we should definitely replicate GNU as here - obviously performing alignment without generating R_RISCV_RELAX is quite liable to break things unexpectedly. But it might not be a bad starting point if it's easy to support. Either way, we should have tests that demonsrate how we handle those cases.

Jan 11 2019, 8:16 PM
shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.
  1. Add test case for alignment directive with a specific padding value
  2. Rename the new target hooks to NopBytesToInsertForAlignDirectiveInCodeSection and insertFixupForAlignDirectiveInCodeSection
Jan 11 2019, 7:03 PM

Jan 7 2019

shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Update patch to reflect James comments.

Jan 7 2019, 11:06 PM
shiva0217 added inline comments to D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.
Jan 7 2019, 11:05 PM

Jan 6 2019

shiva0217 added a comment to D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Ping?

Jan 6 2019, 9:21 PM

Jan 3 2019

shiva0217 accepted D52298: [RISCV][MC] Add support for evaluating constant symbols as immediates.
Jan 3 2019, 9:53 PM
shiva0217 added a comment to D52298: [RISCV][MC] Add support for evaluating constant symbols as immediates.

Hi Alex,
Thanks for the updates, looks good to me.

Jan 3 2019, 9:50 PM

Dec 18 2018

shiva0217 added a comment to D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Hi Alex, I have added a constant pool test case at the end of align.s to verify the padding behavior for constant pool. Once D45961 landing and changing the behavior, we should be able to aware. It seems that GCC will insert Nops for padding constant pool. Could you illustrate more about "use .align with a value to fill with"? I could test on GCC.

Dec 18 2018, 12:13 AM

Dec 17 2018

shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Rebase and rename insertNopBytesForAlignDirectiveInTextSection to NopBytesToInsertForAlignDirectiveInTextSection

Dec 17 2018, 11:51 PM

Dec 7 2018

shiva0217 added a comment to D42374: [RFC] Add IsFixed field to ISD::ArgFlagsTy.

Hi Alex,
I think it's great that the target description file could determine the argument is fixed or not. In this way, the targets have different ABI behavior for non-fixed arguments could describe by TD files without extra custom c++ codes. It seems that Mips and RISCV already have variable argument test cases to cover the changed. Do other targets involve the changed have variable argument test case? If it's not, could you add the test cases to cover the changed?

Dec 7 2018, 12:52 AM

Dec 4 2018

shiva0217 abandoned D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.
Dec 4 2018, 12:59 AM
shiva0217 added a comment to D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.

Hi @rogfer01, got it. Thanks to pointing out the difference. I'll drop the patch.

Dec 4 2018, 12:58 AM

Dec 3 2018

shiva0217 created D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.
Dec 3 2018, 11:30 PM

Nov 22 2018

shiva0217 added a comment to D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Hi @TimNN,
Thanks for the test case, that really help me a lot.

Nov 22 2018, 12:04 AM

Nov 21 2018

shiva0217 updated the diff for D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Add the test case provided by Tim.

Nov 21 2018, 11:56 PM

Nov 20 2018

shiva0217 added a comment to D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Ping?

Nov 20 2018, 11:27 PM

Nov 3 2018

shiva0217 added a comment to D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Hi @samparker,
Thanks for your time to take a look at the code.

Nov 3 2018, 2:31 AM

Nov 2 2018

shiva0217 added reviewers for D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent: eli.friedman, samparker.
Nov 2 2018, 1:35 AM
shiva0217 updated subscribers of D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

I look into the log history of ScheduleDAGRRList.cpp, it seems that @eli.friedman and @samparker have been fixed some issue relative to CallResource.
I'll add them as the reviewers. Hopefully, they could have time to review our patch and won't bother them too much.

Nov 2 2018, 1:35 AM

Oct 22 2018

shiva0217 retitled D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent from [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN to [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.
Oct 22 2018, 11:06 PM
shiva0217 added a comment to D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

What about MachineVerifier::verifyStackFrame()? That currently rejects any function with nested callframe setups. You will probably see your testcases fail when running with -verify-machineinstrs.

Oct 22 2018, 11:05 PM
shiva0217 updated the diff for D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.

Update patch to address Tim's comments.

Oct 22 2018, 8:16 PM
shiva0217 added inline comments to D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.
Oct 22 2018, 8:16 PM
shiva0217 retitled D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent from [ScheduleDAGRRList] Do not preschedule ADJCALLSTACKDOWN to [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN.
Oct 22 2018, 8:14 PM
shiva0217 added a comment to D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.

Probably need to add

def : Pat<(sext_inreg (sdiv GPR:$rs1, GPR:$rs2), i32),
          (DIVW GPR:$rs1, GPR:$rs2)>;
def : Pat<(sext_inreg (udiv GPR:$rs1, GPR:$rs2), i32),
          (DIVUW GPR:$rs1, GPR:$rs2)>;

Because DAG combine may create these patterns.

Oct 22 2018, 2:04 AM

Oct 21 2018

shiva0217 created D53485: [ScheduleDAGRRList] Do not preschedule the node has ADJCALLSTACKDOWN parent.
Oct 21 2018, 10:56 PM

Sep 26 2018

shiva0217 added a comment to D52299: [RISCV][MC] Accept %lo and %pcrel_lo on operands to li.

LGTM.

Sep 26 2018, 1:12 AM
shiva0217 added a comment to D52298: [RISCV][MC] Add support for evaluating constant symbols as immediates.

Hi Alex, another solution could be calling parseExpression for AsmToken::Identifier in RISCVAsmParser::parseImmediate instead of calling parseIdentifier.

case AsmToken::String:
case AsmToken::Identifier: {
  if (getParser().parseExpression(Res))
    return MatchOperand_ParseFail;
  break;
}

parseExpression will call parsePrimaryExpr which contain the logical to call parseIdentifier and also try to get the symbol value when the symbol is variable.
What do you think?

Sep 26 2018, 12:53 AM

Aug 20 2018

shiva0217 added inline comments to D46423: [RISCV] Support .option relax and .option norelax.
Aug 20 2018, 7:04 PM
shiva0217 added a comment to D46423: [RISCV] Support .option relax and .option norelax.

Apology. I thought the assembler will parse all the instructions and then do the encoding which is incorrect. It will parse and encode one instruction at a time. So we don't need using MCinst's Flag to record the instruction state and NoRelaxLocStart shouldn't need.
We could define FeatureNoRelaxREL feature to indicate the suppression of R_RISCV_RELAX relocation type instead of clear FeatureRelax bit.
Because once the .option relax occur in the file, shouldForceRelocation, and requiresDiffExpressionRelocations should return true to make sure the local branches and label differences will leave the relocation types.
With the relocation types, the linker relaxation could do the right adjustment when the code size changed.
I think it's quite similar to the approach @simoncook mention in https://reviews.llvm.org/D45181#1086541.
Is it a feasible way to implement? or we may still break something in certain cases?

Aug 20 2018, 8:09 AM
shiva0217 added a comment to D46423: [RISCV] Support .option relax and .option norelax.

We may need to find a way to indicate the .option norelax effective scope to handle the following case.

.option norelax
 call f1
.option relax
 call f2
.option norelax
 call f3

In this case, only call f2 should insert R_RISCV_RELAX relocation type.

Aug 20 2018, 2:23 AM
shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Rebase and add constant pool test case.

Aug 20 2018, 12:29 AM

Jun 25 2018

shiva0217 removed a parent revision for D44886: [RISCV] Support linker relax function call from auipc and jalr to jal: D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
Jun 25 2018, 1:27 AM
shiva0217 removed a child revision for D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled: D44886: [RISCV] Support linker relax function call from auipc and jalr to jal.
Jun 25 2018, 1:27 AM
shiva0217 removed parent revisions for D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled: D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table, D46674: [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation.
Jun 25 2018, 1:27 AM
shiva0217 removed a child revision for D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table: D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
Jun 25 2018, 1:27 AM
shiva0217 removed a child revision for D46674: [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation: D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
Jun 25 2018, 1:27 AM
shiva0217 added a parent revision for D47127: [RISCV] Default enable RISCV linker relaxation: D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.
Jun 25 2018, 1:26 AM · Restricted Project
shiva0217 added a child revision for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled: D47127: [RISCV] Default enable RISCV linker relaxation.
Jun 25 2018, 1:26 AM
shiva0217 abandoned D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.

There is a new revision D47755 to replace this one.

Jun 25 2018, 1:24 AM

Jun 14 2018

shiva0217 updated the diff for D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.

Update patch to address Alex's comments.

Jun 14 2018, 7:17 PM

Jun 4 2018

shiva0217 added a comment to D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.

Hi Alex. I find a way to emit fixup_riscv_align without introducing PseudoNOPs as you suggest.
The revision D47755 introducing the new target hooks to calculate the nops we need to insert and insert fixup_riscv_align for alignment directive.
Could you help me to check the new approach is ok or not?
Thanks.

Jun 4 2018, 7:31 PM
shiva0217 created D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment when linker relaxation enabled.
Jun 4 2018, 7:15 PM

May 29 2018

shiva0217 retitled D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table from [RISCV] Add missing fixup_riscv_call in MCFixupKindInfo table to [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.
May 29 2018, 6:09 PM

May 28 2018

shiva0217 updated the diff for D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.

Update test cases to address Alex's comments.

May 28 2018, 6:48 PM

May 24 2018

shiva0217 updated the diff for D47127: [RISCV] Default enable RISCV linker relaxation.
May 24 2018, 11:48 PM · Restricted Project
shiva0217 added a comment to D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
In D44888#1111995, @asb wrote:
In D44888#1109361, @asb wrote:

This is looking good to me, just needs an update to address this request for a test in riscv-features.c that demonstrates the default +relax/-relax setting.

Hi Alex. I added the testing line on D47127 which is the patch we turn on relaxation as default. Do you think it's ok?

I saw that. I don't mean to be too nit-picky, but there's an advantage in also testing the default in this patch - it tests the current behaviour and makes it obvious in the follow-up patch that the behaviour actually changed.

May 24 2018, 11:47 PM
shiva0217 updated the diff for D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
May 24 2018, 11:46 PM
shiva0217 added a comment to D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
In D44888#1109361, @asb wrote:

This is looking good to me, just needs an update to address this request for a test in riscv-features.c that demonstrates the default +relax/-relax setting.

May 24 2018, 6:33 PM
shiva0217 updated the diff for D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.

Hi Alex.It seems that fixup fixup_riscv_call by assembler is workable. Thanks for your comments.

May 24 2018, 6:03 AM
shiva0217 added a comment to D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
In D46630#1110712, @asb wrote:

I think that customising the handling of MCAlignFragment is going to be the more correct (with regards to the LLVM MC design and layering) and maintainable way.

I haven't fully stepped through the ordering of function calls when producing an object. Is your concern that the current call to writeNopData from writeFragment comes too late to create the relocation?

May 24 2018, 2:12 AM
shiva0217 added a comment to D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
In D46630#1109492, @asb wrote:

Hi Shiva. As far as testing goes, I think we really need to see testing of corner cases around enabling/disabling rvc support in the same file.

Could you comment about the decision to introduce the PseudoNOP instruction? The obvious alternative approach would be to try to customise the code that handles MCAlignFragments, adding new hooks if necessary. Have you looked in any detail at doing it that way?

May 24 2018, 12:00 AM

May 21 2018

shiva0217 added a comment to D46965: [RISCV] Fix builtin fixup sizes (alternate approach).

LGTM.

May 21 2018, 6:20 AM
shiva0217 updated the diff for D44886: [RISCV] Support linker relax function call from auipc and jalr to jal.

Update the patch to address Alex's comments.

May 21 2018, 5:06 AM
shiva0217 updated the diff for D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.

Rename thd target hook to disableAlignmentPaddingInTextSection.

May 21 2018, 5:04 AM
shiva0217 added a parent revision for D47127: [RISCV] Default enable RISCV linker relaxation: D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
May 21 2018, 1:05 AM · Restricted Project
shiva0217 added a child revision for D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation: D47127: [RISCV] Default enable RISCV linker relaxation.
May 21 2018, 1:05 AM
shiva0217 created D47127: [RISCV] Default enable RISCV linker relaxation.
May 21 2018, 1:05 AM · Restricted Project
shiva0217 updated the diff for D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
May 21 2018, 1:03 AM
shiva0217 added a parent revision for D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled: D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.
May 21 2018, 12:35 AM
shiva0217 added a child revision for D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table: D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.
May 21 2018, 12:35 AM
shiva0217 updated the diff for D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.

Rebase the patch to trunk@332828

May 21 2018, 12:34 AM
shiva0217 added inline comments to D44886: [RISCV] Support linker relax function call from auipc and jalr to jal.
May 21 2018, 12:32 AM
shiva0217 created D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.
May 21 2018, 12:23 AM

May 20 2018

shiva0217 added inline comments to D44886: [RISCV] Support linker relax function call from auipc and jalr to jal.
May 20 2018, 7:51 PM

May 14 2018

shiva0217 added inline comments to D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
May 14 2018, 7:00 PM