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shiva0217 (Shiva Chen)
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User Since
Dec 25 2016, 5:14 PM (160 w, 1 d)

Recent Activity

Mon, Jan 13

shiva0217 added inline comments to D68685: [RISCV] Scheduler description for Rocket Core.
Mon, Jan 13, 10:21 PM · Restricted Project

Tue, Jan 7

shiva0217 added a child revision for D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls: D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.
Tue, Jan 7, 9:29 PM · debug-info, Restricted Project
shiva0217 accepted D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.

LGTM, Labels required to describe call site scope will be generated for the calls after FrameSetup instructions. When the SaveLibcall mark as FrameSetup, the Label will not be generated, so constructing call site entry for SaveLibcall will trigger an assertion. Given that SaveLibcall should be part of the prologue, so I think generating call site begin after FrameSetup instructions should be reasonable. But I hope there could be a second look.

Tue, Jan 7, 9:29 PM · debug-info, Restricted Project
shiva0217 added a parent revision for D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls: D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.
Tue, Jan 7, 9:29 PM · Restricted Project, Restricted Project
shiva0217 added a reviewer for D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls: dblaikie.
Tue, Jan 7, 9:29 PM · debug-info, Restricted Project

Dec 12 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Dec 12 2019, 5:19 AM · Restricted Project, Restricted Project

Dec 9 2019

shiva0217 added inline comments to D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.
Dec 9 2019, 8:57 PM · Restricted Project, Restricted Project

Nov 26 2019

shiva0217 added a comment to D70670: [RISCV] Implement canRealignStack.

With the patch, double load/store instructions may unaligned-access with -mabi=ilp32e -mattr=+d flags. Could the load/store support unaligned-access?

Nov 26 2019, 1:38 AM · Restricted Project

Nov 20 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 20 2019, 6:25 PM · Restricted Project, Restricted Project
shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 20 2019, 12:21 AM · Restricted Project, Restricted Project

Nov 19 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 19 2019, 12:10 AM · Restricted Project, Restricted Project

Nov 15 2019

shiva0217 committed rGcf6cf0cd147a: [RISCV] Handle variable sized objects with the stack need to be realigned (authored by shiva0217).
[RISCV] Handle variable sized objects with the stack need to be realigned
Nov 15 2019, 8:45 PM
shiva0217 closed D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Nov 15 2019, 8:45 PM · Restricted Project
shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Rebase to the master

Nov 15 2019, 12:38 AM · Restricted Project

Nov 14 2019

shiva0217 added inline comments to D69723: [RISCV] Fix wrong CFI directives.
Nov 14 2019, 7:40 AM · Restricted Project

Nov 11 2019

shiva0217 added inline comments to D69723: [RISCV] Fix wrong CFI directives.
Nov 11 2019, 9:32 PM · Restricted Project

Nov 7 2019

shiva0217 added a comment to D69723: [RISCV] Fix wrong CFI directives.

Hi @luismarques,
I tried to generate .cfi_remember_state and .cfi_restore_state in emitEpilogue. It could pass the test case.
But there is an issue that .cfi_restore_state will become incorrect if the shrink wrapping hoists the epilogue.
So I think to remove CFI directives from the epilogue as other targets do might be a reasonable step.

Nov 7 2019, 6:36 AM · Restricted Project

Oct 31 2019

shiva0217 accepted D69385: [RISCV] Fix CFA when doing split sp adjustment with fp.

Hi @luismarques, thanks for the patch, LGTM.

Oct 31 2019, 4:49 AM · Restricted Project

Oct 28 2019

shiva0217 committed rGc1498e37abe6: [RISCV] Remove RA from reserved register to use as callee saved register (authored by shiva0217).
[RISCV] Remove RA from reserved register to use as callee saved register
Oct 28 2019, 8:35 PM
shiva0217 closed D67698: [RISCV] Remove RA from reserved register to use as callee saved register.
Oct 28 2019, 8:34 PM · Restricted Project
shiva0217 added inline comments to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 28 2019, 8:22 PM · Restricted Project

Oct 27 2019

shiva0217 requested changes to D69385: [RISCV] Fix CFA when doing split sp adjustment with fp.

Hi @luismarques, thanks for fixing this.

Oct 27 2019, 10:30 PM · Restricted Project
shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Add CFI checking line in the test case

Oct 27 2019, 6:54 PM · Restricted Project
shiva0217 added inline comments to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 27 2019, 6:52 PM · Restricted Project

Oct 18 2019

shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Update patch to address the comments.

Oct 18 2019, 12:22 AM · Restricted Project

Oct 17 2019

shiva0217 added a comment to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Shiva, I have tried a few workloads like EEMBC, SPEC2000/2006, perennial c++, plumhall.
They don't seem to use variable length arrays nor allocas to test this patch.
Which test suite are you using?

Oct 17 2019, 10:56 PM · Restricted Project

Oct 15 2019

shiva0217 created D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 15 2019, 3:11 AM · Restricted Project

Oct 14 2019

shiva0217 updated the diff for D67698: [RISCV] Remove RA from reserved register to use as callee saved register.

Rebase the test case.

Oct 14 2019, 8:04 PM · Restricted Project
shiva0217 committed rG078bec6c48dd: [RISCV] Support fast calling convention (authored by shiva0217).
[RISCV] Support fast calling convention
Oct 14 2019, 7:09 PM
shiva0217 closed D68559: [RISCV] Support fast calling convention.
Oct 14 2019, 7:09 PM · Restricted Project

Oct 12 2019

shiva0217 added inline comments to D62190: [RISCV] Allow shrink wrapping for RISC-V.
Oct 12 2019, 11:34 PM · Restricted Project

Oct 8 2019

shiva0217 added a comment to D68559: [RISCV] Support fast calling convention.

I like this change.

fastcc is LLVM-internal only, right? Checking that we don't have to care about splitting operands that don't fit into registers, or any other psABI details, right?

Yes, to my understanding, fastcc doesn't need to care about psABI details.

Oct 8 2019, 11:26 AM · Restricted Project
shiva0217 updated the diff for D68559: [RISCV] Support fast calling convention.

Update patch to address the feedbacks

Oct 8 2019, 11:25 AM · Restricted Project
shiva0217 updated the diff for D68559: [RISCV] Support fast calling convention.

Update patch to address the comment

Oct 8 2019, 12:20 AM · Restricted Project

Oct 6 2019

shiva0217 created D68559: [RISCV] Support fast calling convention.
Oct 6 2019, 7:16 PM · Restricted Project

Oct 3 2019

shiva0217 committed rGff55e2e0476b: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill… (authored by shiva0217).
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill…
Oct 3 2019, 7:00 PM
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Fix comment in the patch.

Oct 3 2019, 6:50 PM · Restricted Project
shiva0217 added inline comments to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Oct 3 2019, 6:46 PM · Restricted Project

Sep 26 2019

shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Add splitting SP adjustment boundary test case as @luismarques suggest.

Sep 26 2019, 9:59 PM · Restricted Project
shiva0217 added a comment to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

@shiva0217 Thanks for updating the patch and addressing the previous concerns. This is looking quite good. I have just a couple more concerns before approving this:

  • The boundary condition for doing the two-stage sp adjustment probably needs adjustment. For instance, try this:

    ` int main() { char xx[2048-16]; foo(xx); } -- addi sp, sp, -2032 sd ra, 2024(sp) addi sp, sp, -16 ... `

    I think that one would still fit a single-stage sp update. Related to that, where you have the code if (!isInt<12>(StackSize) && (CSI.size() > 0)), be sure that the isInt<12> check properly accounts for the StackSize, CSI size, StackAlign etc. Which brings me to the second point...
  • Please include tests showing that the boundary condition is correctly computed. For instance, one test where the stack size is just enough not to have to split the sp adjustment and another where the adjustment is needed.

    Thanks!
Sep 26 2019, 7:01 AM · Restricted Project
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

Sep 26 2019, 1:14 AM · Restricted Project

Sep 25 2019

shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

  1. Call getFirstSPAdjustAmount() once in per prologue/epilogue generation as @luismarques suggest
  2. Generate CFI directives in large-stack.ll test case to check the CFI generation
Sep 25 2019, 7:24 PM · Restricted Project
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch to address the comments.

Sep 25 2019, 7:49 AM · Restricted Project
shiva0217 added inline comments to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Sep 25 2019, 6:54 AM · Restricted Project
shiva0217 created D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Sep 25 2019, 2:27 AM · Restricted Project

Sep 19 2019

shiva0217 added a comment to D67698: [RISCV] Remove RA from reserved register to use as callee saved register.

We discussed this in the RISC-V meeting on 19 Sep 2019.

  • Pros: GCC for RISC-V and LLVM for ARM and AArch64 seem to do the same. It can help in situations with particularly bad register pressure requirements.
  • Cons: It can make debugging a lot harder, though this seems not to be an issue in GDB for RISC-V.

    I think we don't want to have yet another configuration flag to control this.

    It would be good to see some performance comparison, but I realise you may not be able to release internal benchmarks, and we have no public benchmarking system for RISC-V.
Sep 19 2019, 10:13 PM · Restricted Project

Sep 18 2019

shiva0217 created D67698: [RISCV] Remove RA from reserved register to use as callee saved register.
Sep 18 2019, 2:03 AM · Restricted Project

Sep 12 2019

shiva0217 committed rGa49a16ddd0eb: [RISCV] Support stack offset exceed 32-bit for RV64 (authored by shiva0217).
[RISCV] Support stack offset exceed 32-bit for RV64
Sep 12 2019, 9:04 PM
shiva0217 committed rGea530ba3ed75: Revert "[RISCV] Support stack offset exceed 32-bit for RV64" (authored by shiva0217).
Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
Sep 12 2019, 9:04 PM
shiva0217 committed rGeaa230fe3c86: [RISCV] Support stack offset exceed 32-bit for RV64 (authored by shiva0217).
[RISCV] Support stack offset exceed 32-bit for RV64
Sep 12 2019, 7:51 PM
shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Choosing virtual register as temp register.

Sep 12 2019, 8:01 AM · Restricted Project

Sep 11 2019

shiva0217 added a comment to D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using t1 (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use a0-5 if it wishes, which can be compressed, unlike t1. Do you have a justification for explicitly choosing t1?

Sep 11 2019, 6:57 PM · Restricted Project
shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Update patch to address the comments.

Sep 11 2019, 7:14 AM · Restricted Project
shiva0217 added inline comments to D61884: [RISCV] Support stack offset exceed 32-bit for RV64.
Sep 11 2019, 7:11 AM · Restricted Project

Sep 10 2019

shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Using T1 as temp register for prologue/epilogue generation if there is no shrink wrapping optimization occur.

Sep 10 2019, 12:08 AM · Restricted Project

Aug 31 2019

shiva0217 committed rGadfdcb9c2652: [TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with… (authored by shiva0217).
[TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with…
Aug 31 2019, 9:54 PM

Aug 28 2019

shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Rebase to the trunk

Aug 28 2019, 7:00 PM · Restricted Project
shiva0217 committed rGb39876d8cddb: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall (authored by shiva0217).
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
Aug 28 2019, 4:42 PM

Aug 21 2019

shiva0217 committed rG72a41e7b0d04: [TargetLowering] Remove optional arguments passing to makeLibCall (authored by shiva0217).
[TargetLowering] Remove optional arguments passing to makeLibCall
Aug 21 2019, 10:02 PM

Aug 20 2019

shiva0217 added a comment to D66278: [RISCV] Enable tail call opt for variadic function.

Hi Jim,

Aug 20 2019, 8:01 PM · Restricted Project
shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Add comment for the new field in MakeLibCallOptions struct.

Aug 20 2019, 6:41 PM · Restricted Project

Aug 19 2019

shiva0217 added inline comments to D62190: [RISCV] Allow shrink wrapping for RISC-V.
Aug 19 2019, 11:25 PM · Restricted Project
shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Update patch to reflect the comments.

Aug 19 2019, 7:45 PM · Restricted Project
shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 19 2019, 7:35 PM · Restricted Project

Aug 8 2019

shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

I remove the IsCastFromFloat flag and store the SDNode before soften in MakeLibCallOptions struct. So that the shouldExtendTypeInLibCall could get the original type directly and get rid of the complicate IsCastFromFloat setting method. I try to illustrate most of the single soft-float functions in rv64i-single-softfloat.ll. Please kindly remind me if I still missing something, thanks.

Aug 8 2019, 11:49 PM · Restricted Project
shiva0217 updated the diff for D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.

Only define the bits will be used for makelibCall in MakeLibCallOptions struct.

Aug 8 2019, 11:33 PM · Restricted Project
shiva0217 added inline comments to D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.
Aug 8 2019, 11:25 PM · Restricted Project

Aug 7 2019

shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Rebase the patch base on D65795 and update test cases.
Thanks for Eli's comments and Alex's excellent floating test cases that we could easily observe the difference.

Aug 7 2019, 1:17 AM · Restricted Project
shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 7 2019, 1:06 AM · Restricted Project

Aug 6 2019

shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 6 2019, 2:31 AM · Restricted Project
shiva0217 added a parent revision for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall: D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.
Aug 6 2019, 2:18 AM · Restricted Project
shiva0217 added a child revision for D65795: [TargetLowering] Remove optional arguments passing to makeLibCall: D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 6 2019, 2:18 AM · Restricted Project
shiva0217 created D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.
Aug 6 2019, 2:18 AM · Restricted Project

Aug 5 2019

shiva0217 committed rGb12056bd3390: [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions (authored by shiva0217).
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
Aug 5 2019, 5:24 PM

Aug 1 2019

shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Update the patch to catch divsf3 case.

Aug 1 2019, 7:13 PM · Restricted Project
shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 1 2019, 7:11 PM · Restricted Project
shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Thanks for pointing me the right direction.
I added shouldExtendTypeInLibCall target hook to indicate the Libcall should do the extension or not.
The parameter IsCastFromFloat will be passed to TargetLowering::makeLibCall and shouldExtendTypeInLibCall. So shouldExtendTypeInLibCall can identify the Type is casting by floating and disable the extensions.
Without generating AssertZext for the Libcall return value, and operation for clearing upper bits will be preserved.

Aug 1 2019, 1:17 AM · Restricted Project

Jul 31 2019

shiva0217 added a comment to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

I thought the problem was in that in the complex add case, we needed to zero-extend the i32 into an i64, in order to zero the upper 32 bits. This patch seems to sign-extend the libcall instead. Is there a shouldZeroExtendTypeInLibCall callback?

Jul 31 2019, 1:13 AM · Restricted Project

Jul 30 2019

shiva0217 created D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Jul 30 2019, 10:45 PM · Restricted Project
shiva0217 updated the diff for D65434: [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions.

Updated the test cases changed by the patch.

Jul 30 2019, 6:40 PM · Restricted Project
shiva0217 created D65434: [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions.
Jul 30 2019, 1:46 AM · Restricted Project

Jun 18 2019

shiva0217 added inline comments to D62592: [RISCV] Add support for RVC HINT instructions.
Jun 18 2019, 11:46 PM · Restricted Project

Jun 4 2019

shiva0217 added inline comments to D62592: [RISCV] Add support for RVC HINT instructions.
Jun 4 2019, 10:49 PM · Restricted Project

May 28 2019

shiva0217 added a comment to D61773: [RISCV] Add CFI directives for RISCV prologue/epilog..

Hi Kai,
We could also generate .cfi_restore for epilogue by:

unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
    nullptr, MRI->getDwarfRegNum(Reg, 1)));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
    .addCFIIndex(CFIIndex);
May 28 2019, 1:20 AM · Restricted Project

May 14 2019

shiva0217 created D61884: [RISCV] Support stack offset exceed 32-bit for RV64.
May 14 2019, 1:50 AM · Restricted Project
shiva0217 added a comment to D61773: [RISCV] Add CFI directives for RISCV prologue/epilog..

Hi Kai,

May 14 2019, 1:46 AM · Restricted Project

May 9 2019

shiva0217 added a comment to D61665: [TailCall] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.
In D61665#1496085, @asb wrote:

Yes, I think leaving the current behaviour probably makes sense. I encountered that test failure too and mask that test on the basis that that those builtins aren't documented as being guaranteed to work https://gcc.gnu.org/onlinedocs/gcc/Return-Address.html (that page even notes that crashing is allowable behaviour).

May 9 2019, 12:14 AM · Restricted Project

May 8 2019

shiva0217 abandoned D61626: [RISCV] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.
May 8 2019, 6:56 PM · Restricted Project
shiva0217 abandoned D61665: [TailCall] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.

I have a few concerns here:

  1. Looping over every instruction in a function is expensive, and makes any pass which checks this for every call in a function take quadratic time overall.

It may too expansive, using function attribute as Hal's comment would be a better approach.

  1. You can't inspect the body of a function pointer, or a function in a different translation unit, so we can't make this work consistently.

Yes, we can't detect the function in a different translation unit or pointed by a function pointer.

  1. Even in the same translation unit, how do we "preserve" the behavior for values greater than 1?

Yes, disabling tail call can only preserve the stack in depth 1, it may have other optimizations change the behavior of the depth greater than one.


I'd prefer to just leave the current behavior if it isn't causing any practical problems. The user can always use -fno-optimize-sibling-calls if their codebase needs it for some reason.

If we do wish to make our "best effort" contain more effort, I think that we'd want to do this during function-attribute inference - there we can iterate over the call graph and add some inhibiting attributes. That having been said, if the only use case we have for this is matching some portion of GCC's heuristic for the purpose of making their test case pass, I'm not sure that this is worthwhile.

May 8 2019, 6:51 PM · Restricted Project
shiva0217 added a comment to D61665: [TailCall] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.
In D61665#1494592, @asb wrote:

The description of the llvm.frameaddress and llvm.returnaddress intrinsics seems to indicate that these are "best effort" and LLVM doesn't really guarantee a correct result for a depth > 1 https://llvm.org/docs/LangRef.html#llvm-returnaddress-intrinsic https://llvm.org/docs/LangRef.html#llvm-returnaddress-intrinsic

Is there a particular use case that is improved by improving the quality of frameaddress/returnaddress results?

May 8 2019, 5:16 AM · Restricted Project

May 7 2019

shiva0217 added a comment to D61626: [RISCV] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.

Is this really a target-independent problem?

May 7 2019, 8:12 PM · Restricted Project
shiva0217 created D61665: [TailCall] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.
May 7 2019, 8:03 PM · Restricted Project

May 6 2019

shiva0217 created D61626: [RISCV] Disable tail call if the callee function contain __builtin_frame_address or __builtin_return_address.
May 6 2019, 11:09 PM · Restricted Project

Apr 10 2019

shiva0217 committed rG7cc03bd06487: [RISCV] Put data smaller than eight bytes to small data section (authored by shiva0217).
[RISCV] Put data smaller than eight bytes to small data section
Apr 10 2019, 9:58 PM
shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Update patch to address Alex's comments.
Hi Alex, thanks for the review.

Apr 10 2019, 6:51 PM · Restricted Project

Mar 31 2019

shiva0217 accepted D59686: [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation).

Thanks for the update, LGTM.

Mar 31 2019, 7:19 PM · Restricted Project

Mar 29 2019

shiva0217 updated the diff for D57493: [RISCV] Put data smaller than eight bytes to small data section.

Update patch to address the comments from Eli and Ana.

Mar 29 2019, 2:39 AM · Restricted Project
shiva0217 added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Mar 29 2019, 2:34 AM · Restricted Project

Mar 28 2019

shiva0217 added inline comments to D57497: [RISCV] Passing small data limitation value to RISCV backend.
Mar 28 2019, 6:39 AM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Add warning message for -msmall-data-limit with -fpic or RV64 with -mcmodel=large

Mar 28 2019, 5:53 AM · Restricted Project