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shiva0217 (Shiva Chen)
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User Since
Dec 25 2016, 5:14 PM (170 w, 1 d)

Recent Activity

Today

shiva0217 added a comment to D77117: [RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp.

Hi @shiva0217 can you clarify as to why this is necessary?

Tue, Mar 31, 4:56 AM · Restricted Project
shiva0217 created D77117: [RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp.
Tue, Mar 31, 12:30 AM · Restricted Project

Thu, Mar 19

shiva0217 committed rGfc3752665f4b: [RISCV] Passing small data limitation value to RISCV backend (authored by shiva0217).
[RISCV] Passing small data limitation value to RISCV backend
Thu, Mar 19, 8:18 PM
shiva0217 closed D57497: [RISCV] Passing small data limitation value to RISCV backend.
Thu, Mar 19, 8:18 PM · Restricted Project

Tue, Mar 17

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update patch to address @apazos's comments.

Tue, Mar 17, 9:36 PM · Restricted Project
shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Shiva, how about making the flag small-data-limit alias of -msmall-data-threshold?

Tue, Mar 17, 9:36 PM · Restricted Project

Sun, Mar 15

shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Thanks Shiva, I res-ynced and rebuilt the patch. It is working fine.

I see there is a msmall-data-threshold flag used by Mips and Hexagon, and now we are adding a new flag msmall-data-limit. Should't we reuse the flag?

Hi Ana,
Thanks for trying the patch. msmall-data-limit is also a RISCV GCC flag, so I would recommend using the same flag as GCC.

How hard would it be to use the -msmall-data-threshold flag work if a -msmall-data-limit flag is not provided?

Sun, Mar 15, 6:48 PM · Restricted Project

Thu, Mar 12

shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Thanks Shiva, I res-ynced and rebuilt the patch. It is working fine.

I see there is a msmall-data-threshold flag used by Mips and Hexagon, and now we are adding a new flag msmall-data-limit. Should't we reuse the flag?

Thu, Mar 12, 7:04 PM · Restricted Project

Wed, Mar 11

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update the patch to address @apazos's comments.

Wed, Mar 11, 10:40 PM · Restricted Project
shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Shiva, I see a warning always being printed:

'+small-data-limit=' is not a recognized feature for this target (ignoring feature)

This is because it is being passed down as a target feature.

Might be good to add a test case to make sure the SmallDataLimit module flag is created, no target feature is passed, and that no warnings are printed.

Wed, Mar 11, 10:33 PM · Restricted Project

Tue, Mar 10

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update patch to address @jrtc27's comment.

Tue, Mar 10, 11:00 PM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update patch to address @evandro's comments.

Tue, Mar 10, 8:14 PM · Restricted Project
shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Update patch to address @lenary's comments.

Tue, Mar 10, 6:23 AM · Restricted Project

Mon, Mar 9

shiva0217 updated the diff for D57497: [RISCV] Passing small data limitation value to RISCV backend.

Rebase to the trunk

Mon, Mar 9, 11:21 PM · Restricted Project
shiva0217 added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Shiva, we forgot about this patch. Can you rebase it so we move on with merging.

Mon, Mar 9, 7:26 PM · Restricted Project
shiva0217 committed rGc3d981aebaba: [RISCV] Add new SchedRead SchedWrite (authored by shiva0217).
[RISCV] Add new SchedRead SchedWrite
Mon, Mar 9, 9:42 AM
shiva0217 closed D75515: [RISCV] Add new SchedRead and SchedWrite.
Mon, Mar 9, 9:41 AM · Restricted Project
shiva0217 added a comment to D75515: [RISCV] Add new SchedRead and SchedWrite.

Hi @HsiangKai,
Thanks for the review.

Mon, Mar 9, 9:08 AM · Restricted Project

Thu, Mar 5

shiva0217 updated the diff for D75515: [RISCV] Add new SchedRead and SchedWrite.

Update the patch to address @HsiangKai's comments.

Thu, Mar 5, 2:14 AM · Restricted Project

Tue, Mar 3

shiva0217 created D75515: [RISCV] Add new SchedRead and SchedWrite.
Tue, Mar 3, 4:35 AM · Restricted Project

Feb 17 2020

shiva0217 added a comment to D74596: [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler.

The patch has landed with https://github.com/llvm/llvm-project/commit/1cae2f9d192c69833e22684ca338660942ab464e. I forgot to add the "Differential Revision:" in the commit message, so I closed the revision manually. Sorry for the inconvenience.

Feb 17 2020, 4:26 AM · Restricted Project

Feb 14 2020

shiva0217 closed D74596: [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler.

Hi @lenary and @luismarques,
Thanks for the review.

Feb 14 2020, 5:34 PM · Restricted Project
shiva0217 committed rG1cae2f9d192c: [RISCV] Correct the CallPreservedMask for the function call in an interrupt… (authored by shiva0217).
[RISCV] Correct the CallPreservedMask for the function call in an interrupt…
Feb 14 2020, 5:16 PM
shiva0217 updated the diff for D74596: [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler.

Update the patch to fix the typo.

Feb 14 2020, 5:07 PM · Restricted Project
shiva0217 created D74596: [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler.
Feb 14 2020, 2:12 AM · Restricted Project

Feb 9 2020

shiva0217 committed rG64f417200e10: [RISCV] Fix incorrect FP base CFI offset for variable argument functions (authored by shiva0217).
[RISCV] Fix incorrect FP base CFI offset for variable argument functions
Feb 9 2020, 7:59 PM
shiva0217 closed D73862: [RISCV] Fix incorrect FP base CFI offset for variable argument functions.
Feb 9 2020, 7:59 PM · Restricted Project
shiva0217 updated the diff for D73862: [RISCV] Fix incorrect FP base CFI offset for variable argument functions.

Update the patch to address the comment.

Feb 9 2020, 7:28 PM · Restricted Project

Feb 2 2020

shiva0217 created D73862: [RISCV] Fix incorrect FP base CFI offset for variable argument functions.
Feb 2 2020, 10:13 PM · Restricted Project

Jan 13 2020

shiva0217 added inline comments to D68685: [RISCV] Scheduler description for Rocket Core.
Jan 13 2020, 10:21 PM · Restricted Project

Jan 7 2020

shiva0217 added a child revision for D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls: D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.
Jan 7 2020, 9:29 PM · debug-info, Restricted Project
shiva0217 accepted D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.

LGTM, Labels required to describe call site scope will be generated for the calls after FrameSetup instructions. When the SaveLibcall mark as FrameSetup, the Label will not be generated, so constructing call site entry for SaveLibcall will trigger an assertion. Given that SaveLibcall should be part of the prologue, so I think generating call site begin after FrameSetup instructions should be reasonable. But I hope there could be a second look.

Jan 7 2020, 9:29 PM · debug-info, Restricted Project
shiva0217 added a parent revision for D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls: D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.
Jan 7 2020, 9:29 PM · Restricted Project, Restricted Project
shiva0217 added a reviewer for D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls: dblaikie.
Jan 7 2020, 9:29 PM · debug-info, Restricted Project

Dec 12 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Dec 12 2019, 5:19 AM · Restricted Project, Restricted Project

Dec 9 2019

shiva0217 added inline comments to D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.
Dec 9 2019, 8:57 PM · Restricted Project, Restricted Project

Nov 26 2019

shiva0217 added a comment to D70670: [RISCV] Implement canRealignStack.

With the patch, double load/store instructions may unaligned-access with -mabi=ilp32e -mattr=+d flags. Could the load/store support unaligned-access?

Nov 26 2019, 1:38 AM · Restricted Project

Nov 20 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 20 2019, 6:25 PM · Restricted Project, Restricted Project
shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 20 2019, 12:21 AM · Restricted Project, Restricted Project

Nov 19 2019

shiva0217 added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 19 2019, 12:10 AM · Restricted Project, Restricted Project

Nov 15 2019

shiva0217 committed rGcf6cf0cd147a: [RISCV] Handle variable sized objects with the stack need to be realigned (authored by shiva0217).
[RISCV] Handle variable sized objects with the stack need to be realigned
Nov 15 2019, 8:45 PM
shiva0217 closed D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Nov 15 2019, 8:45 PM · Restricted Project
shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Rebase to the master

Nov 15 2019, 12:38 AM · Restricted Project

Nov 14 2019

shiva0217 added inline comments to D69723: [RISCV] Fix wrong CFI directives.
Nov 14 2019, 7:40 AM · Restricted Project

Nov 11 2019

shiva0217 added inline comments to D69723: [RISCV] Fix wrong CFI directives.
Nov 11 2019, 9:32 PM · Restricted Project

Nov 7 2019

shiva0217 added a comment to D69723: [RISCV] Fix wrong CFI directives.

Hi @luismarques,
I tried to generate .cfi_remember_state and .cfi_restore_state in emitEpilogue. It could pass the test case.
But there is an issue that .cfi_restore_state will become incorrect if the shrink wrapping hoists the epilogue.
So I think to remove CFI directives from the epilogue as other targets do might be a reasonable step.

Nov 7 2019, 6:36 AM · Restricted Project

Oct 31 2019

shiva0217 accepted D69385: [RISCV] Fix CFA when doing split sp adjustment with fp.

Hi @luismarques, thanks for the patch, LGTM.

Oct 31 2019, 4:49 AM · Restricted Project

Oct 28 2019

shiva0217 committed rGc1498e37abe6: [RISCV] Remove RA from reserved register to use as callee saved register (authored by shiva0217).
[RISCV] Remove RA from reserved register to use as callee saved register
Oct 28 2019, 8:35 PM
shiva0217 closed D67698: [RISCV] Remove RA from reserved register to use as callee saved register.
Oct 28 2019, 8:34 PM · Restricted Project
shiva0217 added inline comments to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 28 2019, 8:22 PM · Restricted Project

Oct 27 2019

shiva0217 requested changes to D69385: [RISCV] Fix CFA when doing split sp adjustment with fp.

Hi @luismarques, thanks for fixing this.

Oct 27 2019, 10:30 PM · Restricted Project
shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Add CFI checking line in the test case

Oct 27 2019, 6:54 PM · Restricted Project
shiva0217 added inline comments to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 27 2019, 6:52 PM · Restricted Project

Oct 18 2019

shiva0217 updated the diff for D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Update patch to address the comments.

Oct 18 2019, 12:22 AM · Restricted Project

Oct 17 2019

shiva0217 added a comment to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Shiva, I have tried a few workloads like EEMBC, SPEC2000/2006, perennial c++, plumhall.
They don't seem to use variable length arrays nor allocas to test this patch.
Which test suite are you using?

Oct 17 2019, 10:56 PM · Restricted Project

Oct 15 2019

shiva0217 created D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.
Oct 15 2019, 3:11 AM · Restricted Project

Oct 14 2019

shiva0217 updated the diff for D67698: [RISCV] Remove RA from reserved register to use as callee saved register.

Rebase the test case.

Oct 14 2019, 8:04 PM · Restricted Project
shiva0217 committed rG078bec6c48dd: [RISCV] Support fast calling convention (authored by shiva0217).
[RISCV] Support fast calling convention
Oct 14 2019, 7:09 PM
shiva0217 closed D68559: [RISCV] Support fast calling convention.
Oct 14 2019, 7:09 PM · Restricted Project

Oct 12 2019

shiva0217 added inline comments to D62190: [RISCV] Allow shrink wrapping for RISC-V.
Oct 12 2019, 11:34 PM · Restricted Project

Oct 8 2019

shiva0217 added a comment to D68559: [RISCV] Support fast calling convention.

I like this change.

fastcc is LLVM-internal only, right? Checking that we don't have to care about splitting operands that don't fit into registers, or any other psABI details, right?

Yes, to my understanding, fastcc doesn't need to care about psABI details.

Oct 8 2019, 11:26 AM · Restricted Project
shiva0217 updated the diff for D68559: [RISCV] Support fast calling convention.

Update patch to address the feedbacks

Oct 8 2019, 11:25 AM · Restricted Project
shiva0217 updated the diff for D68559: [RISCV] Support fast calling convention.

Update patch to address the comment

Oct 8 2019, 12:20 AM · Restricted Project

Oct 6 2019

shiva0217 created D68559: [RISCV] Support fast calling convention.
Oct 6 2019, 7:16 PM · Restricted Project

Oct 3 2019

shiva0217 committed rGff55e2e0476b: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill… (authored by shiva0217).
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill…
Oct 3 2019, 7:00 PM
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Fix comment in the patch.

Oct 3 2019, 6:50 PM · Restricted Project
shiva0217 added inline comments to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Oct 3 2019, 6:46 PM · Restricted Project

Sep 26 2019

shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Add splitting SP adjustment boundary test case as @luismarques suggest.

Sep 26 2019, 9:59 PM · Restricted Project
shiva0217 added a comment to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

@shiva0217 Thanks for updating the patch and addressing the previous concerns. This is looking quite good. I have just a couple more concerns before approving this:

  • The boundary condition for doing the two-stage sp adjustment probably needs adjustment. For instance, try this:

    ` int main() { char xx[2048-16]; foo(xx); } -- addi sp, sp, -2032 sd ra, 2024(sp) addi sp, sp, -16 ... `

    I think that one would still fit a single-stage sp update. Related to that, where you have the code if (!isInt<12>(StackSize) && (CSI.size() > 0)), be sure that the isInt<12> check properly accounts for the StackSize, CSI size, StackAlign etc. Which brings me to the second point...
  • Please include tests showing that the boundary condition is correctly computed. For instance, one test where the stack size is just enough not to have to split the sp adjustment and another where the adjustment is needed.

    Thanks!
Sep 26 2019, 7:01 AM · Restricted Project
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

Sep 26 2019, 1:14 AM · Restricted Project

Sep 25 2019

shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch

  1. Call getFirstSPAdjustAmount() once in per prologue/epilogue generation as @luismarques suggest
  2. Generate CFI directives in large-stack.ll test case to check the CFI generation
Sep 25 2019, 7:24 PM · Restricted Project
shiva0217 updated the diff for D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.

Update patch to address the comments.

Sep 25 2019, 7:49 AM · Restricted Project
shiva0217 added inline comments to D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Sep 25 2019, 6:54 AM · Restricted Project
shiva0217 created D68011: [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore.
Sep 25 2019, 2:27 AM · Restricted Project

Sep 19 2019

shiva0217 added a comment to D67698: [RISCV] Remove RA from reserved register to use as callee saved register.

We discussed this in the RISC-V meeting on 19 Sep 2019.

  • Pros: GCC for RISC-V and LLVM for ARM and AArch64 seem to do the same. It can help in situations with particularly bad register pressure requirements.
  • Cons: It can make debugging a lot harder, though this seems not to be an issue in GDB for RISC-V.

    I think we don't want to have yet another configuration flag to control this.

    It would be good to see some performance comparison, but I realise you may not be able to release internal benchmarks, and we have no public benchmarking system for RISC-V.
Sep 19 2019, 10:13 PM · Restricted Project

Sep 18 2019

shiva0217 created D67698: [RISCV] Remove RA from reserved register to use as callee saved register.
Sep 18 2019, 2:03 AM · Restricted Project

Sep 12 2019

shiva0217 committed rGa49a16ddd0eb: [RISCV] Support stack offset exceed 32-bit for RV64 (authored by shiva0217).
[RISCV] Support stack offset exceed 32-bit for RV64
Sep 12 2019, 9:04 PM
shiva0217 committed rGea530ba3ed75: Revert "[RISCV] Support stack offset exceed 32-bit for RV64" (authored by shiva0217).
Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
Sep 12 2019, 9:04 PM
shiva0217 committed rGeaa230fe3c86: [RISCV] Support stack offset exceed 32-bit for RV64 (authored by shiva0217).
[RISCV] Support stack offset exceed 32-bit for RV64
Sep 12 2019, 7:51 PM
shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Choosing virtual register as temp register.

Sep 12 2019, 8:01 AM · Restricted Project

Sep 11 2019

shiva0217 added a comment to D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using t1 (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use a0-5 if it wishes, which can be compressed, unlike t1. Do you have a justification for explicitly choosing t1?

Sep 11 2019, 6:57 PM · Restricted Project
shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Update patch to address the comments.

Sep 11 2019, 7:14 AM · Restricted Project
shiva0217 added inline comments to D61884: [RISCV] Support stack offset exceed 32-bit for RV64.
Sep 11 2019, 7:11 AM · Restricted Project

Sep 10 2019

shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Using T1 as temp register for prologue/epilogue generation if there is no shrink wrapping optimization occur.

Sep 10 2019, 12:08 AM · Restricted Project

Aug 31 2019

shiva0217 committed rGadfdcb9c2652: [TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with… (authored by shiva0217).
[TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with…
Aug 31 2019, 9:54 PM

Aug 28 2019

shiva0217 updated the diff for D61884: [RISCV] Support stack offset exceed 32-bit for RV64.

Rebase to the trunk

Aug 28 2019, 7:00 PM · Restricted Project
shiva0217 committed rGb39876d8cddb: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall (authored by shiva0217).
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
Aug 28 2019, 4:42 PM

Aug 21 2019

shiva0217 committed rG72a41e7b0d04: [TargetLowering] Remove optional arguments passing to makeLibCall (authored by shiva0217).
[TargetLowering] Remove optional arguments passing to makeLibCall
Aug 21 2019, 10:02 PM

Aug 20 2019

shiva0217 added a comment to D66278: [RISCV] Enable tail call opt for variadic function.

Hi Jim,

Aug 20 2019, 8:01 PM · Restricted Project
shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Add comment for the new field in MakeLibCallOptions struct.

Aug 20 2019, 6:41 PM · Restricted Project

Aug 19 2019

shiva0217 added inline comments to D62190: [RISCV] Allow shrink wrapping for RISC-V.
Aug 19 2019, 11:25 PM · Restricted Project
shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Update patch to reflect the comments.

Aug 19 2019, 7:45 PM · Restricted Project
shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 19 2019, 7:35 PM · Restricted Project

Aug 8 2019

shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

I remove the IsCastFromFloat flag and store the SDNode before soften in MakeLibCallOptions struct. So that the shouldExtendTypeInLibCall could get the original type directly and get rid of the complicate IsCastFromFloat setting method. I try to illustrate most of the single soft-float functions in rv64i-single-softfloat.ll. Please kindly remind me if I still missing something, thanks.

Aug 8 2019, 11:49 PM · Restricted Project
shiva0217 updated the diff for D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.

Only define the bits will be used for makelibCall in MakeLibCallOptions struct.

Aug 8 2019, 11:33 PM · Restricted Project
shiva0217 added inline comments to D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.
Aug 8 2019, 11:25 PM · Restricted Project

Aug 7 2019

shiva0217 updated the diff for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.

Rebase the patch base on D65795 and update test cases.
Thanks for Eli's comments and Alex's excellent floating test cases that we could easily observe the difference.

Aug 7 2019, 1:17 AM · Restricted Project
shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 7 2019, 1:06 AM · Restricted Project

Aug 6 2019

shiva0217 added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 6 2019, 2:31 AM · Restricted Project
shiva0217 added a parent revision for D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall: D65795: [TargetLowering] Remove optional arguments passing to makeLibCall.
Aug 6 2019, 2:18 AM · Restricted Project