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asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (410 w, 2 d)

Recent Activity

Thu, May 27

asb added a comment to D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division.

Personally I prefer to deprecate -mno-div soon, but based on the rule for RISC-V GNU toolchain, it need to wait Zmmul extension frozen.
My plan is deprecate the -mno-div and emit warning to tell user should use Zmmul instead once it frozen.

Thu, May 27, 7:46 AM · Restricted Project, Restricted Project

May 13 2021

asb added a comment to D101919: RISCV: add a few deprecated aliases for CSRs.

I'll put this patch on the agenda for the sync-up call today, but particularly now it emits a warning I'm inclined to think we should accept this in order to provide drop-in compatibility for GNU toolchains.

May 13 2021, 1:12 AM · Restricted Project
asb added inline comments to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
May 13 2021, 12:50 AM · Restricted Project

May 12 2021

asb added a comment to D70401: [WIP][RISCV] Implement ilp32e ABI.

Hi, I would like to add ilp32e ABI support in llvm
Is there anyone working on this?
It seem the one thing missed is ilp32e ABI should disallow D ISA extension.
Is there anything else?

May 12 2021, 9:36 AM · Restricted Project, Restricted Project

Apr 29 2021

asb added a comment to D100529: [PoC] Reduce impact `riscv_vector.h` when testing.

I think using this proxy header for testing seems good.

IMO, maybe we still need to find a way to reduce the compilation time for better user experience.

Apr 29 2021, 8:50 AM

Apr 15 2021

asb added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

The GCC torture suite now gets a 100% pass rate for me - thanks for fixing. I've left various minor notes about comment phrasing and formatting etc.

Apr 15 2021, 8:06 AM · Restricted Project
asb added a comment to D98932: [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk.
In D98932#2663612, @asb wrote:

It would definitely be good to get a test case for this as Fraser says.

I appreciate it's a bit hard to implement an alternate fix that doesn't involve the risk of regressing other backends, but it's not ideal to remove a call to a hook that really RISC-V should be setting (per the description of setHasMultipleConditionRegisters, this should be set for RISC-V).

This is a good point fix for the immediate problem, but the concern is just that future optimiser changes means there are more issues or missed optimisation opportunities down the road.

If we did want to do this, probably worth adding comments to explain that we'd like to setHasMultipleConditionRegisters ideally, but are choosing not to due to codegen regressions.

Apr 15 2021, 3:38 AM · Restricted Project
asb accepted D100532: [RISCV] Don't emit save-restore call if function is a interrupt handler.
Apr 15 2021, 3:17 AM · Restricted Project

Apr 1 2021

asb added a comment to D99087: [RISCV] Fix stack slot for argument types (Bug 49500).

@frasercrmck you mentioned this patch doesn't quite seem right to you - is there a particular part you're concerned about. I've spent some time going over both this and D99068. The logic of this patch makes more intuitive sense to me, but that may be as it's a long time since I have a better memory of the logic it's modifying. Though Luis' approach does indeed seem to reduce stack size in some cases, and of course directly mirrors the matching SystemZ fix.

Apr 1 2021, 7:10 AM · Restricted Project
asb added a comment to D98932: [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk.

It would definitely be good to get a test case for this as Fraser says.

Apr 1 2021, 5:25 AM · Restricted Project
asb accepted D98821: [RISCV] Improve 64-bit integer materialization for some cases..

LGTM, left a couple of nits on comment typos. Thanks!

Apr 1 2021, 4:59 AM · Restricted Project
asb accepted D99479: [RISCV] Add custom type legalization to form MULHSU when possible..

I think it's OK to land without this, but: Running this patch quickly across the GCC torture suite, the only codegen changes are to 20120817-1.c and pr51581-{1,2}.c on RV32 where a mulhsu is now selected rather than a solitary mulh. I believe this is still correct, but it made me wonder if we are missing some test coverage and should have a codegen test that would demonstrate that change.

Apr 1 2021, 4:42 AM · Restricted Project
asb accepted D99021: [RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition..

Needs a rebase for the test changes to apply, but this LGTM.

Apr 1 2021, 4:03 AM · Restricted Project
asb accepted D99148: [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat..

Let's mention it in the community call today just in case anyone has strong differing opinions, but this lowering strategy makes much more intuitive sense to me.

Apr 1 2021, 3:46 AM · Restricted Project
asb requested changes to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

Could you please rebase this to account for D98716?

Apr 1 2021, 3:37 AM · Restricted Project

Mar 31 2021

asb accepted D97646: [ASan][RISCV] Fix RISC-V memory mapping.

LGTM. Luis is the one who's dived deep into the memory mappings etc, but he and I had a discussion offline to help me understand the reasoning for this change, and given it's also had an LGTM from sanitizer devs I think this is good to land.

Mar 31 2021, 8:11 AM · Restricted Project, Restricted Project
asb accepted D99317: [RISCV] Add RISCVISD opcodes for CLZW and CTZW..

LGTM, this seems the right direction to go in.

Mar 31 2021, 8:06 AM · Restricted Project
asb added a comment to D99029: [RISCV] Don't form MULW for (sext_inreg (mul X, Y), i32)) if the mul has another use..

I made a dedicated fix for the motivating issue with 5692fc38e0d17abc55a4a84da98f021a1d53d76d so I'm not as concerned with pushing this patch now.

Mar 31 2021, 7:10 AM · Restricted Project
asb added a comment to D99087: [RISCV] Fix stack slot for argument types (Bug 49500).

I've been a bit busy with some none-LLVM things the past few days too, so sorry for the delay in commenting. I'll try and loop back shortly.

Mar 31 2021, 6:40 AM · Restricted Project
asb accepted D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager.

LGTM.

Mar 31 2021, 6:28 AM · Restricted Project
asb added a comment to D99320: [RISCV] [1/2] Add intrinsic for Zbb extension.

Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes _{rv,rv32,rv64}_{opname} intrinsics. Does the __builtin__{riscv,riscv32,riscv64}_opname format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or something else?

Mar 31 2021, 6:16 AM · Restricted Project, Restricted Project
asb accepted D99655: [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32.
Mar 31 2021, 6:02 AM · Restricted Project
asb added a comment to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.

Are there ever any cases where you _wouldn't_ want a CSR-specific pseudo in order to have control over the scheduling of it specifically? This feels a bit like a middle-ground that's the worst of both worlds to me.

Mar 31 2021, 5:49 AM · Restricted Project

Mar 18 2021

asb accepted D98124: [RISCV] Clean up parsing fence arguments.

Great cleanup, thanks for this.

Mar 18 2021, 8:38 AM · Restricted Project
asb accepted D98125: [RISCV] Clean up parsing floating point rounding mode.

This is much better, thank you.

Mar 18 2021, 8:38 AM · Restricted Project
asb added inline comments to D98236: [RISCV] Add SiFive-VIU75 for llvm.
Mar 18 2021, 4:01 AM · Restricted Project
asb added a comment to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.

@sebastian-ne: to ensure the right people see this, could you file a bug for your problem please? https://llvm.org/docs/HowToSubmitABug.html

Mar 18 2021, 3:36 AM · Restricted Project
asb added inline comments to D98136: [RISCV][RFC] Initially support the K-extension instructions on the LLVM MC layer.
Mar 18 2021, 3:29 AM · Restricted Project
asb accepted D98800: [NFC][RISCV] Pass test through update_llc_tests_checks.py to address whitespace issues.
Mar 18 2021, 2:30 AM · Restricted Project
asb added a comment to D98797: [docs] Document regular LLVM sync-ups.

Great idea - the RISC-V bit looks good to me.

Mar 18 2021, 2:24 AM · Restricted Project

Mar 4 2021

asb added a comment to D94163: [RISCV] Set dependency on floating point CSRs, 1/3.

We discussed this briefly in the RISC-V call as I noted this patchset has been sat open for some time. One thing that might be helpful is whether you could say a little bit more about the goal for this patchset. Once this lands, what's the next step? Is there some relevant RFC, or equivalent changes being made to other in-tree architectures?

Mar 4 2021, 8:27 AM · Restricted Project
asb added a comment to D97896: [Clang][RISCV][RFC] Add byval parameter attribute?.

I think I may have had the impression from some previous discussions that byval may have limited positive impact, and that letting Clang add the copies to the IR might in some cases help optimisations (that may not be written to reason about byval). You've got a good example of a case where the lack of byval causes weaker optimisation though.

Mar 4 2021, 5:06 AM · Restricted Project

Feb 25 2021

asb accepted D92479: [RISCV] remove redundant instruction when eliminate frame index.

This needs a rebase, but LGTM to land after that. Thanks!

Feb 25 2021, 3:38 AM · Restricted Project
asb accepted D97262: [RISCV] Add isel pattern to match X > -1 to bgez..

LGTM, thanks!

Feb 25 2021, 3:26 AM · Restricted Project

Feb 5 2021

asb added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

According to @jrtc27 's review that is
"As for Zfinx itself, well, the idea is fine, but I really detest the way it's being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not work_ so it is not an _extension_. Instead it should really be a set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and Zfhinx, but apparently asking code that complies with a ratified standard to change itself in order to not break when a new extension is introduced is a-ok in the RISC-V world.".
We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and Zfhinx.

Feb 5 2021, 5:14 AM · Restricted Project, Restricted Project
asb added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

I started reviewing this alongside the specification in https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to be used in this patch. I think intent is that rv32ifd_zfinx is the equivalent of "zfdinx" in this patch. Is there a reason to go for different naming, or a different version of the spec I should be looking at?

Feb 5 2021, 2:27 AM · Restricted Project, Restricted Project

Feb 4 2021

asb added a comment to D95588: [RISCV] Implement the MC layer support of P extension.

Per our discussion in the RISC-V community call today, PLCT Lab + Andes are going to reach out to each other to try to coordinate these MC layer and future codegen patches (thanks!).

Feb 4 2021, 8:29 AM · Restricted Project, Restricted Project
asb added a comment to D94579: [RISCV] add the MC layer support of P extension.

Per our discussion in the RISC-V community call today, this patch is intended as more of a "request for comment" at this stage given the P extension encoding issues, and PLCT Lab + Andes are going to reach out to each other to try to coordinate these MC layer and future codegen patches (thanks!).

Feb 4 2021, 8:28 AM · Restricted Project

Jan 29 2021

asb accepted D95680: [RISCV] Update the version number to v0.10 for vector..

LGTM modulo one additional request: please update the comment at the top of RISCVInstrInfoV.td to say "0.10" rather than "0.9".

Jan 29 2021, 8:19 AM · Restricted Project, Restricted Project

Jan 28 2021

asb accepted D95227: [RISCV] Simplify BP initialisation.

LGTM.

Jan 28 2021, 5:31 AM · Restricted Project
asb accepted D95302: [RISCV] Remove isel patterns for Zbs *W instructions..

LGTM. It might be worth adding a comment where the patterns were removed to explain we don't have ISel patterns for those instructions because they've been removed from the 0.94 spec (just in case someone starts looking to add them, having not followed upstream development closely).

Jan 28 2021, 5:28 AM · Restricted Project
asb added a comment to D95422: [RISCV] Copy isUnneededShiftMask from X86..

This was a really nice improvement - thanks Craig!

Jan 28 2021, 5:06 AM · Restricted Project
asb added a reviewer for D95588: [RISCV] Implement the MC layer support of P extension: asb.

Hi Jim, thanks for the contribution. I saw you were on the review thread for D94579 which also aims to implement MC layer support for the P extension - could you please comment on the difference between these two patches as you see it?

Jan 28 2021, 5:04 AM · Restricted Project, Restricted Project
asb added a reviewer for D94579: [RISCV] add the MC layer support of P extension: asb.

Thanks for submitting this. It doesn't apply against current HEAD, could you please rebase?

Jan 28 2021, 5:00 AM · Restricted Project

Jan 22 2021

asb accepted D95150: [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32..

Thanks for extending the test coverage!

Jan 22 2021, 10:58 AM · Restricted Project
asb accepted D95002: [RISCV] Update B extension version to 0.93..
Jan 22 2021, 10:37 AM · Restricted Project, Restricted Project
asb accepted D94999: [RISCV] Add xperm.* instructions to Zbp extension..
Jan 22 2021, 10:35 AM · Restricted Project
asb accepted D94944: [RISCV] Add support for rev8 and orc.b to Zbb..

LGTM, and I agree with the reasoning re preferring to point users towards zbb.

Jan 22 2021, 10:33 AM · Restricted Project
asb accepted D94818: [RISCV] Add zext.h instruction to Zbb..
Jan 22 2021, 10:26 AM · Restricted Project
asb accepted D94742: [RISCV] Move pack instructions to Zbp extension only..
Jan 22 2021, 9:30 AM · Restricted Project
asb accepted D94736: [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack..

LGTM, added two minor notes.

Jan 22 2021, 9:22 AM · Restricted Project
asb accepted D95090: [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec..
Jan 22 2021, 9:15 AM · Restricted Project
asb added inline comments to D94653: [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec..
Jan 22 2021, 9:12 AM · Restricted Project
asb accepted D94653: [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec..

LGTM, going with the 0.94 deconflicted naming seems the only reasonable thing to do https://github.com/riscv/riscv-bitmanip/pull/102/commits/b962f8a04be570a93c3c4788425ee2e8a14e9c56

Jan 22 2021, 9:10 AM · Restricted Project
asb accepted D94652: [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec..
Jan 22 2021, 9:04 AM · Restricted Project

Jan 21 2021

asb added a comment to D94652: [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec..

My hope is to get the 0.93 move into LLVM 12. Zbb is marked frozen in the 0.93 spec and does not include these. So I'd at least like them out of Zbb. Would it be better to just remove them until they have a home?

Mm yes, if Zbb is frozen and doesn't include them then I agree they need to go somewhere. Removing them sounds a bit drastic. If the release branch will be created in 6 days, how long can we delay the decision?

Jan 21 2021, 7:58 AM · Restricted Project
asb accepted D94637: [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec..

Not a blocker as I think this is just something that bitmanip has been less complete with vs the standard extensions, and you're just the last person to touch this, but we should probably be testing that rv32zba rejects rv64-only instructions and that rv64zba accepts the rv32 instructions. See rv64f-valid.s and rv32f-valid.s.

Jan 21 2021, 7:27 AM · Restricted Project
asb accepted D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it..
Jan 21 2021, 7:19 AM · Restricted Project, Restricted Project
asb accepted D94582: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec..
Jan 21 2021, 7:14 AM · Restricted Project, Restricted Project
asb accepted D94580: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec..
Jan 21 2021, 7:13 AM · Restricted Project
asb accepted D94577: [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec..
Jan 21 2021, 7:11 AM · Restricted Project
asb accepted D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..

Straight forward change, LGTM. It seems there's nothing contentious in the patchset, so I'd expect the series can land basically all at once, to minimise the time we support a weird 0.92/0.93 hybrid.

Jan 21 2021, 7:07 AM · Restricted Project
asb accepted D95106: [RISCV] Add isel patterns for SH*ADD(.UW).

These LGTM. This patch should presumably be marked dependent on D94637.

Jan 21 2021, 5:55 AM · Restricted Project
asb added a comment to D95002: [RISCV] Update B extension version to 0.93..

I don't think any of the other patches in the stack update the comment at the top of RISCVInstrInfoB.td to say "version 0.92" rather than "version 0.93", and this is probably a reasonable patch to do it in.

Jan 21 2021, 5:51 AM · Restricted Project, Restricted Project
asb added inline comments to D94931: [RISCV] Add attribute support for all supported extensions.
Jan 21 2021, 5:24 AM · Restricted Project
asb added a comment to D94403: [RISCV] Implement new architecture extension macros.

@kito-cheng could you please confirm that this patch handles sub-extensions in the same way GCC does. i.e. -march=rv32izbb0p92 defines __riscv_zbb but NOT __riscv_b? That seems logical to me, as otherwise it would be cumbersome to check if the whole extension is supported rather than just a subset, but I just wanted to confirm.

Jan 21 2021, 5:18 AM · Restricted Project

Jan 14 2021

asb added a comment to D94589: [RISCV] Add intrinsics for vector AMO instructions.

Nitpick: this would be better titled "[RISCV] Add intrinsics for vector AMO instructions" - I was a little confused seeing the title come past :)

Jan 14 2021, 6:35 AM · Restricted Project
asb added a comment to D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

However it's also a milestone for B-ext, since this version claim zba, zbb and zbc is frozen, maybe those 3 sub-ext. could be removed from the umbrella of -menable-experimental-extension ?

@asb What do you think about this?

Jan 14 2021, 5:25 AM · Restricted Project
asb accepted D93168: [RISCV] Merge Utils library into MCTargetDesc.

I think this is a reasonable change. The pattern of having "Utils" is common to AArch64, AMDGPU, ARM, and RISCV but I agree with your point that it's not cleanly separated from MCTargetDesc, so there's little benefit.

Jan 14 2021, 5:00 AM · Restricted Project

Dec 10 2020

asb updated subscribers of D91901: [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates.

Interesting. So to summarise my views on pros/cons

Dec 10 2020, 5:42 AM · Restricted Project
asb accepted D92008: [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal..

It's great to be able to drop those ugly patterns - nice cleanup. Thanks.

Dec 10 2020, 5:09 AM · Restricted Project
asb accepted D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions.

This needs a rebase, but otherwise looks good to me. Thanks Sam!

Dec 10 2020, 5:00 AM · Restricted Project
asb added a comment to D92715: [Clang][RISCV] Define RISC-V V builtin types.

Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng @khchen @liaolucy

Dec 10 2020, 4:49 AM · Restricted Project

Nov 26 2020

asb added a comment to D83059: [RISCV] Use Generated Instruction Uncompresser.

I'm afraid this causes compile-time failures with 20030323-1.c, multi-ix.c, and pr53645.c.

Nov 26 2020, 8:22 AM · Restricted Project

Nov 13 2020

asb accepted D91414: [RISCV] Use a macro to simplify getTargetNodeName.

I think moving NODE_NAME_CASE(foo) to the left so it's aligned where the case statement would be (same as the equivalent in X86ISelLowering and AMDGPUISelLowering) would be slightly better. I wouldn't be opposed to using // clang-format off to stop clang-format from reformatting (though it seems more common in LLVM right now to just ignore clang-format's preference).

Nov 13 2020, 6:19 AM · Restricted Project

Nov 12 2020

asb added a reviewer for D90973: [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32: kparzysz.

Ouch - I'm sorry to have contributed to the bloating of LLVM binaries!

Nov 12 2020, 5:57 AM · Restricted Project
asb accepted D91114: [RISCV] Don't include CodeGen layer files in MC layer.

This seems like a good cleanup to me - thanks.

Nov 12 2020, 5:50 AM · Restricted Project
asb added a comment to D91199: [RISCV] Remove traces of Glue from RISCVISD::SELECT_CC.

LGTM; from a quick look I can't see anything that would need that glue. Do you have an idea why it was added?

No. As far as I could tell it had been there but not used since the first patch that added RISCVISD::SELECT_CC.

Nov 12 2020, 5:45 AM · Restricted Project
asb added a comment to D90738: [RISCV] Support Zfh half-precision floating-point extension..

Historically for the RISC-V backend we've split patches into the MC layer changes and the codegen changes in order to make them easier to review. Do you think you'd be able to do the same here?

Nov 12 2020, 5:37 AM · Restricted Project

Oct 15 2020

asb accepted D89237: [RISCV] Do not grow the stack a second time when we need to realign the stack.

Thanks Roger, this looks good to me and doesn't seem to break anything in the GCC torture suite at least.

Oct 15 2020, 5:04 AM · Restricted Project
asb added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

I think there's a little more to supporting older names than just the date of the spec. I agree that we don't expect anyone doing serious RISC-V work to be working to the 1.9 spec (unless there are cores taped out with that spec we don't know about), but in cases where there have been CSR renames it's often the case that people migrate to newer specification versions but don't always change the naming. There's an argument for the compiler complaining at them in this case, but there's also the user experience issue. It looks like the RISC-V compliance suite for instance still uses the sptbr name https://github.com/riscv/riscv-compliance/issues/107

Oct 15 2020, 5:02 AM · Restricted Project
asb accepted D86457: [compiler-rt][builtins][RISCV] Always include __mul[sd]i3 builtin definitions.

This LGTM. @lenary are you happy your comments are addressed?

Oct 15 2020, 4:49 AM · Restricted Project
asb accepted D83210: [RISCV][NFC] Add more tests for 32-bit constant materialization.

LGTM, thanks Luis.

Oct 15 2020, 3:33 AM · Restricted Project
asb accepted D89330: [RISCV] [TableGen] Modify RISCVCompressInstEmitter.cpp to use getAllDerivedDefinitions().

LGTM, thanks Paul.

Oct 15 2020, 3:18 AM · Restricted Project

Sep 17 2020

asb accepted D84414: [RISCV] Support Shadow Call Stack.

I think once @jrtc27 confirms all her issues are addressed this is good to land.

Sep 17 2020, 5:49 AM · Restricted Project, Restricted Project

Sep 3 2020

asb accepted D85366: [RISCV] Do not mandate scheduling for CSR instructions.

LGTM, thanks.

Sep 3 2020, 4:55 AM · Restricted Project
asb added a comment to D86836: Support a list of CostPerUse values.

It looks like others are reviewing the implementation details, but I just wanted to chime in to say that this looks like a useful feature for the RISC-V backend too. Currently we set CostPerUse for some registers in order to tweak register allocation in a way that benefits codegen when the compressed instruction set extension is enabled. Although the impact is _very_ minimal, this slightly harms targets that don't support the compressed instruction set (admittedly, this isn't really true of any shipping RISC-V processor so not a big concern). It would be good to use this vary the CostPerUse depending on target RISC-V features.

Sep 3 2020, 4:49 AM · Restricted Project
asb accepted D87069: [NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt.
Sep 3 2020, 4:44 AM · Restricted Project

Aug 21 2020

asb accepted D86286: [RISCV] Fix inaccurate annotations on PseudoBRIND.
Aug 21 2020, 2:30 AM · Restricted Project
asb added a comment to D77152: [SelectionDAG] Better legalization for FSHL and FSHR.

No objections accepting from the RISC-V side. I don't have a set of execution tests for the fshl/fshr changes to validate them, but I didn't see anything obviously wrong. The changes primarily affect the (still experimental) bitmanip extension also, so the bar for review is somewhat lower. The change does seem to improve srliw lowering in a few places in the GCC torture suite as well (in a way that is both correct and beneficial).

Aug 21 2020, 2:27 AM · Restricted Project

Aug 20 2020

asb committed rG1ecf120246e7: [index-while-building] Fix build with -DBUILD_SHARED_LIBS=True (authored by asb).
[index-while-building] Fix build with -DBUILD_SHARED_LIBS=True
Aug 20 2020, 7:14 AM
asb added a comment to D85366: [RISCV] Do not mandate scheduling for CSR instructions.

The description of isNotDuplicable in MachineInstr.h is:

/// Return true if this instruction cannot be safely duplicated.
/// For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::NotDuplicable, Type);
}

I don't think this obviously applies to CSRs, and the property doesn't seem to be applied to instructions that modify control registers for other in-tree targets.

Aug 20 2020, 2:28 AM · Restricted Project

Aug 6 2020

asb accepted D85015: [RISCV] Enable MCCodeEmitter instruction predicate verifier.

Thanks for spotting this one - LGTM.

Aug 6 2020, 6:43 AM · Restricted Project
asb added a comment to D84833: Implement indirect branch generation in position independent code for the RISC-V target.

@jrtc27 are you happy with this patch in its current form or are there outstanding issues to be addressed?

Aug 6 2020, 6:28 AM · Restricted Project

Jul 30 2020

asb added a comment to D84833: Implement indirect branch generation in position independent code for the RISC-V target.

@jrtc27 are you happy with this patch now? Thanks for your review on this and thanks @msizanoen1 for providing this fix.

Jul 30 2020, 5:37 AM · Restricted Project

Jul 21 2020

asb added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

It's a shame this just missed the creation of the llvm 11.0 branch, do we think it's worth trying to get this backported since it only just missed?

Jul 21 2020, 6:51 AM · Restricted Project

Jul 16 2020

asb accepted D71124: [RISCV] support clang driver to select cpu.

LGTM, thanks!

Jul 16 2020, 7:06 AM · Restricted Project, Restricted Project

Jul 14 2020

asb added a comment to D83059: [RISCV] Use Generated Instruction Uncompresser.

I'm getting a test failure on rv64-relax-all.s with this patch?

Jul 14 2020, 11:04 PM · Restricted Project
asb added a comment to D77443: [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos.

Hi @jrtc27 - it would be nice to get this in before LLVM 11 branches. Will you have time to add the extra comment and commit today?

Jul 14 2020, 10:56 PM · Restricted Project
asb added a comment to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

This looks good to land IMHO. It's a nice improvement for RISC-V, and it seems to have been sufficiently reviewed by people active with the DAGCombiner. Thanks Roger.

Jul 14 2020, 10:53 PM · Restricted Project