Added a few minor nits. You'll want to add a test for debug info to select-optimize-multiple.mir. I had a quick play with this and https://reviews.llvm.org/P8135 looks like a sensible way to do it.

Sun, Mar 17, 10:31 PM · Restricted Project

asb created D59470: [RISCV] Add basic RV32E definitions and MC layer support.

Sun, Mar 17, 5:13 AM · Restricted Project

asb committed rG997947961a07: [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cpp (authored by asb).

[RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cpp

Sun, Mar 17, 5:03 AM

asb committed rL356330: [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cpp.

[RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cpp

Sun, Mar 17, 5:03 AM

asb committed rGb18e314a7cbd: [RISCV] Fix RISCVAsmParser::ParseRegister and add tests (authored by asb).

[RISCV] Fix RISCVAsmParser::ParseRegister and add tests

Sun, Mar 17, 5:03 AM

asb committed rL356329: [RISCV] Fix RISCVAsmParser::ParseRegister and add tests.

[RISCV] Fix RISCVAsmParser::ParseRegister and add tests

Sun, Mar 17, 5:03 AM

Thu, Mar 14

asb created D59357: [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs.

Thu, Mar 14, 4:39 AM · Restricted Project

asb committed rGfec503acb667: [RISCV] Fix rL356123 (authored by asb).

[RISCV] Fix rL356123

Thu, Mar 14, 1:33 AM

asb committed rL356124: [RISCV] Fix rL356123.

[RISCV] Fix rL356123

Thu, Mar 14, 1:32 AM

asb committed rG8dbc6398e17a: [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor… (authored by asb).

[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor…

Thu, Mar 14, 1:29 AM

asb committed rL356123: [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor….

[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor…

Thu, Mar 14, 1:28 AM

asb committed rGd08ed38e084b: [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs (authored by asb).

[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs

Thu, Mar 14, 1:17 AM

asb committed rL356122: [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs.

[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs

Thu, Mar 14, 1:16 AM

Wed, Mar 13

asb committed rGbd1c56648fae: [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068 (authored by asb).

[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068

Wed, Mar 13, 11:29 AM

asb committed rL356074: [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068.

[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068

Wed, Mar 13, 11:24 AM

asb committed rG8a70468a2700: [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer (authored by asb).

[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

Wed, Mar 13, 9:36 AM

asb committed rL356063: [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer.

[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

Wed, Mar 13, 9:33 AM

asb committed rG7d546aba6c4d: [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s (authored by asb).

[RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s

Wed, Mar 13, 9:14 AM

asb committed rL356061: [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s.

[RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s

Wed, Mar 13, 9:14 AM

asb committed rG192df587d199: [RISCV] Regenerate umulo-128-legalisation-lowering.ll (authored by asb).

[RISCV] Regenerate umulo-128-legalisation-lowering.ll

Wed, Mar 13, 5:33 AM

asb committed rL356044: [RISCV] Regenerate umulo-128-legalisation-lowering.ll.

[RISCV] Regenerate umulo-128-legalisation-lowering.ll

Wed, Mar 13, 5:33 AM

asb committed rG18f95e6a6f1a: [RISCV] Replace incorrect use of sizeof with array_lengthof (authored by asb).

[RISCV] Replace incorrect use of sizeof with array_lengthof

Wed, Mar 13, 2:22 AM

asb committed rL356035: [RISCV] Replace incorrect use of sizeof with array_lengthof.

[RISCV] Replace incorrect use of sizeof with array_lengthof

Wed, Mar 13, 2:22 AM

Tue, Mar 12

asb committed rGc965d21f3318: [RISCV] Add test cases for the lp64 ABI (authored by asb).

[RISCV] Add test cases for the lp64 ABI

Tue, Mar 12, 2:29 AM

asb committed rL355899: [RISCV] Add test cases for the lp64 ABI.

[RISCV] Add test cases for the lp64 ABI

Tue, Mar 12, 2:28 AM

Mon, Mar 11

asb committed rG4d20cc21c774: [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A (authored by asb).

[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A

Mon, Mar 11, 2:42 PM

asb committed rL355869: [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A.

[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A

Mon, Mar 11, 2:40 PM

asb closed D58829: Do a sign-extension in a compare-and-swap of 32 bit in RV64A.

Mon, Mar 11, 2:40 PM · Restricted Project

asb accepted D58829: Do a sign-extension in a compare-and-swap of 32 bit in RV64A.

Looks good to me. Thanks again for catching this issue, and of course for submitting the fix!

Mon, Mar 11, 2:36 PM · Restricted Project

asb committed rGb6d322bdc25e: [RISCV] Allow fp as an alias of s0 (authored by asb).

[RISCV] Allow fp as an alias of s0

Mon, Mar 11, 2:35 PM

asb committed rL355867: [RISCV] Allow fp as an alias of s0.

[RISCV] Allow fp as an alias of s0

Mon, Mar 11, 2:34 PM

asb closed D59209: Allow fp as an alias of s0.

Mon, Mar 11, 2:34 PM · Restricted Project

asb accepted D59209: Allow fp as an alias of s0.

Looks good to me, thanks!

Mon, Mar 11, 2:04 PM · Restricted Project

asb committed rG2c6c84e52c45: [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator() (authored by asb).

[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()

Mon, Mar 11, 1:43 PM

asb committed rL355864: [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator().

[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()

Mon, Mar 11, 1:42 PM

asb added a comment to D58829: Do a sign-extension in a compare-and-swap of 32 bit in RV64A.

Great catch - thank you!

Mon, Mar 11, 8:36 AM · Restricted Project

asb added a comment to D59209: Allow fp as an alias of s0.

Thanks, I'd missed the fp alias as I was going by the riscv-elf-psabi-doc primarily.

Mon, Mar 11, 8:17 AM · Restricted Project

Sat, Mar 9

asb committed rG62c8a57a7475: [RISCV][NFC] Minor refactoring of CC_RISCV (authored by asb).

[RISCV][NFC] Minor refactoring of CC_RISCV

Sat, Mar 9, 3:17 AM

asb committed rL355773: [RISCV][NFC] Minor refactoring of CC_RISCV.

[RISCV][NFC] Minor refactoring of CC_RISCV

Sat, Mar 9, 3:16 AM

asb committed rGbd0eff316a4c: [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserter (authored by asb).

[RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserter

Sat, Mar 9, 1:30 AM

asb committed rL355772: [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserter.

[RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserter

Sat, Mar 9, 1:29 AM

asb committed rGfea495717731: [RISCV] Support -target-abi at the MC layer and for codegen (authored by asb).

[RISCV] Support -target-abi at the MC layer and for codegen

Sat, Mar 9, 1:28 AM

asb committed rL355771: [RISCV] Support -target-abi at the MC layer and for codegen.

[RISCV] Support -target-abi at the MC layer and for codegen

Sat, Mar 9, 1:27 AM

asb closed D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Sat, Mar 9, 1:27 AM · Restricted Project

Fri, Mar 8

asb updated the diff for D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Add missed MC rv32ifd -target-abi=ilp32d test case.

Fri, Mar 8, 10:40 AM · Restricted Project

asb added inline comments to D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Fri, Mar 8, 10:35 AM · Restricted Project

asb updated the diff for D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Removed unnecessary use of Expected<T> that was missed in the last update.

Fri, Mar 8, 10:35 AM · Restricted Project

asb updated the diff for D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Updated to print a warning if an invalid ABI name is given, or if an ABI can't be selected for the current -march. Also add minimal support for recognising ilp32e, including setting the EF_RISCV_RVE ELF flag if -target-abi ilp32e is specified.

Fri, Mar 8, 4:22 AM · Restricted Project

Thu, Mar 7

asb accepted D58932: [RISCV] Allow access to FP CSRs without F extension.

LGTM, thanks!

Thu, Mar 7, 1:38 PM · Restricted Project

asb added a comment to D59096: [SelectionDAG][RISCV] Add a SELECT_PARTS SelectionDAG node.

In D59096#1421940, @efriedma wrote:

I'm not sure generating SELECT_PARTS in type legalization is the best approach. Instead of specifically considering the case of a SELECT whose result is split by legalization exactly once, you could more generally consider DAGs which, after type legalization, contain multiple SELECTs with the same condition.

The x86 backend actually has some code to try improve the lowering for this sort of construct after isel, in cases where there is no native cmov instruction; see X86TargetLowering::EmitLoweredSelect. As written, it's not completely reliable; it depends on the DAG scheduler to schedule the relevant nodes next to each other. Not suggesting that's the best approach, but maybe a useful reference point.

Thu, Mar 7, 12:30 PM · Restricted Project

asb requested changes to D58932: [RISCV] Allow access to FP CSRs without F extension.

The behaviour I'm seeing with a recent-ish GCC toolchain is that the floating points CSR names are accepted regardless of -march, but the pseudoinstructions (e.g. frcsr) require the F extension to be enabled.

Thu, Mar 7, 6:19 AM · Restricted Project

asb accepted D58943: [RISCV][MC] Find matching pcrel_hi fixup in more cases..

It took me a bit of time to go through the alternate patches and related discussion, but I've now reviewed and this seems like the most straight-forward solution and the right way to go. Many thanks Eli. LGTM.

Thu, Mar 7, 6:11 AM · Restricted Project

Wed, Mar 6

asb added a comment to D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

RV32E is intentionally left out of this patch as well. I feel it will be cleaner to add basic recognition of -target-abi=rv32e alongside basic support for the E extension (e.g. -march=risc32 -mattr=+e).

Wed, Mar 6, 6:27 AM · Restricted Project

asb created D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Wed, Mar 6, 6:23 AM · Restricted Project

Thu, Feb 21

asb committed rGdb67be889d5e: [RISCV][NFC] IsEligibleForTailCallOptimization ->… (authored by asb).

[RISCV][NFC] IsEligibleForTailCallOptimization ->…

Thu, Feb 21, 6:33 AM

asb committed rL354584: [RISCV][NFC] IsEligibleForTailCallOptimization ->….

[RISCV][NFC] IsEligibleForTailCallOptimization ->…

Thu, Feb 21, 6:33 AM

asb committed rG047170cfc3d6: [RISCV] Add implied zero offset load/store alias patterns (authored by asb).

[RISCV] Add implied zero offset load/store alias patterns

Thu, Feb 21, 6:10 AM

asb committed rL354581: [RISCV] Add implied zero offset load/store alias patterns.

[RISCV] Add implied zero offset load/store alias patterns

Thu, Feb 21, 6:09 AM

asb closed D57141: [RISCV] Add implied zero offset load/store alias patterns.

Thu, Feb 21, 6:09 AM · Restricted Project

asb added a comment to D57141: [RISCV] Add implied zero offset load/store alias patterns.

In D57141#1404697, @jrtc27 wrote:

D50496 in the stack has now landed, so other than the TODO comments having been dropped this is now ready. Alex, are you happy to do that rebasing when you commit this, or would you like me to?

Thu, Feb 21, 6:07 AM · Restricted Project

Feb 19 2019

asb committed rG6aae21610954: [RISCV][NFC] Move some std::string to StringRef (authored by asb).

[RISCV][NFC] Move some std::string to StringRef

Feb 19 2019, 6:43 AM

asb committed rL354333: [RISCV][NFC] Move some std::string to StringRef.

[RISCV][NFC] Move some std::string to StringRef

Feb 19 2019, 6:43 AM

asb committed rG1f0c1215aec1: [RISCV] Re-organise calling convention tests (authored by asb).

[RISCV] Re-organise calling convention tests

Feb 19 2019, 5:48 AM

asb committed rL354323: [RISCV] Re-organise calling convention tests.

[RISCV] Re-organise calling convention tests

Feb 19 2019, 5:46 AM

asb added a comment to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

In D57450#1402153, @rogfer01 wrote:

Looks sensible to me.

I'm just curious why we want to prevent emission of atomic LLVM instructions at this point. Won't LLVM's AtomicExpand perform a similar lowering already? Perhaps the goal is to save that pass some work?

Feb 19 2019, 4:14 AM · Restricted Project

Herald added a project to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics: Restricted Project.

Ping?

Feb 19 2019, 3:19 AM · Restricted Project

Feb 18 2019

asb added a reviewer for D57601: Seperate volatility and atomicity/ordering in SelectionDAG: jyknight.

It seems there's a clear plan on the path forwards - is it worth writing it up as a short RFC on the mailing list, particular given the potential for subtle issues for out-of-tree backends?

Feb 18 2019, 5:36 AM · Restricted Project

Feb 15 2019

asb added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

I believe the pre-requisite patches for this are now committed, so please go ahead and commit once you've addressed the minor nits in my previous review. Thanks!

Feb 15 2019, 1:56 AM · Restricted Project

asb committed rG22531c4a146c: [RISCV] Add assembler support for LA pseudo-instruction (authored by asb).

[RISCV] Add assembler support for LA pseudo-instruction

Feb 15 2019, 1:53 AM

asb committed rL354111: [RISCV] Add assembler support for LA pseudo-instruction.

[RISCV] Add assembler support for LA pseudo-instruction

Feb 15 2019, 1:53 AM

asb closed D55325: [RISCV] Add assembler support for LA pseudo-instruction.

Feb 15 2019, 1:53 AM · Restricted Project

asb committed rG8eb87e59a69c: [RISCV] Support assembling %got_pcrel_hi operator (authored by asb).

[RISCV] Support assembling %got_pcrel_hi operator

Feb 15 2019, 1:45 AM

asb committed rL354110: [RISCV] Support assembling %got_pcrel_hi operator.

[RISCV] Support assembling %got_pcrel_hi operator

Feb 15 2019, 1:45 AM

asb closed D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Feb 15 2019, 1:44 AM · Restricted Project

Feb 14 2019

asb updated subscribers of D47127: [RISCV] Default enable RISCV linker relaxation.

Removing llvm-commits and adding cfe-commits. This patch is mistakenly marked as targeting the LLVM repo rather than Clang.

Feb 14 2019, 7:34 AM · Restricted Project

asb accepted D47127: [RISCV] Default enable RISCV linker relaxation.

I think the backend part of this has seen plenty of testing and it would be worth merging this change. Thanks!

Feb 14 2019, 7:34 AM · Restricted Project

asb added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

In D55279#1394818, @asb wrote:

Thanks, this looks good to me (see small nit in comment). Do you need me to commit?

Feb 14 2019, 7:17 AM · Restricted Project

asb committed rG4efa0b674d70: [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test (authored by asb).

[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test

Feb 14 2019, 5:10 AM

asb committed rL354028: [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test.

[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test

Feb 14 2019, 5:10 AM

asb requested changes to D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V.

Did you check the behaviour of 'J' vs GCC, because for e.g. asm volatile ("sub a0, a0, %0" :: "J"(0)); I seem to see it using the integer 0 rather than the zero register?

Feb 14 2019, 5:07 AM · Restricted Project

asb accepted D57141: [RISCV] Add implied zero offset load/store alias patterns.

Thanks, this looks good to me. Needs a small fixup to apply cleanly to the previous patches in the queue (TODO comments in RISCVInstrInfo{F,D}.td were removed).

Feb 14 2019, 2:16 AM · Restricted Project

asb accepted D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

This looks good to me, thanks! Just a few minor comments inline.

Feb 14 2019, 2:07 AM · Restricted Project

Feb 12 2019

asb accepted D55325: [RISCV] Add assembler support for LA pseudo-instruction.

Looks good to me - thanks. I like the refactoring to introduce emitAuipcInstPair. Nit: a comment next to its declaration (along the lines of the comments for neighbouring helper declarations) would be useful.

Feb 12 2019, 8:13 AM · Restricted Project

asb accepted D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Thanks, this looks good to me (see small nit in comment). Do you need me to commit?

Feb 12 2019, 8:02 AM · Restricted Project

Jan 31 2019

asb committed rL352833: [RISCV] Implement RV64D codegen.

[RISCV] Implement RV64D codegen

Jan 31 2019, 7:53 PM

asb closed D53237: [RISCV] Implement RV64D codegen.

Jan 31 2019, 7:53 PM · Restricted Project

asb committed rL352832: [SelectionDAG] Support promotion of the FPOWI integer operand.

[SelectionDAG] Support promotion of the FPOWI integer operand

Jan 31 2019, 7:46 PM

asb closed D54574: [SelectionDAG] Support promotion of the FPOWI integer operand.

Jan 31 2019, 7:46 PM · Restricted Project

asb accepted D57556: Fix for -DBUILD_SHARED_LIBS=ON build after rL352803.

LGTM.

Jan 31 2019, 7:37 PM · Restricted Project

asb committed rL352807: [RISCV] Add RV64F codegen support.

[RISCV] Add RV64F codegen support

Jan 31 2019, 2:48 PM

asb closed D53235: [RISCV] Add RV64F codegen support.

Jan 31 2019, 2:48 PM

asb added inline comments to D53235: [RISCV] Add RV64F codegen support.

Jan 31 2019, 2:07 PM

asb updated the diff for D53235: [RISCV] Add RV64F codegen support.

Hi Eli. Thanks, as always, for the careful review. I've opted to introduce a SEXT_IN_REG in this case, and instead define a target-specific node that produces an anyext result (and a pattern that ensures FMV_X_W is selected for (sexti32 (riscv_fmv_x_anyextw_rv64 ..)). Otherwise there are cases where we end up with an unwanted sext.w in cases where redundant GPR->FPR->GPR moves have been eliminated.

Jan 31 2019, 9:54 AM

asb (Alex Bradbury)Director and Co-founder, lowRISC CIC

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Director and Co-founder, lowRISC CIC

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