asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (275 w, 6 d)

Recent Activity

Fri, Nov 16

asb requested changes to D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V.

Thanks for the patch Lewis. Could I please request the following changes:

  • It would be handy to link to https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html in the patch summary, so people can easily double-check the constraint definitions for themselves
  • Could you add tests for values outside of the expected range. AArch64 and X86 do this in test/Sema/inline-asm-validate-{aarch64,x86}.c
  • It would be worth expanding riscv-inline-asm.c to provide simple sanity checks for "m" and "r"
Fri, Nov 16, 2:59 AM
asb committed rL347043: [RISCV][NFC] Define and use the new CA instruction format.
[RISCV][NFC] Define and use the new CA instruction format
Fri, Nov 16, 2:36 AM
asb closed D54302: [RISCV] Define and use the new CA instruction format.
Fri, Nov 16, 2:36 AM
asb accepted D54302: [RISCV] Define and use the new CA instruction format.

This is an NFC patch and looks good to me.

Fri, Nov 16, 2:34 AM
asb committed rL347042: [RISCV] Constant materialisation for RV64I.
[RISCV] Constant materialisation for RV64I
Fri, Nov 16, 2:17 AM
asb closed D52962: [RISCV] Constant materialisation for RV64I.
Fri, Nov 16, 2:17 AM

Thu, Nov 15

asb committed rL346959: [RISCV] Mark C.EBREAK instruction as having side effects.
[RISCV] Mark C.EBREAK instruction as having side effects
Thu, Nov 15, 6:55 AM
asb closed D54256: [RISCV] Mark C.EBREAK instruction as having side effects.
Thu, Nov 15, 6:55 AM
asb accepted D54256: [RISCV] Mark C.EBREAK instruction as having side effects.

Looks good to me. This won't cause any codegen issues because C_EBREAK is never gets selected in ISel anyway (EBREAK will get converted after it becomes an MCInst). But it's better to have the right metadata.

Thu, Nov 15, 6:52 AM
asb committed rL346958: [RISCV] Mark FREM as Expand.
[RISCV] Mark FREM as Expand
Thu, Nov 15, 6:48 AM
This revision was not accepted when it landed; it landed in state Needs Review.
Thu, Nov 15, 6:48 AM
asb updated the diff for D53233: [RISCV] Add codegen support for 64-bit atomic load/store and atomicrmw.

Refreshing patch, no changes.

Thu, Nov 15, 6:28 AM
asb added a dependency for D53237: [RISCV] Implement RV64D codegen: D54574: [SelectionDAG] Support promotion of the FPOWI integer operand.
Thu, Nov 15, 4:02 AM
asb added a dependent revision for D54574: [SelectionDAG] Support promotion of the FPOWI integer operand: D53237: [RISCV] Implement RV64D codegen.
Thu, Nov 15, 4:02 AM
asb updated the diff for D53237: [RISCV] Implement RV64D codegen.

Update to fix a typo in a comment and reflect changes in double-intrinsics.ll (which now exhaustively checks double intrinsics).

Thu, Nov 15, 4:02 AM
asb added a dependent revision for D53235: [RISCV] Add RV64F codegen support: D54574: [SelectionDAG] Support promotion of the FPOWI integer operand.
Thu, Nov 15, 4:00 AM
asb added a dependency for D54574: [SelectionDAG] Support promotion of the FPOWI integer operand: D53235: [RISCV] Add RV64F codegen support.
Thu, Nov 15, 4:00 AM
asb created D54574: [SelectionDAG] Support promotion of the FPOWI integer operand.
Thu, Nov 15, 4:00 AM
asb updated the diff for D53235: [RISCV] Add RV64F codegen support.

Refresh patch and fix typo in comment. This patch does not update float-intrinsics.ll as new promotion code needs to be added for FPOWI. I will post a patch to do this now.

Thu, Nov 15, 3:56 AM
asb updated the diff for D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.

Patch refresh, no functional changes.

Thu, Nov 15, 3:52 AM
asb updated the diff for D53281: [SelectionDAG] Support promotion of PREFETCH operands.

Refresh patch and use ZExtPromotedInteger.

Thu, Nov 15, 2:42 AM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D53281: [SelectionDAG] Support promotion of PREFETCH operands.
Thu, Nov 15, 2:38 AM
asb added a dependency for D53281: [SelectionDAG] Support promotion of PREFETCH operands: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Thu, Nov 15, 2:38 AM
asb updated the diff for D53279: [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands.

Updated to apply cleanly without fuzz and to use ZExtPromotedInteger as suggested by Eli.

Thu, Nov 15, 2:36 AM
asb updated the diff for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

Refreshing patch so it applies without fuzz. No functional changes.

Thu, Nov 15, 2:25 AM
asb added a comment to D52962: [RISCV] Constant materialisation for RV64I.

Confirming this patch still applies cleanly against current LLVM HEAD. Ping?

Thu, Nov 15, 2:21 AM
asb committed rL346937: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.
[RISCV] Introduce the RISCVMatInt::generateInstSeq helper
Thu, Nov 15, 2:14 AM
asb closed D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.
Thu, Nov 15, 2:14 AM

Tue, Nov 13

asb added inline comments to D46424: [RISCV] Support .option push and .option pop.
Tue, Nov 13, 8:15 AM
asb added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Tue, Nov 13, 5:10 AM

Mon, Nov 12

asb added a comment to D45960: [MC] Add MCSubtargetInfo to MCPaddingFragment [NFC].

Ah - I was waiting for this to be committed before returning to review the rest!

Mon, Nov 12, 7:42 AM
asb added a comment to D50141: Add errors for tiny codemodel on targets other than AArch64.

This seems a positive improvement and I don't want to bikeshed it too much, but it does feel a bit arbitrary to reject tiny and kernel codemodels in getEffectiveCodeModel. You could imagine having a virtual isSupportedCodeModel. Might be more hassle than it's worth though...

Mon, Nov 12, 7:08 AM
asb added a comment to D45960: [MC] Add MCSubtargetInfo to MCPaddingFragment [NFC].

Just a ping on landing this. Are you awaiting additional reviews?

Mon, Nov 12, 6:55 AM
asb added a comment to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.

I've re-checked this patch still applies cleanly against current HEAD.

Mon, Nov 12, 6:47 AM
asb requested changes to D54159: [RISCV] Mark FREM as Expand.

Could you please a double-frem.ll test as well?

Mon, Nov 12, 6:43 AM
asb added a comment to D46424: [RISCV] Support .option push and .option pop.

Thanks Lewis, this looks good to me - just a couple of very minor requested tweaks noted inline.

Mon, Nov 12, 6:40 AM
asb committed rL346655: [RISCV] Support .option relax and .option norelax.
[RISCV] Support .option relax and .option norelax
Mon, Nov 12, 6:27 AM
asb closed D46423: [RISCV] Support .option relax and .option norelax.
Mon, Nov 12, 6:27 AM

Fri, Nov 9

asb committed rL346497: [RISCV] Avoid unnecessary XOR for seteq/setne 0.
[RISCV] Avoid unnecessary XOR for seteq/setne 0
Fri, Nov 9, 6:50 AM
asb closed D53492: [RISCV] Avoid unnecessary XOR for seteq/setne 0.
Fri, Nov 9, 6:50 AM
asb accepted D53492: [RISCV] Avoid unnecessary XOR for seteq/setne 0.

Looks good to me, thanks!

Fri, Nov 9, 6:48 AM
asb committed rL346496: [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432.
[RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
Fri, Nov 9, 6:38 AM

Wed, Nov 7

asb added a comment to D53492: [RISCV] Avoid unnecessary XOR for seteq/setne 0.

Great catch, thanks. I know there's good test coverage for by virtue of it being a common pattern, but could you please add a more targeted unit test to e.g. test/CodeGen/RISCV/i32-icmp.ll? Otherwise, looks good to me.

Wed, Nov 7, 9:03 AM

Fri, Nov 2

asb committed rL346034: [RISCV] Add some missing expansions for floating-point intrinsics.
[RISCV] Add some missing expansions for floating-point intrinsics
Fri, Nov 2, 12:53 PM
asb closed D54034: [RISCV] Add expansions for floating-point intrinsics.
Fri, Nov 2, 12:52 PM
asb accepted D54034: [RISCV] Add expansions for floating-point intrinsics.

Thanks Luis, this looks good to me. Just a minor nitpick re OP -> Op.

Fri, Nov 2, 8:16 AM

Thu, Oct 25

asb updated the diff for D53237: [RISCV] Implement RV64D codegen.

Rebase and improve testing for double<->int conversion.

Thu, Oct 25, 6:46 AM
asb updated the diff for D53235: [RISCV] Add RV64F codegen support.

Updated to use target DAG combines for the int/float conversions.

Thu, Oct 25, 6:42 AM
asb updated the diff for D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.

Updated to:

  • Add missing remw/remuw patterns
  • Add exhaustive testing of the *W patterns introduced inrv64m
  • Add and make use of sexti32 PatFrags
Thu, Oct 25, 6:16 AM
asb updated the diff for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

Updated to fix a PatFrags-related assertion and to add exhaustive testing for the *W instruction patterns. Although verbose, these tests have shown their worth by 1) identifying a missing pattern which I've now added and 2) flagging a few cases where codegen could be improved in future.

Thu, Oct 25, 6:02 AM
asb committed rL345262: [RISCV] Use PatFrags for variable shift patterns.
[RISCV] Use PatFrags for variable shift patterns
Thu, Oct 25, 5:47 AM

Mon, Oct 22

asb added a comment to D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.

Thanks Shiva. I'm updating the patch series in a way that adds much more exhaustive testing for the *W patterns and fleshes out patterns for cases like this. I mused on the RV64I patch review thread whether there was something smarter to do here - maybe some canonicalisation. But regardless of that, it's helpful to have more exhaustive tests.

Mon, Oct 22, 2:11 AM
asb planned changes to D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

I have a number of changes implemented while I was travelling, and will update this patch series.

Mon, Oct 22, 1:21 AM

Oct 18 2018

asb added inline comments to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.
Oct 18 2018, 9:51 AM

Oct 15 2018

asb added a comment to D53291: add riscv32e to the llvm.

Hi Daliang and welcome to the LLVM community.

Oct 15 2018, 8:11 PM
asb planned changes to D53235: [RISCV] Add RV64F codegen support.

The presence of no-op any_extend can cause assertions during the DAG combiner, and there's no guarantee that the no-op any_extend will be visited first. I'll update this to avoid the issue, probably setting a target combiner for any_extend to legalise any_extend + bitcast directly to BitcastAndSextF32ToI64.

Oct 15 2018, 7:23 AM
asb created D53281: [SelectionDAG] Support promotion of PREFETCH operands.
Oct 15 2018, 4:02 AM
asb added a dependency for D53279: [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 15 2018, 3:42 AM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D53279: [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands.
Oct 15 2018, 3:42 AM
asb created D53279: [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands.
Oct 15 2018, 3:41 AM
asb added a comment to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.
In D52961#1258464, @asb wrote:

No real reason to prefer one or the other when they're semantically identical. It's mostly to be closer to gas/gcc which uses addi at least for the isInt<12> case.

I see. makes sense. I just checked gcc and it seems to be favoring addi for that case.

Oct 15 2018, 3:37 AM

Oct 12 2018

asb added a dependent revision for D53235: [RISCV] Add RV64F codegen support: D53237: [RISCV] Implement RV64D codegen.
Oct 12 2018, 6:43 PM
asb added a dependency for D53237: [RISCV] Implement RV64D codegen: D53235: [RISCV] Add RV64F codegen support.
Oct 12 2018, 6:43 PM
asb created D53237: [RISCV] Implement RV64D codegen.
Oct 12 2018, 6:42 PM
asb added a dependency for D53233: [RISCV] Add codegen support for 64-bit atomic load/store and atomicrmw: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 12 2018, 6:30 PM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D53233: [RISCV] Add codegen support for 64-bit atomic load/store and atomicrmw.
Oct 12 2018, 6:30 PM
asb added a dependency for D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 12 2018, 6:29 PM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.
Oct 12 2018, 6:29 PM
asb added a dependency for D53235: [RISCV] Add RV64F codegen support: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 12 2018, 6:28 PM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D53235: [RISCV] Add RV64F codegen support.
Oct 12 2018, 6:28 PM
asb created D53235: [RISCV] Add RV64F codegen support.
Oct 12 2018, 6:27 PM
asb created D53233: [RISCV] Add codegen support for 64-bit atomic load/store and atomicrmw.
Oct 12 2018, 5:38 PM
asb updated the diff for D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.

Fixed out of date comment (thanks @niosHD).

Oct 12 2018, 5:10 PM
asb created D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions.
Oct 12 2018, 5:08 PM
asb added a dependency for D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 12 2018, 4:41 PM
asb added a dependent revision for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V.
Oct 12 2018, 4:41 PM
asb updated the diff for D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V.

Update to address review comments (thanks!).

Oct 12 2018, 4:41 PM
asb added a dependent revision for D52962: [RISCV] Constant materialisation for RV64I: D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 12 2018, 4:37 PM
asb added a dependency for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I: D52962: [RISCV] Constant materialisation for RV64I.
Oct 12 2018, 4:37 PM
asb updated the diff for D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

Update to add zexti32 PatFrag and to eliminate unnecessary masking of shift amount values.

Oct 12 2018, 4:28 PM
asb committed rL344432: [RISCV] Eliminate unnecessary masking of promoted shift amounts.
[RISCV] Eliminate unnecessary masking of promoted shift amounts
Oct 12 2018, 4:21 PM
asb closed D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts.
Oct 12 2018, 4:20 PM
asb updated the diff for D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts.

Updating patch with additional test. Thanks for the review @efriedma.

Oct 12 2018, 4:19 PM
asb added a comment to D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts.

Yes, I'll add the appropraite SLLW/SRAW/SRLW patterns in the RV64I codegen patch. Given this improvement isn't specific to RV64I, I wrote this patch to apply against current HEAD.

Oct 12 2018, 4:19 PM
asb abandoned D52975: [TargetLowering][RISCV] Introduce getExtendForShiftAmount and implement for RISC-V.

Thanks for the feedback @efriedma, I've posted a patch that tackles this at instruction selection time: D53224.

Oct 12 2018, 3:39 PM
asb created D53224: [RISCV] Eliminate unnecessary masking of promoted shift amounts.
Oct 12 2018, 3:36 PM

Oct 11 2018

asb updated the diff for D52962: [RISCV] Constant materialisation for RV64I.

Updated patch to add a TODO to indicate that it may sometimes be preferable to load from the constant pool. As Bruce points out, this isn't always a clear win.

Oct 11 2018, 6:24 AM
asb added a comment to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.

The other motivation is that many of our codegen tests are going to include both RV32 and RV64 check lines. It's distracting to see addiw for materialising constants when it's not necessary, and it represents an unnecessary diff vs the equivalent RV32 code.

Oct 11 2018, 5:52 AM
asb updated the diff for D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.

Rebased patch. No changes, but I had to re-generate the new atomic-cmpxchg.ll lines as regalloc is slightly different after the recent enableMultipleCopyHints change.

Oct 11 2018, 4:51 AM
asb added a comment to D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Hi Ana, just some minor comments. With tweaks along the suggested lines, this looks good to me.

Oct 11 2018, 4:34 AM
asb updated subscribers of D46423: [RISCV] Support .option relax and .option norelax.

Shiva and Kito didn't seem to have any concerns so I was just re-checking prior to committing. I had a closer look at getAssemblerPtr and see this method was introduced by @niravd in rL331218. Nirav - are you happy for this patch to change getAssemblerPtr so it doesn't just return nullptr in MCStreamer.h? I don't think gating on UseAssemblerInfoForParsing makes sense in our case.

Oct 11 2018, 4:24 AM
asb committed rL344238: [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142.
[RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142
Oct 11 2018, 4:13 AM

Oct 9 2018

asb added a comment to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.

I'm trying to keep things separate where possible, but yes we will want getIntImmCost and as you point out it's likely to be more useful for RV64. Ideally it would recognise that compressible code sequences are cheaper than non-compressible sequences.

Oct 9 2018, 3:57 AM

Oct 8 2018

asb added a comment to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.

The helper makes it clear to follow. Thanks!

I am just not sure why you did the change to prefer add to addiw when for 64bit? is addi faster than addiw?

Oct 8 2018, 7:06 PM
asb added a comment to D52975: [TargetLowering][RISCV] Introduce getExtendForShiftAmount and implement for RISC-V.

Thanks for the review, I was hoping there was an opportunity here to avoid the need for backend-specific peepholes. I'll handle in the backend instead. For my own edification, what do you mean by the shift amount being too large to undef?

Oct 8 2018, 6:25 PM
asb added a comment to D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

There's one aspect I'd appreciate some input on. Full coverage of sext/zext/aext inputs and sext/aext outputs would require a lot of repetitive tests. But these tests would have value. e.g. to generate srlw for the following two functions:

Oct 8 2018, 7:56 AM
asb updated the diff for D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V.

Update to attache the correct diff this time.

Oct 8 2018, 3:35 AM
asb created D52978: [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V.
Oct 8 2018, 3:35 AM
asb created D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.
Oct 8 2018, 3:12 AM
asb committed rL343958: [RISCV] Update alu8.ll and alu16.ll test cases.
[RISCV] Update alu8.ll and alu16.ll test cases
Oct 8 2018, 2:11 AM