asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (258 w, 2 d)

Recent Activity

Today

asb added a comment to D49521: WIP Implemented asm proto fuzzer with a sample grammar.

Hi Jocelyn and welcome to the LLVM community. I'm really excited about this approach to testing the assembler. I've just got a few comments for now.

Thu, Jul 19, 7:34 AM
asb accepted D48412: [RISCV] Add support for interrupt attribute.

This looks good to me with two caveats

Thu, Jul 19, 6:58 AM
asb added a comment to D48411: [RISCV] Add support for _interrupt attribute.

This is looking good to me, I've added some comments. The logic around callee/caller save registers is a little confusing but the way you're handling it seems sensible. A comment clarifying things in determineCalleeSaves would be really useful I think.

Thu, Jul 19, 6:31 AM
asb added a comment to D49539: [mips] Replace custom parsing logic for data directives by the `addAliasForDirective`.

Could you add a test that shows .4byte and .long are now correctly handled too? e.g. by extending micromips-label-test.s

Thu, Jul 19, 5:19 AM

Thu, Jul 12

asb added inline comments to D48411: [RISCV] Add support for _interrupt attribute.
Thu, Jul 12, 7:44 AM

Mon, Jul 9

asb added a reviewer for D48602: `llvm.experimental.stackmap` is erroneously marked `Throws`?: reames.

Adding Philip Reames as a reviewer, who kindly offered on Twitter to take a look at this.

Mon, Jul 9, 8:52 AM

Wed, Jul 4

asb abandoned D47001: [Mips] Use addAliasForDirective rather than custom parsing logic for data directives.

Sure, but it does sound like the handling of .4byte, .long may incorrectly set STO_MIPS_MICROMIPS in the current implementation so perhaps there's a bug to be filed.

Wed, Jul 4, 7:45 AM

Mon, Jul 2

asb added a comment to D48411: [RISCV] Add support for _interrupt attribute.

Thanks Ana. I've added some initial review comments. Sorry for the slight delay, I've been on vacation the past week.

Mon, Jul 2, 7:42 AM
asb committed rL336107: [X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104.
[X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104
Mon, Jul 2, 7:18 AM
asb committed rL336104: [X86] Use addAliasForDirective to support the .word directive (reland).
[X86] Use addAliasForDirective to support the .word directive (reland)
Mon, Jul 2, 6:54 AM
asb committed rL336103: Revert r336100.
Revert r336100
Mon, Jul 2, 6:48 AM
asb added a comment to D47004: [X86] Use addAliasForDirective to support the .word directive.

Thanks for the review and sorry for the delay in committing. Committed in rL336100.

Mon, Jul 2, 6:42 AM
asb committed rL336100: [X86] Use addAliasForDirective to support the .word directive.
[X86] Use addAliasForDirective to support the .word directive
Mon, Jul 2, 6:42 AM
asb closed D47004: [X86] Use addAliasForDirective to support the .word directive.
Mon, Jul 2, 6:42 AM

Thu, Jun 21

asb updated subscribers of D46759: WIP [RISCV] Supporting aliases for Machine level CSRs..

Hi Ana, if you're planning on updating it would probably be worth following the work on a replacement for SearchableTable:

Thu, Jun 21, 8:20 AM
asb created D48430: [RISCV] Add support for lowering jumptables.
Thu, Jun 21, 7:02 AM
asb added a comment to D48414: [RISCV] Fix test/CodeGen/RISCV/indirectbr.ll after D48202.

This was fixed in rL335202. In general, do feel free to direct commit minor test or build fixes without pre-commit review.

Thu, Jun 21, 1:39 AM

Wed, Jun 20

asb added inline comments to D47857: [RISCV] Add machine function pass to merge base + offset.
Wed, Jun 20, 1:31 PM
asb committed rL335154: [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w.
[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w
Wed, Jun 20, 11:47 AM
asb committed rL335127: [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}.
[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}
Wed, Jun 20, 7:07 AM
asb committed rL335120: [RISCV] Add InstAlias definitions for sgt and sgtu.
[RISCV] Add InstAlias definitions for sgt and sgtu
Wed, Jun 20, 5:58 AM
asb accepted D48343: [RISCV] Tail calls don't need to save return address.

Looks good to me, thanks!

Wed, Jun 20, 3:58 AM

Jun 14 2018

asb added a comment to D47755: [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for alignment when linker relaxation enabled.

Hi Shiva. I think your tests need to demonstrate the behaviour when there is no C extension support as well.

Jun 14 2018, 7:05 AM
asb accepted D47926: [RISCV] Add tests for overflow intrinsics.

Thanks! Looks good to me, but two minor suggestions:

  • arith-with-overflow.ll might be a better name
  • Add the nounwind attribute to the function definitions, so we still get clean assembly output when cfi directives are emitted.
Jun 14 2018, 6:58 AM
asb accepted D45959: [MC] Move bundling and MCSubtargetInfo to MCEncodedFragment [NFC].

This looks good to me (in that the motivation makes sense and the change seems to implement the desired change). Only caveat is that I'm not familiar with the code paths for bundled instructions.

Jun 14 2018, 6:47 AM
asb added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32I.
Jun 14 2018, 6:12 AM
asb accepted D47857: [RISCV] Add machine function pass to merge base + offset.

Thanks, this looks good to me assuming the minor nits are addressed. The only one requiring code changes is the for loop in matchLargeOffset.

Jun 14 2018, 1:41 AM

Jun 13 2018

asb added inline comments to D47857: [RISCV] Add machine function pass to merge base + offset.
Jun 13 2018, 5:09 PM
asb added a comment to D47857: [RISCV] Add machine function pass to merge base + offset.

Thanks, I'll have to finish stepping through the code tomorrow but this seems to be working great. For the GCC torture suite at O1, ~40 of the test cases see improved codegen (fewer instructions). Two gain a single instruction, but that's just noise due to slight regalloc differences.

Jun 13 2018, 5:09 PM
asb updated the summary of D48130: [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR.
Jun 13 2018, 8:47 AM
asb updated the summary of D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.
Jun 13 2018, 8:46 AM
asb added a dependent revision for D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A: D48131: [RISCV] Implement codegen for cmpxchg on RV32I.
Jun 13 2018, 8:24 AM
asb added a dependent revision for D48130: [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR: D48131: [RISCV] Implement codegen for cmpxchg on RV32I.
Jun 13 2018, 8:24 AM
asb created D48131: [RISCV] Implement codegen for cmpxchg on RV32I.
Jun 13 2018, 8:24 AM
asb added dependencies for D48131: [RISCV] Implement codegen for cmpxchg on RV32I: D48130: [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR, D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A.
Jun 13 2018, 8:24 AM
asb created D48130: [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR.
Jun 13 2018, 8:18 AM
asb added a dependent revision for D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A: D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A.
Jun 13 2018, 8:13 AM
asb added a dependency for D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A: D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.
Jun 13 2018, 8:13 AM
asb created D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A.
Jun 13 2018, 8:13 AM
asb updated the diff for D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.

Updates:

  • Expand masked AMOs to IR for address calculation and masking + an intrinsic for the core LL/SC loop. Introduce a new hook in TargetLowering to allow this
  • Support for part-word atomicrmw max/min/umax/umin
  • Use MaskedMerge rather than calculating an inverse mask
  • Expand atomicrmw sub i32 to (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr)) with appropriate AQ/RL bits
Jun 13 2018, 8:08 AM
asb committed rL334591: [RISCV] Add codegen support for atomic load/stores with RV32A.
[RISCV] Add codegen support for atomic load/stores with RV32A
Jun 13 2018, 5:09 AM
asb closed D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
Jun 13 2018, 5:09 AM
asb committed rL334590: [RISCV] Codegen support for atomic operations on RV32I.
[RISCV] Codegen support for atomic operations on RV32I
Jun 13 2018, 5:03 AM
asb closed D47587: [RISCV] Codegen support for atomic operations on RV32I.
Jun 13 2018, 5:03 AM
asb added inline comments to D47587: [RISCV] Codegen support for atomic operations on RV32I.
Jun 13 2018, 4:58 AM
asb updated the diff for D47587: [RISCV] Codegen support for atomic operations on RV32I.

Update to add atomicrmw max/min/umax/umin to tests.

Jun 13 2018, 4:55 AM

Jun 8 2018

asb added inline comments to D31287: [mips] Fix atomic operations at O0, v3.
Jun 8 2018, 5:32 AM
asb added a comment to D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.

The problem with min and max is that you must not have a branch within the ll/sc loop. But, they can be done branchless with not too many instructions, so ISTM we should just implement them that way.

I think the following will work -- it computes b ^ ((a^b) & -(a < b)). The & -(a < b) either returns the LHS (if comparison is true) or returns 0 (if comparison is false), so you either get b^a^b, or b.

Jun 8 2018, 5:29 AM
asb updated the diff for D47587: [RISCV] Codegen support for atomic operations on RV32I.

Update to use fence.tso for fence acq_rel.

Jun 8 2018, 3:55 AM
asb committed rL334278: [RISCV] Implement MC layer support for the fence.tso instruction.
[RISCV] Implement MC layer support for the fence.tso instruction
Jun 8 2018, 3:43 AM

Jun 7 2018

asb added a comment to D47587: [RISCV] Codegen support for atomic operations on RV32I.
In D47587#1125518, @asb wrote:

Thanks for querying. I actually had been referring to an earlier draft. But even with the current draft I'm concerned that v2.0 of the ISA manual didn't specify that instr[31:28] should be ignored, meaning fence.tso may simply trap on some implementations. I'll query if anyone is tracking this behaviour across available RISC-V IP cores.

Jun 7 2018, 1:05 PM
asb added a comment to D47587: [RISCV] Codegen support for atomic operations on RV32I.

fence.tso is in the draft spec you linked to -- are you not using it because it hasn't been finalized, or was it just added after you left that comment?

Jun 7 2018, 12:49 PM
asb added a comment to D47004: [X86] Use addAliasForDirective to support the .word directive.

Ping?

Jun 7 2018, 9:04 AM
asb committed rL334203: [RISCV] AsmParser support for the li pseudo instruction.
[RISCV] AsmParser support for the li pseudo instruction
Jun 7 2018, 8:40 AM
asb closed D46118: [RISCV] AsmParser support for the li pseudo instruction.
Jun 7 2018, 8:40 AM
asb accepted D46118: [RISCV] AsmParser support for the li pseudo instruction.

Looks good to me. Many thanks for your work on this - I'm committing now.

Jun 7 2018, 8:39 AM
asb committed rL334202: [AVR] Fix build after r334078.
[AVR] Fix build after r334078
Jun 7 2018, 8:33 AM
asb added inline comments to D47587: [RISCV] Codegen support for atomic operations on RV32I.
Jun 7 2018, 8:31 AM
asb added a dependency for D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A: D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
Jun 7 2018, 7:22 AM
asb added a dependent revision for D47589: [RISCV] Add codegen support for atomic load/stores with RV32A: D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.
Jun 7 2018, 7:22 AM
asb removed a reviewer for D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A: javed.absar.
Jun 7 2018, 7:18 AM
asb created D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.
Jun 7 2018, 7:17 AM
asb updated the diff for D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.

This patch now enables lowering of 8, 16, and 32-bit atomic load/stores. We no longer rely on D47553, as the follow-up patch to lower atomicrmw supports partword and native size atomics.

Jun 7 2018, 7:06 AM
asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

Thank you everyone for your comments. I've removed the dependency on this patch from my queue of patches, and instead implement 8/16/32-bit atomics in one go.

Jun 7 2018, 7:03 AM
asb removed a dependency for D47589: [RISCV] Add codegen support for atomic load/stores with RV32A: D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.
Jun 7 2018, 7:03 AM
asb removed a dependent revision for D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass: D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
Jun 7 2018, 7:03 AM
asb updated the diff for D47587: [RISCV] Codegen support for atomic operations on RV32I.

Update to address all outstanding review comments.

Jun 7 2018, 7:02 AM

Jun 1 2018

asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

MachineOutliner doesn't do anything unless target-specific hooks say a transform is safe; it should be possible to guard against the possibility of outlining an ll/sc pair.

Jun 1 2018, 1:13 PM
asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

If you haven't seen it, you might want to read the thread I started a while ago, http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html discussing how AtomicExpandPass's feature of generating LL/SC loops at the IR level is a bad idea, and we need a better mechanism in order for it to generate actually-correct code. (We really ought to not expose ll and sc primitives to the IR level at all, because it's impossible to use them correctly).

That fundamental issue hasn't actually been resolved yet -- the current behavior seems to "work well enough" usually. But, I don't know whether the RISCV hardware requires strict adherence to its spec of max 16 base-ISA instructions, except loads, stores, or taken-branches. If so, the generic code in AtomicExpandPass cannot make that guarantee.

Jun 1 2018, 10:06 AM

May 31 2018

asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

But even if they are lock-free, it still requires linking to the shared library libatomic; we don't want to impose that requirement on users if it isn't necessary.

May 31 2018, 1:04 PM
asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.
In D47553#1117786, @jfb wrote:
In D47553#1117763, @asb wrote:

I could understand an argument that use-case 1) isn't compelling enough to add this new hook, and determining whether use-case 2) makes sense is dependent on the conclusion of the GCC bug 86005 discussion. Thanks @jyknight for sharing your thoughts in that GCC thread - much appreciated.

I think you want the ll/sc code for smaller atomics, it's an assumption on many platforms that you have lock-free 8 / 16. / 32 bit atomics, and often double-pointer-wide atomics too. I don't think your libcalls will generally be lock-free. I'd be worried if, even for bringup, your platform at one point in time didn't have that property, because then it sets a precedent for people saying "oh but this one time RISCV didn't do *blah*" and then we'll have endless debates about silly platforms. Please avoid me the debates 😉

May 31 2018, 12:45 PM
asb added a reviewer for D47004: [X86] Use addAliasForDirective to support the .word directive: RKSimon.

Ping?

May 31 2018, 12:14 PM
asb updated subscribers of D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
In D47589#1117978, @asb wrote:
In D47589#1117778, @jfb wrote:

When the A extension is supported, __atomic libcalls will be generated for any atomic that isn't the native word size or has less than natural alignment.

When do you expect non-natural alignment to occur? Is this purely for C++ support? If so you're guaranteed natural alignment. Otherwise (for intrinsics or for other languages) I'd like to understand what you expect, and whether you have the guarantee that the alignment information you have is correct. Without knowing that it's absolutely correct you're going to codegen bad code (a libcall in one place, and instructions in another).

That comment simply reflects the status quo for behaviour of AtomicExpandPass, that I replicated. Do you think it would be worth doing report_fatal_error if Align < Size?

May 31 2018, 12:13 PM
asb added a comment to D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
In D47589#1117778, @jfb wrote:

When the A extension is supported, __atomic libcalls will be generated for any atomic that isn't the native word size or has less than natural alignment.

When do you expect non-natural alignment to occur? Is this purely for C++ support? If so you're guaranteed natural alignment. Otherwise (for intrinsics or for other languages) I'd like to understand what you expect, and whether you have the guarantee that the alignment information you have is correct. Without knowing that it's absolutely correct you're going to codegen bad code (a libcall in one place, and instructions in another).

May 31 2018, 11:55 AM
asb updated the diff for D47587: [RISCV] Codegen support for atomic operations on RV32I.

Update to address comments from @jfb (thanks!).

May 31 2018, 11:49 AM
asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

On other architectures which have 32-bit atomics, but not 8 and 16-bit atomics, it's generally possible to lower smaller operations using a 32-bit cmpxchg loop. Does that not work on RISCV for some reason?

May 31 2018, 8:25 AM
asb accepted D45773: [RISCV] Don't fold symbol diff.

Thanks Ed, looks good to me.

May 31 2018, 7:35 AM
asb added dependencies for D47589: [RISCV] Add codegen support for atomic load/stores with RV32A: D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass, D47587: [RISCV] Codegen support for atomic operations on RV32I.
May 31 2018, 7:00 AM
asb added a dependent revision for D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass: D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
May 31 2018, 7:00 AM
asb added a dependent revision for D47587: [RISCV] Codegen support for atomic operations on RV32I: D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
May 31 2018, 7:00 AM
asb created D47589: [RISCV] Add codegen support for atomic load/stores with RV32A.
May 31 2018, 6:59 AM
asb updated the diff for D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

Updated patch to document that shouldExpandAtomicToLibCall should return the same result for objects of the same size.

May 31 2018, 6:54 AM
asb updated subscribers of D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

I'm going to un-abandon this patch. This hook is still helpful in order to e.g. lower to __atomic libcalls for all 8 and 16-bit operations but not 32-bit. This seems acceptable based on the linked GCC and LLVM docs, but isn't possible with the current MaxSizeInBitsSupported. Am I missing any problems with that strategy?

May 31 2018, 6:52 AM
asb updated the summary of D47587: [RISCV] Codegen support for atomic operations on RV32I.
May 31 2018, 6:46 AM
asb created D47587: [RISCV] Codegen support for atomic operations on RV32I.
May 31 2018, 6:44 AM

May 30 2018

Herald added a reviewer for D18201: Switch over targets to use AtomicExpandPass, and clean up target atomics code.: javed.absar.

Are there any plans to push this forwards?

May 30 2018, 8:48 PM
asb abandoned D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

Thanks Eli and JF for the rapid feedback. I was too quick to try to replicate GCC behaviour without running sanity checking its output.

May 30 2018, 2:22 PM
asb added a comment to D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.

Thanks Eli, I actually just came to the same conclusion when taking a step back and thinking about it some more. I was caught up on matching RISC-V GCC behaviour in this case, when in fact it seems RISC-V GCC is broken here. The LLVM docs on atomics also do document this requirement https://llvm.org/docs/Atomics.html#atomics-and-codegen. The 'blunt instrument' of MaxSizeInBitsSupported is acting as designed.

May 30 2018, 1:33 PM
asb created D47553: Add TargetLowering::shouldExpandAtomicToLibCall and query it from AtomicExpandPass.
May 30 2018, 1:08 PM

May 29 2018

asb accepted D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.

Thanks, looks good to me. Probably worth retitling the commit to e.g. "[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table"

May 29 2018, 12:12 PM
asb added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

Ok, there _is_ a problem using addi rather than addiw. Consider loading the immediate 0x7fffffff.

May 29 2018, 5:23 AM

May 28 2018

asb accepted D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.

Looks good to me, thanks!

May 28 2018, 6:33 AM
asb added inline comments to D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.
May 28 2018, 5:03 AM
asb added inline comments to D47126: [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table.
May 28 2018, 4:38 AM

May 24 2018

asb added a comment to D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
In D44888#1109361, @asb wrote:

This is looking good to me, just needs an update to address this request for a test in riscv-features.c that demonstrates the default +relax/-relax setting.

Hi Alex. I added the testing line on D47127 which is the patch we turn on relaxation as default. Do you think it's ok?

May 24 2018, 11:24 PM
asb added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.

Yes. Are we still OK with committing this patch as is? I plan to add a test case that shows the peephole's in ability to handle a GlobalAddress uses at multiple blocks then commit this patch.

After that I'll look into doing all of this in a Machine Function Pass to handle all the corner cases. If it looks good we can revert this patch and keep the pass.

Does that sound like a good plan?

May 24 2018, 11:21 PM
asb added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1110644, @asb wrote:

I'm happy to land this patch as-is. It generates good code in a wide variety of cases (more so than many other backends). But please add the above example to your test file with a note about the missed optimisation opportunity.

The example is actually already added to the test (define dso_local i32 @load_half() nounwind).

May 24 2018, 12:25 PM
asb added a reviewer for D46850: [DebugInfo] Generate fixups as emitting DWARF .debug_line.: echristo.

@echristo: Do you think you might be able to help review this?

May 24 2018, 12:14 PM
asb added a comment to D46423: [WIP, RISCV] Support .option relax and .option norelax.

I'd still err towards .option norelax meaning "do what I say". If a user freely intermixes .option relax and .option norelax within a section then there's a whole bunch of things that might break. Simply ignoring the norelax doesn't seem right, and picking out particular cases (e.g. symbol diffs) where we'll act as if relaxation was enabled also seems a bit dodgy. I still think that erroring might be safest and simplest path.

May 24 2018, 6:37 AM
asb added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

By way of update: the only thing stopping me from committing this right now is convincing myself that there's never a reason to use addiw rather than addi for the first constant when expanding li for RV64. I'm just going to step through some more examples...

May 24 2018, 3:21 AM