asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (237 w, 4 d)

Recent Activity

Thu, Feb 22

asb added inline comments to D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag.
Thu, Feb 22, 4:09 PM
asb accepted D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag.

I've added two suggestions on further tweaking the tests which I think it would be worth adopting. Looks good to me.

Thu, Feb 22, 3:06 PM
asb added a comment to D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag.

As @efriedma noted in D43106, it would be good to have some test coverage for ABI lowering. I'd suggest updating test/Driver/riscv32-abi.c with something like:

Thu, Feb 22, 6:09 AM
asb added a comment to D43106: [RISCV] Enable -fforce-enable-int128 through cmake flag COMPILER_RT_HAS_FINT128_FLAG.

RISCV ABI doc specifies the calling convention for __int128_t ("Scalars wider than 2✕XLEN are passed by reference and are replaced in the argument list with the address."). And llc, at least, appears to correctly honor that. So I think we're okay in terms of ABI stability, but someone should verify that clang emits appropriate IR.

Thu, Feb 22, 5:38 AM
asb added inline comments to D23568: [RISCV 10/10] Add common fixups and relocations.
Thu, Feb 22, 5:28 AM
asb committed rL325775: [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensive.
[RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensive
Thu, Feb 22, 5:26 AM
asb accepted D42834: [RISCV] Implement c.lui immedate operand constraint.

Looks good to me now. I had a go at rewording the c_lui_imm comment - feel free to take from that suggestion if you think it's any clearer.

Thu, Feb 22, 5:17 AM
asb added a comment to D42834: [RISCV] Implement c.lui immedate operand constraint.

Only remaining concern:

Thu, Feb 22, 3:21 AM

Tue, Feb 20

asb added a comment to D43157: [RISCV] Properly evaluate VK_RISCV_PCREL_LO.

Sorry for the delay, I've been on paternity leave. Will review this and D43158 ASAP.

Tue, Feb 20, 12:51 AM

Sat, Feb 17

asb committed rL325441: [RISCV] Revert r324172 now r323991 was reverted.
[RISCV] Revert r324172 now r323991 was reverted
Sat, Feb 17, 10:19 AM
asb added a comment to D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag.

So you want int128_t for compiler-rt itself, so you can use the soft-float implementation, but you want to make int128_t opt-in to avoid the possibility of someone getting a link error trying to link code built with clang against libgcc.a? That seems a little convoluted, but I guess it's okay.

Sat, Feb 17, 6:07 AM

Thu, Feb 8

asb added a comment to D42834: [RISCV] Implement c.lui immedate operand constraint.

Ana, can you share the encoded and decoded instruction which causes the qemu crash? This patch shouldn't change the encoding in any way - it should produce the same set of c.lui encodings (all legal), it's just the mapping from logical immediate operand -> encoded form that changes.

Thu, Feb 8, 12:21 AM

Sat, Feb 3

asb committed rL324172: [RISCV] Update two RISCV codegen tests after rL323991.
[RISCV] Update two RISCV codegen tests after rL323991
Sat, Feb 3, 5:04 AM
asb committed rC324170: [RISCV] Create a LinuxTargetInfo when targeting Linux.
[RISCV] Create a LinuxTargetInfo when targeting Linux
Sat, Feb 3, 3:58 AM
asb committed rL324170: [RISCV] Create a LinuxTargetInfo when targeting Linux.
[RISCV] Create a LinuxTargetInfo when targeting Linux
Sat, Feb 3, 3:58 AM

Fri, Feb 2

asb created D42850: [docs] Add guidance on duplicating doc comments to CodingStandards.
Fri, Feb 2, 9:51 AM
asb added a comment to D42805: [utils] Refactor utils/update_{,llc_}test_checks.py to share more code.

These were actually deliberately split apart in the past year, so not sure what makes sense here.

Fri, Feb 2, 9:14 AM
asb added a comment to D42834: [RISCV] Implement c.lui immedate operand constraint.

Thanks Shiva. I've left comments inline regarding the naming convention for this operand type, and the printing policy. As I say, I think we should let c.lui's operand print in the same way as lui for now. Consistently printing hex for lui and c.lui (as I think gnu objdump does) probably makes sense, but lets do that in a separate patch and do it for both instructions at the same time.

Fri, Feb 2, 8:43 AM
asb accepted D42515: [RISCV] Add support for %pcrel_lo..

Thanks, looks good to me.

Fri, Feb 2, 8:07 AM

Thu, Feb 1

asb added a comment to D42465: [RFC][CallingConv] Add CCAssignToRegWithType Calling Convention Interface.

Hi Alex, It seems that getRegisterTypeForCallingCon and relative hooks will split the type before assigning registers. Therefore, f64 will split into two i32. If two i32 types can't allocate to registers, it will generate two i32 load/stores.
Another case is that riscv ilp32d ABI will pass f64 by i32 registers if f64 registers are not available. In this case, we have to do argument analysis to know there are no f64 registers left, then we assign to i32 registers.

Thu, Feb 1, 6:41 AM
asb accepted D42782: [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero.

Looks good to me - thanks!

Thu, Feb 1, 6:31 AM
asb added a comment to D42712: [utils] Add utils/update_cc_test_checks.py.

I agree with @RKSimon that splitting the refactoring to a separate patch would make sense. I've previously missed having an update_cc_test_checks.py for IR tests, so think this is a great improvement. End-to-end clang->assembly tests may not be welcome upstream, but given they're trivial to support after this refactoring it would seem mean not to expose that functionality to out-of-tree users who want it.

Thu, Feb 1, 6:21 AM
asb added a reviewer for D42674: Make utils/UpdateTestChecks/common.py Python 2/3 compatible and fix print statements.: modocache.

Adding @modocache as reviewer, who has been responsible for making the opt-viewer tools Py2+Py3 compatible. The changes look sensible to me, but the vast majority of the Python I've written for a long time has been Py3.

Thu, Feb 1, 6:14 AM
asb added a comment to D42629: [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature.

Looks like there are two more test files you can update to not pass -mattr=+c to llvm-objdump:

Thu, Feb 1, 6:10 AM
asb accepted D42629: [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature.

Nice improvement - looks good to me. Thanks!

Thu, Feb 1, 6:07 AM
asb added a comment to D42515: [RISCV] Add support for %pcrel_lo..

Hi Ahmed. Many thanks for the contribution, and sorry for the slight delay in reviewing.

Thu, Feb 1, 5:56 AM
asb added a comment to D42465: [RFC][CallingConv] Add CCAssignToRegWithType Calling Convention Interface.

rL305083 by @sdardis introduced getRegisterTypeForCallingConv, getNumRegistersForCallingConvention and some other related hooks. These can be used to a similar effect - did you evaluate that approach instead?

Thu, Feb 1, 5:37 AM
asb added a comment to D41949: [RISCV] implement li pseudo instruction.

I'm liking the look of this, looking forward to giving a final review when you're happy to remove the WIP tag. Thanks!

Thu, Feb 1, 5:32 AM
asb accepted D42675: [RISCV] Define getSetCCResultType for setting vector setCC type.

Hi Shiva. update_llc_test_checks.py basically generates CHECK lines for you according to the RUN lines in the file. This is a fairly minor benefit when writing a test for the first time, but the biggest benefit comes from maintaining the test. When there is a codegen change, test files that contain all instructions are much easier to review.

Thu, Feb 1, 4:20 AM

Tue, Jan 30

asb added inline comments to D42675: [RISCV] Define getSetCCResultType for setting vector setCC type.
Tue, Jan 30, 11:57 AM
asb added a comment to D42673: [RISCV] Pick the correct RISCV linker instead of calling riscv-gcc to link.

My main concern with this patch is that the description doesn't really match what it does. The current in-tree code _doesn't_ call gcc to link for the tested configuration (a multilib toolchain), and this is verified with the tests in test/Driver/riscv32-toolchain.c. D39963 originally added support for a baremetal toolchain, but was changed to focus on the multilib Linux toolchain for a couple of reasons:

  1. This was a more straight-forward change
  2. Downstream users such as yourself had a higher priority for building for a Linux target
  3. It looks like we'd want to discuss the possibility of adding RISC-V support to lib/Driver/ToolChains/BareMetal rather than adding yet another target-specific toolchain
Tue, Jan 30, 10:27 AM · Restricted Project

Fri, Jan 26

asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

Sorry, my mistake - the committed version did include the suggested changes.

Fri, Jan 26, 12:43 AM
asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

Hi Shiva. In the future it's worth nothing that if you include the review url in the commit, then Phabricator automatically picks it up.

Fri, Jan 26, 12:39 AM

Jan 25 2018

asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

Hi Shiva, why don't you follow the instructions at http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access and request commit access? Many many thanks again for all of your contributions to the RISC-V backend so far.

Jan 25 2018, 9:59 AM

Jan 23 2018

asb added inline comments to D42374: [RFC] Add IsFixed field to ISD::ArgFlagsTy.
Jan 23 2018, 5:20 AM
asb added a comment to D41949: [RISCV] implement li pseudo instruction.

Addresses all of Alex's comments (thank you) and integrates PseudoLI emission into CodeGen.

More comments are welcome. Especially opinions about the correct location (and name) for the emitLoadImm method which is currently simply copied to both users.

Jan 23 2018, 2:44 AM
asb added inline comments to D42374: [RFC] Add IsFixed field to ISD::ArgFlagsTy.
Jan 23 2018, 2:04 AM

Jan 22 2018

asb updated subscribers of D42374: [RFC] Add IsFixed field to ISD::ArgFlagsTy.
Jan 22 2018, 7:27 AM
asb created D42374: [RFC] Add IsFixed field to ISD::ArgFlagsTy.
Jan 22 2018, 7:27 AM
asb updated subscribers of D29935: [RISCV 13/n] Codegen for conditional branches.
Jan 22 2018, 2:06 AM

Jan 18 2018

asb committed rL322843: [RISCV] Codegen support for the standard RV32M instruction set extension.
[RISCV] Codegen support for the standard RV32M instruction set extension
Jan 18 2018, 4:40 AM
asb added a comment to D42033: [RISCV] Initial Machine Scheduler.

Leslie - there's a huge amount here that's copied and pasted from ARMScheduleA9.td, much of it really isn't relevant to any current RISC-V implementation, such as load-multiple/store-multiple and vector operations. Additionally, the A9 is an out-of-order superscalar core. The majority of the RISC-V community are targeting in-order cores (Rocket, PULP, other microcontroller class cores). If you're keen to explore scheduling models for out-of-order cores then BOOM is of course the obvious target.

Jan 18 2018, 4:30 AM
asb added a comment to D41700: [RISCV] Refactory the existing CC_RISCV32 function to conform to the CCAssignFn type.

Hi Leslie. Obviously we need to resolve the CCState issue before merging this, as it would regress codegen in its current state. Good observation that we can get the DataLayout via CCState. Given that, why not get rid of the various wrapper functions and just determine XLen and XLenVT from the DataLayout?

Jan 18 2018, 4:06 AM
asb accepted D42132: [RISCV] Fixed setting predicates for compressed instructions..

Thanks Ana, looks good to me.

Jan 18 2018, 4:01 AM
asb added a comment to D41653: [RISCV] Initial porting GlobalISel.

Hi Leslie, this patch includes rather a lot which makes it somewhat hard to review - i.e. you're doing call handling, loads/store selection, selection for some ALU ops, FPR32/FPR64 regs + fcmp, and there aren't any tests attached that check this all works.

Jan 18 2018, 3:54 AM
asb committed rL322839: [RISCV] Implement frame pointer elimination.
[RISCV] Implement frame pointer elimination
Jan 18 2018, 3:35 AM
asb committed rL322825: [RISCV][NFC] Add nounwind to functions in div.ll and mul.ll.
[RISCV][NFC] Add nounwind to functions in div.ll and mul.ll
Jan 18 2018, 1:42 AM

Jan 17 2018

asb added a comment to D42132: [RISCV] Fixed setting predicates for compressed instructions..

Thanks for this - definitely a real problem that we want to fix.

Jan 17 2018, 8:24 AM
asb requested changes to D42132: [RISCV] Fixed setting predicates for compressed instructions..

Temporarily unaccepting - sorry, I accidentally added comments and acceptance for a different patch. Comments following shortly.

Jan 17 2018, 6:35 AM
asb accepted D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

clang-format shows me a few minor tweaks:

Jan 17 2018, 6:34 AM
asb accepted D42132: [RISCV] Fixed setting predicates for compressed instructions..
Jan 17 2018, 6:33 AM
asb committed rL322658: [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supported.
[RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supported
Jan 17 2018, 6:18 AM
asb closed D41221: [RISCV] writeNopData support generate c.nop.
Jan 17 2018, 6:18 AM
asb accepted D41221: [RISCV] writeNopData support generate c.nop.

Thanks! Looks good to me.

Jan 17 2018, 6:18 AM
asb added a comment to D41571: RISCV: Add IMAGE_FILE_MACHINE COFF address spaces.

Hi @martell, do you think you might have time to add a test for this?

Jan 17 2018, 6:02 AM
asb added a comment to D41271: [RISCV] Propagate -mabi and -march values to GNU assembler..

I tested this on windows and I had to add an assembler placeholder executable, just like it was done with the linker in the RISCV multilib dir checked under Inputs.
Other observations, are these known issues?

  • multilib dir checked in has only riscv64-unknown-linux-gnu which we see the riscv tests invoking even when the target is 32 bit.
  • riscv64 is not honoring gcc-toolchain flag, it keeps invoking default /usr/bin/as. Anyways, the test now passes on windows.
Jan 17 2018, 6:01 AM
asb added a comment to D41949: [RISCV] implement li pseudo instruction.

Hi Alex, thank you for your comments!

As mentioned two weeks ago, I also think that it would be nice if we can share the code that synthesizes immediates between the assembler and codegen. I plan to experiment with getting this working in the next week. The idea that I plan to investigate is to delay the generation of the immediates until the MC layer is reached. Basically, emitting PseudoLI machine instructions in RISCVInstrInfo::movImm32 and perform the actual expansion manually during MI to MC lowering.

Jan 17 2018, 5:55 AM

Jan 15 2018

asb added a comment to D40023: [RISCV] Implement ABI lowering.

Thanks Eli, that saved me some time - fixed in rL322514 (clang-x86_64-linux-selfhost-modules-2 is now green).

Jan 15 2018, 1:45 PM
asb committed rC322514: [RISCV] Fix test failures on non-assert builds introduced in r322494.
[RISCV] Fix test failures on non-assert builds introduced in r322494
Jan 15 2018, 12:46 PM
asb committed rL322514: [RISCV] Fix test failures on non-assert builds introduced in r322494.
[RISCV] Fix test failures on non-assert builds introduced in r322494
Jan 15 2018, 12:46 PM
asb added a comment to D40023: [RISCV] Implement ABI lowering.

The riscv32-abi and risc64-abi tests are failing (specifically the vararg checks) on the clang-with-thin-lto and modules-slave-2 buildbots:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/7892
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/15300

Jan 15 2018, 11:21 AM
asb committed rC322494: [RISCV] Implement RISCV ABI lowering.
[RISCV] Implement RISCV ABI lowering
Jan 15 2018, 9:56 AM
asb committed rL322494: [RISCV] Implement RISCV ABI lowering.
[RISCV] Implement RISCV ABI lowering
Jan 15 2018, 9:56 AM
asb closed D40023: [RISCV] Implement ABI lowering.
Jan 15 2018, 9:56 AM

Jan 13 2018

asb added inline comments to D40023: [RISCV] Implement ABI lowering.
Jan 13 2018, 1:54 AM
asb added a comment to D39963: [RISCV] Add initial RISC-V target and driver support.

Hi Petr, thanks for the report. This should be addressed in rL322435.

Jan 13 2018, 1:26 AM
asb committed rC322435: Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER.
Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER
Jan 13 2018, 1:22 AM
asb committed rL322435: Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER.
Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER
Jan 13 2018, 1:22 AM

Jan 12 2018

asb updated the diff for D40023: [RISCV] Implement ABI lowering.

Rebase after ABIArgInfo signext/zeroext refactoring D41999 / rL322396. We no longer need to modify CGCall.cpp for unsigned 32-bit return values to be sign extended as required by the RV64 ABI.

Jan 12 2018, 12:24 PM
asb committed rL322396: Refactor handling of signext/zeroext in ABIArgInfo.
Refactor handling of signext/zeroext in ABIArgInfo
Jan 12 2018, 12:09 PM
asb committed rC322396: Refactor handling of signext/zeroext in ABIArgInfo.
Refactor handling of signext/zeroext in ABIArgInfo
Jan 12 2018, 12:09 PM
asb closed D41999: Refactor handling of signext/zeroext in ABIArgInfo.
Jan 12 2018, 12:09 PM
asb added inline comments to D40023: [RISCV] Implement ABI lowering.
Jan 12 2018, 10:23 AM
asb created D41999: Refactor handling of signext/zeroext in ABIArgInfo.
Jan 12 2018, 10:21 AM
asb accepted D41956: [docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web.

I think the change to "To submit an updated patch:" should probably be left out, given we agree there's no benefit currently in specifying the repo for the diff object (as opposed to the review).

Jan 12 2018, 7:41 AM
asb added inline comments to D40023: [RISCV] Implement ABI lowering.
Jan 12 2018, 5:53 AM
asb updated the diff for D40023: [RISCV] Implement ABI lowering.

I've addressed all outstanding comments (a number of response are inline).

Jan 12 2018, 5:53 AM
asb added a comment to D41949: [RISCV] implement li pseudo instruction.

Hi Mario - as this is marked in WIP I've added a few initial comments rather than given a 100% complete review.

Jan 12 2018, 1:24 AM
asb added a comment to D41221: [RISCV] writeNopData support generate c.nop.

Thanks for the update Shiva - a few minor comments in-line

Jan 12 2018, 1:10 AM
asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

My suggestion would be to remove the MCSubtarget field (it can be reintroduced when future changes need it), but obviously keep it as an argument to the constructor where it is used.

Jan 12 2018, 12:48 AM
asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

Hi Shiva. I was just looking at applying this and the STI field is triggering a compiler warning as it's not used: it's initialised in the RISCVTargetELFStreamer constructor, but isn't actually read from anywhere.

Jan 12 2018, 12:45 AM
asb added a comment to D41956: [docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web.

Yes, I'm sure the repository information is stored somewhere attached to the diff object - but it seems we don't use it. For this patch, I think the best way forwards is to advise users they can ignore the field when uploading the diff, and should enter it on the subsequent page. It's possible the workflow will be improved based on your upstream bug report, but we'd have to wait for the LLVM phabricator install to be updated anyway.

Jan 12 2018, 12:20 AM

Jan 11 2018

asb added a comment to D41956: [docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web.

Well spotted. I've just verified that if you enter the repository on the first page it isn't automatically copied through to the "Create Revision" page. I'm assuming that it's setting the repository on the "create revision" stage that results in automatically adding llvm-commits of cfe-commits to the subscriber list?

Jan 11 2018, 11:04 AM
asb added a comment to D41271: [RISCV] Propagate -mabi and -march values to GNU assembler..

I've just had a painful time landing D39963 due to failures on the Windows buildbots. I think you'll have problems on Windows with the tests in this patch, as Windows surely won't default to /usr/bin/as. Sadly I don't have access to a windows Clang build to confirm what path it will default to.

Jan 11 2018, 10:47 AM
asb committed rL322294: [Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test.
[Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test
Jan 11 2018, 9:07 AM
asb committed rC322294: [Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test.
[Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test
Jan 11 2018, 9:07 AM
asb added a comment to D41932: [RISCV] Hooks for enabling instruction compression.

Thanks Ana for outlining your current thinking. Without reviewing the fine details, this seems in the direction we were all discussing.

Jan 11 2018, 8:41 AM
asb added a comment to D41658: [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer.

With a couple of minor nits, looks good to me. Thanks as always Shiva

Jan 11 2018, 8:28 AM
asb accepted D41919: [docs] Update Phabricator docs about setting repository for diffs uploaded via web.

Looks good to me!

Jan 11 2018, 7:59 AM
asb committed rL322286: [Driver][RISCV] Fix r322276 for Windows (path separator issue).
[Driver][RISCV] Fix r322276 for Windows (path separator issue)
Jan 11 2018, 7:39 AM
asb committed rC322286: [Driver][RISCV] Fix r322276 for Windows (path separator issue).
[Driver][RISCV] Fix r322276 for Windows (path separator issue)
Jan 11 2018, 7:39 AM
asb committed rC322277: [Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test….
[Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test…
Jan 11 2018, 5:52 AM
asb committed rL322277: [Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test….
[Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test…
Jan 11 2018, 5:52 AM
asb committed rL322276: [RISCV] Add the RISCV target and compiler driver.
[RISCV] Add the RISCV target and compiler driver
Jan 11 2018, 5:38 AM
asb committed rC322276: [RISCV] Add the RISCV target and compiler driver.
[RISCV] Add the RISCV target and compiler driver
Jan 11 2018, 5:38 AM
asb closed D39963: [RISCV] Add initial RISC-V target and driver support.
Jan 11 2018, 5:38 AM
asb added a comment to D41919: [docs] Update Phabricator docs about setting repository for diffs uploaded via web.

Am I correct in thinking that as long as the repository field is filled out, there should never be a reason to explicitly add llvm-commits or cfe-commits to the subscriber list? If so it would probably make sense to remove the note "subscribe mailing lists that you want to be included in the review. If your patch is for LLVM, add llvm-commits as a Subscriber; if your patch is for Clang, add cfe-commits." Instead, you could expand the bullet point on the repository field to say "Entering the correct repository will ensure that the appropriate mailing list (llvm-commits or cfe-commits) is automatically subscribed to patch patch updates.

Jan 11 2018, 3:37 AM
asb committed rL322269: [RISCV] Reserve an emergency spill slot for the register scavenger when….
[RISCV] Reserve an emergency spill slot for the register scavenger when…
Jan 11 2018, 3:18 AM

Jan 10 2018

asb committed rL322224: [RISCV] Implement support for the BranchRelaxation pass.
[RISCV] Implement support for the BranchRelaxation pass
Jan 10 2018, 1:06 PM
asb closed D40830: [RISCV] Implement support for the BranchRelaxation pass.
Jan 10 2018, 1:06 PM