asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (223 w, 6 d)

Recent Activity

Today

asb added inline comments to rL318738: [RISCV] Use register X0 (ZERO) for constant 0.
Tue, Nov 21, 4:03 AM
asb committed rL318757: [RISCV][NFC] Clean up RISCVDAGToDAGISel::Select.
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
Tue, Nov 21, 4:01 AM
asb updated the diff for D39848: [RISCV] Support lowering FrameIndex.

Rebased and updated to implement getFrameIndexReference.

Tue, Nov 21, 3:53 AM
asb abandoned D37230: Set hasSideEffects=0 for TargetOpcode::BUNDLE.

As mentioned on the mailing list I don't have time to fix up and audit the test case changes. If anyone wants to see BUNDLE with hasSideEffects=0, please do commandeer the revision.

Tue, Nov 21, 2:02 AM
asb updated the diff for D39845: [TableGen] Give the option of tolerating duplicate register names.

Updated to add a TableGen test for the generation of MatchRegisterName and MatchRegisterAltName when AllowDuplicateRegisterNames is set.

Tue, Nov 21, 1:55 AM
asb committed rL318738: [RISCV] Use register X0 (ZERO) for constant 0.
[RISCV] Use register X0 (ZERO) for constant 0
Tue, Nov 21, 12:24 AM
asb added inline comments to D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Tue, Nov 21, 12:12 AM
asb committed rL318737: [RISCV] Support and tests for a variety of additional LLVM IR constructs.
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Tue, Nov 21, 12:11 AM
asb closed D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs by committing rL318737: [RISCV] Support and tests for a variety of additional LLVM IR constructs.
Tue, Nov 21, 12:11 AM

Yesterday

asb committed rL318735: [RISCV] Implement lowering of ISD::SELECT.
[RISCV] Implement lowering of ISD::SELECT
Mon, Nov 20, 11:51 PM
asb closed D29937: [RISCV 15/n] Implement lowering of ISD::SELECT by committing rL318735: [RISCV] Implement lowering of ISD::SELECT.
Mon, Nov 20, 11:51 PM
asb updated subscribers of D40256: [ARM] disable FPU features when using soft floating point..

It would have been much cleaner if it worked as @efriedma suggests and -mfloat-abi was only concerned with the ABI (as its name would suggest), but sadly the -mfloat-abi=soft option seems to be defined in GCC to control more than just the ABI.

Mon, Nov 20, 1:38 PM

Thu, Nov 16

asb added a comment to D39848: [RISCV] Support lowering FrameIndex.

I should add a clarifying comment. These are codegen-only constructs that as far as I can see are required for frameindex lowering, in order to represent a frameindex+offset pair.

Thu, Nov 16, 12:41 PM
asb accepted D40145: [RISCV] Fix 64-bit data layout mismatch between backend and target description.

This is the correct string, as used and tested in the yet-to-be merged patches. I forgot to move this fix from the relevant RV64I patch. Thanks for noticing this.

Thu, Nov 16, 12:25 PM
asb added inline comments to D39963: [RISCV][RFC] Add initial RISC-V target and driver support.
Thu, Nov 16, 12:16 PM
asb updated the diff for D39963: [RISCV][RFC] Add initial RISC-V target and driver support.

Consider this a WIP update. This is not yet ready for merging, but could still benefit from feedback.

Thu, Nov 16, 12:13 PM
asb accepted D40139: Fix RISCV build after r318352.

Thanks, and do feel free to directly commit build fixes like this if you have commit access without pre-commit review.

Thu, Nov 16, 10:39 AM

Wed, Nov 15

asb added inline comments to D40023: [RISCV] Implement ABI lowering.
Wed, Nov 15, 6:42 AM
asb updated the diff for D40023: [RISCV] Implement ABI lowering.

Updated to address review comments. I've added some extra test coverage that demonstrates that argument lowering happens the same once registers are exhausted, as well as more coverage around varargs. Also updated to properly handle the "aligned register pair" rule for variadic arguments, and added tests for this.

Wed, Nov 15, 6:42 AM
asb added a dependency for D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support: D39849: [RISCV] Implement prolog and epilog insertion.
Wed, Nov 15, 1:01 AM
asb added a dependent revision for D39849: [RISCV] Implement prolog and epilog insertion: D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support.
Wed, Nov 15, 1:01 AM

Tue, Nov 14

asb added a comment to D40001: [RISCV] MC layer support for the load/store instructions of standard compress instruction set.

Thanks Shiva. A whole bunch of inline comments are below. Thanks to Simon for spotting the missing -triple in the tests, I was struggling to see why I couldn't get the tests to pass.

Tue, Nov 14, 12:03 PM
asb committed rL318174: Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL….
Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL…
Tue, Nov 14, 11:16 AM
asb closed D39941: Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL,ANNOTATION_LABEL} by committing rL318174: Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL….
Tue, Nov 14, 11:16 AM
asb added inline comments to D39963: [RISCV][RFC] Add initial RISC-V target and driver support.
Tue, Nov 14, 6:15 AM
asb created D40023: [RISCV] Implement ABI lowering.
Tue, Nov 14, 5:59 AM
asb added inline comments to D39848: [RISCV] Support lowering FrameIndex.
Tue, Nov 14, 12:06 AM
asb updated the diff for D39848: [RISCV] Support lowering FrameIndex.

Updated patch to address review comments.

Tue, Nov 14, 12:06 AM

Mon, Nov 13

asb updated the diff for D39941: Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL,ANNOTATION_LABEL}.

Thanks Reid, updated the patch with that change. I'll aim to commit tomorrow.

Mon, Nov 13, 1:31 PM
asb created D39963: [RISCV][RFC] Add initial RISC-V target and driver support.
Mon, Nov 13, 8:59 AM
asb updated the diff for D39848: [RISCV] Support lowering FrameIndex.

Rebase on latest LLVM and remove redundant return in eliminateFrameIndex.

Mon, Nov 13, 4:23 AM
asb updated the diff for D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support.

Fix typo.

Mon, Nov 13, 3:05 AM
asb added inline comments to D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support.
Mon, Nov 13, 2:54 AM
asb updated the diff for D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support.

Updated patch to address review comments (thanks!).

Mon, Nov 13, 2:54 AM

Sat, Nov 11

asb created D39941: Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL,ANNOTATION_LABEL}.
Sat, Nov 11, 9:37 AM

Fri, Nov 10

asb created D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support.
Fri, Nov 10, 5:21 AM
asb added a dependent revision for D39893: [RISCV] MC layer support for the standard RV32F instruction set extension: D39895: [RISCV] MC layer support for the standard RV32D instruction set extension.
Fri, Nov 10, 3:39 AM
asb added dependencies for D39895: [RISCV] MC layer support for the standard RV32D instruction set extension: D39893: [RISCV] MC layer support for the standard RV32F instruction set extension, D39845: [TableGen] Give the option of tolerating duplicate register names.
Fri, Nov 10, 3:39 AM
asb added a dependent revision for D39845: [TableGen] Give the option of tolerating duplicate register names: D39895: [RISCV] MC layer support for the standard RV32D instruction set extension.
Fri, Nov 10, 3:39 AM
asb created D39895: [RISCV] MC layer support for the standard RV32D instruction set extension.
Fri, Nov 10, 3:39 AM
asb updated the diff for D39893: [RISCV] MC layer support for the standard RV32F instruction set extension.

Small fix in rv32f-invalid.s.

Fri, Nov 10, 3:30 AM
asb created D39893: [RISCV] MC layer support for the standard RV32F instruction set extension.
Fri, Nov 10, 3:17 AM
asb added a dependency for D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs: D29937: [RISCV 15/n] Implement lowering of ISD::SELECT.
Fri, Nov 10, 12:24 AM
asb added a dependent revision for D29937: [RISCV 15/n] Implement lowering of ISD::SELECT: D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Fri, Nov 10, 12:24 AM
asb added inline comments to D29937: [RISCV 15/n] Implement lowering of ISD::SELECT.
Fri, Nov 10, 12:19 AM
asb updated the diff for D29937: [RISCV 15/n] Implement lowering of ISD::SELECT.

Adds a bare-select.ll test case, ensuring all code paths in lowerSELECT are tested.

Fri, Nov 10, 12:19 AM

Thu, Nov 9

asb accepted D39881: [RISCV] Silence an unused variable warning in release builds [NFC].

Looks good to me, thanks! Please go ahead and commit.

Thu, Nov 9, 11:45 PM
asb added inline comments to D38894: [RFC][Tablegen] Add CCIfSplitFrom and CCPassIndirectBySamePointer Calling Convention Interfaces.
Thu, Nov 9, 12:39 PM
asb committed rL317826: [utils] Fix RISC-V support in update_llc_test_checks.py.
[utils] Fix RISC-V support in update_llc_test_checks.py
Thu, Nov 9, 12:01 PM
asb updated the diff for D39849: [RISCV] Implement prolog and epilog insertion.

Address @mgrang's review comments (thanks!). I also moved the changes to eliminateFrameIndex to the previous patch, as it makes sense to just do it right from the start.

Thu, Nov 9, 11:51 AM
asb added inline comments to D39848: [RISCV] Support lowering FrameIndex.
Thu, Nov 9, 11:49 AM
asb updated the diff for D39848: [RISCV] Support lowering FrameIndex.

Thanks Mandeep, updated the patch. I've moved a bit of logic from the successor patch (D39849) to this one, as I think it makes more sense to use the correct register in eliminateFrameIndex from the start, rather than adding the extra logic in the next patch.

Thu, Nov 9, 11:48 AM
asb added a dependent revision for D39848: [RISCV] Support lowering FrameIndex: D39849: [RISCV] Implement prolog and epilog insertion.
Thu, Nov 9, 10:02 AM
asb added a dependency for D39849: [RISCV] Implement prolog and epilog insertion: D39848: [RISCV] Support lowering FrameIndex.
Thu, Nov 9, 10:02 AM
asb created D39849: [RISCV] Implement prolog and epilog insertion.
Thu, Nov 9, 10:02 AM
asb added a dependency for D39848: [RISCV] Support lowering FrameIndex: D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Thu, Nov 9, 9:54 AM
asb added a dependent revision for D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs: D39848: [RISCV] Support lowering FrameIndex.
Thu, Nov 9, 9:54 AM
asb created D39848: [RISCV] Support lowering FrameIndex.
Thu, Nov 9, 9:53 AM
asb committed rL317796: [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py.
[RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py
Thu, Nov 9, 7:46 AM
asb created D39845: [TableGen] Give the option of tolerating duplicate register names.
Thu, Nov 9, 7:22 AM
asb committed rL317791: [RISCV] MC layer support for the standard RV32A instruction set extension.
[RISCV] MC layer support for the standard RV32A instruction set extension
Thu, Nov 9, 7:00 AM
asb committed rL317788: [RISCV] MC layer support for the standard RV32M instruction set extension.
[RISCV] MC layer support for the standard RV32M instruction set extension
Thu, Nov 9, 6:46 AM

Wed, Nov 8

asb committed rL317721: Set hasSideEffects=0 for PHI and fix affected passes.
Set hasSideEffects=0 for PHI and fix affected passes
Wed, Nov 8, 12:19 PM
asb closed D37097: Set hasSideEffects=0 for PHI and fix passes relying isSafeToMove/hasUnmodeledSideEffects being true for PHI by committing rL317721: Set hasSideEffects=0 for PHI and fix affected passes.
Wed, Nov 8, 12:19 PM
asb committed rL317693: [utils] Add RISC-V support to update_llc_test_checks.py.
[utils] Add RISC-V support to update_llc_test_checks.py
Wed, Nov 8, 6:25 AM
asb closed D39789: Add RISC-V support to update_llc_test_checks.py by committing rL317693: [utils] Add RISC-V support to update_llc_test_checks.py.
Wed, Nov 8, 6:25 AM
asb added inline comments to D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Wed, Nov 8, 6:04 AM
asb updated the diff for D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.

Updated to address review comments from @reames. Tests are now generated using utils/update_llc_test_checks.py.

Wed, Nov 8, 6:01 AM
asb updated the diff for D29937: [RISCV 15/n] Implement lowering of ISD::SELECT.

This minor revision of the patch switches to lowering ISD::SELECT. This is motivated by future support for the floating point instruction set extensions and the coarse-grained nature of setOperationAction. See the updated patch description and new code comments for more discussion, but essentially we need to ensure that a RISC-V compare+branch instruction is generated whenever the comparison is between two XLEN integers.

Wed, Nov 8, 5:51 AM
asb committed rL317691: [RISCV] Initial support for function calls.
[RISCV] Initial support for function calls
Wed, Nov 8, 5:42 AM
asb closed D29936: [RISCV 14/n] Support for function calls by committing rL317691: [RISCV] Initial support for function calls.
Wed, Nov 8, 5:42 AM
asb committed rL317690: [RISCV] Codegen for conditional branches.
[RISCV] Codegen for conditional branches
Wed, Nov 8, 5:32 AM
asb closed D29935: [RISCV 13/n] Codegen for conditional branches by committing rL317690: [RISCV] Codegen for conditional branches.
Wed, Nov 8, 5:32 AM
asb committed rL317688: [RISCV] Codegen support for memory operations on global addresses.
[RISCV] Codegen support for memory operations on global addresses
Wed, Nov 8, 5:25 AM
asb closed D39103: [RISCV 12.5/n] Codegen support for memory operations on global addresses by committing rL317688: [RISCV] Codegen support for memory operations on global addresses.
Wed, Nov 8, 5:25 AM
asb added a comment to D29934: [RISCV 12/n] Codegen support for memory operations.

Thanks for helping to unblock this Philip. I was holding off on committing as Chandler was hoping to corral another backend maintainer into giving a second opinion. Unfortunately it looks like that person didn't have time, so I'm going ahead and committing.

Wed, Nov 8, 4:45 AM
asb added a comment to D39792: [AArch64][SVE] Asm: More concise test format.

This looks good to me. Tests for invalid operands etc as Florian suggests are definitely worth having. ARM, Mips and RISCV tend to add this in test files prefixed or suffixed with invalid, e.g. add-invalid.s or sve-invalid.s. AArch64 seems to use a diagnostics suffix.

Wed, Nov 8, 4:44 AM
asb committed rL317685: [RISCV] Codegen support for memory operations.
[RISCV] Codegen support for memory operations
Wed, Nov 8, 4:20 AM
asb closed D29934: [RISCV 12/n] Codegen support for memory operations by committing rL317685: [RISCV] Codegen support for memory operations.
Wed, Nov 8, 4:20 AM
asb committed rL317684: [RISCV] Codegen support for materializing constants.
[RISCV] Codegen support for materializing constants
Wed, Nov 8, 4:03 AM
asb closed D39101: [RISCV 11.5/n] Codegen support for materializing constants by committing rL317684: [RISCV] Codegen support for materializing constants.
Wed, Nov 8, 4:02 AM
asb created D39789: Add RISC-V support to update_llc_test_checks.py.
Wed, Nov 8, 3:47 AM
asb committed rL317674: [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0.
[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0
Wed, Nov 8, 1:26 AM
asb closed D37065: Ensure standard pseudo instructions (TargetOpcode::*) are compatible with guessInstructionProperties=0 by committing rL317674: [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0.
Wed, Nov 8, 1:26 AM

Tue, Oct 31

asb added a comment to D39322: [lld] Support RISC-V.

I'm not an LLD expert, but the RISC-V bits seem correct as far as I can see. I've just added a couple of minor comments.

Tue, Oct 31, 2:49 AM · lld

Mon, Oct 23

asb added inline comments to rL316188: [RISCV] Initial codegen support for ALU operations.
Mon, Oct 23, 11:47 PM
asb added a comment to D37065: Ensure standard pseudo instructions (TargetOpcode::*) are compatible with guessInstructionProperties=0.

Hi Alex,

I see that we stuck to hasSideEffects = 1 for BUNDLE, EH_LABEL and so on (the ones I marked with Ditto at some point).
Are we going to do the same thing as PHIs here, or do we plan to leave them with that flag ON?

I am not sure it is the right thing to do, but assuming it is, could you add a comment before each of them to explain why they have side effects.

Mon, Oct 23, 11:52 AM
asb updated the diff for D37065: Ensure standard pseudo instructions (TargetOpcode::*) are compatible with guessInstructionProperties=0.

The change to Lanai.td should not have been included. Refreshing patch.

Mon, Oct 23, 11:08 AM

Oct 20 2017

asb updated the diff for D39101: [RISCV 11.5/n] Codegen support for materializing constants.

Split out the immediate materialisation tests to a separate file and add a TODO for immediates with lo12=0.

Oct 20 2017, 8:54 AM

Oct 19 2017

asb added inline comments to D39091: [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ.
Oct 19 2017, 6:21 PM
asb committed rL316189: [RISCV] Add missing hunk from r316188.
[RISCV] Add missing hunk from r316188
Oct 19 2017, 2:43 PM
asb committed rL316188: [RISCV] Initial codegen support for ALU operations.
[RISCV] Initial codegen support for ALU operations
Oct 19 2017, 2:38 PM
asb closed D29933: [RISCV 11/n] Initial codegen support for ALU operations by committing rL316188: [RISCV] Initial codegen support for ALU operations.
Oct 19 2017, 2:38 PM
asb updated the diff for D39103: [RISCV 12.5/n] Codegen support for memory operations on global addresses.

I accidentally ttached an older version of the patch before, which had an unwanted whitespace change.

Oct 19 2017, 12:24 PM
asb created D39103: [RISCV 12.5/n] Codegen support for memory operations on global addresses.
Oct 19 2017, 12:21 PM
asb updated subscribers of D37052: Add default address space for functions to the data layout (1/4).
Oct 19 2017, 11:58 AM
asb updated the diff for D29934: [RISCV 12/n] Codegen support for memory operations.

Updated to split constant materialization to a preceding patch (D39101) and global addresses to a succeeding patch (to be posted shortly).

Oct 19 2017, 11:25 AM
asb added inline comments to D39101: [RISCV 11.5/n] Codegen support for materializing constants.
Oct 19 2017, 11:10 AM
asb created D39101: [RISCV 11.5/n] Codegen support for materializing constants.
Oct 19 2017, 10:38 AM
asb updated the diff for D29933: [RISCV 11/n] Initial codegen support for ALU operations.

Address review comments from Philip (thanks!).

Oct 19 2017, 10:05 AM