asb (Alex Bradbury)
Director and Co-founder, lowRISC CIC

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User Since
Aug 6 2013, 5:31 AM (206 w, 2 d)

Recent Activity

Mon, Jul 17

asb committed rL308172: [YAMLTraits] Add filename support to yaml::Input.
[YAMLTraits] Add filename support to yaml::Input
Mon, Jul 17, 4:42 AM
asb closed D35398: Add filename support to yaml::Input. by committing rL308172: [YAMLTraits] Add filename support to yaml::Input.
Mon, Jul 17, 4:42 AM

Fri, Jul 14

asb added a comment to D35398: Add filename support to yaml::Input..

This isn't part of LLVM I usually hack on, but I just wanted to comment to say:

  1. I've manually verified this patch applies cleanly to top of tree and all checks pass
  2. The patch looks good to me, and addresses the final nits from @arphaman in the previous revision. The only other changes vs the previous revision seems to be the removal of CurrentNode from the initialiser list as the field now has a default initialiser (as of rL305969).
Fri, Jul 14, 4:58 AM

May 2 2017

asb added a comment to D32117: Update TableGen LangIntro.rst.

Patch committed, many thanks for your contribution @chenwj.

May 2 2017, 7:01 AM
asb committed rL301920: Improvements to TableGen/LangIntro.rst.
Improvements to TableGen/LangIntro.rst
May 2 2017, 7:00 AM
asb closed D32117: Update TableGen LangIntro.rst by committing rL301920: Improvements to TableGen/LangIntro.rst.
May 2 2017, 7:00 AM

Apr 28 2017

asb accepted D32117: Update TableGen LangIntro.rst.

Thank you @chenwj, this is definitely an improvement over the current documentation. Would you like me to commit?

Apr 28 2017, 12:13 AM

Apr 25 2017

asb added a reviewer for D32117: Update TableGen LangIntro.rst: asb.

Hi, thanks for the patch. My feedback is:

  1. Limitations of literal formats shouldn't be discussed when introducing the types.
  2. Perhaps outside the scope of this patch, but it does seem a little odd that a simple string literal can be assigned to either a string or code variable, but code fragment literals can't be assigned to string variables (at least on the couple of months old build on LLVM I have on this machine). The existing description that a code fragment is "just a multiline string literal" seems incorrect due to this.
Apr 25 2017, 4:55 AM

Apr 20 2017

asb accepted D31959: Subtarget support for parametrized register class information.

Looks good to me.

Apr 20 2017, 5:15 AM
asb added a comment to D31951: TableGen support for parametrized register class information.

Phew, this is a monster patch to review but clearly there's no real way it could be reduced further. I have no real experience with the TableGen implementation, which limits my ability to contribute to this code review. I have at least carefully read through the code to try to spot any obvious logic errors or issues.

Apr 20 2017, 4:59 AM

Apr 19 2017

asb accepted D31937: Move value type list from TargetRegisterClass to TargetRegisterInfo.

Thanks, looks good to me.

Apr 19 2017, 11:20 AM
asb requested changes to D31937: Move value type list from TargetRegisterClass to TargetRegisterInfo.

I had a couple of minor review comments. I know the use of pointers vs references is quite inconsistent across LLVM, but I do feel it would be an improvement if isLegalRC took a const TargetRegisterInfo& (though perhaps there's a reason not to do this that I'm missing?).

Apr 19 2017, 9:00 AM

Apr 7 2017

asb accepted D31783: Move size and alignment information of regclass to TargetRegisterInfo.

Reference to previous related discussion: D24631 and http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html

Apr 7 2017, 1:21 AM

Apr 5 2017

asb committed rL299529: Add MCContext argument to MCAsmBackend::applyFixup for error reporting.
Add MCContext argument to MCAsmBackend::applyFixup for error reporting
Apr 5 2017, 3:29 AM
asb closed D30264: Add MCContext argument to MCAsmBackend::applyFixup for error reporting by committing rL299529: Add MCContext argument to MCAsmBackend::applyFixup for error reporting.
Apr 5 2017, 3:29 AM

Mar 28 2017

asb updated the diff for D30264: Add MCContext argument to MCAsmBackend::applyFixup for error reporting.

Refreshed the patch for current HEAD and double-checked all tests still pass. I'd really appreciate a review so we can get this committed.

Mar 28 2017, 12:56 PM

Mar 2 2017

asb added a comment to D30264: Add MCContext argument to MCAsmBackend::applyFixup for error reporting.

I've just verified this patch still applies cleanly to HEAD and, as before, all tests pass. Any comments? I think this is a useful cleanup for backends that already report errors for out-of-range fixups, and will make it easier to improve other backends with similar error reporting.

Mar 2 2017, 6:53 AM

Feb 22 2017

asb added a comment to D30115: [RFC] Add MachineInstr::MIFlag parameter to storeRegToStackSlot.

@nemanjai: MachineInstr::setFlag will do Flags |= Flag, so any previously set flags are maintained.

Feb 22 2017, 12:09 PM
asb created D30264: Add MCContext argument to MCAsmBackend::applyFixup for error reporting.
Feb 22 2017, 11:40 AM
asb added a comment to D18402: [AArch64] Better errors for out-of-range fixups.

Hi all. Sorry for digging up an old review, but I've been looking at reporting fixup overflow errors for RISC-V, and this seems the most appropriate place to discuss how it's currently handled in AArch64. I agree with @rengolin's concerns with this approach - or at least, I think we can do this better. Right now, adjustFixupValue is always called twice. The second time it's called, the MCContext argument is null and the code relies on the fact that any errors should have been caught the first time round, and so this null pointer will never be dereferenced [EDIT: sorry, that's not true - it does consistently check that Ctx is non-null]. I like having error checking alongside the value adjustments, but I propose that instead we achieve this by:

Feb 22 2017, 7:46 AM

Feb 17 2017

asb created D30115: [RFC] Add MachineInstr::MIFlag parameter to storeRegToStackSlot.
Feb 17 2017, 2:31 PM

Feb 14 2017

asb created D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Feb 14 2017, 5:58 AM
asb created D29937: [RISCV 15/n] Implement lowering of ISD::SELECT_CC.
Feb 14 2017, 5:47 AM
asb created D29936: [RISCV 14/n] Support for function calls.
Feb 14 2017, 5:38 AM
asb created D29935: [RISCV 13/n] Codegen for conditional branches.
Feb 14 2017, 5:32 AM
asb created D29934: [RISCV 12/n] Codegen support for memory operations.
Feb 14 2017, 5:09 AM
asb created D29933: [RISCV 11/n] Initial codegen support for ALU operations.
Feb 14 2017, 4:56 AM
asb updated the diff for D23567: [RISCV 9/10] Add support for disassembly.

The previous version of this patch made the mistake when decoding a GPR of assuming you can use the parsed RegNo as an index into the register class. In the general case, a register class will have the registers in preferred allocation order, meaning this will fail. Instead, we have a GPRDecoderTable to select the appropriate register based on the parsed RegNo.

Feb 14 2017, 2:03 AM
asb updated the diff for D23568: [RISCV 10/10] Add common fixups and relocations.

Here's the same patch as before with full context, apologies for the noise.

Feb 14 2017, 1:03 AM
asb updated the diff for D23566: [RISCV 8/10] Add support for all RV32I instructions.

The diff I attached a few hours ago didn't include all context, this update fixes that. Sorry for the noise.

Feb 14 2017, 1:01 AM
asb updated the diff for D23568: [RISCV 10/10] Add common fixups and relocations.

This refresh adds support for relocations and fixups on branch and jal instructions. This is sufficient for compiling simple programs.

Feb 14 2017, 12:54 AM

Feb 13 2017

asb added inline comments to D23566: [RISCV 8/10] Add support for all RV32I instructions.
Feb 13 2017, 10:26 PM
asb updated the diff for D23566: [RISCV 8/10] Add support for all RV32I instructions.

Refresh patch and incorporate suggestion from @jyknight regarding FENCE and FENCEI (thanks!).

Feb 13 2017, 10:25 PM
asb added inline comments to D23563: [RISCV 6/10] Add basic RISCVAsmParser.
Feb 13 2017, 9:56 PM
asb updated the diff for D23563: [RISCV 6/10] Add basic RISCVAsmParser.

Update to address review comment (just use StringRef rather than introducing Token struct).

Feb 13 2017, 9:55 PM
asb added a comment to rL294753: [Hexagon] Replace instruction definitions with auto-generated ones.

I think that, as you point out, it will depend on what sort of changes you're making. The use of multiclasses etc do sometimes make it more difficult to jump in and make a small change, but also give you power to make changes across a large number of definitions at once.

Feb 13 2017, 9:40 PM
asb committed rL295028: [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called.
[RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called
Feb 13 2017, 9:31 PM
asb committed rL295027: [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr.
[RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr
Feb 13 2017, 9:29 PM
asb committed rL295026: [RISCV] Fix unused variable in RISCVMCTargetDesc. NFC.
[RISCV] Fix unused variable in RISCVMCTargetDesc. NFC
Feb 13 2017, 9:27 PM

Feb 11 2017

asb added a comment to rL294753: [Hexagon] Replace instruction definitions with auto-generated ones.

Hi Krzysztof - is the tool that generated these instruction definitions open source, or at least available somewhere? I know that given Hexagon's current development pattern this is more of a theoretical concern than a practical one, but it does seem a barrier to people preparing patches for these .td files.

Feb 11 2017, 10:29 AM
asb updated subscribers of rL294341: This patch adds a ssa_copy intrinsic, as part of splitting up D29316..
Feb 11 2017, 10:01 AM
asb updated subscribers of rL294341: This patch adds a ssa_copy intrinsic, as part of splitting up D29316..

@dberlin, @davide: Perhaps this is my confusion rather than anything else, but should it read "The `llvm.ssa_copy` intrinsic can be used to attach information to operands" rather than to operations?

Feb 11 2017, 10:00 AM

Feb 2 2017

asb added a comment to D23568: [RISCV 10/10] Add common fixups and relocations.

@theraven @jyknight What's the state of this change?

Feb 2 2017, 2:29 AM
asb added a comment to D23563: [RISCV 6/10] Add basic RISCVAsmParser.

Hi Alex,

I silently followed the RISC-V patches being upstreamed and did not see an update here for a little while. Is this patch blocked on something or did you just not get to this one yet?

Feb 2 2017, 2:18 AM

Nov 1 2016

asb committed rL285770: [RISCV] Add bare-bones RISC-V MCTargetDesc.
[RISCV] Add bare-bones RISC-V MCTargetDesc
Nov 1 2016, 4:57 PM
asb closed D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc by committing rL285770: [RISCV] Add bare-bones RISC-V MCTargetDesc.
Nov 1 2016, 4:57 PM
asb committed rL285769: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
Nov 1 2016, 4:50 PM
asb closed D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td by committing rL285769: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.
Nov 1 2016, 4:50 PM
asb committed rL285730: [RISCV] Add RISCV.def to module.modulemap.
[RISCV] Add RISCV.def to module.modulemap
Nov 1 2016, 12:41 PM
asb committed rL285712: [RISCV] Add stub backend.
[RISCV] Add stub backend
Nov 1 2016, 10:37 AM
asb closed D23560: [RISCV 3/10] Add stub backend by committing rL285712: [RISCV] Add stub backend.
Nov 1 2016, 10:37 AM
asb closed D23558: [RISCV 2/10] Add RISC-V ELF defines.

Closed by rL285708 and rL285709.

Nov 1 2016, 10:24 AM
asb committed rL285709: [RISCV] Add missing RISCV.def.
[RISCV] Add missing RISCV.def
Nov 1 2016, 10:19 AM
asb committed rL285708: [RISCV] Add RISC-V ELF defines.
[RISCV] Add RISC-V ELF defines
Nov 1 2016, 10:09 AM
asb committed rL285707: [RISCV] Recognise riscv32 and riscv64 in triple parsing code.
[RISCV] Recognise riscv32 and riscv64 in triple parsing code
Nov 1 2016, 9:57 AM
asb closed D23557: [RISCV 1/10] Recognise riscv32 and riscv64 in triple parsing code by committing rL285707: [RISCV] Recognise riscv32 and riscv64 in triple parsing code.
Nov 1 2016, 9:57 AM
asb committed rL285705: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h.
[TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h
Nov 1 2016, 9:42 AM
asb closed D23496: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h by committing rL285705: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h.
Nov 1 2016, 9:41 AM

Oct 12 2016

asb added a reviewer for D23667: [AAP] (3) Add AAP backend stub: asb.
Oct 12 2016, 8:07 AM
asb updated the diff for D23568: [RISCV 10/10] Add common fixups and relocations.

Update test style as suggested by @jyknight in D23564

Oct 12 2016, 7:56 AM
asb updated the diff for D23567: [RISCV 9/10] Add support for disassembly.

Fix rv32i-valid.s, so CHECK-INST is used rather than CHECK-DIS.

Oct 12 2016, 7:56 AM
asb updated the diff for D23566: [RISCV 8/10] Add support for all RV32I instructions.

Update test style as suggested by @jyknight in D23564

Oct 12 2016, 7:55 AM
asb added inline comments to D23564: [RISCV 7/10] Add RISCVInstPrinter and basic MC assembler tests.
Oct 12 2016, 7:54 AM
asb updated the diff for D23564: [RISCV 7/10] Add RISCVInstPrinter and basic MC assembler tests.

Update test style as suggested by @jyknight

Oct 12 2016, 7:54 AM

Oct 11 2016

asb updated the diff for D23567: [RISCV 9/10] Add support for disassembly.

Refresh to follow changes made in rL283702, putting TheRISCV32Target and TheRISCV64Target behind accessors.

Oct 11 2016, 3:55 AM
asb updated the diff for D23563: [RISCV 6/10] Add basic RISCVAsmParser.

Refresh to follow changes made in rL283702, putting TheRISCV32Target and TheRISCV64Target behind accessors. Additionally, drop the unused getEndLoc after rL283691 removed it from MCParsedAsmOperand

Oct 11 2016, 3:52 AM
asb updated the diff for D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc.

Refresh to follow changes made in rL283702, putting TheRISCV32Target and TheRISCV64Target behind accessors.

Oct 11 2016, 3:49 AM
asb updated the diff for D23560: [RISCV 3/10] Add stub backend.

Refresh patch to follow the changes made to other backends in rL283702, moving TheRISCV32Target and TheRISCV64Target behind an accessor function.

Oct 11 2016, 3:47 AM

Oct 10 2016

asb added a comment to D25407: [lit] Remove (or allow specific) unused imports.

Hi Brian, I have a error after that change on windows (when reverting r283710, it is works fine again):

C:\c_make_build_dir\Debug\bin\llvm-lit.py -v C:\llvm\test\Object\invalid.test
Traceback (most recent call last):

  File "C:\c_make_build_dir\Debug\bin\llvm-lit.py", line 44, in <module>
    lit.main(builtin_parameters)
AttributeError: 'module' object has no attribute 'main'
Oct 10 2016, 6:17 AM

Oct 9 2016

asb updated the diff for D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

Fix the issue described in my previous comment by not defining an AsmName and AltName for the RISCV64 registers. With this approach, the generated MatchRegisterName and MatchAltRegisterName functions can be used. In the future, a little bit of extra logic in RISCVAsmParser.cpp can be added to coerce a parsed register from 32-bit to 64-bit when desired.

Oct 9 2016, 5:10 AM

Oct 8 2016

asb updated D23496: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h.
Oct 8 2016, 1:22 PM
asb updated the diff for D23496: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h.

The last update of this patch was incomplete. Now fixed.

Oct 8 2016, 1:20 PM
asb updated the diff for D23496: [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h.

Rather than the hacky previous approach (unconditionally emittingthe enum), move it to a header.

Oct 8 2016, 11:56 AM
asb added a comment to D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

It only shows up upon a clean compile (CMake issue?), but I've just found the introduction of registers with the same assembly name now leads to an assertion during compilation within llvm-tblgen. I'll investigate a fix.

Oct 8 2016, 7:41 AM
asb updated the diff for D23568: [RISCV 10/10] Add common fixups and relocations.

Refresh patch to reflect changes earlier in the series.

Oct 8 2016, 6:28 AM
asb added inline comments to D23567: [RISCV 9/10] Add support for disassembly.
Oct 8 2016, 6:26 AM
asb added inline comments to D23566: [RISCV 8/10] Add support for all RV32I instructions.
Oct 8 2016, 6:25 AM
asb updated the diff for D23567: [RISCV 9/10] Add support for disassembly.

Tests now check both assembly printing and disassembly. I've added a comment/TODO regarding decode of instructions outside of the RV32/RV64 core that might be 16-bit, 48bit, 64bit, ...

Oct 8 2016, 6:24 AM
asb updated the diff for D23566: [RISCV 8/10] Add support for all RV32I instructions.

Make use of isShiftedInt from MathExtras.h. Rename {simm21,simm13}_mask1 to {simm21,simm13}_lsb0. Tests are updated to check instruction printing.

Oct 8 2016, 6:20 AM
asb updated the diff for D23564: [RISCV 7/10] Add RISCVInstPrinter and basic MC assembler tests.

Tests have been modified to check instruction printing.

Oct 8 2016, 6:12 AM
asb updated the diff for D23563: [RISCV 6/10] Add basic RISCVAsmParser.

Address review comments from @jyknight and @t.p.northover. Also use # rather than !strconcat in RISCVInstrInfo.td

Oct 8 2016, 6:07 AM
asb updated the diff for D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

I have updated RISCVRegisterInfo.td so it defines both the 32-bit and 64-bit GPRs, marking the 32-bit GPRs as subregs. As explained in comments, the hope is that we can later move to using something like D24631.

Oct 8 2016, 6:02 AM
asb added inline comments to D23566: [RISCV 8/10] Add support for all RV32I instructions.
Oct 8 2016, 1:26 AM
asb added inline comments to D23566: [RISCV 8/10] Add support for all RV32I instructions.
Oct 8 2016, 1:18 AM

Oct 3 2016

asb added inline comments to D23564: [RISCV 7/10] Add RISCVInstPrinter and basic MC assembler tests.
Oct 3 2016, 9:42 AM

Sep 26 2016

asb committed rL282392: s/MV/MC.
s/MV/MC
Sep 26 2016, 2:04 AM

Sep 25 2016

asb committed rL282354: LLVM Cauldron slide link typo fix.
LLVM Cauldron slide link typo fix
Sep 25 2016, 5:39 AM
asb committed rL282353: Add links to slides and videos from 2016 LLVM Cauldron.
Add links to slides and videos from 2016 LLVM Cauldron
Sep 25 2016, 5:37 AM

Sep 16 2016

asb added a comment to D24631: [RFC] Implement variable-width register classes, step 1: API changes.

Hi Krzysztof. So as discussed in D23561 the motivating problem for this work is cases (as in Hexagon HVX) where instructions with identical encodings but different RegisterClasses currently need to be defined twice. An example of this is valignb. Having a register class with a non-constant register size and alignment would solve the issue for HVX, but there's also the hope it will be useful for other targets. For these HVX instructions there is no list<dag> pattern defined. If a pattern was specified, surely even with this new functionality you'd need to have repeated instruction definitions in order to define multiple patterns, because they would need different ValueTypes? Do you have something in mind that would address this as well?

Sep 16 2016, 3:08 AM

Sep 15 2016

asb updated subscribers of D24631: [RFC] Implement variable-width register classes, step 1: API changes.
Sep 15 2016, 10:38 PM

Sep 14 2016

asb added a comment to D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

@jyknight: Yes, that's a good point, once codegen is added I'll need to thread through a ValueType in a similar way to how I currently pass RegisterClass. I can definitely see the argument that describing instructions twice and abstracting later might lead to the best solution. I think it's definitely worth considering the alternatives early on though, even if I do go ahead with the duplication approach.

Sep 14 2016, 8:41 AM
asb added a comment to D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

Apologies for the slight delay, organising last week's LLVM Cauldron and other activities in my life had limited my time.

Sep 14 2016, 3:54 AM

Sep 5 2016

asb committed rL280663: Add timings for 2016 LLVM Cauldron.
Add timings for 2016 LLVM Cauldron
Sep 5 2016, 8:30 AM

Aug 31 2016

asb added inline comments to D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.
Aug 31 2016, 7:47 AM
asb added inline comments to D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.
Aug 31 2016, 5:25 AM

Aug 27 2016

asb updated the diff for D23557: [RISCV 1/10] Recognise riscv32 and riscv64 in triple parsing code.

Fix whitespace damage (thanks @emaste!)

Aug 27 2016, 1:25 AM

Aug 26 2016

asb updated the diff for D23562: [RISCV 5/10] Add bare-bones RISC-V MCTargetDesc.

Address review comment from @theraven

Aug 26 2016, 1:01 PM
asb updated subscribers of D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.
Aug 26 2016, 12:49 PM
asb updated the diff for D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td.

Rename ProcessorModels to generic-rv32 and generic-rv64 and fix incorrect immediate size spotted by @jordy.potman.lists

Aug 26 2016, 12:49 PM
asb added inline comments to D23560: [RISCV 3/10] Add stub backend.
Aug 26 2016, 6:34 AM