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dmgreen (Dave Green)
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May 24 2016, 8:35 AM (313 w, 4 d)

Recent Activity

Yesterday

dmgreen added inline comments to D77804: [DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits (WIP).
Fri, May 27, 6:37 AM · Restricted Project, Restricted Project
dmgreen added a comment to D115462: [SLP]Improve shuffles cost estimation where possible..

Thanks for the updates.

Fri, May 27, 5:42 AM · Restricted Project, Restricted Project

Thu, May 26

dmgreen accepted D125335: Give option to use isCopyInstr to determine which MI is treated as Copy instruction in MCP.

So it looks like roughly a 0.2/126 = 0.16% increase in compile time? I think that is OK for -O3, even though the expected gains will likely not be very large. It did come up as an improvement in the tests I ran though.

Thu, May 26, 9:37 AM · Restricted Project, Restricted Project
dmgreen accepted D126322: [ARM] Recognize t2LoopEnd for software pipelining.

Thanks. LGTM

Thu, May 26, 9:36 AM · Restricted Project, Restricted Project
dmgreen accepted D126234: [AArch64] Add support for FMA intrinsics to shouldSinkOperands..

From the publicly available ARM software optimization guides, it looks like the indexed/non-indexed variants should give the same performance on A57/A75, but the indexed variants have less throughput on A55. A quick glance at the scheduling model for A55 seems to indicate that this difference is not reflected in the model though.

It also looks like the same issue would exist for other indexed variants handled there. If issues show up investigating handling this more granually sounds like a good idea. We could also limit the sinking to cores where indexed and non-indexed variants have the same performance, if needed.

Thu, May 26, 9:23 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D115462: [SLP]Improve shuffles cost estimation where possible..
Thu, May 26, 8:48 AM · Restricted Project, Restricted Project
dmgreen added a comment to D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3.

as for the second I'm not sure when it would be profitable to transform back and emit the table

You really just have to weigh it against the current default expansion on targets where ctlz/cttz aren't legal, which is popcount(v & -v). It should be a straightforward comparison, generally. If you have popcount, use it. If multiply is legal, use a table lookup. Otherwise... maybe stick with the popcount expansion? Probably any approach is expensive at that point.

Compare the generated code for arm-eabi.

You may not want to do that for non-hot ctzs?

As opposed to what, calling into compiler-rt?

Thu, May 26, 8:39 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D115462: [SLP]Improve shuffles cost estimation where possible..
Thu, May 26, 8:17 AM · Restricted Project, Restricted Project
dmgreen added a comment to D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3.

Hello - We were having a discussion about a very similar patch in D125755. I think the outcome for this patch is that either:

  • We need to do this later (maybe in CodeGenPrepare).
  • We need to do this unconditionally without the call to TTI.preferCTTZLowering() and have the reverse transform later for targets that do not have a cheaper alternative.
  • We need to argue some more :)
Thu, May 26, 6:23 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D126449: [AArch64] Reuse larger DUP if available.
Thu, May 26, 2:20 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D109368: [LV] Don't vectorize if we can prove RT + vector cost >= scalar cost..
Thu, May 26, 2:19 AM · Restricted Project, Restricted Project
dmgreen committed rG75631438e333: [AArch64] Costmodel tests for llvm.vscale intrinsics. NFC (authored by dmgreen).
[AArch64] Costmodel tests for llvm.vscale intrinsics. NFC
Thu, May 26, 2:16 AM · Restricted Project, Restricted Project
dmgreen requested review of D126449: [AArch64] Reuse larger DUP if available.
Thu, May 26, 12:32 AM · Restricted Project, Restricted Project

Wed, May 25

dmgreen added inline comments to D126322: [ARM] Recognize t2LoopEnd for software pipelining.
Wed, May 25, 6:08 AM · Restricted Project, Restricted Project
dmgreen committed rG18cb3b35066e: [ARM] Fix vcvtb/t.f16 input liveness (authored by dmgreen).
[ARM] Fix vcvtb/t.f16 input liveness
Wed, May 25, 4:16 AM · Restricted Project, Restricted Project
dmgreen closed D126118: [ARM] Fix vcvtb/t.f16 input liveness.
Wed, May 25, 4:16 AM · Restricted Project, Restricted Project
dmgreen added a comment to D126234: [AArch64] Add support for FMA intrinsics to shouldSinkOperands..

I think that non-legal types will be legalized to legal types where a splat can still be used for lane indexing.
And it seems like the first two operands of a fma are commutative?
And I don't the splat index can be out of range, if we consider illegal types to be legalized.

Wed, May 25, 4:08 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125588: [MachineCombiner] Improve MachineCombiner's cost model.

Thanks - do you have AArch64 numbers? The MachineCombiner does seem to be used on X86, but to a much smaller degree than on AArch64 where there are many more patterns. The reassociation might be useful, but it is the converting madd to mul+add and the fmla changes that are more worrying.

Wed, May 25, 3:40 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

Would it be better for this be done later, by the backend? I worry that the BETC would not be calculable any more for the loop, and the new structure would be more difficult to analyze in general. Handling it separately from the vectorizer would also allow other loops to be transformed. What happens at the moment for loops with ACLE intrinsics, for example?

Hi @dmgreen, it's worth pointing out that this behaviour is toggled under a TTI interface so it is currently only enabled for SVE targets where this structure happens to be the most optimal. Any targets that rely upon the existing structure (e.g. MVE) remain unaffected.

Wed, May 25, 3:26 AM · Restricted Project, Restricted Project
dmgreen added a comment to D124612: [AArch64][LV] AArch64 does not prefer vectorized addressing.

Thanks for getting the numbers.

Wed, May 25, 3:11 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

Would it be better for this be done later, by the backend? I worry that the BETC would not be calculable any more for the loop, and the new structure would be more difficult to analyze in general. Handling it separately from the vectorizer would also allow other loops to be transformed. What happens at the moment for loops with ACLE intrinsics, for example?

Wed, May 25, 3:06 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125755: [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat.

The primary downside of target-specific transforms is that it goes against canonicalization: if a combine is expecting a specific form of IR, that form will only show up on specific targets. So we either miss some transforms on some targets, or we write code to match the same thing in each possible form.

It's always been a bit of a spectrum; transforms like inlining are fundamentally driven by heuristics, and those heuristics are going to lead to different IR on different targets. But we want to encourage using canonical forms, even when we sometimes end up transforming from A->B, then later end up transforming B->A in the target's code generator. This shapes the way we define IR to some extent; for example, llvm.cttz has an "is_zero_poison" flag so we can use the same intrinsic on all targets.

This isn't to say we can never make a target-specific decision early, but we should explore alternatives that allow making a target-specific decisions later, where possible.

Wed, May 25, 2:57 AM · Restricted Project, Restricted Project

Mon, May 23

dmgreen added a comment to D125335: Give option to use isCopyInstr to determine which MI is treated as Copy instruction in MCP.

I hadn't expected MachineCopyPropgation would be too expensive - it sounds like a simple concept and seems to already be run twice in the default pipeline. This is only adding an extra at -O3, so hopefully won't be too bad for compile time.

Mon, May 23, 9:31 AM · Restricted Project, Restricted Project
dmgreen committed rG6ef5e242f2f7: [AArch64] Fix assumptions on input type of tryCombineFixedPointConvert (authored by dmgreen).
[AArch64] Fix assumptions on input type of tryCombineFixedPointConvert
Mon, May 23, 12:56 AM · Restricted Project, Restricted Project

Sat, May 21

dmgreen committed rGa86cfaea5497: [ARM] Add register-mask for tail returns (authored by dmgreen).
[ARM] Add register-mask for tail returns
Sat, May 21, 7:29 AM · Restricted Project, Restricted Project
dmgreen closed D125906: [ARM] Add register-mask for tail returns.
Sat, May 21, 7:28 AM · Restricted Project, Restricted Project
dmgreen requested review of D126118: [ARM] Fix vcvtb/t.f16 input liveness.
Sat, May 21, 7:13 AM · Restricted Project, Restricted Project

Fri, May 20

dmgreen committed rG534ea8bca51d: [AArch64] Generate AND in place of CSEL for predicated CTTZ (authored by rahular-rrlogic).
[AArch64] Generate AND in place of CSEL for predicated CTTZ
Fri, May 20, 5:42 AM · Restricted Project, Restricted Project
dmgreen committed rGb4dd9fc370a1: [ARM] Cost modelling for MVE vector fptoi_sat (authored by dmgreen).
[ARM] Cost modelling for MVE vector fptoi_sat
Fri, May 20, 3:00 AM · Restricted Project, Restricted Project
dmgreen closed D125666: [ARM] Cost modelling for MVE vector fptoi_sat.
Fri, May 20, 3:00 AM · Restricted Project, Restricted Project
dmgreen committed rG1379b150991f: [AArch64] Fix the generation of BE Nops (authored by dmgreen).
[AArch64] Fix the generation of BE Nops
Fri, May 20, 1:31 AM · Restricted Project, Restricted Project
dmgreen closed D125980: [AArch64] Fix the generation of BE Nops.
Fri, May 20, 1:31 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125588: [MachineCombiner] Improve MachineCombiner's cost model.

Thanks for splitting this out. I've been trying to run some tests.

Fri, May 20, 12:49 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3.

Thanks for checking. Lets give this another go then. LGTM

Fri, May 20, 12:11 AM · Restricted Project, Restricted Project
dmgreen accepted D125653: [TypePromotion] Fix another case for sext vs zext in promoted constant..

OK thanks. LGTM

Fri, May 20, 12:10 AM · Restricted Project, Restricted Project

Thu, May 19

dmgreen committed rG80aab0312ace: [ARM] Cost modelling for scalar fptoi_sat (authored by dmgreen).
[ARM] Cost modelling for scalar fptoi_sat
Thu, May 19, 11:53 AM · Restricted Project, Restricted Project
dmgreen closed D125665: [ARM] Cost modelling for scalar fptoi_sat.
Thu, May 19, 11:53 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125377: [AArch64] Order STP Q's by ascending address.

So long as there is no issues from @fhahn, this LGTM.

Thu, May 19, 10:22 AM · Restricted Project, Restricted Project
dmgreen requested review of D125980: [AArch64] Fix the generation of BE Nops.
Thu, May 19, 8:16 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125956: [NOT YET FOR REVIEW][AArch64][LV] Implement AArch64TTIImpl::getRegisterClassForType.

A fair point on the vector/fp overlap, will consider.

Thu, May 19, 7:45 AM · Restricted Project, Restricted Project
dmgreen committed rG602f81ec3363: [AArch64] Fix zero element TBL indices (authored by dmgreen).
[AArch64] Fix zero element TBL indices
Thu, May 19, 5:55 AM · Restricted Project, Restricted Project
dmgreen closed D125865: [AArch64] Fix zero element TBL indices.
Thu, May 19, 5:54 AM · Restricted Project, Restricted Project
dmgreen accepted D125895: [AArch64] implement isReassocProfitable, disable for (u|s)mlal..

Sounds good to me.

Thu, May 19, 5:49 AM · Restricted Project, Restricted Project
dmgreen committed rGdd644ddf85be: [AArch64] Extend zero vector TBL codegen tests. NFC (authored by dmgreen).
[AArch64] Extend zero vector TBL codegen tests. NFC
Thu, May 19, 5:02 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125956: [NOT YET FOR REVIEW][AArch64][LV] Implement AArch64TTIImpl::getRegisterClassForType.

It might be worth teaching AArch64TTIImpl::getRegisterClassForType that fp regs and vector regs are the same thing. That would require some testing to make sure it actually produces better results though.

Thu, May 19, 4:31 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125918: [LV] Improve register pressure estimate at high VFs.

I think for the case of D118979 it makes sense to prevent maximizing the vector bandwidth for fixed-length sve. The larger vectors will already be wide enough and as far as I understand they don't benefit from the wider types in the same way that NEON does.

Thu, May 19, 4:29 AM · Restricted Project, Restricted Project
dmgreen updated subscribers of D125755: [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat.

Thanks for the comments.

Thu, May 19, 2:23 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125653: [TypePromotion] Fix another case for sext vs zext in promoted constant..

If I haven't got this wrong, this says we could just always be zexting the constant from a sub:
https://alive2.llvm.org/ce/z/kTAyt2
https://alive2.llvm.org/ce/z/a6HHq4
That sounds like it would make simpler constants too, although I'm not sure there are any tests that show it.

Thu, May 19, 1:29 AM · Restricted Project, Restricted Project

Wed, May 18

dmgreen added a comment to D125906: [ARM] Add register-mask for tail returns.

Seems to match what other targets do, so I guess it's fine. Not sure what you're planning on doing with this, though...

Wed, May 18, 12:19 PM · Restricted Project, Restricted Project
dmgreen requested review of D125906: [ARM] Add register-mask for tail returns.
Wed, May 18, 9:56 AM · Restricted Project, Restricted Project
dmgreen committed rGfc0229fd6bfd: [ARM] Clean up a test check from D125604. NFC (authored by dmgreen).
[ARM] Clean up a test check from D125604. NFC
Wed, May 18, 8:12 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125335: Give option to use isCopyInstr to determine which MI is treated as Copy instruction in MCP.

I was taking a look at some of the ARM/Thumb tests that were failing if this used TII.isCopyInstr. There are definitely some problems happening in there, with undefined register.

Wed, May 18, 7:18 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D125604: [FileCheck] Catch missspelled directives..
Wed, May 18, 6:52 AM · Restricted Project, Restricted Project, Restricted Project, Restricted Project, Restricted Project
dmgreen requested review of D125865: [AArch64] Fix zero element TBL indices.
Wed, May 18, 2:43 AM · Restricted Project, Restricted Project

Tue, May 17

dmgreen committed rG4c6a070a2ce1: [AArch64] Teach perfect shuffles tables about D-lane movs (authored by dmgreen).
[AArch64] Teach perfect shuffles tables about D-lane movs
Tue, May 17, 10:17 AM · Restricted Project, Restricted Project, Restricted Project
dmgreen closed D125477: [AArch64] Teach perfect shuffles tables about D-lane movs.
Tue, May 17, 10:16 AM · Restricted Project, Restricted Project, Restricted Project
dmgreen added a comment to D125755: [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat.

Yeah - it needs to be earlier than that, before vectorization and preferably unrolling to get the costs correct.

Tue, May 17, 5:04 AM · Restricted Project, Restricted Project
dmgreen accepted D125607: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses.

I think AArch64 should be able to do the And efficiently in most cases. There is an instcombine equivalent fold that doesn't check one-use, so from that perspective it will only be things that come up from DAG combine that this alters. I see two win vararg tests changing, with code that comes from AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC.

Tue, May 17, 5:01 AM · Restricted Project, Restricted Project
dmgreen committed rG8311fb75127d: [AArch64] Extra tests useful for D-lane shuffles. NFC (authored by dmgreen).
[AArch64] Extra tests useful for D-lane shuffles. NFC
Tue, May 17, 3:16 AM · Restricted Project, Restricted Project
dmgreen updated the summary of D125755: [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat.
Tue, May 17, 3:03 AM · Restricted Project, Restricted Project
dmgreen requested review of D125755: [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat.
Tue, May 17, 3:03 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125607: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses.

Do you know what makes the AArch64::shouldFoldConstantShiftPairToMask necessary? Is it just something about those tests, or something fundamental to the architecture?

Tue, May 17, 2:43 AM · Restricted Project, Restricted Project
dmgreen updated the summary of D125666: [ARM] Cost modelling for MVE vector fptoi_sat.
Tue, May 17, 12:40 AM · Restricted Project, Restricted Project

Mon, May 16

dmgreen committed rG5d29d752735e: [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32 (authored by dmgreen).
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32
Mon, May 16, 10:00 AM · Restricted Project, Restricted Project
dmgreen closed D125470: [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32.
Mon, May 16, 10:00 AM · Restricted Project, Restricted Project
dmgreen committed rG7272a8c23ceb: [AArch64] Update check lines in arm64-scvt.ll. NFC (authored by dmgreen).
[AArch64] Update check lines in arm64-scvt.ll. NFC
Mon, May 16, 7:51 AM · Restricted Project, Restricted Project
dmgreen committed rG4c3e51ecfa33: [AArch64] Handle 64bit vectors in tryCombineFixedPointConvert (authored by dmgreen).
[AArch64] Handle 64bit vectors in tryCombineFixedPointConvert
Mon, May 16, 3:09 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3.

Thanks for the update. Have you tried a bootstrap to make sure it passes now?

I never had any test failures even in the previous revision. How do I include all tests?

Mon, May 16, 12:24 AM · Restricted Project, Restricted Project
dmgreen requested review of D125666: [ARM] Cost modelling for MVE vector fptoi_sat.
Mon, May 16, 12:16 AM · Restricted Project, Restricted Project
dmgreen requested review of D125665: [ARM] Cost modelling for scalar fptoi_sat.
Mon, May 16, 12:16 AM · Restricted Project, Restricted Project

Fri, May 13

dmgreen added a comment to D125470: [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32.

Looks like a good fix. One quick question: I see that some CPUs have FeatureAlternateSExtLoadCVTF32Pattern set. Is that something we want too?

Fri, May 13, 1:34 AM · Restricted Project, Restricted Project
dmgreen accepted D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum.

Thanks. LGTM

Fri, May 13, 1:21 AM · Restricted Project, Restricted Project, Restricted Project

Thu, May 12

dmgreen requested review of D125477: [AArch64] Teach perfect shuffles tables about D-lane movs.
Thu, May 12, 10:28 AM · Restricted Project, Restricted Project, Restricted Project
dmgreen requested review of D125470: [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32.
Thu, May 12, 8:00 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3.

Thanks for the update. Have you tried a bootstrap to make sure it passes now?

Thu, May 12, 6:16 AM · Restricted Project, Restricted Project
dmgreen accepted D125308: [AArch64] Add missing HasNEON predicates to int->float patterns.

Cheers

Thu, May 12, 3:16 AM · Restricted Project, Restricted Project
dmgreen accepted D125240: [AArch64] Baseline test for D125307.

Thanks. LGTM

Thu, May 12, 3:15 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125240: [AArch64] Baseline test for D125307.

Do we need --asm-show-inst, or is it enough to just show the instructions? It seems quite verbose for the information it gives.

Thu, May 12, 2:06 AM · Restricted Project, Restricted Project
dmgreen accepted D125308: [AArch64] Add missing HasNEON predicates to int->float patterns.

I noticed that for signed conversions, some non-NEON instruction sequences are shorter. I don't know if the longer one is still faster on current architectures (the patterns date back to the initial backend import)

Thu, May 12, 2:06 AM · Restricted Project, Restricted Project
dmgreen updated subscribers of D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency.

Hello. This looks like two different patches.

Thu, May 12, 1:11 AM · Restricted Project, Restricted Project
dmgreen added reviewers for D125377: [AArch64] Order STP Q's by ascending address: fhahn, t.p.northover.

In order sounds sensible to me. We may need a subtarget feature for this, it depends on what the Apple folks think, but we can always add one later if needed.

Thu, May 12, 1:08 AM · Restricted Project, Restricted Project

Wed, May 11

dmgreen committed rG5feeceddb2b5: [TypePromotion] Fix sext vs zext in promoted constant (authored by dmgreen).
[TypePromotion] Fix sext vs zext in promoted constant
Wed, May 11, 2:48 AM · Restricted Project, Restricted Project
dmgreen closed D125294: [TypePromotion] Fix sext vs zext in promoted constant.
Wed, May 11, 2:47 AM · Restricted Project, Restricted Project
dmgreen added a comment to D125335: Give option to use isCopyInstr to determine which MI is treated as Copy instruction in MCP.

I thought you said you were just going to write a new pass for this? :)

Wed, May 11, 2:08 AM · Restricted Project, Restricted Project
dmgreen committed rG764a7f486472: [TypePromotion] Format Type Promotion. NFC (authored by dmgreen).
[TypePromotion] Format Type Promotion. NFC
Wed, May 11, 12:19 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3.

Yeah I think the issue is that @cttztrunc should be doing and 0x3f, not and 0x1f.

Wed, May 11, 12:07 AM · Restricted Project, Restricted Project

Tue, May 10

dmgreen added a reverting change for rG7dcd0ea683ed: [AArch64] Generate AND in place of CSEL for predicated CTTZ: rG442c351b2bb1: Revert "[AArch64] Generate AND in place of CSEL for predicated CTTZ".
Tue, May 10, 9:17 AM · Restricted Project, Restricted Project
dmgreen committed rG442c351b2bb1: Revert "[AArch64] Generate AND in place of CSEL for predicated CTTZ" (authored by dmgreen).
Revert "[AArch64] Generate AND in place of CSEL for predicated CTTZ"
Tue, May 10, 9:17 AM · Restricted Project, Restricted Project
dmgreen added a reverting change for D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3: rG442c351b2bb1: Revert "[AArch64] Generate AND in place of CSEL for predicated CTTZ".
Tue, May 10, 9:17 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3.

Oh yeah, I missed that testcase. I'll revert for now. Thanks for the report.

Tue, May 10, 8:35 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D125111: [SLP] Make reordering aware of external vectorizable scalar stores..
Tue, May 10, 8:15 AM · Restricted Project, Restricted Project
dmgreen added inline comments to D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum.
Tue, May 10, 5:54 AM · Restricted Project, Restricted Project, Restricted Project
dmgreen accepted D125237: [AArch64] Avoid emitting MOVID when NEON is disabled.

Sounds good to me.

Tue, May 10, 3:11 AM · Restricted Project, Restricted Project
dmgreen accepted D125234: [AArch64] Remove redundant f{min,max}nm intrinsics..

Sounds good to me.

Tue, May 10, 3:02 AM · Restricted Project, Restricted Project
dmgreen updated the summary of D125294: [TypePromotion] Fix sext vs zext in promoted constant.
Tue, May 10, 1:29 AM · Restricted Project, Restricted Project
dmgreen requested review of D125294: [TypePromotion] Fix sext vs zext in promoted constant.
Tue, May 10, 1:29 AM · Restricted Project, Restricted Project

Mon, May 9

dmgreen updated the diff for D123587: [SLP] Generate shuffles if we can reorder an existing node.

Rebase

Mon, May 9, 6:15 AM · Restricted Project, Restricted Project
dmgreen added a comment to D123587: [SLP] Generate shuffles if we can reorder an existing node.

No, it tries to do the same as your patch - find reused scalars in the previously build nodes and emit shuffles, if possible, instead of bunch of extracts.
The problem is that we need to track the dependencies between nodes, that's why it is so big.

Mon, May 9, 6:14 AM · Restricted Project, Restricted Project
dmgreen committed rG2cfb243bcd6a: [DAG] Use isAnyConstantBuildVector. NFC (authored by dmgreen).
[DAG] Use isAnyConstantBuildVector. NFC
Mon, May 9, 6:13 AM · Restricted Project, Restricted Project
dmgreen added inline comments to rG02f851950244: [DAG] Prevent infinite loop combining bitcast shuffle.
Mon, May 9, 5:33 AM · Restricted Project, Restricted Project