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dmgreen (Dave Green)
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May 24 2016, 8:35 AM (243 w, 3 d)

Recent Activity

Today

dmgreen accepted D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.

LGTM

Fri, Jan 22, 8:38 AM · Restricted Project
dmgreen committed rGaf0332498405: [ARM] Disable sign extended SSAT pattern recognition. (authored by dmgreen).
[ARM] Disable sign extended SSAT pattern recognition.
Fri, Jan 22, 6:08 AM
dmgreen added a comment to D94779: [Clang] Ensure vector predication pragma is ignored only when vectorization width is 1..

Thanks. @fhahn @SjoerdMeijer what do we think about the edge case where the width==1? As far as I understand (with this patch):

#pragma clang loop vectorize_predicate(disable) vectorize_width(4)
Gives llvm.loop.vectorize.predicate.enable=false, llvm.loop.vectorize.width=4, llvm.loop.vectorize.scalable.enable=false, llvm.loop.vectorize.enable=true
Fri, Jan 22, 4:17 AM · Restricted Project
dmgreen added a comment to D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.

Sounds good to me. Can you clean up the tests a little?

Fri, Jan 22, 3:32 AM · Restricted Project
dmgreen committed rG9ae73cdbc1e5: [ARM] Adjust isSaturatingConditional to return a new SDValue. NFC (authored by dmgreen).
[ARM] Adjust isSaturatingConditional to return a new SDValue. NFC
Fri, Jan 22, 3:12 AM
dmgreen committed rG476de8cea353: [ARM] Add new and regenerate SSAT tests. NFC (authored by dmgreen).
[ARM] Add new and regenerate SSAT tests. NFC
Fri, Jan 22, 2:43 AM
dmgreen accepted D94480: [NFC] [DAGCombine] Correct the result for sqrt even the iteration is zero.

but someone who knows AArch should comment.

Fri, Jan 22, 1:25 AM · Restricted Project

Yesterday

dmgreen committed rG39db5753f993: [LV][ARM] Inloop reduction cost modelling (authored by dmgreen).
[LV][ARM] Inloop reduction cost modelling
Thu, Jan 21, 1:04 PM
dmgreen closed D93476: [LV][ARM] Inloop reduction cost modelling.
Thu, Jan 21, 1:04 PM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.

Oh, that's a good idea! Updated to use InstructionCost where it can. Thanks.

Thu, Jan 21, 8:55 AM · Restricted Project
dmgreen committed rGdfac521da1b9: [ARM] Fix vector saddsat costs. (authored by dmgreen).
[ARM] Fix vector saddsat costs.
Thu, Jan 21, 7:31 AM
dmgreen accepted D95039: [SVE] Add support for scalable vectorization of loops with selects and cmps.

The code changes look simple enough, LGTM.

Thu, Jan 21, 6:40 AM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.

Rename to getExtendedAddReductionCost and adjust some hasOneUse early exits.

Thu, Jan 21, 6:35 AM · Restricted Project
dmgreen added inline comments to D93476: [LV][ARM] Inloop reduction cost modelling.
Thu, Jan 21, 6:33 AM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.
Thu, Jan 21, 4:00 AM · Restricted Project
dmgreen added inline comments to D93476: [LV][ARM] Inloop reduction cost modelling.
Thu, Jan 21, 4:00 AM · Restricted Project

Wed, Jan 20

dmgreen committed rG045d84f4e6d7: D94954: Fixes Snapdragon Kryo CPU core detection (authored by Sonicadvance1).
D94954: Fixes Snapdragon Kryo CPU core detection
Wed, Jan 20, 2:24 PM
dmgreen closed D94954: Fixes Snapdragon Kryo CPU core detection.
Wed, Jan 20, 2:24 PM · Restricted Project
dmgreen added inline comments to D94928: [llvm-mca] Add support for in-order CPUs.
Wed, Jan 20, 11:29 AM · Restricted Project
dmgreen requested review of D95073: [ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu.
Wed, Jan 20, 10:56 AM · Restricted Project
dmgreen added a comment to D93478: [LoopVectorizer] Fix invalid scenario that is allowed to interleave.

I could not replicate the bug in https://bugs.llvm.org/show_bug.cgi?id=48546 with the latest clang, as I mentioned in the ticket. Can you provide a more specific reproducer, and use it as a test case for what is being fixed?

Wed, Jan 20, 7:31 AM · Restricted Project
dmgreen added inline comments to D95039: [SVE] Add support for scalable vectorization of loops with selects and cmps.
Wed, Jan 20, 6:17 AM · Restricted Project

Tue, Jan 19

dmgreen accepted D94954: Fixes Snapdragon Kryo CPU core detection.

Thanks. LGTM

Tue, Jan 19, 11:13 PM · Restricted Project
dmgreen added a comment to D94954: Fixes Snapdragon Kryo CPU core detection.

There are some tests in llvm/unittests/Support/Host.cpp. Can you add test for these cpu's and the multiple infos you were seeing? I suppose it now gets the info from the last one?

Tue, Jan 19, 2:27 PM · Restricted Project
dmgreen requested review of D94990: [ARM] Simplify extract of VMOVDRR.
Tue, Jan 19, 11:47 AM · Restricted Project
dmgreen requested review of D94989: [ARM] Simplify VMOVRRD from extracts of buildvectors.
Tue, Jan 19, 11:42 AM · Restricted Project
dmgreen committed rG6a563eef1321: [ARM] Expand vXi1 VSELECT's (authored by dmgreen).
[ARM] Expand vXi1 VSELECT's
Tue, Jan 19, 9:57 AM
dmgreen closed D94946: [ARM] Expand vXi1 VSELECT's.
Tue, Jan 19, 9:57 AM · Restricted Project
dmgreen committed rGf373b30923d7: [ARM] Add MVE add.sat costs (authored by dmgreen).
[ARM] Add MVE add.sat costs
Tue, Jan 19, 7:39 AM
dmgreen closed D94958: [ARM] Add MVE add.sat costs.
Tue, Jan 19, 7:39 AM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.

Fix base getExtendedReductionCost to use Extend Type for the reduction cost.

Tue, Jan 19, 7:32 AM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.
Tue, Jan 19, 7:24 AM · Restricted Project
dmgreen added a comment to D93476: [LV][ARM] Inloop reduction cost modelling.

I'm not up-to-date with the current state of MVE and other Arm ISA additions, so others should feel free to chime in. :)
Instead of adding a specialization parameter for MLA to normal math reductions, would it be simpler/cleaner to add a dedicated cost model API for MLA? For example, we already distinguish min/max from other ops via getMinMaxReductionCost().

Tue, Jan 19, 7:22 AM · Restricted Project
dmgreen committed rG54e38440e74f: [ARM] Expand add.sat/sub.sat cost checks. NFC (authored by dmgreen).
[ARM] Expand add.sat/sub.sat cost checks. NFC
Tue, Jan 19, 7:06 AM
dmgreen added inline comments to D94946: [ARM] Expand vXi1 VSELECT's.
Tue, Jan 19, 2:52 AM · Restricted Project
dmgreen requested review of D94958: [ARM] Add MVE add.sat costs.
Tue, Jan 19, 2:49 AM · Restricted Project

Mon, Jan 18

dmgreen requested review of D94946: [ARM] Expand vXi1 VSELECT's.
Mon, Jan 18, 10:02 PM · Restricted Project
dmgreen added a comment to D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE.

I only looked at the ARM equivalent. From what I remember, the sequence of events was something like:

  • One of the two operands to the mul was converted from a sext to an anyext. The other was not due to having multiple uses.
  • That anyext was folded into a load to produce a zextload (we don't produce a vector anyext load)
  • We couldn't match anything due one operand being a sext and the other being a zextload.

So in that case we would either need to use demanded bits know the top bits are not needed when converting it to a mull, create an anyextload instead of a zextload or handle multiple uses so both inputs turn into anyext or zextloads.

Mon, Jan 18, 10:27 AM · Restricted Project
dmgreen added a reverting change for rG372eb2bbb6fb: [ARM] Add low overhead loops terminators to AnalyzeBranch: rGe7dc083a410f: [ARM] Don't handle low overhead branches in AnalyzeBranch.
Mon, Jan 18, 9:16 AM
dmgreen committed rGe7dc083a410f: [ARM] Don't handle low overhead branches in AnalyzeBranch (authored by dmgreen).
[ARM] Don't handle low overhead branches in AnalyzeBranch
Mon, Jan 18, 9:16 AM
dmgreen added a reverting change for D94392: [ARM] Add low overhead loops terminators to AnalyzeBranch: rGe7dc083a410f: [ARM] Don't handle low overhead branches in AnalyzeBranch.
Mon, Jan 18, 9:16 AM · Restricted Project
dmgreen committed rG69295815ed92: [ARM] Update test target triple. NFC (authored by dmgreen).
[ARM] Update test target triple. NFC
Mon, Jan 18, 8:36 AM
dmgreen accepted D94778: [AArch64] Further restricts when a dup(*ext) can be rearranged.

Thanks. Hopefully that doesn't just cause other problems :)
LGTM

Mon, Jan 18, 6:02 AM · Restricted Project
dmgreen added a comment to D94779: [Clang] Ensure vector predication pragma is ignored only when vectorization width is 1..

I believe this sentence is the important part (the width=1 is just an edge case):

For all other non-zero vectorization widths, the pragma is not ignored unless vectorization is explicitly disabled using vectorize(disable)

Mon, Jan 18, 5:59 AM · Restricted Project
dmgreen added a comment to D94867: [ARM] Make a BE predicate bitcast consistent with the rest of llvm.

We were storing predicate registers, such as a <8 x i1>, in the opposite order to how the rest of llvm expects.

It should be mentioned that it is, at least to me, unclear what llvm expects wrt this and as far as I know it is not documented anywhere. Simple experiment suggest that bit order is reversed for big endian targets

define i8 @foo() {
entry:
  %v = insertelement <8 x i1> zeroinitializer, i1 true, i8 0
  %bc = bitcast <8 x i1> %v to i8
  ret i8 %bc
}
$ llc -O3 bitcast.ll --mtriple arm -o -     # lsb is set in scalar
$ llc -O3 bitcast.ll --mtriple armeb -o -     # msb is set in scalar

with similar results for mips (big-endian) and amd64 (little-endian).

Mon, Jan 18, 12:54 AM · Restricted Project

Sat, Jan 16

dmgreen committed rG145472421535: [ARM] Align blocks that are not fallthough targets (authored by dmgreen).
[ARM] Align blocks that are not fallthough targets
Sat, Jan 16, 2:20 PM
dmgreen committed rG2a5b576e3ea4: [ARM] Test for aligned blocks. NFC (authored by dmgreen).
[ARM] Test for aligned blocks. NFC
Sat, Jan 16, 2:20 PM
dmgreen closed D94394: [ARM] Align blocks that are not fallthough targets.
Sat, Jan 16, 2:20 PM · Restricted Project
dmgreen added reviewers for D94604: [CodeGen] Allow parallel uses of a resource: steven.zhang, atrick, evgeny777, andreadb.
Sat, Jan 16, 10:38 AM · Restricted Project
dmgreen committed rG372eb2bbb6fb: [ARM] Add low overhead loops terminators to AnalyzeBranch (authored by dmgreen).
[ARM] Add low overhead loops terminators to AnalyzeBranch
Sat, Jan 16, 10:31 AM
dmgreen committed rGc1ab698dce8d: [ARM] Remove LLC tests from transform/hardware loop tests. (authored by dmgreen).
[ARM] Remove LLC tests from transform/hardware loop tests.
Sat, Jan 16, 10:31 AM
dmgreen closed D94392: [ARM] Add low overhead loops terminators to AnalyzeBranch.
Sat, Jan 16, 10:31 AM · Restricted Project
dmgreen added inline comments to D94778: [AArch64] Further restricts when a dup(*ext) can be rearranged.
Sat, Jan 16, 10:23 AM · Restricted Project
dmgreen added a comment to D94765: [WIP]Expand masked mem intrinsics correctly wrt big-endian.

Thanks for the patch. There is a patch to make MVE consistent with the rest of MVE in D94867. This will need rebasing on top of that, with update tests to make the two consistent again.

Sat, Jan 16, 9:00 AM · Restricted Project
dmgreen requested review of D94867: [ARM] Make a BE predicate bitcast consistent with the rest of llvm.
Sat, Jan 16, 8:57 AM · Restricted Project

Fri, Jan 15

dmgreen committed rGf5abf0bd485a: [ARM] Tail predication with constant loop bounds (authored by dmgreen).
[ARM] Tail predication with constant loop bounds
Fri, Jan 15, 10:18 AM
dmgreen closed D94608: [ARM] Tail predication with constant loop bounds.
Fri, Jan 15, 10:18 AM · Restricted Project
dmgreen committed rGa0770f9e4e92: [ARM] Constant tripcount tail predication loop tests. NFC (authored by dmgreen).
[ARM] Constant tripcount tail predication loop tests. NFC
Fri, Jan 15, 10:02 AM
dmgreen accepted D94780: [ARM][Block placement] Check the predecessor exists before processing it.

Thanks. LGTM

Fri, Jan 15, 7:10 AM · Restricted Project
dmgreen accepted D94671: [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - improve shuffle(shuffle(x,y),shuffle(x,y)) merging.

LGTM. We sometimes generate a lot of shuffles in an attempt to do lane interleaving and I know the simplification of them isn't always what it could be once all the lowering has happened. I thought more happened through simplifying buildvectors but apparently not. This looks like a good continuation to the existing code.

Fri, Jan 15, 6:09 AM · Restricted Project
dmgreen added a comment to D93476: [LV][ARM] Inloop reduction cost modelling.

Ping

Fri, Jan 15, 5:39 AM · Restricted Project

Wed, Jan 13

dmgreen accepted D94620: [NFC] Disallow unused prefixes under MC/ARM.

Yeah, LGTM

Wed, Jan 13, 11:52 PM · Restricted Project
dmgreen requested review of D94608: [ARM] Tail predication with constant loop bounds.
Wed, Jan 13, 8:43 AM · Restricted Project
dmgreen accepted D91271: [AArch64] Attempt to sink mul operands.

Thanks for the changes. LGTM

Wed, Jan 13, 6:05 AM · Restricted Project
dmgreen committed rGc29ca8551aff: [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors (authored by dmgreen).
[ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors
Wed, Jan 13, 12:51 AM
dmgreen closed D94189: [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors.
Wed, Jan 13, 12:51 AM · Restricted Project
dmgreen committed rG3aeb30d1a68a: [ARM] Additional tests for different interleaving patterns. NFC (authored by dmgreen).
[ARM] Additional tests for different interleaving patterns. NFC
Wed, Jan 13, 12:32 AM

Mon, Jan 11

dmgreen updated the diff for D94034: [ARM] Flatten identity shuffles through vqdmulh nodes.

Fix typo.

Mon, Jan 11, 11:52 AM · Restricted Project
dmgreen added inline comments to D91271: [AArch64] Attempt to sink mul operands.
Mon, Jan 11, 6:11 AM · Restricted Project
dmgreen accepted D94398: [ARM] Add uses for locals introduced for debug messages. NFC..

Oh yeah. Sorry. Forgot about that.

Mon, Jan 11, 3:41 AM · Restricted Project
dmgreen added inline comments to D93629: [LV] Don't sink into replication regions.
Mon, Jan 11, 2:25 AM · Restricted Project
dmgreen committed rG8165a0342033: [ARM] Add debug messages for the load store optimizer. NFC (authored by dmgreen).
[ARM] Add debug messages for the load store optimizer. NFC
Mon, Jan 11, 1:25 AM
dmgreen requested review of D94394: [ARM] Align blocks that are not fallthough targets.
Mon, Jan 11, 1:23 AM · Restricted Project
dmgreen committed rGdcefcd51e017: [ARM] Update trunc costs (authored by dmgreen).
[ARM] Update trunc costs
Mon, Jan 11, 1:00 AM
dmgreen closed D94260: [ARM] Update trunc costs.
Mon, Jan 11, 12:59 AM · Restricted Project
dmgreen requested review of D94392: [ARM] Add low overhead loops terminators to AnalyzeBranch.
Mon, Jan 11, 12:58 AM · Restricted Project
dmgreen committed rG0c8b748f3217: [ARM] Additional trunc cost tests. NFC (authored by dmgreen).
[ARM] Additional trunc cost tests. NFC
Mon, Jan 11, 12:35 AM

Fri, Jan 8

dmgreen committed rG024af42c6010: [ARM] Custom lower i1 vector truncates (authored by dmgreen).
[ARM] Custom lower i1 vector truncates
Fri, Jan 8, 10:21 AM
dmgreen closed D94226: [ARM] Custom lower i1 vector truncates.
Fri, Jan 8, 10:21 AM · Restricted Project
dmgreen updated the diff for D93476: [LV][ARM] Inloop reduction cost modelling.

Rebase and ping. I also adjusted some code and better dealt with loop invariant operands.

Fri, Jan 8, 9:10 AM · Restricted Project
dmgreen added a comment to D94226: [ARM] Custom lower i1 vector truncates.

Thanks. I made a typo in the summary, it should have said "do not seem to be correct", not "do seem...".

Fri, Jan 8, 8:15 AM · Restricted Project
dmgreen committed rGe185b1dd7b34: [ConstProp] Constant propagation for get.active.lane.mask instrinsics (authored by dmgreen).
[ConstProp] Constant propagation for get.active.lane.mask instrinsics
Fri, Jan 8, 8:10 AM
dmgreen closed D94103: [ConstProp] Constant propagation for get.active.lane.mask instrinsics.
Fri, Jan 8, 8:10 AM · Restricted Project
dmgreen committed rGa36a2864c0d4: [ARM][LV] Additional loop invariant reduction test. NFC (authored by dmgreen).
[ARM][LV] Additional loop invariant reduction test. NFC
Fri, Jan 8, 7:15 AM
dmgreen committed rG1ae762469fd1: [ARM] Update and regenerate test checks. NFC (authored by dmgreen).
[ARM] Update and regenerate test checks. NFC
Fri, Jan 8, 6:54 AM
dmgreen committed rG72fb5ba07901: [LV] Don't sink into replication regions (authored by dmgreen).
[LV] Don't sink into replication regions
Fri, Jan 8, 1:50 AM
dmgreen closed D93629: [LV] Don't sink into replication regions.
Fri, Jan 8, 1:50 AM · Restricted Project
dmgreen added a comment to D93629: [LV] Don't sink into replication regions.

Thanks Florian.

Fri, Jan 8, 1:44 AM · Restricted Project
dmgreen added a comment to D90094: [BasicAA] Handle recursive queries more efficiently (NFCI).

Hello. I tried running our downstream benchmarks with this patch and it did not appear to have any effect, either in performance or codesize. (That doesn't mean that nothing is effected, but it's at least a good sign).

Fri, Jan 8, 1:42 AM · Restricted Project

Thu, Jan 7

dmgreen accepted D94234: [AArch64] Fix crash caused by invalid vector element type.

LGTM thanks, but please try and simplify the test case if you can.

Thu, Jan 7, 2:55 PM · Restricted Project
dmgreen requested review of D94260: [ARM] Update trunc costs.
Thu, Jan 7, 1:28 PM · Restricted Project
dmgreen requested review of D94226: [ARM] Custom lower i1 vector truncates.
Thu, Jan 7, 4:33 AM · Restricted Project
dmgreen added inline comments to D91271: [AArch64] Attempt to sink mul operands.
Thu, Jan 7, 3:06 AM · Restricted Project

Wed, Jan 6

dmgreen requested review of D94189: [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors.
Wed, Jan 6, 12:50 PM · Restricted Project
dmgreen accepted D91255: [AArch64] Rearrange mul(dup(sext/zext)) to mul(sext/zext(dup)).

Thanks. LGTM with a couple of suggestions.

Wed, Jan 6, 5:44 AM · Restricted Project
dmgreen added inline comments to D93629: [LV] Don't sink into replication regions.
Wed, Jan 6, 3:47 AM · Restricted Project
dmgreen updated the diff for D93629: [LV] Don't sink into replication regions.

Added a unit test, that caught that the Parent was not set correctly.

Wed, Jan 6, 3:47 AM · Restricted Project
dmgreen committed rG63dce70b794e: [ARM] Handle any extend whilst lowering addw/addl/subw/subl (authored by dmgreen).
[ARM] Handle any extend whilst lowering addw/addl/subw/subl
Wed, Jan 6, 3:27 AM
dmgreen closed D93835: [ARM] Handle any extend whilst lowering addw/addl/subw/subl.
Wed, Jan 6, 3:27 AM · Restricted Project
dmgreen committed rGddb82fc76ceb: [ARM] Handle any extend whilst lowering mull (authored by dmgreen).
[ARM] Handle any extend whilst lowering mull
Wed, Jan 6, 2:51 AM