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arsenm (Matt Arsenault)
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Dec 5 2012, 4:53 PM (333 w, 1 h)

Recent Activity

Today

arsenm added inline comments to D61045: [AMDGPU] gfx1010 sgpr register changes.
Wed, Apr 24, 10:38 AM · Restricted Project

Yesterday

arsenm added a comment to D60052: Add Connex vector processor back end.

There's a lot of clutter that makes this hard to review. All of the extra debug, special ifdef blocks, and commented out code should be removed.

Tue, Apr 23, 2:20 PM · Restricted Project
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

Also needs a comment explaining why LCSSA is needed

Tue, Apr 23, 7:08 AM · Restricted Project
arsenm requested changes to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

This should really be expressed as a pass dependency, not explicitly adding the pass to the pipeline

Tue, Apr 23, 7:03 AM · Restricted Project
arsenm added inline comments to D60999: AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies.
Tue, Apr 23, 6:20 AM · Restricted Project

Mon, Apr 22

arsenm committed rG2b744665308f: Use const DebugLoc& (authored by arsenm).
Use const DebugLoc&
Mon, Apr 22, 12:13 PM
arsenm committed rGf84ce75cd1c4: AMDGPU: Skip debug instructions in assert (authored by arsenm).
AMDGPU: Skip debug instructions in assert
Mon, Apr 22, 12:13 PM
arsenm committed rL358910: Use const DebugLoc&.
Use const DebugLoc&
Mon, Apr 22, 12:12 PM
arsenm committed rL358909: AMDGPU: Skip debug instructions in assert.
AMDGPU: Skip debug instructions in assert
Mon, Apr 22, 12:12 PM
arsenm committed rG2b6f76f05f74: AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources (authored by arsenm).
AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources
Mon, Apr 22, 8:23 AM
arsenm committed rL358894: AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources.
AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources
Mon, Apr 22, 8:22 AM
arsenm committed rG8f624abc1d99: GlobalISel: Legalize scalar G_EXTRACT sources (authored by arsenm).
GlobalISel: Legalize scalar G_EXTRACT sources
Mon, Apr 22, 8:09 AM
arsenm committed rL358892: GlobalISel: Legalize scalar G_EXTRACT sources.
GlobalISel: Legalize scalar G_EXTRACT sources
Mon, Apr 22, 8:08 AM
arsenm closed D60315: AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources.

r358892

Mon, Apr 22, 8:08 AM
arsenm committed rG70346d127be6: AMDGPU: Fix not checking for copy when looking at copy src (authored by arsenm).
AMDGPU: Fix not checking for copy when looking at copy src
Mon, Apr 22, 7:54 AM
arsenm added a comment to D59772: AMDGPU: Remove unnecessary check for isFullCopy.

Hi Matt,

This change introduces a regression with Overwatch and RADV (cf. https://bugs.freedesktop.org/show_bug.cgi?id=110476).

Here's the attached LLVM IR https://pastebin.com/raw/VqRF4unW

Can you have a look?
Thanks!

Mon, Apr 22, 7:54 AM
arsenm committed rL358890: AMDGPU: Fix not checking for copy when looking at copy src.
AMDGPU: Fix not checking for copy when looking at copy src
Mon, Apr 22, 7:54 AM
arsenm accepted D60462: [TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling.

LGTM

Mon, Apr 22, 6:54 AM · Restricted Project
arsenm updated the diff for D60858: AMDGPU: Skip debug instructions in assert.

Reduce test a bit

Mon, Apr 22, 6:33 AM

Thu, Apr 18

arsenm added a comment to D60858: AMDGPU: Skip debug instructions in assert.

Looks ok to me. Are you worried about the correctness of the code? That seems to be a lot of matching?

Thu, Apr 18, 1:44 PM
arsenm added a comment to D54366: RegAllocFast: Add heuristic to detect values not live-out of a block.

ping

Thu, Apr 18, 11:43 AM · Restricted Project
arsenm added a comment to D60602: [InferAddressSpaces] Add AS parameter to the pass factory.

The AMDGPU usage could be changed to use this instead of TTI. There’s no real difference

Thu, Apr 18, 7:30 AM · Restricted Project
arsenm added a comment to D60858: AMDGPU: Skip debug instructions in assert.

I could do a MIR test that only runs the asm printer, which will be less useful whenever the long branch expansion is fixed

Thu, Apr 18, 5:09 AM
arsenm added a comment to D60858: AMDGPU: Skip debug instructions in assert.

FWIW they're fine IMO too :)

Testcase and match seem a little long - any chance of shrinking either?

Thu, Apr 18, 4:48 AM
arsenm added a comment to D60858: AMDGPU: Skip debug instructions in assert.

Are the function attributes in the test necessary? Watching other reviews leads me to believe these are undesirable. Apart from this it LGTMy untrained eyes (I'm new to reviewing!).

Thu, Apr 18, 3:35 AM
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

I think there are some misunderstandings here. None of the IR passes require LCSSA. The problem is in getting the divergence data into the SelectionDAG.

Specifically, you can have, in a weird mixture of IR and SelectionDAG:

loop:
  ...
  %uni = ...                             ; Value is uniform here
  ...
  br i1 %div, label %loop, label %next   ; Divergent loop exit

next:
  %0 = CopyFromReg N(corresponding to %uni)
  use %0

In this case, %0 must be labeled divergent. However, %0 does not exist at an IR level, and so the code in isSDNodeSourceOfDivergence can only query for the divergence of %uni. However, %uni itself is uniform.

One way to look at the problem is that DivergenceAnalysis::isDivergent is really "isDivergentAtDefinition", and what we need is a query "isDivergentAtUse". Implementing that query isn't entirely trivial, and LCSSA is effectively an alternative way of making the right query.

Thu, Apr 18, 3:01 AM · Restricted Project
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

I am hitting this assert in LuxMark with this patch:
Assertion failed: (IncomingDef->isPHI()), function lowerPhis, file ../lib/Target/AMDGPU/SILowerI1Copies.cpp, line 534.
Stack dump:
0. Program arguments: /Users/matt/src/llvm/build_debug/bin/clang -cc1 -triple amdgcn-amd-amdhsa -emit-obj -disable-free -main-file-name t_9348_21.bc -mrelocation-model pic -pic-level 1 -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fvisibility hidden -fapply-global-visibility-to-externs -target-cpu gfx900 -target-feature -wavefrontsize16 -target-feature -wavefrontsize32 -target-feature +wavefrontsize64 -target-feature -sram-ecc -target-feature -code-object-v3 -target-feature +cumode -dwarf-column-info -debugger-tuning=gdb -resource-dir /home/marsenau/builds/opencl_amdgpu_scratch/bin/lib/clang/8.0 -O3 -fdebug-compilation-dir /home/marsenau/src/LuxMark-3.1 -ferror-limit 19 -fmessage-length 201 -cl-kernel-arg-info -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -mllvm -amdgpu-internalize-symbols -mllvm -amdgpu-early-inline-all -o /tmp/t_9348_21-9f1436.o -x ir AMD_9348_7/t_9348_21.bc -faddrsig

  1. Code generation
  2. Running pass 'CallGraph Pass Manager' on module 'AMD_9348_7/t_9348_21.bc'.
  3. Running pass 'SI Lower i1 Copies' on function '@scheduler'

0 clang 0x0000000109a1f8bc llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 60
1 clang 0x0000000109a1fe79 PrintStackTraceSignalHandler(void*) + 25
2 clang 0x0000000109a1db36 llvm::sys::RunSignalHandlers() + 118
3 clang 0x0000000109a23a42 SignalHandler(int) + 210
4 libsystem_platform.dylib 0x00007fff7ddd1b5d _sigtramp + 29
5 libsystem_platform.dylib 0x000000012a983938 _sigtramp + 2897944056
6 libsystem_c.dylib 0x00007fff7dc916a6 abort + 127
7 libsystem_c.dylib 0x00007fff7dc5a20d basename_r + 0
8 clang 0x0000000106af4af5 (anonymous namespace)::SILowerI1Copies::lowerPhis() + 1141
9 clang 0x0000000106af40ba (anonymous namespace)::SILowerI1Copies::runOnMachineFunction(llvm::MachineFunction&) + 186
10 clang 0x000000010860f8de llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 542
11 clang 0x0000000108bfab35 llvm::FPPassManager::runOnFunction(llvm::Function&) + 613
12 clang 0x0000000107f5c8ad (anonymous namespace)::CGPassManager::RunPassOnSCC(llvm::Pass*, llvm::CallGraphSCC&, llvm::CallGraph&, bool&, bool&) + 925
13 clang 0x0000000107f596ed (anonymous namespace)::CGPassManager::RunAllPassesOnSCC(llvm::CallGraphSCC&, llvm::CallGraph&, bool&) + 541
14 clang 0x0000000107f58ec1 (anonymous namespace)::CGPassManager::runOnModule(llvm::Module&) + 433
15 clang 0x0000000108bfb8d5 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) + 789

Thu, Apr 18, 3:01 AM · Restricted Project
arsenm created D60858: AMDGPU: Skip debug instructions in assert.
Thu, Apr 18, 2:22 AM
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

It sort of intuitively makes sense to me that the control flow lowering would like LCSSA. However, this should not be handled by adding it directly to the pass pipeline. You can add this as a dependency, e.g. AU.addRequiredID(LCSSAID);

I would also like to see the an IR->IR testcase showing LCSSA was implicitly run

Actually, what really requires LCSSA? Is it DivergenceAnalysis or StructurizeCFG directly?

How I understand the problem is that DA is not looking across blocks and therefore won't see that tmp62 is actually divergent in loop exit (though it is uniform in the loop). LCSSA provides a phi node for the loop exit block (where it is divergent) and allows DA to mark it divergent so that the s_buffer_load can be lowered to a buffer_load.

Thu, Apr 18, 12:27 AM · Restricted Project

Wed, Apr 17

arsenm accepted D60844: [GISel]: IRTranslator: Prefer a buidInstr form that allows CSE of cast instructions.

LGTM

Wed, Apr 17, 4:05 PM · Restricted Project
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

It sort of intuitively makes sense to me that the control flow lowering would like LCSSA. However, this should not be handled by adding it directly to the pass pipeline. You can add this as a dependency, e.g. AU.addRequiredID(LCSSAID);

I would also like to see the an IR->IR testcase showing LCSSA was implicitly run

Wed, Apr 17, 1:49 PM · Restricted Project
arsenm added a comment to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

It sort of intuitively makes sense to me that the control flow lowering would like LCSSA. However, this should not be handled by adding it directly to the pass pipeline. You can add this as a dependency, e.g. AU.addRequiredID(LCSSAID);

Wed, Apr 17, 1:42 PM · Restricted Project
arsenm requested changes to D60834: [AMDGPU] Uniform values being used outside loop marked non-divergent.

This is a workaround. The structurizer / annotator must be correct without relying on another pass to hide situations they don't handle correctly

Wed, Apr 17, 12:58 PM · Restricted Project
arsenm accepted D60602: [InferAddressSpaces] Add AS parameter to the pass factory.

LGTM

Wed, Apr 17, 12:08 PM · Restricted Project
arsenm accepted D59971: [GlobalISel] Add legalization support for non-power-2 loads and stores.

LGTM

Wed, Apr 17, 12:08 PM · Restricted Project
arsenm added inline comments to D59917: [SelectionDAG][FIX] Allow "returned" arguments to be bit-casted.
Wed, Apr 17, 6:13 AM · Restricted Project
arsenm added inline comments to D59917: [SelectionDAG][FIX] Allow "returned" arguments to be bit-casted.
Wed, Apr 17, 6:13 AM · Restricted Project
arsenm accepted D60767: [AMDGPU][MC] Parser cleanup and refactoring.

LGTM

Wed, Apr 17, 6:08 AM · Restricted Project
arsenm added a comment to D60772: [AMDGPU] Add optional bounds checking for scratch accesses.

If the goal is to have a semantically always dereferencable stack pointer, I think we need to create a new addrspace. It would then be a no-op addrspacecast from an alloca, which the frontend desiring safe stack access would be responsible for inserting. We would then need to track the current global stack size in the ABI somewhere, and selection would need to insert this kind of bounds check code based on that

Wed, Apr 17, 5:28 AM · Restricted Project
arsenm added a comment to D60772: [AMDGPU] Add optional bounds checking for scratch accesses.

I don't understand the problem being solved here. Who/what is this intended to benefit? An out of bounds access is going to be undefined. I don't want to start trying to define in at an arbitrary point in the backend. Crashing on the invalid access is much easier problem to debug. This seems to be a partial replacement for asan? If this is intended as some user visible semantic fix, that requires more thought and probably needs to be a new address space.

Wed, Apr 17, 5:19 AM · Restricted Project
arsenm accepted D60679: [LowerAtomic] Lower fadd and fsub atomicrmw instructions.

LGTM

Wed, Apr 17, 5:00 AM · Restricted Project
arsenm accepted D60633: [AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0)).

LGTM

Wed, Apr 17, 4:59 AM · Restricted Project
arsenm added a comment to D60602: [InferAddressSpaces] Add AS parameter to the pass factory.

This is still requiring the TTI as a dependency, so I don't understand what this solves?

Wed, Apr 17, 4:59 AM · Restricted Project
arsenm added inline comments to D60640: AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT.
Wed, Apr 17, 4:59 AM · Restricted Project
arsenm added inline comments to D60799: Add a getSizeInBits() accessor to MachineMemOperand. NFC..
Wed, Apr 17, 2:42 AM · Restricted Project
arsenm added inline comments to D59971: [GlobalISel] Add legalization support for non-power-2 loads and stores.
Wed, Apr 17, 2:41 AM · Restricted Project
arsenm accepted D60731: [AMDGPU] Flag new raw/struct atomic ops as source of divergence.

LGTM

Wed, Apr 17, 2:27 AM · Restricted Project

Tue, Apr 16

arsenm added inline comments to D59971: [GlobalISel] Add legalization support for non-power-2 loads and stores.
Tue, Apr 16, 12:38 AM · Restricted Project
arsenm added a comment to D59971: [GlobalISel] Add legalization support for non-power-2 loads and stores.

Reviving this as the overall approach was fine, it seems the alignment of non pow2 types is assumed to be the alignment of the next largest pow-2 type, so we don't need to worry about alignment during the breakdown.

I did however change the legalization method to not use extracts/inserts, but instead use extending loads and truncating stores, so that the artifacts get combined away and it Just Works.

Tue, Apr 16, 12:33 AM · Restricted Project

Mon, Apr 15

arsenm added a comment to D60731: [AMDGPU] Flag new raw/struct atomic ops as source of divergence.

The test should go with the rest in test/Analysis/DivergenceAnalysis

Mon, Apr 15, 2:45 PM · Restricted Project
arsenm committed rG101abd219b3d: AMDGPU: Fix unreachable when counting register usage of SGPR96 (authored by arsenm).
AMDGPU: Fix unreachable when counting register usage of SGPR96
Mon, Apr 15, 1:50 PM
arsenm committed rL358447: AMDGPU: Fix unreachable when counting register usage of SGPR96.
AMDGPU: Fix unreachable when counting register usage of SGPR96
Mon, Apr 15, 1:49 PM
arsenm added inline comments to D58982: DAG: allow DAG pointer size different from memory representation..
Mon, Apr 15, 1:47 PM · Restricted Project
arsenm committed rGfbdd2a18874d: AMDGPU: Fix printed format of SReg_96 (authored by arsenm).
AMDGPU: Fix printed format of SReg_96
Mon, Apr 15, 1:42 PM
arsenm committed rL358446: AMDGPU: Fix printed format of SReg_96.
AMDGPU: Fix printed format of SReg_96
Mon, Apr 15, 1:42 PM
arsenm accepted D58984: DAG: propagate ConsecutiveRegs flags to returns too..

LGTM

Mon, Apr 15, 4:14 AM · Restricted Project
arsenm added inline comments to D58983: DAG: propagate whether an arg is a pointer for CallingConv decisions..
Mon, Apr 15, 4:10 AM · Restricted Project
arsenm accepted D58983: DAG: propagate whether an arg is a pointer for CallingConv decisions..

LGTM

Mon, Apr 15, 4:10 AM · Restricted Project
arsenm added inline comments to D58982: DAG: allow DAG pointer size different from memory representation..
Mon, Apr 15, 4:04 AM · Restricted Project
arsenm added a comment to D58233: Allow replacing intrinsic operands with variables.

ping

Mon, Apr 15, 3:53 AM
arsenm added a comment to D60679: [LowerAtomic] Lower fadd and fsub atomicrmw instructions.

This still needs tests, but it seems this duplicate pass thing could use some work. Both passes have essentially the same switch to turn the atomic into the equivalent non-atomic. It seems to be me like AtomicExpandPass is a superset of LowerAtomic, except AtomicExpand seems to ignore fences

Mon, Apr 15, 3:41 AM · Restricted Project
arsenm added a reviewer for D60679: [LowerAtomic] Lower fadd and fsub atomicrmw instructions: reames.
Mon, Apr 15, 3:39 AM · Restricted Project
arsenm added a comment to D60682: [AMDGPU] Fixed +DumpCode.

Do we really still need DumpCode? I've long wanted to remove it. Is there any real obstacle remaining to users switching to some combination of the assembler and disassembler?

Mon, Apr 15, 3:25 AM · Restricted Project
arsenm added a comment to D60633: [AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0)).
In D60633#1466195, @tpr wrote:

I have cut down the test a bit more and put it into fneg-combines.ll. I did not manage to repro any problems with the other cases that I added fixes for.

I don't have a massive amount of time to spend on this. Would you prefer I land it as is, without tests for the other cases, or remove the precautionary fix for those cases and wait for someone else to possibly encounter them?

Mon, Apr 15, 3:25 AM · Restricted Project
arsenm added a comment to D60679: [LowerAtomic] Lower fadd and fsub atomicrmw instructions.

Apparently we have both lib/CodeGEn/AtomicExpandPass.cpp, and lib/Transforms/Scalar/LowerAtomic.cpp. It's unclear to me what the difference is, or why both exist

Mon, Apr 15, 3:17 AM · Restricted Project
arsenm added a comment to D60679: [LowerAtomic] Lower fadd and fsub atomicrmw instructions.

Needs tests. Also I'm about 90% sure I added this already?

Mon, Apr 15, 3:11 AM · Restricted Project
arsenm updated the diff for D54366: RegAllocFast: Add heuristic to detect values not live-out of a block.

Rebase

Mon, Apr 15, 2:05 AM · Restricted Project

Sun, Apr 14

arsenm updated the diff for D60315: AMDGPU/GlobalISel: Fix non-power-of-2 G_EXTRACT sources.

Fix UnableToLegalize

Sun, Apr 14, 2:10 PM

Sat, Apr 13

arsenm accepted D60652: [AMDGPU] Fixed incorrect test in vcnd/vcmp optimization.

LGTM. We should probably start matching these though

Sat, Apr 13, 1:06 PM · Restricted Project

Fri, Apr 12

arsenm added inline comments to D60633: [AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0)).
Fri, Apr 12, 1:28 PM · Restricted Project
arsenm added inline comments to D60381: FileCheck [1/12]: Move variable table in new object.
Fri, Apr 12, 1:02 AM · Restricted Project
arsenm added a comment to D60597: Fix lib/Target/* layering issues by merging InstPrinter into MCTargetDesc.

I don't understand exactly what the layering issue you're fixing is. Can you elaborate in the commit message?

Fri, Apr 12, 12:58 AM

Thu, Apr 11

arsenm added inline comments to D60459: SILoadStoreOptimizer pass schedules s_add,s_addc with interfering s_lshl.
Thu, Apr 11, 12:54 PM · Restricted Project
arsenm added inline comments to D60387: FileCheck [7/12]: Arbitrary long numeric expressions.
Thu, Apr 11, 12:51 PM · Restricted Project
arsenm added inline comments to D60385: FileCheck [5/12]: Introduce regular numeric variables.
Thu, Apr 11, 12:46 PM · Restricted Project
arsenm added inline comments to D60384: FileCheck [4/12]: Introduce @LINE numeric expressions.
Thu, Apr 11, 12:37 PM · Restricted Project
arsenm added inline comments to D60383: FileCheck [3/12]: Stricter parsing of @LINE expressions.
Thu, Apr 11, 12:34 PM · Restricted Project
arsenm added inline comments to D60382: FileCheck [2/12]: Stricter parsing of -D option.
Thu, Apr 11, 12:34 PM · Restricted Project
arsenm added inline comments to D60381: FileCheck [1/12]: Move variable table in new object.
Thu, Apr 11, 12:12 PM · Restricted Project
arsenm added inline comments to D60386: FileCheck [6/12]: Introduce numeric variable definition.
Thu, Apr 11, 11:50 AM · Restricted Project
arsenm added inline comments to D60534: [AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers.
Thu, Apr 11, 11:11 AM · Restricted Project
arsenm added inline comments to D60534: [AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers.
Thu, Apr 11, 10:44 AM · Restricted Project
arsenm added inline comments to D45308: [IPRA] Do not collect register usage information on functions that can be derefined.
Thu, Apr 11, 9:48 AM · Restricted Project

Wed, Apr 10

arsenm added inline comments to D60534: [AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers.
Wed, Apr 10, 2:06 PM · Restricted Project
arsenm committed rG2064e45ce35a: GlobalISel: Move computeValueLLTs (authored by arsenm).
GlobalISel: Move computeValueLLTs
Wed, Apr 10, 10:27 AM
arsenm committed rG0aab99902ba5: GlobalISel: Fix invoke lowering creating invalid type registers (authored by arsenm).
GlobalISel: Fix invoke lowering creating invalid type registers
Wed, Apr 10, 10:27 AM
arsenm committed rG7187272b2bcb: GlobalISel: Support legalizing G_CONSTANT with irregular breakdown (authored by arsenm).
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
Wed, Apr 10, 10:27 AM
arsenm closed D60338: GlobalISel: Move computeValueLLTs.

r358111

Wed, Apr 10, 10:27 AM
arsenm closed D60339: GlobalISel: Fix invoke lowering creating invalid type registers.

r358110

Wed, Apr 10, 10:26 AM
arsenm committed rL358111: GlobalISel: Move computeValueLLTs.
GlobalISel: Move computeValueLLTs
Wed, Apr 10, 10:26 AM
arsenm committed rL358110: GlobalISel: Fix invoke lowering creating invalid type registers.
GlobalISel: Fix invoke lowering creating invalid type registers
Wed, Apr 10, 10:26 AM
arsenm closed D60280: GlobalISel: Support legalizing G_CONSTANT with irregular breakdown.

r358109

Wed, Apr 10, 10:26 AM
arsenm committed rL358109: GlobalISel: Support legalizing G_CONSTANT with irregular breakdown.
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
Wed, Apr 10, 10:26 AM
arsenm committed rG9e0eeba56928: GlobalISel: Handle odd breakdowns for bit ops (authored by arsenm).
GlobalISel: Handle odd breakdowns for bit ops
Wed, Apr 10, 10:10 AM
arsenm committed rL358105: GlobalISel: Handle odd breakdowns for bit ops.
GlobalISel: Handle odd breakdowns for bit ops
Wed, Apr 10, 10:10 AM
arsenm closed D60277: GlobalISel: Handle odd breakdowns for bit ops.

r358105

Wed, Apr 10, 10:09 AM
arsenm added a comment to D60457: [CodeGen] Fixed de-optimization of legalize subvector extract.

Can you reduce the test further?

Wed, Apr 10, 3:38 AM · Restricted Project

Tue, Apr 9

arsenm requested changes to D60459: SILoadStoreOptimizer pass schedules s_add,s_addc with interfering s_lshl.

You should use computeRegisterLiveness instead of adding a more naive search for a def, which may not exist.

Tue, Apr 9, 6:44 AM · Restricted Project

Sat, Apr 6

arsenm accepted D59506: [ValueTracking][InstSimplify] Support min/max selects in computeConstantRange().

LGTM, although if -O0 works that would be preferable to introducing a new pass control flag

Sat, Apr 6, 9:26 AM · Restricted Project

Fri, Apr 5

arsenm added a comment to D60339: GlobalISel: Fix invoke lowering creating invalid type registers.

Is there a reasonably sized test?

Fri, Apr 5, 2:59 PM