Page MenuHomePhabricator

arsenm (Matt Arsenault)
User

Projects

User does not belong to any projects.

User Details

User Since
Dec 5 2012, 4:53 PM (342 w, 4 h)

Recent Activity

Today

arsenm added inline comments to D63851: [AMDGPU] Packed thread ids in function call ABI.
Wed, Jun 26, 4:49 PM
arsenm added inline comments to D63849: AMDGPU: Make s34 the FP register.
Wed, Jun 26, 4:15 PM
arsenm created D63849: AMDGPU: Make s34 the FP register.
Wed, Jun 26, 3:54 PM
arsenm committed rGc0cad9836342: AMDGPU: Assert SPAdj is 0 (authored by arsenm).
AMDGPU: Assert SPAdj is 0
Wed, Jun 26, 1:58 PM
arsenm committed rG47345534aacc: PEI: Add default handling of spills to registers (authored by arsenm).
PEI: Add default handling of spills to registers
Wed, Jun 26, 1:57 PM
arsenm committed rL364473: AMDGPU: Assert SPAdj is 0.
AMDGPU: Assert SPAdj is 0
Wed, Jun 26, 1:57 PM
arsenm committed rL364472: PEI: Add default handling of spills to registers.
PEI: Add default handling of spills to registers
Wed, Jun 26, 1:57 PM
arsenm closed D63825: PEI: Add default handling of spills to registers.

r364472

Wed, Jun 26, 1:57 PM
arsenm added a comment to D63525: LangRef: Attempt to formulate some rules for addrspacecast.

ping

Wed, Jun 26, 1:40 PM
arsenm committed rG6a87e0fc6ab4: [AMDGPU] Fix Livereg computation during epilogue insertion (authored by arsenm).
[AMDGPU] Fix Livereg computation during epilogue insertion
Wed, Jun 26, 1:39 PM
arsenm closed D63765: [AMDGPU] Fix Livereg computation during epilogue insertion.

r364470

Wed, Jun 26, 1:35 PM · Restricted Project
arsenm committed rL364470: [AMDGPU] Fix Livereg computation during epilogue insertion.
[AMDGPU] Fix Livereg computation during epilogue insertion
Wed, Jun 26, 1:35 PM
arsenm accepted D63712: [AMDGPU] Fix +DumpCode to print an entry label for the first function.

LGTM, but I really don't like how this keeps getting put off

Wed, Jun 26, 1:34 PM · Restricted Project
arsenm closed D63659: Update phis in AMDGPUUnifyDivergentExitNodes.

Looks like this was r364342

Wed, Jun 26, 1:31 PM
arsenm accepted D63494: [AMDGPU] Fix for branch offset hardware workaround.

LGTM

Wed, Jun 26, 9:53 AM · Restricted Project
arsenm added a comment to D63825: PEI: Add default handling of spills to registers.

Any way we can get a test case for this? Other than that, LGTM.

Wed, Jun 26, 9:04 AM
arsenm created D63825: PEI: Add default handling of spills to registers.
Wed, Jun 26, 8:18 AM
arsenm created D63824: AMDGPU: Add pass to lower SGPR spills.
Wed, Jun 26, 8:14 AM
arsenm added a comment to D63808: AMDGPU/GFX10: fix scratch resource descriptor.

Needs test

Wed, Jun 26, 6:53 AM · Restricted Project
arsenm committed rG5f798f134659: AMDGPU: Fix unused variable (authored by arsenm).
AMDGPU: Fix unused variable
Wed, Jun 26, 6:50 AM
arsenm committed rL364426: AMDGPU: Fix unused variable.
AMDGPU: Fix unused variable
Wed, Jun 26, 6:50 AM
arsenm committed rGe0b844346061: AMDGPU: Check MRI for callee saved regs instead of TRI (authored by arsenm).
AMDGPU: Check MRI for callee saved regs instead of TRI
Wed, Jun 26, 6:41 AM
arsenm closed D63796: AMDGPU: Check MRI for callee saved regs instead of TRI.

r364425

Wed, Jun 26, 6:40 AM
arsenm committed rL364425: AMDGPU: Check MRI for callee saved regs instead of TRI.
AMDGPU: Check MRI for callee saved regs instead of TRI
Wed, Jun 26, 6:39 AM
arsenm created D63819: AMDGPU/GlobalISel: Improve icmp selection coverage..
Wed, Jun 26, 6:16 AM

Yesterday

arsenm added a comment to D63410: AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane.

ping

Tue, Jun 25, 6:28 PM
arsenm created D63799: AMDGPU/GlobalISel: Fix scc->vcc copy handling.
Tue, Jun 25, 5:53 PM
arsenm created D63798: AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT.
Tue, Jun 25, 5:49 PM
arsenm updated the diff for D63420: AMDGPU: Fix s.buffer.load being marked as readnone.

Fix selection

Tue, Jun 25, 5:44 PM
arsenm commandeered D63520: AMDGPU: Use ReversePostOrder when fixing i1 copies.
Tue, Jun 25, 4:27 PM · Restricted Project
arsenm updated the diff for D63520: AMDGPU: Use ReversePostOrder when fixing i1 copies.
Tue, Jun 25, 4:27 PM · Restricted Project
arsenm accepted D63795: Fix leaks in LLVMCreateDisasmCPUFeatures.
Tue, Jun 25, 4:08 PM · Restricted Project
arsenm created D63796: AMDGPU: Check MRI for callee saved regs instead of TRI.
Tue, Jun 25, 4:08 PM
arsenm added a comment to D63520: AMDGPU: Use ReversePostOrder when fixing i1 copies.

Diff looks wrong and is missing test

Tue, Jun 25, 4:01 PM · Restricted Project
arsenm committed rG8fcc70f14148: Don't look for the TargetFrameLowering in the implementation (authored by arsenm).
Don't look for the TargetFrameLowering in the implementation
Tue, Jun 25, 1:56 PM
arsenm committed rL364349: Don't look for the TargetFrameLowering in the implementation.
Don't look for the TargetFrameLowering in the implementation
Tue, Jun 25, 1:56 PM
arsenm accepted D63780: [AMDGPU] Removed dead SIMachineFunctionInfo::getWorkItemIDVGPR().
Tue, Jun 25, 11:32 AM · Restricted Project
arsenm accepted D63765: [AMDGPU] Fix Livereg computation during epilogue insertion.

LGTM

Tue, Jun 25, 10:20 AM · Restricted Project
arsenm accepted D63776: [AVR] Adjust to Register class change.
Tue, Jun 25, 9:42 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

I think things are going from from this heuristic:

// Heuristics #3: If the common subexpression is used by PHIs, do not reuse
// it unless the defined value is already used in the BB of the new use.
bool HasPHI = false;
for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
  HasPHI |= UseMI.isPHI();
  if (UseMI.getParent() == MI->getParent())
    return true;
}
Tue, Jun 25, 9:05 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

Other targets seem to not have this problem with a slightly generalized version, so I would look into how this is cleaned up there

It seems we're missing a simplifycfg run somewhere, so maybe we're thinking of this on the wrong level entirely.. If I run simplify cfg on any of the testcase variants, this problem disappears

Other targets seem to run SimiplifyCFG after AtomicExpand, which we are missing. Even with that disabled and the phi survives to machineinstrs, aarch64 and hexagon both avoid this

Tue, Jun 25, 8:51 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

Other targets seem to not have this problem with a slightly generalized version, so I would look into how this is cleaned up there

It seems we're missing a simplifycfg run somewhere, so maybe we're thinking of this on the wrong level entirely.. If I run simplify cfg on any of the testcase variants, this problem disappears

Tue, Jun 25, 8:51 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

Other targets seem to not have this problem with a slightly generalized version, so I would look into how this is cleaned up there

Tue, Jun 25, 8:24 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.
Tue, Jun 25, 8:17 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

Reduced further: https://paste.debian.net/1089194

Tue, Jun 25, 8:11 AM · Restricted Project
arsenm added a comment to D63731: [AMDGPU] Prevent VGPR copies from moving across the EXEC mask definitions.

I'm still not convinced just sticking EXEC reads on copies like this is a complete solution. Yes, we'll now insert the exec read on any copies that came out of isel, but any pass could introduce new copies. I guess if generic passes were more restricted when copies have implicit uses? It would require careful auditing of any generic code that can introduce copies, and may be more pessimizing than we really want

Tue, Jun 25, 7:21 AM
arsenm committed rL364316: AMDGPU/GlobalISel: Fix broken test.
AMDGPU/GlobalISel: Fix broken test
Tue, Jun 25, 7:02 AM
arsenm committed rGf4e51dd2cd5b: AMDGPU/GlobalISel: Fix broken test (authored by arsenm).
AMDGPU/GlobalISel: Fix broken test
Tue, Jun 25, 7:00 AM
arsenm created D63766: AMDGPU/GlobalISel: Use and instead of BFE with inline immediate.
Tue, Jun 25, 6:50 AM
arsenm committed rL364309: AMDGPU/GlobalISel: Fix duplicated test.
AMDGPU/GlobalISel: Fix duplicated test
Tue, Jun 25, 6:32 AM
arsenm committed rGdcd8b72e1a7e: AMDGPU/GlobalISel: Fix duplicated test (authored by arsenm).
AMDGPU/GlobalISel: Fix duplicated test
Tue, Jun 25, 6:31 AM
arsenm committed rL364308: AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT.
AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT
Tue, Jun 25, 6:31 AM
arsenm committed rGd7ffa2a94833: AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT (authored by arsenm).
AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT
Tue, Jun 25, 6:27 AM
arsenm committed rL364304: AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly.
AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly
Tue, Jun 25, 6:20 AM
arsenm committed rGd1dc1f4901ae: AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly (authored by arsenm).
AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly
Tue, Jun 25, 6:18 AM
arsenm closed D63751: AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT.

r364308

Tue, Jun 25, 6:18 AM
arsenm closed D63749: AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly.

r364304

Tue, Jun 25, 6:13 AM
arsenm added inline comments to D63751: AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT.
Tue, Jun 25, 5:45 AM

Mon, Jun 24

arsenm created D63751: AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT.
Mon, Jun 24, 8:23 PM
arsenm created D63749: AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly.
Mon, Jun 24, 6:22 PM
arsenm committed rG25bc27965a43: AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class (authored by arsenm).
AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class
Mon, Jun 24, 6:08 PM
arsenm committed rL364262: AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class.
AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class
Mon, Jun 24, 6:07 PM
arsenm created D63746: MachineFrameInfo: Make StackSize Optional..
Mon, Jun 24, 5:30 PM
arsenm committed rG5495f7816560: AMDGPU: Fix missing declaration for mbcnt builtins (authored by arsenm).
AMDGPU: Fix missing declaration for mbcnt builtins
Mon, Jun 24, 4:36 PM
arsenm committed rL364251: AMDGPU: Fix missing declaration for mbcnt builtins.
AMDGPU: Fix missing declaration for mbcnt builtins
Mon, Jun 24, 4:36 PM
arsenm added inline comments to D62766: [Attributor] Deduce "nosync" function attribute..
Mon, Jun 24, 3:43 PM · Restricted Project
arsenm committed rG2100caf7f68b: AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor (authored by arsenm).
AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor
Mon, Jun 24, 3:22 PM
arsenm committed rL364244: AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor.
AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor
Mon, Jun 24, 3:21 PM
arsenm accepted D61493: AMDGPU/MC: Add .amdgpu_lds directive.

LGTM

Mon, Jun 24, 3:17 PM · Restricted Project
arsenm accepted D59657: [LangRef] Clarify codegen expectations for intrinsics with fp/integer-only overloads.

LGTM

Mon, Jun 24, 3:11 PM · Restricted Project
arsenm committed rG80258425999b: InstCombine: Preserve nuw when reassociating nuw ops [3/3] (authored by arsenm).
InstCombine: Preserve nuw when reassociating nuw ops [3/3]
Mon, Jun 24, 2:39 PM
arsenm committed rG5d82ecd5d952: InstCombine: Preserve nuw when reassociating nuw ops [2/3] (authored by arsenm).
InstCombine: Preserve nuw when reassociating nuw ops [2/3]
Mon, Jun 24, 2:39 PM
arsenm committed rG5a89ba7343a6: InstCombine: Preserve nuw when reassociating nuw ops [1/3] (authored by arsenm).
InstCombine: Preserve nuw when reassociating nuw ops [1/3]
Mon, Jun 24, 2:38 PM
arsenm committed rL364235: InstCombine: Preserve nuw when reassociating nuw ops [3/3].
InstCombine: Preserve nuw when reassociating nuw ops [3/3]
Mon, Jun 24, 2:38 PM
arsenm committed rL364234: InstCombine: Preserve nuw when reassociating nuw ops [2/3].
InstCombine: Preserve nuw when reassociating nuw ops [2/3]
Mon, Jun 24, 2:38 PM
arsenm closed D63528: InstCombine: Preserve nuw when reassociating nuw ops [3/3].

r364235

Mon, Jun 24, 2:38 PM
arsenm committed rL364233: InstCombine: Preserve nuw when reassociating nuw ops [1/3].
InstCombine: Preserve nuw when reassociating nuw ops [1/3]
Mon, Jun 24, 2:38 PM
arsenm closed D39417: InstCombine: Preserve nuw when reassociating nuw ops [1/3].

r364233

Mon, Jun 24, 2:37 PM
arsenm closed D63527: InstCombine: Preserve nuw when reassociating nuw ops [2/3].

r364234

Mon, Jun 24, 2:37 PM
arsenm added a comment to D63712: [AMDGPU] Fix +DumpCode to print an entry label for the first function.
In D63712#1555460, @tpr wrote:

I don't think anyone is a fan of dumpcode. But we're still in the position that the proper disassembler does not support gfx6 or gfx7, and we need to get this particular problem fixed in the short term.

Mon, Jun 24, 2:28 PM · Restricted Project
arsenm added a comment to D62739: AMDGPU: Always emit amdgpu-flat-work-group-size.

ping

Mon, Jun 24, 2:22 PM
arsenm added inline comments to D63731: [AMDGPU] Prevent VGPR copies from moving across the EXEC mask definitions.
Mon, Jun 24, 11:29 AM
arsenm committed rGdbb6c0317539: AMDGPU/GlobalISel: Select G_TRUNC (authored by arsenm).
AMDGPU/GlobalISel: Select G_TRUNC
Mon, Jun 24, 11:03 AM
arsenm committed rL364215: AMDGPU/GlobalISel: Select G_TRUNC.
AMDGPU/GlobalISel: Select G_TRUNC
Mon, Jun 24, 11:02 AM
arsenm closed D63698: AMDGPU/GlobalISel: Select G_TRUNC.

r364215

Mon, Jun 24, 11:02 AM
arsenm committed rG14d0b646b7b9: AMDGPU/GlobalISel: RegBankSelect for amdgcn.class (authored by arsenm).
AMDGPU/GlobalISel: RegBankSelect for amdgcn.class
Mon, Jun 24, 11:02 AM
arsenm committed rL364214: AMDGPU/GlobalISel: RegBankSelect for amdgcn.class.
AMDGPU/GlobalISel: RegBankSelect for amdgcn.class
Mon, Jun 24, 11:01 AM
arsenm committed rG8fcd5ade3e5e: AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect (authored by arsenm).
AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect
Mon, Jun 24, 10:55 AM
arsenm committed rL364212: AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect.
AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect
Mon, Jun 24, 10:55 AM
arsenm closed D63715: AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect.

r364212

Mon, Jun 24, 10:55 AM
arsenm added inline comments to D63709: [AMDGPU] Add peephole to optimize MOV.
Mon, Jun 24, 10:53 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

I do suspect the handling of the EXEC physreg use in MachineCSE. I don't see any of the typical sources of late visible constants in this testcase?

Mon, Jun 24, 10:15 AM · Restricted Project
arsenm added a comment to D63709: [AMDGPU] Add peephole to optimize MOV.

This opt opportunity presents itself after the register coalescer, where inline constants are moved to the same registers (attaching IR example testcase imminently). MachineCSE is run too early to spot this and the last occurence of si-shrink-instructions is run at the right time. I think, for similar reasons some other peepholes were also placed in this pass, even though they are not about 32-bit encoding.

Mon, Jun 24, 10:06 AM · Restricted Project
arsenm updated the diff for D63485: AMDGPU/GlobalISel: Improve regbankselect for icmp s16.

Fix test diff

Mon, Jun 24, 9:30 AM
arsenm updated the diff for D63484: AMDGPU/GlobalISel: Make s16 G_ICMP legal.

Remove tests that belong with the next patch

Mon, Jun 24, 9:28 AM
arsenm committed rGf8a841b88e2e: AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1 (authored by arsenm).
AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1
Mon, Jun 24, 9:27 AM
arsenm committed rL364199: AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1.
AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1
Mon, Jun 24, 9:24 AM
arsenm closed D63414: AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1.
Mon, Jun 24, 9:24 AM
arsenm committed rGae171f1e9fe3: Hexagon: Rename another copy of Register class (authored by arsenm).
Hexagon: Rename another copy of Register class
Mon, Jun 24, 9:18 AM
arsenm added a comment to D63413: AMDGPU/GlobalISel: RegBankSelect for WWM/WQM.

ping

Mon, Jun 24, 9:18 AM