Page MenuHomePhabricator

arsenm (Matt Arsenault)
User

Projects

User does not belong to any projects.

User Details

User Since
Dec 5 2012, 4:53 PM (349 w, 4 d)

Recent Activity

Yesterday

arsenm updated the diff for D66387: AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE.

Test fixes

Sun, Aug 18, 3:03 PM
arsenm created D66402: AMDGPU/GlobalISel: Select atomic loads.
Sun, Aug 18, 2:50 PM
arsenm created D66400: AMDGPU: Remove code address space predicates.
Sun, Aug 18, 2:26 PM
arsenm added a child revision for D66385: AMDGPU/GlobalISel: Fix load/store of types in other address spaces: D66400: AMDGPU: Remove code address space predicates.
Sun, Aug 18, 2:26 PM
arsenm added a parent revision for D66400: AMDGPU: Remove code address space predicates: D66385: AMDGPU/GlobalISel: Fix load/store of types in other address spaces.
Sun, Aug 18, 2:26 PM
arsenm updated the diff for D66385: AMDGPU/GlobalISel: Fix load/store of types in other address spaces.

Missed one

Sun, Aug 18, 2:12 PM
arsenm added a comment to D66309: Introduce infrastructure for an incremental port of SelectionDAG atomic load/store handling.

This will help atomic store handling for global isel. Right now there's a complication because ISD::ATOMIC_STORE swaps the operand order from a normal store

Sun, Aug 18, 12:05 PM · Restricted Project
arsenm accepted D65756: [GlobalISel] Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands.

LGTM

Sun, Aug 18, 11:28 AM · Restricted Project
arsenm added a comment to D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..

I think the standard for what is committed for the triple is quite low. We already have out of tree targets included in the upstream triple, so it doesn't really matter what happens with the follow up patches. This should be fine to commit without waiting for the rest of the backend review

Sun, Aug 18, 11:05 AM · Restricted Project
arsenm accepted D65644: [AMDGPU] gfx10 atomic optimizer changes..

LGTM

Sun, Aug 18, 8:21 AM · Restricted Project

Sat, Aug 17

arsenm added a child revision for D66388: AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace: D66389: AMDGPU/GlobalISel: Legalize constant 32-bit loads.
Sat, Aug 17, 9:39 PM
arsenm created D66389: AMDGPU/GlobalISel: Legalize constant 32-bit loads.
Sat, Aug 17, 9:39 PM
arsenm added a parent revision for D66389: AMDGPU/GlobalISel: Legalize constant 32-bit loads: D66388: AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace.
Sat, Aug 17, 9:39 PM
arsenm updated the diff for D66388: AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace.

Fix for SI

Sat, Aug 17, 9:39 PM
arsenm updated the diff for D66388: AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace.
Sat, Aug 17, 9:01 PM
arsenm created D66388: AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace.
Sat, Aug 17, 8:57 PM
arsenm added a parent revision for D66387: AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE: D66386: AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads.
Sat, Aug 17, 8:14 PM
arsenm added a child revision for D66386: AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads: D66387: AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE.
Sat, Aug 17, 8:14 PM
arsenm created D66387: AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE.
Sat, Aug 17, 8:14 PM
arsenm created D66386: AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads.
Sat, Aug 17, 6:47 PM
arsenm updated the diff for D66385: AMDGPU/GlobalISel: Fix load/store of types in other address spaces.
Sat, Aug 17, 5:52 PM
arsenm created D66385: AMDGPU/GlobalISel: Fix load/store of types in other address spaces.
Sat, Aug 17, 5:51 PM
arsenm added a comment to D66180: [GlobalISel][CallLowering] Add support for splitting types according to calling conventions.

I'm somewhat confused by what the responsibilities of handleAssignments are vs. target code. I already have multiple register breakdowns without this patch in AMDGPU

Sat, Aug 17, 5:28 PM · Restricted Project
arsenm committed rG479f3bdb2c87: AMDGPU: Fix iterator error when lowering SI_END_CF (authored by arsenm).
AMDGPU: Fix iterator error when lowering SI_END_CF
Sat, Aug 17, 5:22 PM
arsenm committed rGcfdc2b9bd92b: AMDGPU: Disambiguate v3f16 format in load/store tables (authored by arsenm).
AMDGPU: Disambiguate v3f16 format in load/store tables
Sat, Aug 17, 5:21 PM
arsenm committed rG8651ec6a8449: TableGen: Revert changes from r369038 (authored by arsenm).
TableGen: Revert changes from r369038
Sat, Aug 17, 5:21 PM
arsenm committed rL369203: AMDGPU: Fix iterator error when lowering SI_END_CF.
AMDGPU: Fix iterator error when lowering SI_END_CF
Sat, Aug 17, 5:20 PM
arsenm closed D66382: AMDGPU: Fix iterator error when lowering SI_END_CF.

r369203

Sat, Aug 17, 5:20 PM
arsenm committed rL369202: AMDGPU: Disambiguate v3f16 format in load/store tables.
AMDGPU: Disambiguate v3f16 format in load/store tables
Sat, Aug 17, 5:20 PM
arsenm closed D65719: AMDGPU: Disambiguate v3f16 format in load/store tables.

r369203

Sat, Aug 17, 5:19 PM
arsenm committed rL369201: TableGen: Revert changes from r369038.
TableGen: Revert changes from r369038
Sat, Aug 17, 5:19 PM
arsenm added a comment to D65413: GlobalISel: Implement moreElementsVector for G_UNMERGE_VALUES sources.

ping

Sat, Aug 17, 5:00 PM
arsenm updated the diff for D58232: GlobalISel: Don't materialize immarg arguments to intrinsics.

Use common tablegen test target

Sat, Aug 17, 4:55 PM
arsenm updated the diff for D58232: GlobalISel: Don't materialize immarg arguments to intrinsics.

Manually fix hexagon

Sat, Aug 17, 4:48 PM
arsenm created D66382: AMDGPU: Fix iterator error when lowering SI_END_CF.
Sat, Aug 17, 1:43 PM

Fri, Aug 16

arsenm added a comment to D64931: Change X86 datalayout for three address spaces that specify pointer sizes..

Address space have backend defined semantics, and aren’t really reserved for front end use. I think the fact that non-0 address spaces on X86 codegen the same as address space 0 and could be used for something by a front end is an accident of how SelectionDAG is implemented. If X86 wants to reserve address space ranges for frontend use, that would need to be decided and documented. You don’t necessarily get the current behavior for free in GlobalISel since pointer types are distinct, so this would specifically need to be implemented.

By this do you mean that this would be an instance of address spaces being used by the frontend? Or just that adding meaning to address spaces shouldn't be breaking other frontends?

Fri, Aug 16, 2:31 PM · Restricted Project, Restricted Project

Thu, Aug 15

arsenm committed rG1f2b727298de: MVT: Add v3i16/v3f16 vectors (authored by arsenm).
MVT: Add v3i16/v3f16 vectors
Thu, Aug 15, 12:01 PM
arsenm committed rL369038: MVT: Add v3i16/v3f16 vectors.
MVT: Add v3i16/v3f16 vectors
Thu, Aug 15, 11:58 AM
arsenm closed D65683: MVT: Add v3i16/v3f16 vectors.

r369038

Thu, Aug 15, 11:57 AM
arsenm added a comment to D65542: [PeepholeOptimizer] Don't assume bitcast def always has input.

@arsenm Is this MIR test OK?

Thu, Aug 15, 10:48 AM · Restricted Project
arsenm added inline comments to D65542: [PeepholeOptimizer] Don't assume bitcast def always has input.
Thu, Aug 15, 10:09 AM · Restricted Project
arsenm added a comment to D58232: GlobalISel: Don't materialize immarg arguments to intrinsics.

ping

Thu, Aug 15, 9:30 AM
arsenm added inline comments to D66287: GlobalISel: add combiner for indexed loads and stores.
Thu, Aug 15, 9:05 AM · Restricted Project
arsenm added inline comments to D66287: GlobalISel: add combiner for indexed loads and stores.
Thu, Aug 15, 9:02 AM · Restricted Project

Wed, Aug 14

arsenm accepted D66246: [AMDGPU] Do not assume a default GCN target.

LGTM

Wed, Aug 14, 1:35 PM · Restricted Project
arsenm added inline comments to D66246: [AMDGPU] Do not assume a default GCN target.
Wed, Aug 14, 1:15 PM · Restricted Project
arsenm committed rG0b864bb04322: AMDGPU: Reduce number of registers in test (authored by arsenm).
AMDGPU: Reduce number of registers in test
Wed, Aug 14, 12:10 PM
arsenm committed rL368901: AMDGPU: Reduce number of registers in test.
AMDGPU: Reduce number of registers in test
Wed, Aug 14, 12:09 PM
arsenm added a comment to D66197: AMDGPU: Add intrinsics for address space identification.

Do we really need these to be "amdgpu" specific?

Are you envisioning these would be used for OpenCL implementations? OpenCL doesn't exactly have these. It instead has to_<addrspacename> functions which return NULL if the generic pointer isn't actually pointing at a object in <addrrspacename>.

We (will) have various languages/targets that have corresponding address spaces and we already reserve some numbers for specific address spaces (afaik), why not make this a generic functionality.

The IR doesn't reserve any numbers for specific usage (except 0 has some special properties, which do not include being a flat/generic pointer as defined in OpenCL). It might make more sense to add a clang builtin for this, which could then be implemented with the target specific intrinsic. I don't want to add a generic target intrinsic while guessing at how this might work on other targets. Something truly generic, like llvm.is.address.space(ptr, address_space_id) I don't think really works generally enough to add. There isn't necessarily a 1:1 mapping between the language address space and IR address space. There could possibly be multiple IR address spaces to handle, and not all targets might be able to do this test at all

I see, still, we have llvm.nvvm.isspacep.const and friends already. Now we get llvm.amdgcn.is.private, which seems to be the same thing for amdgpu. As long as people only use this in the backend, great, but if we want middle-end passes that deal with address spaces and optimize accordingly, e.g., introduce data movement, we should have generic intrinsics or helper functions. I would prefer the former and I was curious if there is a problem with that. If the folding (I described earlier) is triple/target specific, sure, but if we do not have multiple llvm.XYZ.is.private we would simplify things.

Wed, Aug 14, 12:06 PM
arsenm added a comment to D66197: AMDGPU: Add intrinsics for address space identification.

Do we really need these to be "amdgpu" specific?

Are you envisioning these would be used for OpenCL implementations? OpenCL doesn't exactly have these. It instead has to_<addrspacename> functions which return NULL if the generic pointer isn't actually pointing at a object in <addrrspacename>.

We (will) have various languages/targets that have corresponding address spaces and we already reserve some numbers for specific address spaces (afaik), why not make this a generic functionality.

Wed, Aug 14, 11:49 AM
arsenm committed rGdbc1f207fa72: InferAddressSpaces: Move target intrinsic handling to TTI (authored by arsenm).
InferAddressSpaces: Move target intrinsic handling to TTI
Wed, Aug 14, 11:13 AM
arsenm committed rL368895: InferAddressSpaces: Move target intrinsic handling to TTI.
InferAddressSpaces: Move target intrinsic handling to TTI
Wed, Aug 14, 11:12 AM
arsenm closed D66170: InferAddressSpaces: Move target intrinsic handling to TTI.

r368895

Wed, Aug 14, 11:12 AM
arsenm added a comment to D66197: AMDGPU: Add intrinsics for address space identification.

Do we really need these to be "amdgpu" specific?

Wed, Aug 14, 11:12 AM
arsenm committed rG0eac2a296398: InferAddressSpaces: Remove unnecessary check for ConstantInt (authored by arsenm).
InferAddressSpaces: Remove unnecessary check for ConstantInt
Wed, Aug 14, 11:05 AM
arsenm committed rL368893: InferAddressSpaces: Remove unnecessary check for ConstantInt.
InferAddressSpaces: Remove unnecessary check for ConstantInt
Wed, Aug 14, 11:01 AM
arsenm updated the diff for D66198: AMDGPU: Add builtins for is_local/is_private.

rename

Wed, Aug 14, 10:43 AM
arsenm updated the diff for D66197: AMDGPU: Add intrinsics for address space identification.

Rename

Wed, Aug 14, 10:43 AM
arsenm updated the diff for D66170: InferAddressSpaces: Move target intrinsic handling to TTI.

Also move operand collection to TTI

Wed, Aug 14, 9:27 AM
arsenm added a comment to D66197: AMDGPU: Add intrinsics for address space identification.

Looks fine to me. Thanks!

Wed, Aug 14, 8:40 AM
arsenm created D66223: AMDGPU/GlobalISel: Fix assert on load from constant address.
Wed, Aug 14, 8:36 AM
arsenm added inline comments to D66170: InferAddressSpaces: Move target intrinsic handling to TTI.
Wed, Aug 14, 7:51 AM

Tue, Aug 13

arsenm added a parent revision for D66198: AMDGPU: Add builtins for is_local/is_private: D66197: AMDGPU: Add intrinsics for address space identification.
Tue, Aug 13, 11:16 PM
arsenm added a child revision for D66197: AMDGPU: Add intrinsics for address space identification: D66198: AMDGPU: Add builtins for is_local/is_private.
Tue, Aug 13, 11:16 PM
arsenm added parent revisions for D66197: AMDGPU: Add intrinsics for address space identification: D66196: AMDGPU/GlobalISel: Restore insert point when getting aperture, D66194: AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast, D66170: InferAddressSpaces: Move target intrinsic handling to TTI.
Tue, Aug 13, 11:16 PM
arsenm added a child revision for D66170: InferAddressSpaces: Move target intrinsic handling to TTI: D66197: AMDGPU: Add intrinsics for address space identification.
Tue, Aug 13, 11:16 PM
arsenm created D66198: AMDGPU: Add builtins for is_local/is_private.
Tue, Aug 13, 11:16 PM
arsenm added a child revision for D66196: AMDGPU/GlobalISel: Restore insert point when getting aperture: D66197: AMDGPU: Add intrinsics for address space identification.
Tue, Aug 13, 11:16 PM
arsenm added a child revision for D66194: AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast: D66197: AMDGPU: Add intrinsics for address space identification.
Tue, Aug 13, 11:16 PM
arsenm created D66197: AMDGPU: Add intrinsics for address space identification.
Tue, Aug 13, 11:13 PM
arsenm created D66196: AMDGPU/GlobalISel: Restore insert point when getting aperture.
Tue, Aug 13, 11:04 PM
arsenm created D66194: AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast.
Tue, Aug 13, 10:11 PM
arsenm added inline comments to D66181: [AArch64][GlobalISel] Add support for narrowScalar of G_ZEXT.
Tue, Aug 13, 5:23 PM · Restricted Project
arsenm accepted D66182: [GlobalISel]: Fix lowering of G_Shuffle_vector where we pick up the wrong source index.

LGTM, although I copied this from the DAG lowering, which does seem to use the result number of elements?

Tue, Aug 13, 4:35 PM · Restricted Project
arsenm accepted D66171: [GlobalISel]: Fix lowering of G_SHUFFLE_VECTOR with scalar sources.

LGTM, although I rather dislike that we allow these. Maybe the IRTranslator should be trying to turn these into the equivalent G_BUILD_VECTOR?

Tue, Aug 13, 2:33 PM · Restricted Project
arsenm created D66170: InferAddressSpaces: Move target intrinsic handling to TTI.
Tue, Aug 13, 2:29 PM
arsenm created D66150: GlobalISel: Don't create G_UADDE with constant false carry in.
Tue, Aug 13, 10:26 AM
arsenm added a comment to D54368: RegAllocFast: Record internal state based on register units.

ping

Tue, Aug 13, 10:17 AM · Restricted Project
arsenm added a comment to D65440: GlobalISel: Add widenScalar for G_UNMERGE_VALUES sources.

ping

Tue, Aug 13, 10:17 AM
arsenm accepted D65962: Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM.

LGTM

Tue, Aug 13, 9:46 AM · Restricted Project
arsenm committed rG28215caa60a4: GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES (authored by arsenm).
GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES
Tue, Aug 13, 9:29 AM
arsenm committed rL368713: GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES.
GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES
Tue, Aug 13, 9:26 AM
arsenm closed D65412: GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES.

r368713

Tue, Aug 13, 9:26 AM
arsenm added a comment to D65473: GlobalISel: Avoid widening unmerge with matching source type.

ping

Tue, Aug 13, 9:16 AM
arsenm committed rG690645bda088: GlobalISel: Implement lower for G_SHUFFLE_VECTOR (authored by arsenm).
GlobalISel: Implement lower for G_SHUFFLE_VECTOR
Tue, Aug 13, 9:10 AM
arsenm committed rL368709: GlobalISel: Implement lower for G_SHUFFLE_VECTOR.
GlobalISel: Implement lower for G_SHUFFLE_VECTOR
Tue, Aug 13, 9:10 AM
arsenm added a comment to D64899: AMDGPU/GlobalISel: First pass at attempting to legalize load/stores.

ping

Tue, Aug 13, 9:10 AM
arsenm closed D66111: GlobalISel: Implement lower for G_SHUFFLE_VECTOR.

r368709

Tue, Aug 13, 9:08 AM
arsenm added inline comments to D66145: [DebugInfo] Allow bundled calls in the MIR's call site info.
Tue, Aug 13, 9:02 AM · Restricted Project, debug-info
arsenm committed rG0a04a062500e: GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR (authored by arsenm).
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR
Tue, Aug 13, 8:54 AM
arsenm committed rL368705: GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR.
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR
Tue, Aug 13, 8:51 AM
arsenm closed D66118: GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR.

r368705

Tue, Aug 13, 8:51 AM
arsenm committed rG5af9cf042f21: GlobalISel: Change representation of shuffle masks (authored by arsenm).
GlobalISel: Change representation of shuffle masks
Tue, Aug 13, 8:38 AM
arsenm committed rL368704: GlobalISel: Change representation of shuffle masks.
GlobalISel: Change representation of shuffle masks
Tue, Aug 13, 8:37 AM
arsenm added a comment to D66109: GlobalISel: Change representation of shuffle masks.

Thanks for doing this. Overall the patch LGTM. On a side note, should we try to document all the links we have to IR in GlobalISel somewhere?

Not sure where that would go

Perhaps in the bottom of https://www.llvm.org/docs/GlobalISel.html ? Alternatively we can document in GenericOpcodes.td right along the instructions which have links.

I added a note to GenericOpcodes.td

Tue, Aug 13, 8:37 AM
arsenm closed D66109: GlobalISel: Change representation of shuffle masks.

r368704

Tue, Aug 13, 8:37 AM
arsenm accepted D66133: [AMDGPU] Fix to 'Fold readlane from copy of SGPR or imm'.

LGTM

Tue, Aug 13, 8:26 AM · Restricted Project
arsenm updated the diff for D65683: MVT: Add v3i16/v3f16 vectors.

Fix size

Tue, Aug 13, 8:05 AM

Mon, Aug 12

arsenm accepted D65685: Eliminate implicit Register->unsigned conversions in VirtRegMap. NFC.

LGTM

Mon, Aug 12, 4:40 PM · Restricted Project
arsenm updated the diff for D66111: GlobalISel: Implement lower for G_SHUFFLE_VECTOR.

Use buildBiuildVector

Mon, Aug 12, 4:36 PM