In D60260#1499005, @nikic wrote:

This looks good, but please also update existing tests that specify three types in the intrinstic name. Here's ones I found:

• test/CodeGen/X86/haddsub.ll
• test/CodeGen/X86/vector-reduce-fadd-fast.ll
• test/CodeGen/X86/vector-reduce-fadd.ll
• test/CodeGen/X86/vector-reduce-fmul-fast.ll
• test/CodeGen/X86/vector-reduce-fmul.ll

Good spot! I've updated these tests now.

• Updated more tests.

In D61437#1501444, @thegameg wrote:

This sounds like it will report the wrong stack size in PEI for the StackSize remark and the stack size warning. Is that expected?

For now the answer is yes. One of our primary concerns at the moment is adding basic SVE spill/fill support and we appreciate the caveat that nothing in LLVM really supports the concept of scalable types yet, including offsets and sizes.

In D61437#1498210, @efriedma wrote:

If the SVE spill area is below the CSRs, you can leverage the existing checks to handle stack realignment, so I don't think it's that complicated to implement. But maybe your approach requires changing fewer places.

I think you've made some compelling reasons to try the change in layout! I'll actually try this out downstream first before updating this patch, so I can run it through our SVE testing and see if there is any impact on performance or if I run into anything unexpected.

In D61437#1498242, @efriedma wrote:

Ignore the bit about Windows unwinding. I remembered how it actually works; the Microsoft document is just wrong, and it's not actually necessary to allocate the frame record in any particular position on WIndows (except that it has to be somewhere that isn't allocated using _chkstk... but that wouldn't happen anyway with the layout I'm suggesting).

Thanks for clarifying!

In D60261#1499008, @nikic wrote:

Rereading the ML discussion just now, it looks like the consensus is to go with this option. Move forward?

Thanks for the prod! I've sent an update to the ML.

In D32530#1496945, @greened wrote:

What's the status of this? It seems like discussion has died down a bit. I think Graham's idea to change from <scalable 2 x float> to <vscale x 2 x float> will make the IR more readable/understandable but it's not a show-stopper for me.

While I don't want to hold up this patch, a name change to the type will be difficult to get through once the type is in and the terminology has settled, so it may be worth getting it right from the start. Personally I think <vscale x 16 x i8> is more explicit (and therefore easier to understand for those new to the type) than <scalable 16 x i8>. And now that we all have a better understanding and clear definition of scalable types, I wonder if <n x 16 x i8> instead of <vscale x 16 x i8> is worth considering again, since it is much easier to read in tests.

Thanks for your suggestions @efriedma!

In D61435#1489293, @rovka wrote:

I'd also add a unit test for StackOffset.

• Added more unittests for StackOffset.

• Added unit tests for StackOffset.
• Moved around file comments in AArch64StackOffset.h and fixed typo.

We've actually experimented with various layouts and eventually chose this layout for our HPC compiler.

Added several asserts.

@SjoerdMeijer Yes the patch is indeed quite substantial in size :) In contrast to the original SVE MC patches though, these changes are only new TableGen instruction definitions and encoding classes, corresponding (dis)assembler tests and a few flags. For example, there aren't any code changes to e.g. implement/parse new operand types.

LGTM. The compiler will have more opportunity to use cheaper shuffles if part of the (sub)vector is undef, so this looks like a general improvement.

From looking at the A57 scheduler model in LLVM this seems like an improvement, with for example VUZPq taking twice as long as VUZPd. But in general I could imagine shuffles on shorter vectors to be cheaper.
It will probably also be easier to spot that one of concatenated subvectors becomes fully undef after doing the shuffling on the subvector first.

Thanks @spatel. I'll also create a follow-up patch to use a switch statement as you suggested!

• Removed redundant checks for predicate value.
• Renamed ArgV to Cmp

We found a case where repeated calls into computeKnownBits(FromAssume) skyrocketed our build-times after we added a call to llvm.assume after vectorized loops to describe the range of a newly introduced induction variable, causing some builds to time-out.
Because the 'less then' or 'less then equal' case was way down this list in this function, it had to go through all the matching calls. Unfortunately I don't have any real numbers to back this up, because we did this work a while ago.

ping!

• Renamed sgpr_spill -> sgpr-spill.
• Renamed TargetStackID::SGPR_Spill -> TargetStackID::SGPRSpill.

In D60137#1451655, @thegameg wrote:

This is definitely nicer, thanks for working on it.

I have two concerns about this though:

• we're going from a target-specific "namespace" to a target-independent one, which means in this case that no other target can use the stack id 1
• we're exposing target-specific names and enums in the target-independent code

Thanks! Yes, you're right that exposing the target-specific names/enums in target-independent code is less desirable, although note that this happens in some other places in LLVM as well; think for example of the enum in CallingConv. I made the trade-off to use the enum for several reasons:

• By using an enum way we don't get target-specific MIR parsing of common properties.
• If we want to make it target-independent, we'll need to manually parse it as a string and we lose out on out-of-the box YAML parsing, printing, verification and diagnostics of having an enum value.
• If the value needs to be a string, it will have ugly quotes around it :)
• At the moment there seems to be only very limited use of stack-id, in trunk only the AMDGPU target as far as I know. Unless we care deeply about allowing to programatically generate a range of stack-ids at compile-time (with their meaning only known at compile-time), I don't think it is much of a limitation to have a single namespace.

Thanks!

Closing this patch manually. I accidentally changed the last digit to be D59636 when I committed this patch :)

• This patch now uses Optional<unsigned> for getUnscaledLdSt()
• Separate out the non-functional changes from the functional change (the added cases in AArch64InstrInfo::getMemOpInfo)
• Some more simplification of the arithmetic in isAArch64FrameOffsetLegal.

Thanks @c-rhodes, LGTM.

(not sure why Phabricator marked these comments as 'done' since they're not done yet)

Thanks @c-rhodes, this was indeed a mismatch with the SVE spec. Minor nit: the SVE spill/fill instructions also take ZPRAny operands, you could add some tests for those instructions as well to ensure it is not limited to movprfx alone.

@nikic thanks for pointing me to that discussion! I clearly misread the LangRef for this change :)
I agree it makes more sense to change these intrinsics and to make its accumulator argument always relevant (regardless of what flags are set) and AutoUpgrading older IR. Given that I'm currently working on this, I'd be happy to move this forward with patches and a proposal/discussion on the mailing list to change the experimental reduction intrinsics. @aemerson you expressed an intention to work on it later this year, do you have any objection to me moving forward with this now?

Updated the tests to use a scalar accumulator value (instead of a vector accumulator value, which was wrong, but seemed to be completely ignored by SelectionDAGBuilder).

This patch now matches ISD::VECREDUCE_FADD directly, and shows the diff with test/CodeGen/AArch64/vecreduce-fadd.ll.

Thanks for updating your patch @sanjoy ! LGTM (with a side-note on a follow up patch to take more specific flags in expandReductions).
You may want to update the commit message before you commit :)

Thanks for making these changes, I think the patch looks good now!

Thanks for these changes to your patch @sanjoy! The patch is looking in good shape, just a few remaining nits mostly.

Thanks for this patch @nikic! Please find some comments inline.

LGTM, thanks.

The patch looks fine to me (with nit on the const_cast)

• resolved editorial comments.

Just to double check before committing, @aaron.ballman are you happy with the tests?

Thanks for making this change, I think having the interface more generic makes sense. Please find some comments inlined.

Thanks all for the suggestions and comments! I've updated the patch with a better description of the attribute's behaviour (thanks @rjmccall for the starting point!) and added Sema tests.

• Removed _aarch64_vector_pcs and __aarch64_vector_pcs keywords in favour of supporting only __attribute__(aarch64_vector_pcs)).

ping!

• Calculate CSStackSize by accumulating reg-size for each saved register.
• Only sets PairedReg in SavedRegs when it is not AArch64::NoRegister.
• Removed trailing whitespace from test.

The code in hasLoadFromStackSlot filters out MMO's that have a pseudo source value of type Stack. If that function populates an array of only those MMOs, I think its safe to do a cast<FixedStackPseudoSourceValue>(mmo->getPseudoValue()) and get rid of the FrameAccess struct.

Thanks @thegameg ! I've also created a patch to better describe the size of bytes spilled/reloaded for LDP/STP instructions in D51537.

• Some refactoring to maintain CSStackSize.
• Migrated .ll test to a .mir test.

Fixed issue with incorrect size of MachineMemOperand.