sdesmalen (Sander de Smalen)
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User Since
Oct 21 2016, 1:19 AM (100 w, 5 d)

Recent Activity

Thu, Sep 6

sdesmalen added a comment to D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..

ping!

Thu, Sep 6, 1:38 AM

Tue, Sep 4

sdesmalen added a reviewer for D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute.: thegameg.
Tue, Sep 4, 5:25 AM
sdesmalen created D51617: Remove FrameAccess struct from hasLoadFromStackSlot.
Tue, Sep 4, 2:52 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Calculate CSStackSize by accumulating reg-size for each saved register.
  • Only sets PairedReg in SavedRegs when it is not AArch64::NoRegister.
  • Removed trailing whitespace from test.
Tue, Sep 4, 2:45 AM

Mon, Sep 3

sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Mon, Sep 3, 8:10 AM
sdesmalen added a comment to D51537: Extend hasStoreToStackSlot with list of FI accesses..

The code in hasLoadFromStackSlot filters out MMO's that have a pseudo source value of type Stack. If that function populates an array of only those MMOs, I think its safe to do a cast<FixedStackPseudoSourceValue>(mmo->getPseudoValue()) and get rid of the FrameAccess struct.

Mon, Sep 3, 7:05 AM

Fri, Aug 31

sdesmalen added a comment to D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Thanks @thegameg ! I've also created a patch to better describe the size of bytes spilled/reloaded for LDP/STP instructions in D51537.

Fri, Aug 31, 5:45 AM
sdesmalen created D51537: Extend hasStoreToStackSlot with list of FI accesses..
Fri, Aug 31, 5:44 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Some refactoring to maintain CSStackSize.
  • Migrated .ll test to a .mir test.
Fri, Aug 31, 2:56 AM
sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Fri, Aug 31, 2:55 AM
sdesmalen updated the diff for D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Fixed issue with incorrect size of MachineMemOperand.

Fri, Aug 31, 2:55 AM
sdesmalen added inline comments to D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..
Fri, Aug 31, 2:51 AM

Thu, Aug 30

sdesmalen added a dependent revision for D51478: [AArch64] NFC: Refactoring to prepare for vector PCS.: D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Thu, Aug 30, 2:17 AM
sdesmalen added dependencies for D51479: [AArch64] Implement aarch64_vector_pcs codegen support.: D51478: [AArch64] NFC: Refactoring to prepare for vector PCS., D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..
Thu, Aug 30, 2:17 AM
sdesmalen added a dependent revision for D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute.: D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Thu, Aug 30, 2:17 AM
sdesmalen created D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Thu, Aug 30, 2:17 AM
sdesmalen created D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..
Thu, Aug 30, 2:16 AM
sdesmalen created D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..
Thu, Aug 30, 2:16 AM

Aug 17 2018

sdesmalen updated the diff for D50885: [AArch64][SVE] Asm: Add SVE System registers.

Added negative tests and moved the tests to their own files test/MC/AArch64/SVE (system-regs.s and system-regs-diagnostics.s).

Aug 17 2018, 4:55 AM
sdesmalen added a comment to D50885: [AArch64][SVE] Asm: Add SVE System registers.

These system registers were missing from my previous SVE MC patches.

Aug 17 2018, 1:54 AM
sdesmalen created D50885: [AArch64][SVE] Asm: Add SVE System registers.
Aug 17 2018, 1:52 AM

Jul 30 2018

sdesmalen updated the diff for D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
  • Updated to reflect changes in D49592 to use TSFlags instead of separate table for annotating instructions as destructive operations.
  • Added negative tests for new SVE instructions that were added since uploading the previous patch.
Jul 30 2018, 12:42 AM
sdesmalen updated the diff for D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..

Updated the patch to use TSFlags instead of a separate look-up table to annotate instructions as being destructive operations.

Jul 30 2018, 12:42 AM

Jul 27 2018

sdesmalen added a comment to D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..

Hi Sjoerd, thanks for your feedback! We actually use the TSFlags in our downstream assembler, but had a few reasons to re-implement it with a GenericTable instead:

  • The TSFlags are used for all instructions, taking up global bits for only a relatively small selection of instructions, where these bits make little sense to non-movprfxable instructions. To better utilize the (potentially) cheap move/zeroing capabilities of MOVPRFX, we'll need more fields/bits to describe the kind of operation e.g. whether it is unary, binary, commutative, whether it has a reversed operation (e.g. sub and subr), which in our downstream compiler takes a total of 9 bits. With this in mind, I thought it made more sense to describe this in a separate table instead.
  • The table is not queried that often (only when encountered together with a MOVPRFX), so there is little runtime overhead.
Jul 27 2018, 2:08 AM

Jul 20 2018

sdesmalen added a comment to D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..

It is probably worth noting that the positive and negative tests to explicitly test that instructions (and/or specific forms of those instructions) are or are not movprfx-able, are auto-generated using a separate tool (so my apologies for the large diff :)). The movprfx-diagnostics.s is worth pointing out as testing the specific rules of the MOVPRFX instruction.

Jul 20 2018, 2:43 AM
sdesmalen added a dependency for D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed.: D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:37 AM
sdesmalen added a dependent revision for D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions.: D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:37 AM
sdesmalen updated the summary of D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:37 AM
sdesmalen updated the summary of D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:37 AM
sdesmalen created D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:36 AM
sdesmalen created D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:36 AM

Jul 4 2018

sdesmalen created D48937: [TableGen] Increase the number of supported decoder fix-ups..
Jul 4 2018, 6:42 AM

Jul 3 2018

sdesmalen created D48870: [AArch64][SVE] Asm: Support for ADR instruction..
Jul 3 2018, 2:42 AM
sdesmalen added inline comments to D48869: [AArch64][SVE] Asm: Support for SVE condition code aliases.
Jul 3 2018, 2:38 AM
sdesmalen created D48869: [AArch64][SVE] Asm: Support for SVE condition code aliases.
Jul 3 2018, 2:36 AM

Jul 2 2018

sdesmalen added a dependent revision for D48823: [AArch64][SVE] Asm: Support for FMUL (indexed): D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:26 AM
sdesmalen added a dependency for D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA.: D48823: [AArch64][SVE] Asm: Support for FMUL (indexed).
Jul 2 2018, 3:26 AM
sdesmalen updated the summary of D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:26 AM
sdesmalen created D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:25 AM
sdesmalen created D48823: [AArch64][SVE] Asm: Support for FMUL (indexed).
Jul 2 2018, 2:51 AM

Jun 18 2018

sdesmalen added a comment to D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..

Thanks @fhahn I've added a comment to regsEqual describing what it can be used for.

Jun 18 2018, 6:46 AM

Jun 15 2018

sdesmalen added dependencies for D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics.: D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions., D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 15 2018, 8:04 AM
sdesmalen added a dependent revision for D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.: D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:04 AM
sdesmalen added a dependent revision for D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.: D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:04 AM
sdesmalen created D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:03 AM
sdesmalen added inline comments to D47713: [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions..
Jun 15 2018, 7:14 AM

Jun 14 2018

sdesmalen added a comment to D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..

Friendly ping..

Jun 14 2018, 2:17 PM
sdesmalen added inline comments to D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 14 2018, 4:48 AM

Jun 6 2018

sdesmalen updated the diff for D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

Merged k_ExactFPImm with k_FPImm.

Jun 6 2018, 8:05 AM

Jun 5 2018

sdesmalen added a comment to D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

Hi @olista01 , I just tried merging this change with k_FPImm and one of the problems I'm running into is with the '#0.0' and InstAliases.
For example in SVEInstrFormats.td, class sve_int_dup_imm:

InstAlias<"fmov $Zd, #0.0", (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>;
Jun 5 2018, 7:47 AM
sdesmalen added a comment to D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

The k_FPImm case works a little different.. Instead of it storing the APFloat value, it stores the (AArch64_AM) encoded FP imm value. If the value cannot be encoded, the parser throws an error. Also not all values can be encoded, such as '0.0', for which the parser (for k_FPImm) puts in a "#0.0" string literal into the parsed operands list. The two cases can be merged, but I think it may be better to do that in a separate patch as this will require some refactoring and changes to match e.g. the #0.0 case in existing FP instructions.

Jun 5 2018, 4:21 AM

Jun 4 2018

sdesmalen added dependencies for D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.: D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases., D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen added a dependent revision for D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.: D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen added a dependent revision for D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases.: D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen created D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:49 AM
sdesmalen created D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions..
Jun 4 2018, 6:49 AM
sdesmalen created D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..
Jun 4 2018, 6:49 AM
sdesmalen created D47713: [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions..
Jun 4 2018, 6:36 AM
sdesmalen added a dependency for D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.: D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..
Jun 4 2018, 6:21 AM
sdesmalen added a dependent revision for D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.: D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions..
Jun 4 2018, 6:21 AM
sdesmalen created D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions..
Jun 4 2018, 6:21 AM
sdesmalen created D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..
Jun 4 2018, 6:21 AM

Jun 3 2018

sdesmalen added inline comments to D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions..
Jun 3 2018, 11:44 PM

Jun 1 2018

sdesmalen updated the diff for D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

Removed some redundant test-cases for fmov alias that are already tested by test/MC/AArch64/SVE/fdup.s

Jun 1 2018, 5:42 AM
sdesmalen added a comment to D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

I think the difference with other immediates that have a limited set, is that these immediates have a non-trivial parsing/decoding/printing. Rather than just allowing a given range of integer values the string is first parsed as FP value and then encoded as integer value between 0-255. And the opposite for the decode. I think it makes sense to test these cases individually, although I can see how doing this for the FMOV alias as well could be a bit excessive, so I'll reduce those.

Jun 1 2018, 2:35 AM
sdesmalen added a comment to D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

Looks good, but do the tests have to be that big? That makes it really hard to spot if the edge cases & aliases are handled properly. Can you reduce the size a bit?

Since the immediate encoding only allows for a limited set of 256 different floating-point immediates, I thought it would make sense to test each of them separately to make sure they are all correctly parsed, assembled and printed, since basically these are all the edge-cases. The negative tests are much smaller and test a few floating point values that cannot be encoded. I can easily reduce the tests, but I think these tests are valuable. What do you think?

Jun 1 2018, 1:56 AM
sdesmalen created D47619: [AArch64][SVE] Fix range for DUP immediates (16bit elts).
Jun 1 2018, 12:33 AM

May 31 2018

sdesmalen added inline comments to D47328: [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction..
May 31 2018, 7:30 AM
sdesmalen added inline comments to D47328: [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction..
May 31 2018, 2:35 AM

May 30 2018

sdesmalen added a dependent revision for D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions.: D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR..
May 30 2018, 11:47 PM
sdesmalen added a dependency for D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR.: D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions..
May 30 2018, 11:47 PM
sdesmalen created D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR..
May 30 2018, 11:47 PM
sdesmalen created D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions..
May 30 2018, 11:46 PM
sdesmalen added a comment to D47518: [AArch64][SVE] Asm: Support for FCPY immediate instructions..

Should the commit message be " Splat floating-point immediate value to SVE vector". Or may be i am wrong on this?

That sounds similar, but there is some distinction in that it uses predication. It is a predicated splat of an immediate value into the result vector with merging predication.
I used the word 'copy' instead of 'splat' since that is the name of the instruction. Splat would be more appropriate for D47482 .

May 30 2018, 7:00 AM
sdesmalen created D47518: [AArch64][SVE] Asm: Support for FCPY immediate instructions..
May 30 2018, 1:40 AM
sdesmalen created D47517: [AArch64][SVE] Asm: Support for CPY immediate instructions.
May 30 2018, 1:40 AM

May 29 2018

sdesmalen created D47483: [AArch64][AsmParser] Fix segfault on illegal fpimm..
May 29 2018, 9:00 AM
sdesmalen created D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..
May 29 2018, 9:00 AM

May 25 2018

sdesmalen created D47365: [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors).
May 25 2018, 3:08 AM
sdesmalen updated the diff for D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..

Addressed nits and cleanup isSVEAddSubImm.

May 25 2018, 3:05 AM
sdesmalen created D47363: [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions..
May 25 2018, 2:33 AM

May 24 2018

sdesmalen created D47328: [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction..
May 24 2018, 7:33 AM
sdesmalen updated the diff for D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..
  • Removed some brackets and updated the patch to reflect change in D47309.
May 24 2018, 3:59 AM
sdesmalen updated the diff for D47309: [AArch64][SVE] Asm: Support for DUP (immediate) instructions..
  • Some simplifications (such as getShiftedVal())
  • Moved a change from patch D47310 (in isAddSubImm()) into this patch to resolve a failing test that would otherwise be solved by D47310, related to checking whether a value is a shifted value.
May 24 2018, 3:56 AM
sdesmalen added a dependent revision for D47309: [AArch64][SVE] Asm: Support for DUP (immediate) instructions.: D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..
May 24 2018, 12:15 AM
sdesmalen added a dependency for D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions.: D47309: [AArch64][SVE] Asm: Support for DUP (immediate) instructions..
May 24 2018, 12:15 AM
sdesmalen created D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..
May 24 2018, 12:14 AM
sdesmalen created D47309: [AArch64][SVE] Asm: Support for DUP (immediate) instructions..
May 24 2018, 12:14 AM

May 23 2018

sdesmalen accepted D47239: [InstCombine] Combine XOR and AES insructions on ARM/ARM64.

LGTM! Thanks for adding the negative tests and rationale.

May 23 2018, 11:14 PM
sdesmalen added inline comments to D47239: [InstCombine] Combine XOR and AES insructions on ARM/ARM64.
May 23 2018, 1:09 PM

May 15 2018

sdesmalen abandoned D41697: [DebugInfo][Metadata] Add support for a DIExpression as 'count' field of DISubrange..
May 15 2018, 12:45 PM

May 10 2018

sdesmalen added inline comments to D46688: [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size..
May 10 2018, 4:59 AM
sdesmalen added a comment to D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..

I might be good to put commit-message/description.

May 10 2018, 4:07 AM
sdesmalen added a dependent revision for D46686: [AArch64][SVE] Asm: Support for gather PRF prefetch instructions: D46688: [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size..
May 10 2018, 3:57 AM
sdesmalen added a dependency for D46688: [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.: D46686: [AArch64][SVE] Asm: Support for gather PRF prefetch instructions.
May 10 2018, 3:57 AM
sdesmalen created D46688: [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size..
May 10 2018, 3:57 AM
sdesmalen added a dependency for D46686: [AArch64][SVE] Asm: Support for gather PRF prefetch instructions: D46681: [AArch64][SVE] Extend parsing of Prefetch operation for SVE..
May 10 2018, 3:52 AM
sdesmalen added a dependent revision for D46681: [AArch64][SVE] Extend parsing of Prefetch operation for SVE.: D46686: [AArch64][SVE] Asm: Support for gather PRF prefetch instructions.
May 10 2018, 3:52 AM
sdesmalen created D46686: [AArch64][SVE] Asm: Support for gather PRF prefetch instructions.
May 10 2018, 3:52 AM
sdesmalen created D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..
May 10 2018, 2:16 AM