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sdesmalen (Sander de Smalen)
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Oct 21 2016, 1:19 AM (125 w, 6 d)

Recent Activity

Today

sdesmalen created D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Thu, Mar 21, 4:34 AM

Thu, Mar 14

sdesmalen added a comment to D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.

@nikic thanks for pointing me to that discussion! I clearly misread the LangRef for this change :)
I agree it makes more sense to change these intrinsics and to make its accumulator argument always relevant (regardless of what flags are set) and AutoUpgrading older IR. Given that I'm currently working on this, I'd be happy to move this forward with patches and a proposal/discussion on the mailing list to change the experimental reduction intrinsics. @aemerson you expressed an intention to work on it later this year, do you have any objection to me moving forward with this now?

Thu, Mar 14, 11:02 AM
sdesmalen added a parent revision for D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL: D59259: [AArch64] Use faddp to implement fadd reductions..
Thu, Mar 14, 4:21 AM
sdesmalen added a child revision for D59259: [AArch64] Use faddp to implement fadd reductions.: D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.
Thu, Mar 14, 4:21 AM
sdesmalen created D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.
Thu, Mar 14, 4:21 AM
sdesmalen updated the diff for D59259: [AArch64] Use faddp to implement fadd reductions..

Updated the tests to use a scalar accumulator value (instead of a vector accumulator value, which was wrong, but seemed to be completely ignored by SelectionDAGBuilder).

Thu, Mar 14, 4:18 AM

Wed, Mar 13

sdesmalen added inline comments to D59259: [AArch64] Use faddp to implement fadd reductions..
Wed, Mar 13, 4:01 PM
sdesmalen updated the diff for D59259: [AArch64] Use faddp to implement fadd reductions..

This patch now matches ISD::VECREDUCE_FADD directly, and shows the diff with test/CodeGen/AArch64/vecreduce-fadd.ll.

Wed, Mar 13, 8:20 AM
sdesmalen committed rG72fc7b842c81: [AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll (authored by sdesmalen).
[AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
Wed, Mar 13, 8:18 AM

Tue, Mar 12

sdesmalen created D59259: [AArch64] Use faddp to implement fadd reductions..
Tue, Mar 12, 8:44 AM
sdesmalen added inline comments to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.
Tue, Mar 12, 8:34 AM · Restricted Project

Mon, Mar 11

sdesmalen added inline comments to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.
Mon, Mar 11, 2:26 PM · Restricted Project
sdesmalen accepted D57728: Relax constraints for reduction vectorization.

Thanks for updating your patch @sanjoy ! LGTM (with a side-note on a follow up patch to take more specific flags in expandReductions).
You may want to update the commit message before you commit :)

Mon, Mar 11, 4:54 AM · Restricted Project
sdesmalen accepted D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.

Thanks for making these changes, I think the patch looks good now!

Mon, Mar 11, 4:26 AM · Restricted Project

Wed, Mar 6

sdesmalen added a comment to D57728: Relax constraints for reduction vectorization.

Thanks for these changes to your patch @sanjoy! The patch is looking in good shape, just a few remaining nits mostly.

Wed, Mar 6, 7:20 AM · Restricted Project

Tue, Feb 26

sdesmalen added a comment to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.

Thanks for this patch @nikic! Please find some comments inline.

Tue, Feb 26, 4:04 AM · Restricted Project

Wed, Feb 20

sdesmalen added inline comments to D57728: Relax constraints for reduction vectorization.
Wed, Feb 20, 8:19 AM · Restricted Project

Dec 31 2018

sdesmalen accepted D56128: [AArch64] Accept "sve" as arch feature in assembler.

LGTM, thanks.

Dec 31 2018, 1:47 AM

Nov 27 2018

sdesmalen accepted D54846: [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand.

The patch looks fine to me (with nit on the const_cast)

Nov 27 2018, 8:28 AM

Nov 26 2018

sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
  • resolved editorial comments.
Nov 26 2018, 6:09 AM
sdesmalen added a comment to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.

Just to double check before committing, @aaron.ballman are you happy with the tests?

Nov 26 2018, 5:38 AM
sdesmalen added a comment to D54846: [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand.

Thanks for making this change, I think having the interface more generic makes sense. Please find some comments inlined.

Nov 26 2018, 5:32 AM

Nov 19 2018

sdesmalen updated subscribers of D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 19 2018, 2:38 AM
sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.

Thanks all for the suggestions and comments! I've updated the patch with a better description of the attribute's behaviour (thanks @rjmccall for the starting point!) and added Sema tests.

Nov 19 2018, 2:34 AM

Nov 13 2018

sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
  • Removed _aarch64_vector_pcs and __aarch64_vector_pcs keywords in favour of supporting only __attribute__(aarch64_vector_pcs)).
Nov 13 2018, 4:16 AM
sdesmalen added inline comments to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 13 2018, 4:13 AM

Nov 12 2018

sdesmalen added inline comments to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 12 2018, 5:58 AM
sdesmalen created D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 12 2018, 5:51 AM

Sep 6 2018

sdesmalen added a comment to D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..

ping!

Sep 6 2018, 1:38 AM

Sep 4 2018

sdesmalen added a reviewer for D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute.: thegameg.
Sep 4 2018, 5:25 AM
sdesmalen created D51617: Remove FrameAccess struct from hasLoadFromStackSlot.
Sep 4 2018, 2:52 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Calculate CSStackSize by accumulating reg-size for each saved register.
  • Only sets PairedReg in SavedRegs when it is not AArch64::NoRegister.
  • Removed trailing whitespace from test.
Sep 4 2018, 2:45 AM

Sep 3 2018

sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Sep 3 2018, 8:10 AM
sdesmalen added a comment to D51537: Extend hasStoreToStackSlot with list of FI accesses..

The code in hasLoadFromStackSlot filters out MMO's that have a pseudo source value of type Stack. If that function populates an array of only those MMOs, I think its safe to do a cast<FixedStackPseudoSourceValue>(mmo->getPseudoValue()) and get rid of the FrameAccess struct.

Sep 3 2018, 7:05 AM

Aug 31 2018

sdesmalen added a comment to D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Thanks @thegameg ! I've also created a patch to better describe the size of bytes spilled/reloaded for LDP/STP instructions in D51537.

Aug 31 2018, 5:45 AM
sdesmalen created D51537: Extend hasStoreToStackSlot with list of FI accesses..
Aug 31 2018, 5:44 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Some refactoring to maintain CSStackSize.
  • Migrated .ll test to a .mir test.
Aug 31 2018, 2:56 AM
sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Aug 31 2018, 2:55 AM
sdesmalen updated the diff for D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Fixed issue with incorrect size of MachineMemOperand.

Aug 31 2018, 2:55 AM
sdesmalen added inline comments to D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..
Aug 31 2018, 2:51 AM

Aug 30 2018

sdesmalen added a child revision for D51478: [AArch64] NFC: Refactoring to prepare for vector PCS.: D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Aug 30 2018, 2:17 AM
sdesmalen added parent revisions for D51479: [AArch64] Implement aarch64_vector_pcs codegen support.: D51478: [AArch64] NFC: Refactoring to prepare for vector PCS., D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..
Aug 30 2018, 2:17 AM
sdesmalen added a child revision for D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute.: D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Aug 30 2018, 2:17 AM
sdesmalen created D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Aug 30 2018, 2:17 AM
sdesmalen created D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..
Aug 30 2018, 2:16 AM
sdesmalen created D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..
Aug 30 2018, 2:16 AM

Aug 17 2018

sdesmalen updated the diff for D50885: [AArch64][SVE] Asm: Add SVE System registers.

Added negative tests and moved the tests to their own files test/MC/AArch64/SVE (system-regs.s and system-regs-diagnostics.s).

Aug 17 2018, 4:55 AM
sdesmalen added a comment to D50885: [AArch64][SVE] Asm: Add SVE System registers.

These system registers were missing from my previous SVE MC patches.

Aug 17 2018, 1:54 AM
sdesmalen created D50885: [AArch64][SVE] Asm: Add SVE System registers.
Aug 17 2018, 1:52 AM

Jul 30 2018

sdesmalen updated the diff for D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
  • Updated to reflect changes in D49592 to use TSFlags instead of separate table for annotating instructions as destructive operations.
  • Added negative tests for new SVE instructions that were added since uploading the previous patch.
Jul 30 2018, 12:42 AM
sdesmalen updated the diff for D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..

Updated the patch to use TSFlags instead of a separate look-up table to annotate instructions as being destructive operations.

Jul 30 2018, 12:42 AM

Jul 27 2018

sdesmalen added a comment to D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..

Hi Sjoerd, thanks for your feedback! We actually use the TSFlags in our downstream assembler, but had a few reasons to re-implement it with a GenericTable instead:

  • The TSFlags are used for all instructions, taking up global bits for only a relatively small selection of instructions, where these bits make little sense to non-movprfxable instructions. To better utilize the (potentially) cheap move/zeroing capabilities of MOVPRFX, we'll need more fields/bits to describe the kind of operation e.g. whether it is unary, binary, commutative, whether it has a reversed operation (e.g. sub and subr), which in our downstream compiler takes a total of 9 bits. With this in mind, I thought it made more sense to describe this in a separate table instead.
  • The table is not queried that often (only when encountered together with a MOVPRFX), so there is little runtime overhead.
Jul 27 2018, 2:08 AM

Jul 20 2018

sdesmalen added a comment to D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..

It is probably worth noting that the positive and negative tests to explicitly test that instructions (and/or specific forms of those instructions) are or are not movprfx-able, are auto-generated using a separate tool (so my apologies for the large diff :)). The movprfx-diagnostics.s is worth pointing out as testing the specific rules of the MOVPRFX instruction.

Jul 20 2018, 2:43 AM
sdesmalen added a parent revision for D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed.: D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:37 AM
sdesmalen added a child revision for D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions.: D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:37 AM
sdesmalen updated the summary of D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:37 AM
sdesmalen updated the summary of D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:37 AM
sdesmalen created D49593: [AArch64][SVE] Asm: Enable instructions to be prefixed..
Jul 20 2018, 2:36 AM
sdesmalen created D49592: [AArch64][SVE] Asm: Add MOVPRFX instructions..
Jul 20 2018, 2:36 AM

Jul 4 2018

sdesmalen created D48937: [TableGen] Increase the number of supported decoder fix-ups..
Jul 4 2018, 6:42 AM

Jul 3 2018

sdesmalen created D48870: [AArch64][SVE] Asm: Support for ADR instruction..
Jul 3 2018, 2:42 AM
sdesmalen added inline comments to D48869: [AArch64][SVE] Asm: Support for SVE condition code aliases.
Jul 3 2018, 2:38 AM
sdesmalen created D48869: [AArch64][SVE] Asm: Support for SVE condition code aliases.
Jul 3 2018, 2:36 AM

Jul 2 2018

sdesmalen added a child revision for D48823: [AArch64][SVE] Asm: Support for FMUL (indexed): D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:26 AM
sdesmalen added a parent revision for D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA.: D48823: [AArch64][SVE] Asm: Support for FMUL (indexed).
Jul 2 2018, 3:26 AM
sdesmalen updated the summary of D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:26 AM
sdesmalen created D48824: [AArch64][SVE] Asm: Support for FP Complex ADD/MLA..
Jul 2 2018, 3:25 AM
sdesmalen created D48823: [AArch64][SVE] Asm: Support for FMUL (indexed).
Jul 2 2018, 2:51 AM

Jun 18 2018

sdesmalen added a comment to D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..

Thanks @fhahn I've added a comment to regsEqual describing what it can be used for.

Jun 18 2018, 6:46 AM

Jun 15 2018

sdesmalen added parent revisions for D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics.: D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions., D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 15 2018, 8:04 AM
sdesmalen added a child revision for D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.: D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:04 AM
sdesmalen added a child revision for D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.: D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:04 AM
sdesmalen created D48220: [AArch64][SVE] Asm: Fix predicate pattern diagnostics..
Jun 15 2018, 8:03 AM
sdesmalen added inline comments to D47713: [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions..
Jun 15 2018, 7:14 AM

Jun 14 2018

sdesmalen added a comment to D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..

Friendly ping..

Jun 14 2018, 2:17 PM
sdesmalen added inline comments to D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 14 2018, 4:48 AM

Jun 6 2018

sdesmalen updated the diff for D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

Merged k_ExactFPImm with k_FPImm.

Jun 6 2018, 8:05 AM

Jun 5 2018

sdesmalen added a comment to D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

Hi @olista01 , I just tried merging this change with k_FPImm and one of the problems I'm running into is with the '#0.0' and InstAliases.
For example in SVEInstrFormats.td, class sve_int_dup_imm:

InstAlias<"fmov $Zd, #0.0", (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>;
Jun 5 2018, 7:47 AM
sdesmalen added a comment to D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

The k_FPImm case works a little different.. Instead of it storing the APFloat value, it stores the (AArch64_AM) encoded FP imm value. If the value cannot be encoded, the parser throws an error. Also not all values can be encoded, such as '0.0', for which the parser (for k_FPImm) puts in a "#0.0" string literal into the parsed operands list. The two cases can be merged, but I think it may be better to do that in a separate patch as this will require some refactoring and changes to match e.g. the #0.0 case in existing FP instructions.

Jun 5 2018, 4:21 AM

Jun 4 2018

sdesmalen added parent revisions for D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.: D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases., D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen added a child revision for D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.: D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen added a child revision for D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases.: D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:50 AM
sdesmalen created D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Jun 4 2018, 6:49 AM
sdesmalen created D47715: [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions..
Jun 4 2018, 6:49 AM
sdesmalen created D47714: [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in aliases..
Jun 4 2018, 6:49 AM
sdesmalen created D47713: [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions..
Jun 4 2018, 6:36 AM
sdesmalen added a parent revision for D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.: D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..
Jun 4 2018, 6:21 AM
sdesmalen added a child revision for D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.: D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions..
Jun 4 2018, 6:21 AM
sdesmalen created D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions..
Jun 4 2018, 6:21 AM
sdesmalen created D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..
Jun 4 2018, 6:21 AM

Jun 3 2018

sdesmalen added inline comments to D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions..
Jun 3 2018, 11:44 PM

Jun 1 2018

sdesmalen updated the diff for D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

Removed some redundant test-cases for fmov alias that are already tested by test/MC/AArch64/SVE/fdup.s

Jun 1 2018, 5:42 AM
sdesmalen added a comment to D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

I think the difference with other immediates that have a limited set, is that these immediates have a non-trivial parsing/decoding/printing. Rather than just allowing a given range of integer values the string is first parsed as FP value and then encoded as integer value between 0-255. And the opposite for the decode. I think it makes sense to test these cases individually, although I can see how doing this for the FMOV alias as well could be a bit excessive, so I'll reduce those.

Jun 1 2018, 2:35 AM
sdesmalen added a comment to D47482: [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction..

Looks good, but do the tests have to be that big? That makes it really hard to spot if the edge cases & aliases are handled properly. Can you reduce the size a bit?

Since the immediate encoding only allows for a limited set of 256 different floating-point immediates, I thought it would make sense to test each of them separately to make sure they are all correctly parsed, assembled and printed, since basically these are all the edge-cases. The negative tests are much smaller and test a few floating point values that cannot be encoded. I can easily reduce the tests, but I think these tests are valuable. What do you think?

Jun 1 2018, 1:56 AM
sdesmalen created D47619: [AArch64][SVE] Fix range for DUP immediates (16bit elts).
Jun 1 2018, 12:33 AM

May 31 2018

sdesmalen added inline comments to D47328: [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction..
May 31 2018, 7:30 AM
sdesmalen added inline comments to D47328: [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction..
May 31 2018, 2:35 AM

May 30 2018

sdesmalen added a child revision for D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions.: D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR..
May 30 2018, 11:47 PM
sdesmalen added a parent revision for D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR.: D47570: [AArch64][SVE] Asm: Support for indexed DUP instructions..
May 30 2018, 11:47 PM
sdesmalen created D47571: [AArch64][SVE] Asm: Print indexed element 0 as FPR..
May 30 2018, 11:47 PM