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sdesmalen (Sander de Smalen)
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Oct 21 2016, 1:19 AM (134 w, 4 d)

Recent Activity

Yesterday

sdesmalen committed rGf83cccf917c1: Match types of accumulator and result for llvm.experimental.vector.reduce. (authored by sdesmalen).
Match types of accumulator and result for llvm.experimental.vector.reduce.
Mon, May 20, 2:54 AM

Fri, May 17

sdesmalen added a comment to D60260: Match types of accumulator and result for llvm.experimental.vector.reduce.fadd/fmul.

This looks good, but please also update existing tests that specify three types in the intrinstic name. Here's ones I found:

  • test/CodeGen/X86/haddsub.ll
  • test/CodeGen/X86/vector-reduce-fadd-fast.ll
  • test/CodeGen/X86/vector-reduce-fadd.ll
  • test/CodeGen/X86/vector-reduce-fmul-fast.ll
  • test/CodeGen/X86/vector-reduce-fmul.ll

Good spot! I've updated these tests now.

Fri, May 17, 3:21 AM · Restricted Project
sdesmalen updated the diff for D60260: Match types of accumulator and result for llvm.experimental.vector.reduce.fadd/fmul.
  • Updated more tests.
Fri, May 17, 3:21 AM · Restricted Project

Thu, May 16

sdesmalen added a comment to D61437: [AArch64] Static (de)allocation of SVE stack objects..

This sounds like it will report the wrong stack size in PEI for the StackSize remark and the stack size warning. Is that expected?

For now the answer is yes. One of our primary concerns at the moment is adding basic SVE spill/fill support and we appreciate the caveat that nothing in LLVM really supports the concept of scalable types yet, including offsets and sizes.

Thu, May 16, 8:05 AM
sdesmalen added a comment to D61437: [AArch64] Static (de)allocation of SVE stack objects..

If the SVE spill area is below the CSRs, you can leverage the existing checks to handle stack realignment, so I don't think it's that complicated to implement. But maybe your approach requires changing fewer places.

I think you've made some compelling reasons to try the change in layout! I'll actually try this out downstream first before updating this patch, so I can run it through our SVE testing and see if there is any impact on performance or if I run into anything unexpected.

Thu, May 16, 7:17 AM
sdesmalen added a comment to D61437: [AArch64] Static (de)allocation of SVE stack objects..

Ignore the bit about Windows unwinding. I remembered how it actually works; the Microsoft document is just wrong, and it's not actually necessary to allocate the frame record in any particular position on WIndows (except that it has to be somewhere that isn't allocated using _chkstk... but that wouldn't happen anyway with the layout I'm suggesting).

Thanks for clarifying!

Thu, May 16, 7:17 AM
sdesmalen added a comment to D60261: [Option A] Change semantics of fadd/fmul vector reductions..

Rereading the ML discussion just now, it looks like the consensus is to go with this option. Move forward?

Thanks for the prod! I've sent an update to the ML.

Thu, May 16, 5:55 AM

Fri, May 10

sdesmalen added a comment to D32530: [SVE][IR] Scalable Vector IR Type.

What's the status of this? It seems like discussion has died down a bit. I think Graham's idea to change from <scalable 2 x float> to <vscale x 2 x float> will make the IR more readable/understandable but it's not a show-stopper for me.

While I don't want to hold up this patch, a name change to the type will be difficult to get through once the type is in and the terminology has settled, so it may be worth getting it right from the start. Personally I think <vscale x 16 x i8> is more explicit (and therefore easier to understand for those new to the type) than <scalable 16 x i8>. And now that we all have a better understanding and clear definition of scalable types, I wonder if <n x 16 x i8> instead of <vscale x 16 x i8> is worth considering again, since it is much easier to read in tests.

Fri, May 10, 9:45 AM
sdesmalen added a comment to D61437: [AArch64] Static (de)allocation of SVE stack objects..

Thanks for your suggestions @efriedma!

Fri, May 10, 6:33 AM

Tue, May 7

sdesmalen added a comment to D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets..

I'd also add a unit test for StackOffset.

Tue, May 7, 5:16 AM
sdesmalen updated the diff for D61437: [AArch64] Static (de)allocation of SVE stack objects..
  • Added more unittests for StackOffset.
Tue, May 7, 5:08 AM
sdesmalen updated the diff for D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets..
  • Added unit tests for StackOffset.
  • Moved around file comments in AArch64StackOffset.h and fixed typo.
Tue, May 7, 5:04 AM

Fri, May 3

sdesmalen added a comment to D61437: [AArch64] Static (de)allocation of SVE stack objects..

We've actually experimented with various layouts and eventually chose this layout for our HPC compiler.

Fri, May 3, 8:52 AM
sdesmalen added inline comments to D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets..
Fri, May 3, 8:25 AM
sdesmalen updated the diff for D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets..

Added several asserts.

Fri, May 3, 8:20 AM

Thu, May 2

sdesmalen added parent revisions for D61437: [AArch64] Static (de)allocation of SVE stack objects.: D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets., D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets..
Thu, May 2, 5:39 AM
sdesmalen added a child revision for D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets.: D61437: [AArch64] Static (de)allocation of SVE stack objects..
Thu, May 2, 5:39 AM
sdesmalen added a child revision for D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets.: D61437: [AArch64] Static (de)allocation of SVE stack objects..
Thu, May 2, 5:39 AM
sdesmalen added a child revision for D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets.: D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets..
Thu, May 2, 5:39 AM
sdesmalen added a parent revision for D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets.: D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets..
Thu, May 2, 5:39 AM
sdesmalen created D61437: [AArch64] Static (de)allocation of SVE stack objects..
Thu, May 2, 5:38 AM
sdesmalen created D61435: [AArch64] NFC: Add generic StackOffset to describe scalable offsets..
Thu, May 2, 5:38 AM
sdesmalen created D61436: [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets..
Thu, May 2, 5:38 AM

Tue, Apr 30

sdesmalen added a comment to D61262: [AArch64] Implement MC support for Scalable Vector Extension 2 (SVE2).

@SjoerdMeijer Yes the patch is indeed quite substantial in size :) In contrast to the original SVE MC patches though, these changes are only new TableGen instruction definitions and encoding classes, corresponding (dis)assembler tests and a few flags. For example, there aren't any code changes to e.g. implement/parse new operand types.

Tue, Apr 30, 1:33 AM · Restricted Project

Apr 12 2019

sdesmalen accepted D60545: [DAGCombiner] narrow shuffle of concatenated vectors.

LGTM. The compiler will have more opportunity to use cheaper shuffles if part of the (sub)vector is undef, so this looks like a general improvement.

Apr 12 2019, 6:32 AM · Restricted Project

Apr 11 2019

sdesmalen added a comment to D60545: [DAGCombiner] narrow shuffle of concatenated vectors.

From looking at the A57 scheduler model in LLVM this seems like an improvement, with for example VUZPq taking twice as long as VUZPd. But in general I could imagine shuffles on shorter vectors to be cheaper.
It will probably also be easier to spot that one of concatenated subvectors becomes fully undef after doing the shuffling on the subvector first.

Apr 11 2019, 9:05 AM · Restricted Project
sdesmalen committed rG4f5d2df48d57: [ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssume (authored by sdesmalen).
[ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssume
Apr 11 2019, 6:03 AM

Apr 10 2019

sdesmalen committed rG0e66db5d7718: Improve compile-time performance in computeKnownBitsFromAssume. (authored by sdesmalen).
Improve compile-time performance in computeKnownBitsFromAssume.
Apr 10 2019, 9:24 AM
sdesmalen added a comment to D60504: NFC: Improve pattern matching in computeKnownBitsFromAssume..

Thanks @spatel. I'll also create a follow-up patch to use a switch statement as you suggested!

Apr 10 2019, 9:23 AM · Restricted Project
sdesmalen updated the diff for D60504: NFC: Improve pattern matching in computeKnownBitsFromAssume..
  • Removed redundant checks for predicate value.
  • Renamed ArgV to Cmp
Apr 10 2019, 8:36 AM · Restricted Project
sdesmalen added a comment to D60504: NFC: Improve pattern matching in computeKnownBitsFromAssume..

We found a case where repeated calls into computeKnownBits(FromAssume) skyrocketed our build-times after we added a call to llvm.assume after vectorized loops to describe the range of a newly introduced induction variable, causing some builds to time-out.
Because the 'less then' or 'less then equal' case was way down this list in this function, it had to go through all the matching calls. Unfortunately I don't have any real numbers to back this up, because we did this work a while ago.

Apr 10 2019, 8:36 AM · Restricted Project
sdesmalen created D60504: NFC: Improve pattern matching in computeKnownBitsFromAssume..
Apr 10 2019, 4:48 AM · Restricted Project

Apr 5 2019

sdesmalen added a comment to D59259: [AArch64] Use faddp to implement fadd reductions..

ping!

Apr 5 2019, 8:57 AM

Apr 4 2019

sdesmalen updated the diff for D60137: Describe stack-id as an enum.
  • Renamed sgpr_spill -> sgpr-spill.
  • Renamed TargetStackID::SGPR_Spill -> TargetStackID::SGPRSpill.
Apr 4 2019, 8:48 AM
sdesmalen created D60262: [Option B] Create explicit ordered/unordered reduction intrinsics for fadd/fmul..
Apr 4 2019, 5:51 AM
sdesmalen created D60261: [Option A] Change semantics of fadd/fmul vector reductions..
Apr 4 2019, 5:51 AM
sdesmalen created D60260: Match types of accumulator and result for llvm.experimental.vector.reduce.fadd/fmul.
Apr 4 2019, 5:26 AM · Restricted Project
sdesmalen committed rG772e4734d9d6: [AArch64][AsmParser] Fix .arch_extension directive parsing (authored by sdesmalen).
[AArch64][AsmParser] Fix .arch_extension directive parsing
Apr 4 2019, 2:12 AM

Apr 3 2019

sdesmalen added inline comments to D60137: Describe stack-id as an enum.
Apr 3 2019, 4:55 AM
sdesmalen added a comment to D60137: Describe stack-id as an enum.

This is definitely nicer, thanks for working on it.

I have two concerns about this though:

  • we're going from a target-specific "namespace" to a target-independent one, which means in this case that no other target can use the stack id 1
  • we're exposing target-specific names and enums in the target-independent code

Thanks! Yes, you're right that exposing the target-specific names/enums in target-independent code is less desirable, although note that this happens in some other places in LLVM as well; think for example of the enum in CallingConv. I made the trade-off to use the enum for several reasons:

  • By using an enum way we don't get target-specific MIR parsing of common properties.
  • If we want to make it target-independent, we'll need to manually parse it as a string and we lose out on out-of-the box YAML parsing, printing, verification and diagnostics of having an enum value.
  • If the value needs to be a string, it will have ugly quotes around it :)
  • At the moment there seems to be only very limited use of stack-id, in trunk only the AMDGPU target as far as I know. Unless we care deeply about allowing to programatically generate a range of stack-ids at compile-time (with their meaning only known at compile-time), I don't think it is much of a limitation to have a single namespace.
Apr 3 2019, 4:55 AM

Apr 2 2019

sdesmalen created D60137: Describe stack-id as an enum.
Apr 2 2019, 9:29 AM
sdesmalen committed rG7f23e0a62fc9: Enforce StackID definition in PEI (authored by sdesmalen).
Enforce StackID definition in PEI
Apr 2 2019, 2:47 AM
sdesmalen added a comment to D60062: Enforce StackID definition in PEI.

Thanks!

Apr 2 2019, 2:43 AM · Restricted Project

Apr 1 2019

sdesmalen created D60062: Enforce StackID definition in PEI.
Apr 1 2019, 5:46 AM · Restricted Project

Mar 27 2019

sdesmalen removed 2 commit(s) for D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix: rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal, rL357064: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 27 2019, 10:30 AM · Restricted Project
sdesmalen removed an edge from rL357064: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal: D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix.
Mar 27 2019, 10:30 AM
sdesmalen removed an edge from rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal: D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix.
Mar 27 2019, 10:30 AM
sdesmalen closed D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.

Closing this patch manually. I accidentally changed the last digit to be D59636 when I committed this patch :)

Mar 27 2019, 10:26 AM
sdesmalen committed rGe1eab42f65f2: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix (authored by sdesmalen).
[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix
Mar 27 2019, 10:25 AM
sdesmalen added 1 commit(s) for D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal: rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 27 2019, 10:24 AM
sdesmalen added an edge to rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal: D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 27 2019, 10:24 AM
sdesmalen committed rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal (authored by sdesmalen).
[AArch64] NFC: Cleanup isAArch64FrameOffsetLegal
Mar 27 2019, 6:17 AM
sdesmalen committed rG46edefe3c498: [AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfo (authored by sdesmalen).
[AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfo
Mar 27 2019, 3:38 AM

Mar 25 2019

sdesmalen added inline comments to D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 25 2019, 1:28 PM
sdesmalen added inline comments to D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 25 2019, 10:18 AM
sdesmalen updated the diff for D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
  • This patch now uses Optional<unsigned> for getUnscaledLdSt()
  • Separate out the non-functional changes from the functional change (the added cases in AArch64InstrInfo::getMemOpInfo)
  • Some more simplification of the arithmetic in isAArch64FrameOffsetLegal.
Mar 25 2019, 10:17 AM
sdesmalen accepted D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix.

Thanks @c-rhodes, LGTM.

Mar 25 2019, 2:59 AM · Restricted Project
sdesmalen added inline comments to D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix.
Mar 25 2019, 2:41 AM · Restricted Project

Mar 22 2019

sdesmalen added a comment to D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.

(not sure why Phabricator marked these comments as 'done' since they're not done yet)

Mar 22 2019, 10:30 AM
sdesmalen added inline comments to D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 22 2019, 10:24 AM
sdesmalen accepted D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix.

Thanks @c-rhodes, this was indeed a mismatch with the SVE spec. Minor nit: the SVE spill/fill instructions also take ZPRAny operands, you could add some tests for those instructions as well to ensure it is not limited to movprfx alone.

Mar 22 2019, 9:51 AM · Restricted Project

Mar 21 2019

sdesmalen created D59635: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal.
Mar 21 2019, 4:34 AM

Mar 14 2019

sdesmalen added a comment to D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.

@nikic thanks for pointing me to that discussion! I clearly misread the LangRef for this change :)
I agree it makes more sense to change these intrinsics and to make its accumulator argument always relevant (regardless of what flags are set) and AutoUpgrading older IR. Given that I'm currently working on this, I'd be happy to move this forward with patches and a proposal/discussion on the mailing list to change the experimental reduction intrinsics. @aemerson you expressed an intention to work on it later this year, do you have any objection to me moving forward with this now?

Mar 14 2019, 11:02 AM
sdesmalen added a parent revision for D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL: D59259: [AArch64] Use faddp to implement fadd reductions..
Mar 14 2019, 4:21 AM
sdesmalen added a child revision for D59259: [AArch64] Use faddp to implement fadd reductions.: D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.
Mar 14 2019, 4:21 AM
sdesmalen created D59356: [SelectionDAGBuilder] Use accumulator value in VECREDUCE_FADD/FMUL.
Mar 14 2019, 4:21 AM
sdesmalen updated the diff for D59259: [AArch64] Use faddp to implement fadd reductions..

Updated the tests to use a scalar accumulator value (instead of a vector accumulator value, which was wrong, but seemed to be completely ignored by SelectionDAGBuilder).

Mar 14 2019, 4:18 AM

Mar 13 2019

sdesmalen added inline comments to D59259: [AArch64] Use faddp to implement fadd reductions..
Mar 13 2019, 4:01 PM
sdesmalen updated the diff for D59259: [AArch64] Use faddp to implement fadd reductions..

This patch now matches ISD::VECREDUCE_FADD directly, and shows the diff with test/CodeGen/AArch64/vecreduce-fadd.ll.

Mar 13 2019, 8:20 AM
sdesmalen committed rG72fc7b842c81: [AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll (authored by sdesmalen).
[AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
Mar 13 2019, 8:18 AM

Mar 12 2019

sdesmalen created D59259: [AArch64] Use faddp to implement fadd reductions..
Mar 12 2019, 8:44 AM
sdesmalen added inline comments to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.
Mar 12 2019, 8:34 AM · Restricted Project

Mar 11 2019

sdesmalen added inline comments to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.
Mar 11 2019, 2:26 PM · Restricted Project
sdesmalen accepted D57728: Relax constraints for reduction vectorization.

Thanks for updating your patch @sanjoy ! LGTM (with a side-note on a follow up patch to take more specific flags in expandReductions).
You may want to update the commit message before you commit :)

Mar 11 2019, 4:54 AM · Restricted Project
sdesmalen accepted D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.

Thanks for making these changes, I think the patch looks good now!

Mar 11 2019, 4:26 AM · Restricted Project

Mar 6 2019

sdesmalen added a comment to D57728: Relax constraints for reduction vectorization.

Thanks for these changes to your patch @sanjoy! The patch is looking in good shape, just a few remaining nits mostly.

Mar 6 2019, 7:20 AM · Restricted Project

Feb 26 2019

sdesmalen added a comment to D58015: [SelectionDAG][AArch64] Legalize VECREDUCE.

Thanks for this patch @nikic! Please find some comments inline.

Feb 26 2019, 4:04 AM · Restricted Project

Feb 20 2019

sdesmalen added inline comments to D57728: Relax constraints for reduction vectorization.
Feb 20 2019, 8:19 AM · Restricted Project

Dec 31 2018

sdesmalen accepted D56128: [AArch64] Accept "sve" as arch feature in assembler.

LGTM, thanks.

Dec 31 2018, 1:47 AM

Nov 27 2018

sdesmalen accepted D54846: [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand.

The patch looks fine to me (with nit on the const_cast)

Nov 27 2018, 8:28 AM

Nov 26 2018

sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
  • resolved editorial comments.
Nov 26 2018, 6:09 AM
sdesmalen added a comment to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.

Just to double check before committing, @aaron.ballman are you happy with the tests?

Nov 26 2018, 5:38 AM
sdesmalen added a comment to D54846: [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand.

Thanks for making this change, I think having the interface more generic makes sense. Please find some comments inlined.

Nov 26 2018, 5:32 AM

Nov 19 2018

sdesmalen updated subscribers of D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 19 2018, 2:38 AM
sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.

Thanks all for the suggestions and comments! I've updated the patch with a better description of the attribute's behaviour (thanks @rjmccall for the starting point!) and added Sema tests.

Nov 19 2018, 2:34 AM

Nov 13 2018

sdesmalen updated the diff for D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
  • Removed _aarch64_vector_pcs and __aarch64_vector_pcs keywords in favour of supporting only __attribute__(aarch64_vector_pcs)).
Nov 13 2018, 4:16 AM
sdesmalen added inline comments to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 13 2018, 4:13 AM

Nov 12 2018

sdesmalen added inline comments to D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 12 2018, 5:58 AM
sdesmalen created D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang.
Nov 12 2018, 5:51 AM

Sep 6 2018

sdesmalen added a comment to D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute..

ping!

Sep 6 2018, 1:38 AM

Sep 4 2018

sdesmalen added a reviewer for D51477: [AArch64] Add parsing of aarch64_vector_pcs attribute.: thegameg.
Sep 4 2018, 5:25 AM
sdesmalen created D51617: Remove FrameAccess struct from hasLoadFromStackSlot.
Sep 4 2018, 2:52 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Calculate CSStackSize by accumulating reg-size for each saved register.
  • Only sets PairedReg in SavedRegs when it is not AArch64::NoRegister.
  • Removed trailing whitespace from test.
Sep 4 2018, 2:45 AM

Sep 3 2018

sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Sep 3 2018, 8:10 AM
sdesmalen added a comment to D51537: Extend hasStoreToStackSlot with list of FI accesses..

The code in hasLoadFromStackSlot filters out MMO's that have a pseudo source value of type Stack. If that function populates an array of only those MMOs, I think its safe to do a cast<FixedStackPseudoSourceValue>(mmo->getPseudoValue()) and get rid of the FrameAccess struct.

Sep 3 2018, 7:05 AM

Aug 31 2018

sdesmalen added a comment to D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Thanks @thegameg ! I've also created a patch to better describe the size of bytes spilled/reloaded for LDP/STP instructions in D51537.

Aug 31 2018, 5:45 AM
sdesmalen created D51537: Extend hasStoreToStackSlot with list of FI accesses..
Aug 31 2018, 5:44 AM
sdesmalen updated the diff for D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
  • Some refactoring to maintain CSStackSize.
  • Migrated .ll test to a .mir test.
Aug 31 2018, 2:56 AM
sdesmalen added inline comments to D51479: [AArch64] Implement aarch64_vector_pcs codegen support..
Aug 31 2018, 2:55 AM
sdesmalen updated the diff for D51478: [AArch64] NFC: Refactoring to prepare for vector PCS..

Fixed issue with incorrect size of MachineMemOperand.

Aug 31 2018, 2:55 AM