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StephenFan (luxufan)
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User Since
Jul 14 2020, 5:33 AM (39 w, 5 h)

Recent Activity

Sun, Apr 11

StephenFan requested review of D100286: [RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed.
Sun, Apr 11, 10:43 PM · Restricted Project
StephenFan requested review of D100284: [RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed.
Sun, Apr 11, 10:29 PM · Restricted Project

Thu, Apr 8

StephenFan added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
In D98101#2663432, @asb wrote:

Could you please rebase this to account for D98716?

I _think_ the right fix is to change the call for needsStackRealignment to shouldRealignStack. But I'm seeing multiple runtime failures for the GCC torture suite with the patch applied. e.g. 20031012-1.c at O0 for rv32imafdc ilp32.

Thu, Apr 8, 10:02 PM · Restricted Project
StephenFan updated the diff for D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

Fix error.

Thu, Apr 8, 9:51 PM · Restricted Project

Wed, Apr 7

StephenFan accepted D100035: [RISCV] Add scalable offset under very large stack size..
Wed, Apr 7, 11:15 PM · Restricted Project

Sun, Mar 21

StephenFan closed D98922: Delete Redundant parameters in clang/unittests/AST/CMakeLists.txt.
Sun, Mar 21, 10:55 PM · Restricted Project
StephenFan added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

Ping.

Sun, Mar 21, 10:38 PM · Restricted Project
StephenFan committed rG02ffbac844e0: [RISCV] remove redundant instruction when eliminate frame index (authored by StephenFan).
[RISCV] remove redundant instruction when eliminate frame index
Sun, Mar 21, 3:55 AM
StephenFan closed D92479: [RISCV] remove redundant instruction when eliminate frame index.
Sun, Mar 21, 3:55 AM · Restricted Project

Fri, Mar 19

StephenFan accepted D98802: [RISCV] Fix offset computation for RVV.
Fri, Mar 19, 6:56 AM · Restricted Project
StephenFan added inline comments to D98802: [RISCV] Fix offset computation for RVV.
Fri, Mar 19, 6:53 AM · Restricted Project

Thu, Mar 18

StephenFan added inline comments to D98802: [RISCV] Fix offset computation for RVV.
Thu, Mar 18, 10:46 PM · Restricted Project
StephenFan added a comment to D98802: [RISCV] Fix offset computation for RVV.
Thu, Mar 18, 10:45 PM · Restricted Project
StephenFan added a comment to D98802: [RISCV] Fix offset computation for RVV.

Hi @rogfer01 ! It is reasonable to me. But I think the instruction of BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), SPReg) can be eliminated. Firstly, the value of calleeSavedStackSize can be regarded as a aligned value(For example, aligned to MFI.getStackAlign()). Then we can calculate the padding size by the aligned calleeSavedStackSize minus the original calleeSavedStackSize. When emits prologue, we can minus the value of
MFI.getStackSize() - original calleeSavedStackSize + aligned calleeSavedStackSize. When get the offset of the rvv object, we can MFI.getStackSize() - original calleesavedStackSize, because we just want to calculate the
non-calleesaved field size. My English is poor and I am a beginner of LLVM-RISCV. So I don't know if it makes sense to you.

Thu, Mar 18, 9:03 AM · Restricted Project

Mar 13 2021

StephenFan committed rGa9b9c64fd4c8: change rvv frame layout (authored by StephenFan).
change rvv frame layout
Mar 13 2021, 12:12 AM
StephenFan closed D97111: [RISCV] change rvv frame layout.
Mar 13 2021, 12:11 AM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

rebase

Mar 13 2021, 12:06 AM · Restricted Project

Mar 12 2021

StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

Address @rogfer01 's comment.

Mar 12 2021, 11:47 PM · Restricted Project
StephenFan committed rG5ddbd1fdbb08: [RISCV] Remove redundancy -mattr=+d in test file (authored by StephenFan).
[RISCV] Remove redundancy -mattr=+d in test file
Mar 12 2021, 11:22 PM
StephenFan closed D97177: [RISCV] Remove redundancy -mattr=+d in test file.
Mar 12 2021, 11:21 PM · Restricted Project

Mar 5 2021

StephenFan updated the diff for D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

Fix comment error.

Mar 5 2021, 10:51 PM · Restricted Project
StephenFan added inline comments to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Mar 5 2021, 10:39 PM · Restricted Project
StephenFan updated the diff for D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

Pre-commit local-stack-allocation.ll test.

Mar 5 2021, 10:32 PM · Restricted Project
StephenFan added inline comments to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Mar 5 2021, 10:25 PM · Restricted Project
StephenFan added inline comments to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Mar 5 2021, 10:10 PM · Restricted Project
StephenFan updated the summary of D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Mar 5 2021, 9:36 PM · Restricted Project
StephenFan requested review of D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Mar 5 2021, 9:35 PM · Restricted Project

Mar 3 2021

StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

Delete white spaces.

Mar 3 2021, 5:04 AM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

Address @rogfer01 's comment. Add rvv-framelayout.ll test.

Mar 3 2021, 5:02 AM · Restricted Project

Mar 1 2021

StephenFan added a comment to D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.
Mar 1 2021, 1:50 AM · Restricted Project
StephenFan updated the diff for D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.

Address @luismarques 's comment

Mar 1 2021, 12:36 AM · Restricted Project

Feb 27 2021

StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

delete unnecessary white space

Feb 27 2021, 10:15 PM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

Address @jrtc27 's comments

Feb 27 2021, 10:04 PM · Restricted Project

Feb 25 2021

StephenFan added a comment to D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.

Ping.

Feb 25 2021, 4:02 AM · Restricted Project

Feb 24 2021

StephenFan added inline comments to D97111: [RISCV] change rvv frame layout.
Feb 24 2021, 5:20 AM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

Address @rogfer01 's comments.

Feb 24 2021, 5:18 AM · Restricted Project

Feb 23 2021

StephenFan requested review of D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.
Feb 23 2021, 5:07 AM · Restricted Project

Feb 22 2021

StephenFan updated the summary of D97111: [RISCV] change rvv frame layout.
Feb 22 2021, 3:58 AM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

address @HsiangKai and @rogfer01 's comments

Feb 22 2021, 3:52 AM · Restricted Project

Feb 21 2021

StephenFan requested review of D97177: [RISCV] Remove redundancy -mattr=+d in test file.
Feb 21 2021, 9:48 PM · Restricted Project
StephenFan added a comment to D97111: [RISCV] change rvv frame layout.

Hi @StephenFan. I wonder if we want to do this only when we index via sp.

My understanding is that the emergency slot will be close enough when we index via fp/bp in the previous layout. In the previous layout, when indexing a scalar via sp we have to cross the RVV part (which needs an extra register) to reach the scalar registers (where the emergency slot will be located). IIUC, your approach it fixes the sp case but complicates the fp/bp case to access the emergency slot because now we need to jump over RVV.

My suggestion means we want to have the RVV vectors as far from the frame pointer as possible (the one being used sp/fp/bp), so scalars are still straightforward to access even in the presence of RVV. This means different layouts when indexing with sp and when indexing with fp/bp. In summary: your new layout for sp but the previous one for fp/bp. Does this make sense?

Make sense to me. I didn't consider the case that needs fp to access the emergency spill slot. In my patch, It seems that make use of the bp register is necessary when variable-sized local variables and rvv stack objects exist at the same time. Because if uses fp to access the emergency spill slot needs an extra register. In the original patch, make use of the fp register is necessary when rvv stack objects exist. I prefer the current frame layout, Because it only needs a bp register when variable-sized local variables and rvv stack objects exist. Do you agree it?

When it is necessary to have fp, the frame layout will look like as below.

|---------------------------------| <- frame pointer (fp)
| scalar callee-saved registers   |
|---------------------------------|
| scalar local variables          |
|---------------------------------|
| ///// realignment /////         |
|---------------------------------|
| scalar outgoing arguments       |
|---------------------------------|
| RVV local variables &&          |
| RVV outgoing arguments          |
|---------------------------------| <- end of frame (sp)

What do you mean "if uses fp to access the emergency spill slot needs an extra register"?

I agree with Roger. We only need to change the frame layout when accessing frame objects only using sp. That is, we should put RVV objects as far as 'base' as possible. The 'base' could be sp, fp or bp.

Feb 21 2021, 9:20 PM · Restricted Project

Feb 20 2021

StephenFan added a comment to D97111: [RISCV] change rvv frame layout.

Hi @StephenFan. I wonder if we want to do this only when we index via sp.

My understanding is that the emergency slot will be close enough when we index via fp/bp in the previous layout. In the previous layout, when indexing a scalar via sp we have to cross the RVV part (which needs an extra register) to reach the scalar registers (where the emergency slot will be located). IIUC, your approach it fixes the sp case but complicates the fp/bp case to access the emergency slot because now we need to jump over RVV.

My suggestion means we want to have the RVV vectors as far from the frame pointer as possible (the one being used sp/fp/bp), so scalars are still straightforward to access even in the presence of RVV. This means different layouts when indexing with sp and when indexing with fp/bp. In summary: your new layout for sp but the previous one for fp/bp. Does this make sense?

Make sense to me. I didn't consider the case that needs fp to access the emergency spill slot. In my patch, It seems that make use of the bp register is necessary when variable-sized local variables and rvv stack objects exist at the same time. Because if uses fp to access the emergency spill slot needs an extra register. In the original patch, make use of the fp register is necessary when rvv stack objects exist. I prefer the current frame layout, Because it only needs a bp register when variable-sized local variables and rvv stack objects exist. Do you agree it?

Feb 20 2021, 10:25 PM · Restricted Project
StephenFan added a comment to D97111: [RISCV] change rvv frame layout.

Hi @StephenFan. I wonder if we want to do this only when we index via sp.

My understanding is that the emergency slot will be close enough when we index via fp/bp in the previous layout. In the previous layout, when indexing a scalar via sp we have to cross the RVV part (which needs an extra register) to reach the scalar registers (where the emergency slot will be located). IIUC, your approach it fixes the sp case but complicates the fp/bp case to access the emergency slot because now we need to jump over RVV.

My suggestion means we want to have the RVV vectors as far from the frame pointer as possible (the one being used sp/fp/bp), so scalars are still straightforward to access even in the presence of RVV. This means different layouts when indexing with sp and when indexing with fp/bp. In summary: your new layout for sp but the previous one for fp/bp. Does this make sense?

Feb 20 2021, 9:53 PM · Restricted Project
StephenFan added a comment to D97111: [RISCV] change rvv frame layout.

address @criag.topper 's comment

Feb 20 2021, 3:19 AM · Restricted Project

Feb 19 2021

StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

add test cases that deleted incautious

Feb 19 2021, 10:49 PM · Restricted Project
StephenFan updated the diff for D97111: [RISCV] change rvv frame layout.

address @criag.topper 's comment

Feb 19 2021, 10:41 PM · Restricted Project
StephenFan added inline comments to D97111: [RISCV] change rvv frame layout.
Feb 19 2021, 10:29 PM · Restricted Project
StephenFan retitled D97111: [RISCV] change rvv frame layout from change rvv frame layout to [RISCV] change rvv frame layout.
Feb 19 2021, 10:25 PM · Restricted Project
StephenFan requested review of D97111: [RISCV] change rvv frame layout.
Feb 19 2021, 10:22 PM · Restricted Project

Feb 17 2021

StephenFan committed rG709ea8bc8781: [RISCV] Simplify BP initialisation (authored by StephenFan).
[RISCV] Simplify BP initialisation
Feb 17 2021, 4:34 AM
StephenFan closed D95227: [RISCV] Simplify BP initialisation.
Feb 17 2021, 4:34 AM · Restricted Project

Feb 12 2021

StephenFan committed rGfeaf1d81e39e: [RISCV] Change parseVTypeI function (authored by StephenFan).
[RISCV] Change parseVTypeI function
Feb 12 2021, 3:39 AM
StephenFan closed D96218: [RISCV] Change parseVTypeI function.
Feb 12 2021, 3:39 AM · Restricted Project
StephenFan added a comment to D92479: [RISCV] remove redundant instruction when eliminate frame index.

Ping.

Feb 12 2021, 2:49 AM · Restricted Project

Feb 11 2021

StephenFan updated the diff for D96218: [RISCV] Change parseVTypeI function.

Address @craig.topper 's comments

Feb 11 2021, 11:17 PM · Restricted Project
StephenFan updated the diff for D96218: [RISCV] Change parseVTypeI function.

Address craig.topper 's comment

Feb 11 2021, 11:13 PM · Restricted Project
StephenFan abandoned D96576: Address craig.topper 's comment.
Feb 11 2021, 11:05 PM · Restricted Project
StephenFan updated the diff for D96576: Address craig.topper 's comment.

Address craig.topper 's comment

Feb 11 2021, 11:03 PM · Restricted Project
StephenFan requested review of D96576: Address craig.topper 's comment.
Feb 11 2021, 11:00 PM · Restricted Project
StephenFan added a comment to D96218: [RISCV] Change parseVTypeI function.

ping.

Feb 11 2021, 2:06 AM · Restricted Project

Feb 7 2021

StephenFan updated the summary of D96218: [RISCV] Change parseVTypeI function.
Feb 7 2021, 12:44 AM · Restricted Project

Feb 6 2021

StephenFan retitled D96218: [RISCV] Change parseVTypeI function from Correct parseVTypeI function 1. Make the assembler detect the out of range immediate in vsetivli instruction. 2. Make the added vsetvli instrction test cases report more concrete error message. to [RISCV] Change parseVTypeI function.
Feb 6 2021, 11:57 PM · Restricted Project
StephenFan requested review of D96218: [RISCV] Change parseVTypeI function.
Feb 6 2021, 11:56 PM · Restricted Project

Feb 5 2021

StephenFan added inline comments to D92479: [RISCV] remove redundant instruction when eliminate frame index.
Feb 5 2021, 5:36 AM · Restricted Project
StephenFan added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.
In D93298#2544775, @asb wrote:

According to @jrtc27 's review that is
"As for Zfinx itself, well, the idea is fine, but I really detest the way it's being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not work_ so it is not an _extension_. Instead it should really be a set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and Zfhinx, but apparently asking code that complies with a ratified standard to change itself in order to not break when a new extension is introduced is a-ok in the RISC-V world.".
We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and Zfhinx.

Ah I see. I interpreted jrtc27's comment as a general gripe about the spec (which perhaps could be relayed to those working on the zfinx spec) rather as a direction for changing this patch in particular. Anyway, it's a detail that shouldn't affect an initial review. Thanks for clarifying.

Feb 5 2021, 5:27 AM · Restricted Project, Restricted Project
StephenFan added a reviewer for D93298: [RISCV] add the MC layer support of Zfinx extension: asb.
Feb 5 2021, 2:42 AM · Restricted Project, Restricted Project
StephenFan added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.
In D93298#2544443, @asb wrote:

I started reviewing this alongside the specification in https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to be used in this patch. I think intent is that rv32ifd_zfinx is the equivalent of "zfdinx" in this patch. Is there a reason to go for different naming, or a different version of the spec I should be looking at?

According to @jrtc27 's review that is
"As for Zfinx itself, well, the idea is fine, but I really detest the way it's being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not work_ so it is not an _extension_. Instead it should really be a set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and Zfhinx, but apparently asking code that complies with a ratified standard to change itself in order to not break when a new extension is introduced is a-ok in the RISC-V world.".
We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and Zfhinx.

Feb 5 2021, 2:42 AM · Restricted Project, Restricted Project

Jan 24 2021

StephenFan updated the diff for D95227: [RISCV] Simplify BP initialisation.

Address craig.topper's comment.

Jan 24 2021, 6:11 PM · Restricted Project

Jan 22 2021

StephenFan added a comment to D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.

@StephenFan thank you for the bug report. I had a feeling that converting FPR32 to FPR64 with a SUBREG_TO_REG could cause a problem.

I have a question that why not make the scalar float point as FPR64 (not FPR32) then when encounter the FPR32 or FPR16, use the EXTRACT_SUBREG opcode.

If you look at the current output for the fpr-spill-scalar.ll test added in D95234, you'll see that we would generate a 8 byte spill slot for float and half if we use FPR64. But the instruction to store an 8 byte F register isn't supported without the D extension.

@StephenFan thank you for the bug report. I had a feeling that converting FPR32 to FPR64 with a SUBREG_TO_REG could cause a problem.

I have a question that why not make the scalar float point as FPR64 (not FPR32) then when encounter the FPR32 or FPR16, use the EXTRACT_SUBREG opcode.

Get it.

Jan 22 2021, 7:36 PM · Restricted Project
StephenFan added a comment to D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.

@StephenFan thank you for the bug report. I had a feeling that converting FPR32 to FPR64 with a SUBREG_TO_REG could cause a problem.

Jan 22 2021, 7:25 PM · Restricted Project
StephenFan abandoned D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.
Jan 22 2021, 7:06 PM · Restricted Project
StephenFan added a comment to D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.

In D95234, I defined different pseudo instructions for different floating-point register classes. The floating-point vector pseudo instructions have correct register class information in D95234. I think it also solves the issue you encountered.

Jan 22 2021, 7:01 PM · Restricted Project
StephenFan added a comment to D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.

The commit message could do with improving in many respects (all of spelling, grammar, formatting, style and content). Please clearly state what the actual issue is and why this change is correct given the comment that is already there to explain the current behaviour.

Jan 22 2021, 7:00 PM · Restricted Project
StephenFan retitled D95227: [RISCV] Simplify BP initialisation from DRY for copy physical register to [RISCV]DRY for copy physical register.
Jan 22 2021, 6:53 AM · Restricted Project
StephenFan retitled D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll from A bug when llc -O0 vfmv.f.s.ll to [RISCV]A bug when llc -O0 vfmv.f.s.ll.
Jan 22 2021, 6:52 AM · Restricted Project
StephenFan requested review of D95227: [RISCV] Simplify BP initialisation.
Jan 22 2021, 6:15 AM · Restricted Project
StephenFan retitled D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll from fix a bug when llc -O0 vfmv.f.s.ll to A bug when llc -O0 vfmv.f.s.ll.
Jan 22 2021, 1:21 AM · Restricted Project
StephenFan requested review of D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll.
Jan 22 2021, 1:18 AM · Restricted Project

Jan 21 2021

StephenFan added a comment to D92479: [RISCV] remove redundant instruction when eliminate frame index.

ping...

Jan 21 2021, 6:42 AM · Restricted Project

Jan 4 2021

StephenFan added inline comments to D93298: [RISCV] add the MC layer support of Zfinx extension.
Jan 4 2021, 4:23 AM · Restricted Project, Restricted Project
StephenFan added inline comments to D93298: [RISCV] add the MC layer support of Zfinx extension.
Jan 4 2021, 4:19 AM · Restricted Project, Restricted Project
StephenFan added inline comments to D93298: [RISCV] add the MC layer support of Zfinx extension.
Jan 4 2021, 3:20 AM · Restricted Project, Restricted Project

Dec 28 2020

StephenFan added a comment to D53291: add riscv32e to the llvm.

Are you have plans to promote the codegen of rv32e, if not, I want to try it

Dec 28 2020, 9:57 PM · Restricted Project

Dec 24 2020

StephenFan added inline comments to D93750: [RISCV] Frame handling for RISC-V V extension..
Dec 24 2020, 7:21 PM · Restricted Project
StephenFan added inline comments to D93750: [RISCV] Frame handling for RISC-V V extension..
Dec 24 2020, 6:57 AM · Restricted Project

Dec 23 2020

StephenFan added inline comments to D93750: [RISCV] Frame handling for RISC-V V extension..
Dec 23 2020, 8:17 PM · Restricted Project

Dec 17 2020

StephenFan added inline comments to D93298: [RISCV] add the MC layer support of Zfinx extension.
Dec 17 2020, 7:21 AM · Restricted Project, Restricted Project

Dec 11 2020

StephenFan added inline comments to D92479: [RISCV] remove redundant instruction when eliminate frame index.
Dec 11 2020, 4:52 AM · Restricted Project

Dec 10 2020

StephenFan retitled D92479: [RISCV] remove redundant instruction when eliminate frame index from [RISCV] remove instruction mv a0, a0 to [RISCV] remove redundant instruction when eliminate frame index.
Dec 10 2020, 10:36 PM · Restricted Project

Dec 3 2020

StephenFan added a comment to D92479: [RISCV] remove redundant instruction when eliminate frame index.

It's also wrong if the ADDI has FrameReg as its destination. A neater approach might be to always use the destination register (if there is one, using general instruction query information) as the destination for the ADD, keeping the scratch register for the movImm call. Then you'd only need special logic to work out whether you need to keep the (modified) existing instruction.

Dec 3 2020, 10:30 PM · Restricted Project
StephenFan updated the diff for D92479: [RISCV] remove redundant instruction when eliminate frame index.
Dec 3 2020, 10:27 PM · Restricted Project

Dec 2 2020

StephenFan added reviewers for D92479: [RISCV] remove redundant instruction when eliminate frame index: asb, lenary, craig.topper.
Dec 2 2020, 6:46 AM · Restricted Project
StephenFan requested review of D92479: [RISCV] remove redundant instruction when eliminate frame index.
Dec 2 2020, 6:45 AM · Restricted Project

Nov 23 2020

StephenFan added a comment to D91931: [RISCV][GlobalISel] Select add i32, i32.

There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.

I noticed that these patches have been silent for several months, how can I promote this?

I've not been able to work on those patches for some time but if someone might commandeer them to rebase them and work on top of them I think that would be a good starting point and I would happily take a look at the changes. Otherwise I may get some time to update them myself within a month or two.

Nov 23 2020, 6:25 AM · Restricted Project

Nov 22 2020

StephenFan added a comment to D91931: [RISCV][GlobalISel] Select add i32, i32.

There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.

Nov 22 2020, 6:45 PM · Restricted Project
StephenFan updated the summary of D91931: [RISCV][GlobalISel] Select add i32, i32.
Nov 22 2020, 6:46 AM · Restricted Project
StephenFan requested review of D91931: [RISCV][GlobalISel] Select add i32, i32.
Nov 22 2020, 6:34 AM · Restricted Project

Nov 19 2020

StephenFan added inline comments to D89788: [RISCV] Add GHC calling convention.
Nov 19 2020, 6:06 PM · Restricted Project

Oct 16 2020

StephenFan added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 2:13 AM · Restricted Project
StephenFan added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 2:00 AM · Restricted Project