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StephenFan (luxufan)
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Jul 14 2020, 5:33 AM (19 w, 3 d)

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Mon, Nov 23

• StephenFan added a comment to D91931: [RISCV][GlobalISel] Select add i32, i32.
In D91931#2410704, @lewis-revill wrote:
In D91931#2410405, @StephenFan wrote:
In D91931#2410204, @craig.topper wrote:

There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.

I noticed that these patches have been silent for several months, how can I promote this?

I've not been able to work on those patches for some time but if someone might commandeer them to rebase them and work on top of them I think that would be a good starting point and I would happily take a look at the changes. Otherwise I may get some time to update them myself within a month or two.

Mon, Nov 23, 6:25 AM · Restricted Project

Sun, Nov 22

• StephenFan added a comment to D91931: [RISCV][GlobalISel] Select add i32, i32.
In D91931#2410204, @craig.topper wrote:

There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.

Sun, Nov 22, 6:45 PM · Restricted Project
• StephenFan updated the summary of D91931: [RISCV][GlobalISel] Select add i32, i32.
Sun, Nov 22, 6:46 AM · Restricted Project
• StephenFan requested review of D91931: [RISCV][GlobalISel] Select add i32, i32.
Sun, Nov 22, 6:34 AM · Restricted Project

Thu, Nov 19

• StephenFan added inline comments to D89788: [RISCV] Add GHC calling convention.
Thu, Nov 19, 6:06 PM · Restricted Project

Oct 16 2020

• StephenFan added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 2:13 AM · Restricted Project
• StephenFan added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 2:00 AM · Restricted Project

Aug 26 2020

• StephenFan updated the diff for D85400: [RISCV] add the MC layer support of riscv vector Zvqmac extension.

rebaes to the latest upstream master

Aug 26 2020, 11:28 PM · Restricted Project
• StephenFan abandoned D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Aug 26 2020, 11:23 PM · Restricted Project
• StephenFan committed rG888c02deee26: [RISCV] add the MC layer support of riscv vector Zvamo extension (authored by • StephenFan).
[RISCV] add the MC layer support of riscv vector Zvamo extension
Aug 26 2020, 11:12 PM
• StephenFan closed D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
Aug 26 2020, 11:12 PM · Restricted Project

Aug 24 2020

• StephenFan updated the diff for D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.

rebase to latest master

Aug 24 2020, 12:18 AM · Restricted Project

Aug 20 2020

• StephenFan updated the diff for D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
Aug 20 2020, 5:07 AM · Restricted Project
• StephenFan updated the diff for D85400: [RISCV] add the MC layer support of riscv vector Zvqmac extension.

change the VALUr_IV_V_X to VALUr_IV_X, change the 0b111111 to 0b111111

Aug 20 2020, 4:52 AM · Restricted Project
• StephenFan updated the diff for D85400: [RISCV] add the MC layer support of riscv vector Zvqmac extension.
Aug 20 2020, 4:47 AM · Restricted Project

Aug 19 2020

• StephenFan committed rG6c5039a10f33: [RISCV] add the assemble and disassemble support of Zvlsseg instructions (authored by • StephenFan).
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
Aug 19 2020, 1:26 AM
• StephenFan closed D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Aug 19 2020, 1:26 AM · Restricted Project

Aug 14 2020

• StephenFan updated the diff for D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Aug 14 2020, 2:12 AM · Restricted Project
• StephenFan updated the diff for D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.

Remove sumop, Remove MOPSTIndexedOrder. zvlsseg -> FeatureStdExtV

Aug 14 2020, 2:08 AM · Restricted Project

Aug 7 2020

• StephenFan added a comment to D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
In D85069#2201754, @HsiangKai wrote:

I confused the relationship of sub-extensions before. Sorry for that.
There are some discussions[0] about the relationship between vector sub-extensions. It seems that


V-extension implies Zvamo + Zvlsseg

Zvqmac, Zvamo and Zvlsseg are stand alone sub extensions. That is, Zvamo does not imply V extension.

Zvqmac has no implied extensions.
Zvamo implies A-extension.
Zvlsseg has no implied extensions.

Do you agree with that?

[0] https://github.com/riscv/riscv-v-spec/issues/546

Aug 7 2020, 6:49 PM · Restricted Project

Aug 5 2020

• StephenFan requested review of D85400: [RISCV] add the MC layer support of riscv vector Zvqmac extension.
Aug 5 2020, 11:53 PM · Restricted Project

Aug 4 2020

• StephenFan added a comment to D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
In D84416#2192037, @HsiangKai wrote:

D80802 is landed. Please rebase on master.

Please merge D83775 and this revision into one revision.

Aug 4 2020, 7:20 AM · Restricted Project
• StephenFan updated the diff for D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Aug 4 2020, 7:19 AM · Restricted Project
• StephenFan updated the diff for D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
Aug 4 2020, 6:41 AM · Restricted Project
• StephenFan updated the diff for D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
Aug 4 2020, 6:39 AM · Restricted Project
• StephenFan updated the diff for D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.

remove the hasStdExtV and hasStdExtA predicates, and add the IsRV64 predicates

Aug 4 2020, 6:32 AM · Restricted Project

Aug 2 2020

• StephenFan committed rGa96921afa702: [RISCV] eliminate the repetition declare of SDLoc DL (authored by • StephenFan).
[RISCV] eliminate the repetition declare of SDLoc DL
Aug 2 2020, 7:26 PM
• StephenFan closed D85002: [RISCV] eliminate the repetition declare of SDLoc DL.
Aug 2 2020, 7:26 PM · Restricted Project

Jul 31 2020

• StephenFan requested review of D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.
Jul 31 2020, 11:42 PM · Restricted Project

Jul 30 2020

• StephenFan requested review of D85002: [RISCV] eliminate the repetition declare of SDLoc DL.
Jul 30 2020, 10:57 PM · Restricted Project

Jul 29 2020

• StephenFan added a reviewer for D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions: evandro.
Jul 29 2020, 5:53 AM · Restricted Project

Jul 25 2020

Herald added a project to D84585: Fix a comment error in stack object part : Restricted Project.
Jul 25 2020, 6:42 AM · Restricted Project

Jul 23 2020

Herald added a project to D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions: Restricted Project.
Jul 23 2020, 7:59 AM · Restricted Project

Jul 16 2020

• StephenFan added a comment to D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
In D83775#2152595, @simoncook wrote:

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?

Jul 16 2020, 12:52 AM · Restricted Project
• StephenFan updated the diff for D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Jul 16 2020, 12:49 AM · Restricted Project

Jul 14 2020

• StephenFan retitled D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions from add the assemble and disassemble support of Zvlsseg instructions to [RISCV] add the assemble and disassemble support of Zvlsseg instructions.
Jul 14 2020, 7:39 AM · Restricted Project
Herald added a project to D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions: Restricted Project.
Jul 14 2020, 7:35 AM · Restricted Project