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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (232 w, 2 d)

Recent Activity

Wed, Oct 21

rogfer01 added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

Could you demonstrate that RVV intrinsic can share the same infrastructure?

Wed, Oct 21, 5:39 AM · Restricted Project
rogfer01 added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Wed, Oct 21, 5:39 AM · Restricted Project

Mon, Oct 19

rogfer01 added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Mon, Oct 19, 2:42 AM · Restricted Project

Fri, Oct 16

rogfer01 added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html

Fri, Oct 16, 1:03 AM · Restricted Project

Mon, Oct 12

rogfer01 added a comment to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.

Looking into the origin of this problem, git bisect points at cb82de29601 but I don't think it is the culprit. Looks like we may have been a bit unlucky during register allocation with the new sequence of instructions.

Mon, Oct 12, 11:31 AM · Restricted Project
rogfer01 updated the diff for D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.

ChangeLog:

  • Forgot to add the test for RISC-V
Mon, Oct 12, 7:46 AM · Restricted Project
rogfer01 requested review of D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.
Mon, Oct 12, 7:44 AM · Restricted Project
rogfer01 requested review of D89237: [RISCV] Do not grow the stack a second time when we need to realign the stack.
Mon, Oct 12, 7:09 AM · Restricted Project

Sep 1 2020

rogfer01 added inline comments to D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV..
Sep 1 2020, 11:13 PM · Restricted Project

Aug 12 2020

rogfer01 added a comment to D85794: [llvm][LV] Replace `unsigned VF` with `ElementCount VF` [NFCI].

Out of curiosity, what is your approach? Carrying around a bool Scalable flag?

Aug 12 2020, 1:14 PM · Restricted Project
rogfer01 added a comment to D85794: [llvm][LV] Replace `unsigned VF` with `ElementCount VF` [NFCI].

I have applied all feedback, but I have proposed an alternative approach to the one suggested by @rengolin in one of the comments, for static methods like ElementCount::get[Non]Scalable.

Aug 12 2020, 1:11 PM · Restricted Project

Aug 11 2020

rogfer01 added a comment to D85794: [llvm][LV] Replace `unsigned VF` with `ElementCount VF` [NFCI].

Hi @fpetrogalli, thanks for this proposal.

Aug 11 2020, 10:50 PM · Restricted Project

Aug 10 2020

rogfer01 added inline comments to D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV..
Aug 10 2020, 11:10 PM · Restricted Project

Jul 15 2020

rogfer01 committed rG14bc5e149d11: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1) (authored by rogfer01).
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
Jul 15 2020, 12:40 AM
rogfer01 committed rG2b6215f188bf: [NFC] Add tests for boolean comparisons (authored by rogfer01).
[NFC] Add tests for boolean comparisons
Jul 15 2020, 12:40 AM
rogfer01 closed D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Jul 15 2020, 12:40 AM · Restricted Project
rogfer01 closed D65801: [NFC] Add tests for boolean comparisons.
Jul 15 2020, 12:40 AM · Restricted Project
rogfer01 added a comment to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

Thanks all for the review, I'll land this shortly.

Jul 15 2020, 12:32 AM · Restricted Project

Jul 14 2020

rogfer01 committed rG0cbdd2a82ad8: [RISCV] Fix isStoreToStackSlot (authored by rogfer01).
[RISCV] Fix isStoreToStackSlot
Jul 14 2020, 6:07 AM
rogfer01 committed rGc1d021e2cc9f: [NFC][RISCV] Test for D81805 (authored by rogfer01).
[NFC][RISCV] Test for D81805
Jul 14 2020, 6:07 AM
rogfer01 closed D81805: [RISCV] Fix isStoreToStackSlot.
Jul 14 2020, 6:07 AM · Restricted Project
rogfer01 closed D83750: [NFC][RISCV] Test for D81805.
Jul 14 2020, 6:07 AM · Restricted Project
rogfer01 updated the diff for D81805: [RISCV] Fix isStoreToStackSlot.

ChangeLog:

  • Rebase
Jul 14 2020, 3:36 AM · Restricted Project
rogfer01 updated the diff for D83750: [NFC][RISCV] Test for D81805.

ChangeLog:

  • Remove dubious branch using undef. Use a plain ret void instead.
Jul 14 2020, 3:34 AM · Restricted Project
rogfer01 added a comment to D83750: [NFC][RISCV] Test for D81805.

Are we sure we want to branch on undef to one of two unreachables?

I suppose we cannot use ret as we don't have a non-constant to return anyway.

Given this shows a change in the behaviour of D81805, I'm happy for this to land.

Jul 14 2020, 2:47 AM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Remove assert
Jul 14 2020, 2:11 AM · Restricted Project
rogfer01 updated the diff for D81805: [RISCV] Fix isStoreToStackSlot.

ChangeLog:

Jul 14 2020, 12:37 AM · Restricted Project
Herald added a project to D83750: [NFC][RISCV] Test for D81805: Restricted Project.
Jul 14 2020, 12:35 AM · Restricted Project

Jul 13 2020

rogfer01 added a comment to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

Apologies, I totally forgot about this one. I'll update it ASAP.

Jul 13 2020, 8:30 AM · Restricted Project
rogfer01 added a comment to D82988: [RISCV] Avoid Splitting MBB in RISCVExpandPseudo.

Would it make sense to still expand these constructs late (e.g. renaming RISCVExpandAtomicPseudoInsts.cpp into RISCVLateExpandPseudoInsts.cpp) still using PreInstrSymbol?

Jul 13 2020, 6:20 AM · Restricted Project
rogfer01 added a comment to D82988: [RISCV] Avoid Splitting MBB in RISCVExpandPseudo.

I'm sorry to report that this approach is still problematic. In some of the testcases of the LLVM test-suite the pass when built with -fPIC -O3, pass Branch Probability Basic Block Placement decides to copy the AUIPC / LD pair but the copies carry around the same symbol. This fails with:

Jul 13 2020, 5:48 AM · Restricted Project

Jul 1 2020

rogfer01 added a comment to D82988: [RISCV] Avoid Splitting MBB in RISCVExpandPseudo.

Thanks a lot @lenary, this seems a much better approach.

Jul 1 2020, 1:32 PM · Restricted Project
rogfer01 added a comment to D79635: [RISCV] Split the pseudo instruction splitting pass.

This patch breaks compiling the Linux kernel:

Thanks for the detailed bug report. I have addressed this by temporarily reverting the part of this patch that wasn't NFC. This should solve the problem for now, if not please let me know.

Jul 1 2020, 8:37 AM · Restricted Project
rogfer01 added inline comments to D80802: [RISCV] Upgrade RVV MC to v0.9..
Jul 1 2020, 1:35 AM · Restricted Project, Restricted Project

Jun 14 2020

rogfer01 added a comment to D81805: [RISCV] Fix isStoreToStackSlot.

I have been unable to come up with a test that shows any change (I may check LNT to see if something changes), so ideas are welcome here.

Jun 14 2020, 7:29 AM · Restricted Project
rogfer01 set the repository for D81805: [RISCV] Fix isStoreToStackSlot to rG LLVM Github Monorepo.
Jun 14 2020, 7:29 AM · Restricted Project
rogfer01 created D81805: [RISCV] Fix isStoreToStackSlot.
Jun 14 2020, 7:29 AM · Restricted Project

Jun 12 2020

rogfer01 added inline comments to D81724: [MVT] Add new MVT types for RISC-V vector..
Jun 12 2020, 6:26 AM · Restricted Project
rogfer01 added inline comments to D81724: [MVT] Add new MVT types for RISC-V vector..
Jun 12 2020, 6:26 AM · Restricted Project

Jun 8 2020

rogfer01 added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

The patch as it stands now LGTM and I think it can be committed. Is there any objection remaining?

Jun 8 2020, 6:30 AM · Restricted Project, Restricted Project

May 27 2020

rogfer01 added inline comments to D79706: [CodeGen][BFloat] Add bfloat MVT type.
May 27 2020, 9:11 AM · Restricted Project

May 20 2020

rogfer01 added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

@HsiangKai: just to confirm and to avoid confusion for other reviewers.

May 20 2020, 1:02 AM · Restricted Project, Restricted Project

May 18 2020

rogfer01 added a comment to D79100: [LV] Emit new IR intrinsic llvm.get.active.mask for tail-folded loops.

Tail-predication is a new form of predication in MVE for vector loops that implicitely predicates the last vector loop iteration by implicitely setting active/inactive lanes, i.e. the tail loop is predicated. In order to set up a tail-predicated vector loop, we need to know the number of data elements processed by the vector loop, which corresponds the the tripcount of the scalar loop. We would like to propagate the scalar trip count to the backend, so that this can be picked up by the MVE tail-predication pass.

May 18 2020, 2:06 PM · Restricted Project

May 7 2020

rogfer01 added inline comments to D79543: [RISCV] Enable 'undisturbed' semantics in instruction definitions..
May 7 2020, 1:07 AM · Restricted Project

Apr 17 2020

rogfer01 committed rG5f236864124d: [RISCV][AsmParser] Implement .option (no)pic (authored by rogfer01).
[RISCV][AsmParser] Implement .option (no)pic
Apr 17 2020, 5:22 AM
rogfer01 closed D77867: [RISCV][AsmParser] Implement .option (no)pic.
Apr 17 2020, 5:22 AM · Restricted Project
rogfer01 added a comment to D77867: [RISCV][AsmParser] Implement .option (no)pic.

Thanks for the review @lenary!

Apr 17 2020, 5:22 AM · Restricted Project

Apr 13 2020

rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Remove new hasOneUse and assert opcode of operand.
Apr 13 2020, 3:44 AM · Restricted Project
rogfer01 updated the diff for D65801: [NFC] Add tests for boolean comparisons.

ChangeLog:

  • Refresh
Apr 13 2020, 3:44 AM · Restricted Project
rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Apr 13 2020, 3:44 AM · Restricted Project

Apr 10 2020

rogfer01 created D77867: [RISCV][AsmParser] Implement .option (no)pic.
Apr 10 2020, 6:25 AM · Restricted Project

Mar 20 2020

rogfer01 committed rGebb04e9ca936: [NFC][RISCV] Test for 0.0 fp immediate (authored by rogfer01).
[NFC][RISCV] Test for 0.0 fp immediate
Mar 20 2020, 3:13 AM
rogfer01 committed rG3c24aee7ee8b: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w (authored by rogfer01).
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
Mar 20 2020, 3:13 AM
rogfer01 closed D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.
Mar 20 2020, 3:13 AM · Restricted Project
rogfer01 closed D75728: [NFC][RISCV] Test for 0.0 fp immediate.
Mar 20 2020, 3:13 AM · Restricted Project
rogfer01 updated the diff for D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.

ChangeLog:

  • Remove whitespace prior committing
Mar 20 2020, 2:40 AM · Restricted Project
rogfer01 added a comment to D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.

Thanks a lot for the review @luismarques !

Mar 20 2020, 1:35 AM · Restricted Project

Mar 11 2020

rogfer01 updated the diff for D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.

ChangeLog:

  • Use fmv.{w,d}.x / fcvt.d.w instead
Mar 11 2020, 2:41 PM · Restricted Project

Mar 9 2020

rogfer01 added a comment to D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.

A quick check with the GCC 10 in Fedora Rawhide shows the following results for this small testcase

Mar 9 2020, 10:13 AM · Restricted Project

Mar 6 2020

rogfer01 created D75729: [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w.
Mar 6 2020, 2:46 AM · Restricted Project
rogfer01 created D75728: [NFC][RISCV] Test for 0.0 fp immediate.
Mar 6 2020, 2:46 AM · Restricted Project

Feb 19 2020

rogfer01 added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Feb 19 2020, 12:49 AM · Restricted Project, Restricted Project

Feb 18 2020

rogfer01 added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Feb 18 2020, 1:03 PM · Restricted Project, Restricted Project

Feb 14 2020

rogfer01 committed rG2bef1c0e5645: [OpenMP] Lower taskyield using OpenMP IR Builder (authored by rogfer01).
[OpenMP] Lower taskyield using OpenMP IR Builder
Feb 14 2020, 3:46 AM
rogfer01 closed D70799: [OpenMP] Lower taskyield using OpenMP IR Builder.
Feb 14 2020, 3:46 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D70799: [OpenMP] Lower taskyield using OpenMP IR Builder.

ChangeLog:

  • Rebase
Feb 14 2020, 3:46 AM · Restricted Project, Restricted Project
rogfer01 committed rGa82f35e17621: [OpenMP] Lower taskwait using OpenMP IR Builder (authored by rogfer01).
[OpenMP] Lower taskwait using OpenMP IR Builder
Feb 14 2020, 1:56 AM
rogfer01 closed D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.
Feb 14 2020, 1:56 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Rebase
Feb 14 2020, 12:50 AM · Restricted Project, Restricted Project

Feb 10 2020

rogfer01 added inline comments to D74372: [OpenMP][IRBuilder] Perform finalization (incl. outlining) late.
Feb 10 2020, 11:36 PM · Restricted Project, Restricted Project
rogfer01 abandoned D70092: [PoC][RISC-V][Vext] Unify masked and unmasked instructions.
Feb 10 2020, 5:12 AM · Restricted Project

Feb 6 2020

rogfer01 added a comment to D57504: RFC: Prototype & Roadmap for vector predication in LLVM.

2.) Optimization passes and (vectorizing) frontends
Vectorizers/frontends should query TTI to decide whether they should be using %evl.
For VL targets, the loop vectorizer could use %evl to implement tail loop predication (as in the DAXPY example https://www.sigarch.org/simd-instructions-considered-harmful/ , linked by @lkcl).
For non-VL targets, you should make the iteration mask the root mask of all other predicates in the loop and set %evl to -1.

Feb 6 2020, 1:39 PM · Restricted Project

Feb 4 2020

rogfer01 added inline comments to D73891: [RISCV] Support experimental/unratified extensions.
Feb 4 2020, 12:59 AM · Restricted Project

Jan 14 2020

rogfer01 added a comment to D71989: [OpenMP][IRBuilder][WIP] Prototype `omp task` support.

and we then call the copy constructors like this:

void *local_addr = ...;
for (kmp_uint32 u = 0; u < sizeof_copy_infos; ++u)
  local_addr = copy_wrapper_list[u](copied_obj_list[u], local_addr);
Jan 14 2020, 11:32 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Rebase
Jan 14 2020, 12:17 AM · Restricted Project, Restricted Project

Jan 13 2020

rogfer01 added inline comments to D71989: [OpenMP][IRBuilder][WIP] Prototype `omp task` support.
Jan 13 2020, 11:48 PM · Restricted Project, Restricted Project

Dec 12 2019

rogfer01 accepted D68863: [LNT] Python 3 support: don't assume order of cmake args.

Thanks again @thopre !

Dec 12 2019, 5:40 AM
rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Rebase
Dec 12 2019, 1:21 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D70799: [OpenMP] Lower taskyield using OpenMP IR Builder.

ChangeLog:

  • Rebase
Dec 12 2019, 12:53 AM · Restricted Project, Restricted Project
rogfer01 added inline comments to D68863: [LNT] Python 3 support: don't assume order of cmake args.
Dec 12 2019, 12:07 AM

Dec 11 2019

rogfer01 added a comment to D68863: [LNT] Python 3 support: don't assume order of cmake args.

Thanks for the patch @thopre ! I've got a comment above.

Dec 11 2019, 9:01 AM

Nov 28 2019

rogfer01 added inline comments to D69785: [OpenMP] Introduce the OpenMP-IR-Builder.
Nov 28 2019, 11:59 AM · Restricted Project, Restricted Project

Nov 27 2019

rogfer01 created D70799: [OpenMP] Lower taskyield using OpenMP IR Builder.
Nov 27 2019, 11:35 PM · Restricted Project, Restricted Project
rogfer01 added inline comments to D69785: [OpenMP] Introduce the OpenMP-IR-Builder.
Nov 27 2019, 11:11 PM · Restricted Project, Restricted Project
rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Remove unnecessary return of the insertion point and update code accordingly.
Nov 27 2019, 3:34 AM · Restricted Project, Restricted Project
rogfer01 retitled D69828: [OpenMP] Lower taskwait using OpenMP IR Builder from [WIP][OpenMP] Lower taskwait using OpenMP IR Builder to [OpenMP] Lower taskwait using OpenMP IR Builder.
Nov 27 2019, 3:17 AM · Restricted Project, Restricted Project
rogfer01 added inline comments to D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.
Nov 27 2019, 2:31 AM · Restricted Project, Restricted Project
rogfer01 updated the summary of D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.
Nov 27 2019, 2:31 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

Also for taskwait inside untied tasks we should be reusing the available global_tid instead of calling __kmpc_global_thread_num again.

FWIW, We will just clean up in a later pass (under review). We have to do that anyway, adding some smarts here is barely worth it and I also removed similar logic from my patches.

Nov 27 2019, 2:31 AM · Restricted Project, Restricted Project

Nov 26 2019

rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Enable the new code generation in codegen tests using taskwait
Nov 26 2019, 11:35 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D69828: [OpenMP] Lower taskwait using OpenMP IR Builder.

ChangeLog:

  • Update patch against changes in D69785
Nov 26 2019, 11:08 AM · Restricted Project, Restricted Project

Nov 20 2019

rogfer01 removed a reviewer for D70258: [OpenMP][IR-Builder] Introduce the finalization stack: rogfer01.
Nov 20 2019, 8:07 AM · Restricted Project, Restricted Project
rogfer01 removed a reviewer for D70109: [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation: rogfer01.
Nov 20 2019, 7:57 AM · Restricted Project
rogfer01 removed a reviewer for D70109: [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation: rogfer01.
Nov 20 2019, 7:57 AM · Restricted Project
rogfer01 added a comment to D70109: [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation.

Apologies I screwed my Herald rule!

Nov 20 2019, 7:57 AM · Restricted Project
rogfer01 removed a reviewer for D70109: [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation: rogfer01.
Nov 20 2019, 7:57 AM · Restricted Project
Herald added a reviewer for D70109: [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation: rogfer01.
Nov 20 2019, 7:57 AM · Restricted Project
Herald added a reviewer for D70258: [OpenMP][IR-Builder] Introduce the finalization stack: rogfer01.
Nov 20 2019, 7:57 AM · Restricted Project, Restricted Project

Nov 18 2019

rogfer01 added a comment to rG2b8115b10b03: [OpenMP] Add implementation and tests of Archer tool.

I'm building clang + openmp like this

Nov 18 2019, 11:58 PM

Nov 15 2019

rogfer01 added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

Isn't that already done by virtue of the uses of llvm-objdump -d - in the existing tests?

Nov 15 2019, 12:28 PM · Restricted Project, Restricted Project