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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (135 w, 1 d)

Recent Activity

Mon, Dec 10

rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

The build issue was fixed in rL348783

Mon, Dec 10, 11:09 PM
rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

Hi all,

Mon, Dec 10, 10:00 AM

Fri, Dec 7

rogfer01 abandoned D48643: Define LLVM_IS_TRIVIALLY_COPYABLE.

Not needed for now.

Fri, Dec 7, 3:18 AM
rogfer01 abandoned D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.

Upstream recently amended the ABI spec so it looks to me this is not going to be needed.

Fri, Dec 7, 3:17 AM
rogfer01 committed rL348576: [utils] Use operator "in" instead of bound function "has_key".
[utils] Use operator "in" instead of bound function "has_key"
Fri, Dec 7, 1:52 AM
rogfer01 closed D55310: [utils] Use operator "in" instead of bound function "has_key".
Fri, Dec 7, 1:52 AM
rogfer01 added a comment to D55310: [utils] Use operator "in" instead of bound function "has_key".

Thanks for the review @gbedwell @MaskRay

Fri, Dec 7, 1:00 AM

Thu, Dec 6

rogfer01 added inline comments to D55341: [RISCV, WIP] Support assembling TLS add and associated modifiers.
Thu, Dec 6, 5:13 AM
rogfer01 added a comment to D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium.

My only problem with that approach is that it seems wrong to expand PseudoLLA the same way I am expanding PseudoAddrPCRel, IE allowing the AUIPC operand to be decided by codegen.

Thu, Dec 6, 3:45 AM

Wed, Dec 5

rogfer01 added a comment to D55335: [RISCV, WIP] Support assembling @plt symbol operands.

Ah of course. I hadn't thought of that case. I guess we don't expect symbols to end in @plt as part of their name, do we?

Wed, Dec 5, 2:19 PM
rogfer01 added a comment to D55335: [RISCV, WIP] Support assembling @plt symbol operands.

Would it make sense to add an operand that allows a bare symbol or bare symbol + @plt and use it only in CALL and TAIL instead of allowing identifier@plt everywhere?

Wed, Dec 5, 12:24 PM
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Wed, Dec 5, 11:29 AM
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Wed, Dec 5, 7:50 AM
rogfer01 updated subscribers of D55310: [utils] Use operator "in" instead of bound function "has_key".
Wed, Dec 5, 12:08 AM

Tue, Dec 4

rogfer01 created D55310: [utils] Use operator "in" instead of bound function "has_key".
Tue, Dec 4, 10:45 PM
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Yeah, upstream suggested axing the list of assembly operators from the psABI doc as it's unnecessary duplication that gets out of date. Volunteers?...

Tue, Dec 4, 11:42 AM
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Ah, thanks @asb definitely I was looking at the wrong place!

Tue, Dec 4, 11:13 AM
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

This patch is a very reasonable one: it is a bit weird we can't expand la (under -fPIC) because R_RISCV_GOT_HI20 relocation does not have any associated syntax.

Tue, Dec 4, 10:49 AM
rogfer01 added a comment to D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.

Hi, thanks for the patch. I don't think this usage is wrong so we don't have to change it.

Tue, Dec 4, 12:02 AM

Mon, Dec 3

rogfer01 added a comment to rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

Thanks both for the prompt answer!

Mon, Dec 3, 2:51 AM
rogfer01 updated subscribers of rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

the test MC/Disassembler/RISCV/invalid-instruction.txt contains this case

Mon, Dec 3, 1:48 AM

Wed, Nov 21

rogfer01 added a comment to D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium.

In my downstream I have a single RISCVISD::WRAPPER_PIC and then I use a target flag to remember whether later we want just PCREL (lla) or GOT based on what shouldAssumeDSOLocal returns.

Wed, Nov 21, 9:50 AM

Tue, Nov 13

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Tue, Nov 13, 1:11 PM

Nov 7 2018

rogfer01 planned changes to D50634: [RISCV] Add support for local PIC addressing.

On hold for now.

Nov 7 2018, 12:36 PM
rogfer01 accepted D54159: [RISCV] Mark FREM as Expand.

Thanks Luis. I merged your earlier change D54034 into my downstream compiler just to find that frem was missing (triggered by a downstream test).

Nov 7 2018, 10:36 AM

Nov 6 2018

rogfer01 added inline comments to D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 9:47 AM
rogfer01 updated subscribers of D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 6:11 AM

Oct 31 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Here is an example of two dvl invocations, which compute the same result:

a) llvm_dvl_fadd.v256f64(%x, %y, <full mask>, 13)
Since 13 < 32, the hardware will only issue 1 operation to its SIMD execution units. The occupation is thus something like 13/32 ~ 40%.

b`) llvm_dvl_fadd.v256f64(%x, %y, <mask with first 13 bits set>, 256)
Since the DVL is 256, the hardware will issue 8 operations to its SIMD units. However, only the first 13 elements are relevant leading to an occupation of 13/256 ~ 5%.

Oct 31 2018, 3:18 AM
rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I agree with @fpetrogalli here that there is some overlap between a "dynamic vector length" i32 %dvl and a mask of the form %m = <i1 0, ..., i1 0, i1 1, ..., i1 1> (or the reverse, if the lanes are to be interpreted in the other direction) where %dvl = llvm.ctpop(%m). As Francesco, puts it, we can always construct %m from %dvl. Perhaps I'm wrong, but I think in the context of strip-mined loops or whole function vectorisation, more elaborated masks that might arise due to control flow would always be subsumed by %m (i.e. will have a strict subset of the lanes enabled by %dvl).

Oct 31 2018, 1:40 AM

Oct 30 2018

rogfer01 accepted D53848: [ARM] Add missing pseudo-instruction for Thumb1 RSBS..

Hi @efriedma thanks a lot for this improvement.

Oct 30 2018, 12:19 AM

Oct 25 2018

rogfer01 added inline comments to D53235: [RISCV] Add RV64F codegen support.
Oct 25 2018, 8:22 AM

Oct 24 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Yes, the changes in this RFC are compatible with a physical simdlen that is unknown at compile time.

Oct 24 2018, 3:47 AM

Oct 23 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Hi Simon,

Oct 23 2018, 10:49 PM

Oct 22 2018

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Oct 22 2018, 9:41 AM

Oct 15 2018

rogfer01 added inline comments to D53291: add riscv32e to the llvm.
Oct 15 2018, 8:34 AM

Oct 4 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

Sorry I missed the RFC. After having read it I agree with you. Sorry for the noise.

Oct 4 2018, 3:43 AM

Oct 3 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

rv64i has a few specific *w instructions that we probably want to test them too. For instance,

Oct 3 2018, 9:21 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 7:27 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 6:35 AM

Sep 12 2018

rogfer01 committed rL342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 committed rC342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 closed D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 8:56 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

The updated testcase does not fail locally anymore.

Sep 12 2018, 8:35 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks I will do it shortly.

Sep 12 2018, 8:29 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

I can commit it.

Sep 12 2018, 8:23 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks for the review!

Sep 12 2018, 7:53 AM
rogfer01 created D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 3:28 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

on a second thought, "InstalledDir" only appears with -v, and is still too fragile (e.g if installed dir name also contains checked strings)

Sep 12 2018, 2:37 AM

Sep 10 2018

rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Sure, I didn't mean to do that broader change here. Apologies if it read that way.

Sep 10 2018, 10:47 AM
rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Thanks for reopening this @kristina.

Sep 10 2018, 9:45 AM
rogfer01 added inline comments to rL341547: Fix the -print-multi-directory flag to print the selected multilib..
Sep 10 2018, 7:28 AM
rogfer01 added inline comments to rL341655: Differential Revision: https://reviews.llvm.org/D50246.
Sep 10 2018, 6:35 AM

Sep 6 2018

rogfer01 accepted D51733: [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand type.

Oh this is great! Scales much better than my earlier hack. Thanks a lot @asb !

Sep 6 2018, 10:46 PM

Sep 3 2018

rogfer01 added a comment to D50634: [RISCV] Add support for local PIC addressing.

If I'm understanding correctly, the problem here is that the lui has to have the address of the auipc as a parameter.

Sep 3 2018, 3:55 AM

Aug 29 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 29 2018, 9:06 AM

Aug 27 2018

rogfer01 committed rL340722: [RISCV] atomic_store_nn have a different layout to regular store.
[RISCV] atomic_store_nn have a different layout to regular store
Aug 27 2018, 12:09 AM
rogfer01 closed D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 27 2018, 12:09 AM

Aug 26 2018

rogfer01 updated the diff for D51217: [RISCV] atomic_store_nn have a different layout to regular store.

ChangeLog:

  • Align syntax
Aug 26 2018, 11:22 PM
rogfer01 added a comment to D51217: [RISCV] atomic_store_nn have a different layout to regular store.

Thanks for the prompt review @asb!

Aug 26 2018, 11:18 PM

Aug 24 2018

rogfer01 added inline comments to D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 24 2018, 7:39 AM
rogfer01 created D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 24 2018, 7:24 AM

Aug 17 2018

rogfer01 committed rL340024: [RISCV] Remove unused function.
[RISCV] Remove unused function
Aug 17 2018, 6:41 AM
rogfer01 closed D50836: [RISCV] Remove unused function.
Aug 17 2018, 6:41 AM

Aug 16 2018

rogfer01 added a comment to D50836: [RISCV] Remove unused function.

Thanks for the review @asb

Aug 16 2018, 6:48 AM
rogfer01 added a parent revision for D50634: [RISCV] Add support for local PIC addressing: D50836: [RISCV] Remove unused function.
Aug 16 2018, 2:33 AM
rogfer01 added a child revision for D50836: [RISCV] Remove unused function: D50634: [RISCV] Add support for local PIC addressing.
Aug 16 2018, 2:33 AM
rogfer01 created D50836: [RISCV] Remove unused function.
Aug 16 2018, 2:33 AM
rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 16 2018, 1:36 AM

Aug 14 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 14 2018, 5:59 AM
rogfer01 updated the diff for D50634: [RISCV] Add support for local PIC addressing.

ChangeLog

  • Add test for ConstantPools
Aug 14 2018, 5:52 AM
rogfer01 added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Thanks for the update @kito-cheng . Some more comments inline as the change is propagating a mistake of mine I introduced in rL339314 (fixed in rL339654).

Aug 14 2018, 1:43 AM
rogfer01 committed rL339654: [RISCV] Fix incorrect use of MCInstBuilder.
[RISCV] Fix incorrect use of MCInstBuilder
Aug 14 2018, 1:31 AM

Aug 13 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:49 AM
rogfer01 retitled D50634: [RISCV] Add support for local PIC addressing from [RISCV] Add support for local PIC accessing to [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:46 AM
rogfer01 created D50634: [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:46 AM

Aug 9 2018

rogfer01 added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Hi, thanks a lot for the patch. A few comments inline.

Aug 9 2018, 3:57 AM
rogfer01 committed rL339314: [RISCV] Add "lla" pseudo-instruction to assembler.
[RISCV] Add "lla" pseudo-instruction to assembler
Aug 9 2018, 12:08 AM
rogfer01 closed D49661: [RISCV] Add "lla" pseudo-instruction to assembler.
Aug 9 2018, 12:08 AM

Aug 8 2018

rogfer01 added a comment to D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks for the review @asb . I will commit soon.

Aug 8 2018, 8:29 AM

Aug 3 2018

rogfer01 added inline comments to rC338837: clang-format: [JS] don't break comments before any '{'.
Aug 3 2018, 5:48 AM
rogfer01 added inline comments to rC338837: clang-format: [JS] don't break comments before any '{'.
Aug 3 2018, 5:47 AM
rogfer01 updated the diff for D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks @asb for the review!

Aug 3 2018, 12:55 AM

Jul 30 2018

rogfer01 abandoned D49905: [RISCV] Fix test after new support of "interrupt" attribute landed.

Fixed in rL338341

Jul 30 2018, 11:06 PM

Jul 27 2018

rogfer01 created D49905: [RISCV] Fix test after new support of "interrupt" attribute landed.
Jul 27 2018, 12:03 AM

Jul 26 2018

rogfer01 updated the diff for D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks a lot for the review @asb !

Jul 26 2018, 11:52 PM

Jul 23 2018

rogfer01 created D49661: [RISCV] Add "lla" pseudo-instruction to assembler.
Jul 23 2018, 3:46 AM

Jul 2 2018

rogfer01 accepted D48846: [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m..

Ah, I didn't notice it was exactly the same. You're right no need to add it again.

Jul 2 2018, 12:50 PM
rogfer01 added a comment to D48846: [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m..

Thanks a lot for the patch @pftbest!

Jul 2 2018, 12:45 PM
rogfer01 added a comment to D40922: [ARM] Optimize {s|u}mul.with.overflow..

Thanks @alexcrichton . I cannot login to bugzilla yet (I'd reply there instead, hope I can soon). Looks like {S,U}MUL_LOHI are expanded in Thumb1 so a stop-gap approach could be not implementing this optimisation in that subtarget.

Jul 2 2018, 2:39 AM

Jun 27 2018

rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

Ping?

Jun 27 2018, 9:00 PM
rogfer01 added a comment to D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.

@rjmccall because we do not want to impact the clients of ABIArgInfo I thought of two possible approaches

Jun 27 2018, 6:42 AM
rogfer01 updated the diff for D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.

ChangeLog:

  • Use a ConstantDataArray instead of a struct of types.
  • Use LLVM_IS_TRIVIALLY_COPYABLE
Jun 27 2018, 6:19 AM
rogfer01 added a parent revision for D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand: D48643: Define LLVM_IS_TRIVIALLY_COPYABLE.
Jun 27 2018, 6:12 AM
rogfer01 added a child revision for D48643: Define LLVM_IS_TRIVIALLY_COPYABLE: D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.
Jun 27 2018, 6:12 AM
rogfer01 created D48643: Define LLVM_IS_TRIVIALLY_COPYABLE.
Jun 27 2018, 6:12 AM

Jun 26 2018

rogfer01 added inline comments to D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.
Jun 26 2018, 2:03 PM
rogfer01 added inline comments to D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.
Jun 26 2018, 2:38 AM
rogfer01 created D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.
Jun 26 2018, 2:37 AM

Jun 22 2018

rogfer01 added a comment to D47927: [RISCV] Custom lower ISD::{U,S}{ADD,SUB}O nodes.

Thanks for the review @efriedma

Jun 22 2018, 12:42 AM

Jun 20 2018

rogfer01 added inline comments to D48357: [RISCV] Remove duplicated logic when determining the target ABI.
Jun 20 2018, 3:56 AM