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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (359 w, 2 d)

Recent Activity

Mon, Mar 27

rogfer01 added inline comments to rG5ab9ae12b703: [RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware.
Mon, Mar 27, 3:10 AM · Restricted Project, Restricted Project

Feb 13 2023

rogfer01 added a comment to D142247: Fix initialization of th_task_state on each thread on expanding hot teams..

@rogfer01 th_task_state is used to refer to one of two task teams that are reused for each hot team. These two task teams exist because of a need to start using a new one while there may still be activity on the old task team, so we flip between the two. Each thread has a th_task_state so it knows which task team is in use for a particular parallel region. When a hot team is expanded in size for a larger parallel region, new threads added to the team need to have their th_task_state initialized to exactly what the other threads in the team are using, so that they are all in sync. So instead, we just initialize from a thread that was in the team before the resize.

Feb 13 2023, 8:09 AM · Restricted Project, Restricted Project
rogfer01 committed rGa9329a96ada3: Adjust #pragma warning so GCC is not unhappy (authored by rogfer01).
Adjust #pragma warning so GCC is not unhappy
Feb 13 2023, 2:10 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D143885: Adjust #pragma warning so GCC is not unhappy.

Thanks for double checking, I'll land it soon.

Feb 13 2023, 2:10 AM · Restricted Project, Restricted Project
rogfer01 closed D143885: Adjust #pragma warning so GCC is not unhappy.
Feb 13 2023, 2:10 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D143885: Adjust #pragma warning so GCC is not unhappy.

flang still uses this header.

Feb 13 2023, 1:50 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D143885: Adjust #pragma warning so GCC is not unhappy.

Which configurations are still using this? Just Polly (via isl), or others too?

Feb 13 2023, 1:42 AM · Restricted Project, Restricted Project
rogfer01 requested review of D143885: Adjust #pragma warning so GCC is not unhappy.
Feb 13 2023, 1:09 AM · Restricted Project, Restricted Project

Feb 9 2023

rogfer01 added a comment to D142247: Fix initialization of th_task_state on each thread on expanding hot teams..

Hi @tlwilmar could you elaborate a bit on this part as it is very unobvious at first

Feb 9 2023, 1:03 AM · Restricted Project, Restricted Project

Feb 2 2023

rogfer01 accepted D143220: [RISCV] Remove side effects from vsetvli intrinsics..

I believe that "unfettered" reads (and other uncontrolled changes) to the vl / vtype should not prevent us from creating an efficient intrinsics-based programming model for RVV and this change aligns with this view.

Feb 2 2023, 10:51 PM · Restricted Project, Restricted Project

Dec 22 2022

rogfer01 added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

I'm seeing failures on the llvm testsuite after this change (scalar only).

Failed Tests (3):
  test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/CLAMR/CLAMR.test
  test-suite :: MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4.test
  test-suite :: SingleSource/UnitTests/matrix-types-spec.test

Does anyone else see them too? Thanks!

Are those the exact same tests you reported last time?

Dec 22 2022, 11:30 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

I'm seeing failures on the llvm testsuite after this change (scalar only).

Dec 22 2022, 7:58 AM · Restricted Project, Restricted Project

Oct 25 2022

rogfer01 added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.

I'm seeing failures in the llvm-testsuite on riscv64-unknown-linux-gnu with -O2 (no vectors) which git bisect attributes to this change.

Oct 25 2022, 10:23 AM · Restricted Project, Restricted Project

Oct 11 2022

rogfer01 added a comment to D129735: [RISCV] Add new pass to transform undef to pseudo for vector values..

At risk of introducing noise: would it make sense to use some pseudo instruction (e.g. RISCV::PseudoVUNDEF_Mx) instead of the zero initializations and then drop it later (say when emitting MCInst)?

Oct 11 2022, 12:14 AM · Restricted Project, Restricted Project

Oct 10 2022

rogfer01 added inline comments to D134285: [flang][RFC] Adding higher level FIR ops to ease expression lowering.
Oct 10 2022, 7:42 AM · Restricted Project, Restricted Project

Oct 6 2022

rogfer01 added a comment to D134285: [flang][RFC] Adding higher level FIR ops to ease expression lowering.

The whole proposal seems very reasonable to me and definitely an improvement to the current status quo. Thanks a lot for putting this together @jeanPerier.

Oct 6 2022, 12:04 AM · Restricted Project, Restricted Project

Aug 31 2022

rogfer01 accepted D133048: [VP] Correct LEGALPOS for more VP nodes..

Good catch. LGTM.

Aug 31 2022, 11:04 PM · Restricted Project, Restricted Project

Jul 27 2022

rogfer01 added inline comments to D129959: [flang] Support intrinsic `selected_int_kind` for variables.
Jul 27 2022, 12:23 AM · Restricted Project, Restricted Project

Jul 26 2022

rogfer01 added inline comments to D129959: [flang] Support intrinsic `selected_int_kind` for variables.
Jul 26 2022, 8:02 AM · Restricted Project, Restricted Project

Jul 13 2022

rogfer01 accepted D129646: [RISCV] Disable subregister liveness by default.

I'm too in favour of disabling subregister liveness until we can model the problematic instructions constraints in a more robust way.

Jul 13 2022, 12:50 PM · Restricted Project, Restricted Project
rogfer01 accepted D129639: [RISCV] Add a test showing a miscompilation with subreg liveness.
Jul 13 2022, 12:47 PM · Restricted Project, Restricted Project

Jun 28 2022

rogfer01 added inline comments to D128431: [flang] Increase support for intrinsic module procedures.
Jun 28 2022, 9:21 AM · Restricted Project, Restricted Project

Jun 8 2022

rogfer01 accepted D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC).

This is a huge number of test changes so I have checked a subset of files but the changes seems reasonable, as I imagine they're generated mechanically.

Jun 8 2022, 11:46 PM · Restricted Project, Restricted Project
rogfer01 accepted D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC).

LGTM. Thanks @khchen !

Jun 8 2022, 11:29 PM · Restricted Project, Restricted Project
rogfer01 accepted D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC).

(I was a bit confused by the refactoring of computeBuiltinTypes but it is definitely better this way)

Jun 8 2022, 11:24 PM · Restricted Project, Restricted Project
rogfer01 accepted D126860: [RISCV] Pre-commit testcase for PR55442.

LGTM

Jun 8 2022, 11:14 PM · Restricted Project, Restricted Project
rogfer01 accepted D126861: [RISCV] Fix missing stack pointer recover.

LGTM. Thanks @kito-cheng

Jun 8 2022, 11:13 PM · Restricted Project, Restricted Project
rogfer01 added inline comments to D126861: [RISCV] Fix missing stack pointer recover.
Jun 8 2022, 11:13 PM · Restricted Project, Restricted Project
rogfer01 added inline comments to D126861: [RISCV] Fix missing stack pointer recover.
Jun 8 2022, 11:09 PM · Restricted Project, Restricted Project

May 25 2022

rogfer01 added a comment to D126372: [RISCV]Add basic cost model for vector reduce for scalable vector.

Can we test some illegal type here (e.g. vscale x 16 x i64). The patch includes logic for that so it may be worth having it.

May 25 2022, 11:04 PM · Restricted Project, Restricted Project

May 19 2022

rogfer01 added inline comments to D125546: [RISCV] Use tail agnostic if inserting subvector/element at the end of the vector..
May 19 2022, 12:17 AM · Restricted Project, Restricted Project

May 13 2022

rogfer01 closed D125560: [RISCV] Use the new chain when converting a fixed RVV load.

I added the link but I forgot the Differential Revision: marker. This was fixed in 189ca6958e84

May 13 2022, 3:23 PM · Restricted Project, Restricted Project
rogfer01 committed rG189ca6958e84: [RISCV] Use the new chain when converting a fixed RVV load (authored by rogfer01).
[RISCV] Use the new chain when converting a fixed RVV load
May 13 2022, 3:22 PM · Restricted Project, Restricted Project
rogfer01 committed rGfc9bed025e33: [RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV (authored by rogfer01).
[RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV
May 13 2022, 3:22 PM · Restricted Project, Restricted Project
rogfer01 closed D125553: [RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV.
May 13 2022, 3:22 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D125560: [RISCV] Use the new chain when converting a fixed RVV load.

Accidents happen.. Thanks for the prompt review @craig.topper.

May 13 2022, 3:21 PM · Restricted Project, Restricted Project
rogfer01 added reviewers for D125560: [RISCV] Use the new chain when converting a fixed RVV load: craig.topper, reames, frasercrmck.
May 13 2022, 9:16 AM · Restricted Project, Restricted Project
rogfer01 requested review of D125560: [RISCV] Use the new chain when converting a fixed RVV load.
May 13 2022, 9:15 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D125553: [RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV.

I'll post a fix shortly.

May 13 2022, 8:57 AM · Restricted Project, Restricted Project
rogfer01 requested review of D125553: [RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV.
May 13 2022, 8:55 AM · Restricted Project, Restricted Project

Apr 28 2022

rogfer01 added a comment to D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.

Just to understand the design principle behind these patches: adding FRM as Use to the v*cvt instructions (like we did in D121087 ) would not help us to implement floor and ceil. I imagine one option could be adding specific pseudos for round up and round down and then a later pass could set the rounding mode and restore it later. However, this would not give great code generation and it adds even more instructions to our already large number of pseudos. So your approach goes by adding a new operand with the rounding mode, similar to the scalar operations, and in D123371 you propose a pass that adjusts the FRM register.

Apr 28 2022, 12:08 AM · Restricted Project, Restricted Project

Apr 27 2022

rogfer01 added inline comments to D124101: [RISCV] Add cost model for SK_Broadcast.
Apr 27 2022, 11:06 PM · Restricted Project, Restricted Project

Apr 25 2022

rogfer01 accepted D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup..

LGTM. Thanks @khchen !

Apr 25 2022, 3:23 AM · Restricted Project, Restricted Project, Restricted Project
rogfer01 added inline comments to D124161: [RISCV][AsmParser] Fix parsing of the components of the vtype immediate of vsetvli.
Apr 25 2022, 2:15 AM · Restricted Project, Restricted Project

Apr 21 2022

rogfer01 requested review of D124161: [RISCV][AsmParser] Fix parsing of the components of the vtype immediate of vsetvli.
Apr 21 2022, 5:32 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D124089: [RISCV] Add a test showing incorrect VSETVLI insertion.

One interesting thing is that computeIncomingVLVTYPE doesn't seem to be fully aligned with what emitVSETVLIs will do. If the latter chooses to skip a vsetvl then the Exit of that basic block might potentially be different to the one that we determined in computeVLVTYPEChanges and computeIncomingVLVTYPE.

Apr 21 2022, 12:20 AM · Restricted Project, Restricted Project

Apr 7 2022

rogfer01 accepted D123324: [VP] Explicitly map from VP intrinsic to ISD opcode.

Other than the nit above, this LGTM.

Apr 7 2022, 11:06 AM · Restricted Project, Restricted Project
rogfer01 accepted D123180: [RISCV] Fixing stack offset for RVV object with vararg in stack..

This looks good to me, based on what we discussed on D123179 with this change the stack looks like this

Apr 7 2022, 4:27 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D123179: [RISCV] Pre-commit for fixing stack offset for RVV object.

@rogfer01, almost right, but a6 and a7 is wrong on your table, that has added vlenb, so you only need to care about the offset, so the layout is something like this:

Currently, v8 will corrupt s0 and s1.

Apr 7 2022, 3:53 AM · Restricted Project, Restricted Project
rogfer01 accepted D123179: [RISCV] Pre-commit for fixing stack offset for RVV object.
Apr 7 2022, 12:59 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D123179: [RISCV] Pre-commit for fixing stack offset for RVV object.

I'm ok with this once D123178 lands.

Apr 7 2022, 12:45 AM · Restricted Project, Restricted Project

Apr 6 2022

rogfer01 accepted D123239: [RISCV] Add swapped patterns to VPatIntegerSetCCVL_VIPlus1..

This is a sensible low hanging fruit we want to have until VP_SETCC is taught more tricks.

Apr 6 2022, 11:11 PM · Restricted Project, Restricted Project
rogfer01 accepted D123255: [RISCV] Add more .vx patterns for VLMax integer setccs..

LGTM. Thanks for the cleanup @craig.topper !

Apr 6 2022, 11:07 PM · Restricted Project, Restricted Project
Herald added a project to D120483: [flang] Handle allocatable dummy arguments: Restricted Project.
Apr 6 2022, 5:42 AM · Restricted Project, Restricted Project, Restricted Project
rogfer01 accepted D123150: [RISCV] Add lowering for vp.sext and vp.zext..

LGTM. Thanks @craig.topper !

Apr 6 2022, 3:37 AM · Restricted Project, Restricted Project

Apr 1 2022

rogfer01 added inline comments to D122743: [RISCV][VP] Add basic RVV codegen for vp.icmp.
Apr 1 2022, 12:14 AM · Restricted Project, Restricted Project

Mar 30 2022

rogfer01 added a comment to D122678: [RISCV] Add support for vp.fptosi where the result is a mask type..

I must be missing something very obvious: wouldn't 2.0 round to 2 and then give us i1 0 because its LSB is 0?

2.0 is out of range for the integer so it is UB and produces poison.

Mar 30 2022, 11:46 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D122678: [RISCV] Add support for vp.fptosi where the result is a mask type..

I must be missing something very obvious: wouldn't 2.0 round to 2 and then give us i1 0 because its LSB is 0?

Mar 30 2022, 8:33 AM · Restricted Project, Restricted Project

Mar 24 2022

rogfer01 accepted D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

I understand we need this for proper modelling of FRM when lowering constrained FP operations

Mar 24 2022, 12:30 AM · Restricted Project, Restricted Project

Mar 23 2022

rogfer01 committed rGd2663fcc391d: [flang][Evaluate] Fold DBLE (authored by rogfer01).
[flang][Evaluate] Fold DBLE
Mar 23 2022, 10:30 AM · Restricted Project, Restricted Project
rogfer01 closed D122214: [flang][Evaluate] Fold DBLE.
Mar 23 2022, 10:29 AM · Restricted Project, Restricted Project

Mar 22 2022

rogfer01 updated the diff for D122214: [flang][Evaluate] Fold DBLE.

ChangeLog:

  • Improve the test with assertions verified by test_folding.py as suggested
Mar 22 2022, 10:53 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D122214: [flang][Evaluate] Fold DBLE.

Yes, SNGL is a specific intrinsic (defined in section 16.8 in Fortran 2018 standard), while DBLE is a generic intrinsic (defined in section 16.9). Intrinsic procedure call resolution (Probe in lib/Evaluate/intrinsics.cpp) replaces specific names by the related generic names. So SGNL is replaced by REAL there, but DBLE is not. So your patch in folding makes sense to me.

Mar 22 2022, 10:52 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D122214: [flang][Evaluate] Fold DBLE.

I was wondering why similar intrinsics SNGL and FLOAT work already but they seem to be lowered earlier to REAL, does this make sense?

Mar 22 2022, 1:33 AM · Restricted Project, Restricted Project
rogfer01 requested review of D122214: [flang][Evaluate] Fold DBLE.
Mar 22 2022, 1:31 AM · Restricted Project, Restricted Project

Mar 17 2022

rogfer01 added a comment to D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

FRM for scalar instructions is modeled. D116694, D116323, D115680, D115555 probably some others.

Mar 17 2022, 1:58 AM · Restricted Project, Restricted Project
rogfer01 accepted D121645: [RISCV] Simplify scalable vector case in lowerVectorMaskExt..

LGTM. Thanks for the cleanup @craig.topper

Mar 17 2022, 1:24 AM · Restricted Project, Restricted Project
rogfer01 added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Mar 17 2022, 1:21 AM · Restricted Project, Restricted Project

Mar 9 2022

rogfer01 accepted D120287: [RISCV] Add isel patterns for masked RISCVISD::FMA_VL with RISCVISD::FNEG_VL..

I fear that adding more custom combined nodes would get unwieldy as they don't scale particularly well: we'd probably want corresponding ones for integer madd/macc, for narrowing operations, etc. They may inhibit theoretical optimizations we can perform on generic VP nodes. But the key word is "theoretical" and so that's just a gut reaction. We do have custom nodes for all of the widening operations, so it's feasible.

Mar 9 2022, 10:43 PM · Restricted Project, Restricted Project
rogfer01 added a comment to D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

Hi @arcbbb I may be missing context here

Mar 9 2022, 10:35 PM · Restricted Project, Restricted Project
rogfer01 accepted D121166: [RISCV] Remove RISCVISD::VLE_VL/VSE_VL. Use intrinsics instead..

Let's do that, otherwise there is doubt when to use one approach or the other.

Mar 9 2022, 10:27 PM · Restricted Project, Restricted Project

Mar 7 2022

rogfer01 added a comment to D121111: [RISCV] Also sink a splat for the first operand of instructions with vector-scalar cases.

Ok, regarding the testing in sink-splat-operands-commute.ll I took the relevant operations in sink-splat-operands.ll and swapped the input so the broadcast operand is the first one. They generate the same input (the only difference is the basic block IDs).

Mar 7 2022, 6:25 AM · Restricted Project, Restricted Project
rogfer01 requested review of D121111: [RISCV] Also sink a splat for the first operand of instructions with vector-scalar cases.
Mar 7 2022, 6:21 AM · Restricted Project, Restricted Project

Mar 2 2022

rogfer01 accepted D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td..

Thanks for the cleanup @khchen !

Mar 2 2022, 11:20 PM · Restricted Project, Restricted Project, Restricted Project

Feb 24 2022

rogfer01 added a comment to D120287: [RISCV] Add isel patterns for masked RISCVISD::FMA_VL with RISCVISD::FNEG_VL..

I understand srcval here is

Feb 24 2022, 12:42 AM · Restricted Project, Restricted Project
rogfer01 accepted D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics..

LGTM. Thanks @khchen !

Feb 24 2022, 12:26 AM · Restricted Project, Restricted Project, Restricted Project
rogfer01 accepted D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics..

LGTM. Thanks @khchen !

Feb 24 2022, 12:23 AM · Restricted Project, Restricted Project, Restricted Project

Feb 16 2022

rogfer01 accepted D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics..

LGTM. Thanks @khchen!

Feb 16 2022, 11:38 PM · Restricted Project, Restricted Project
rogfer01 accepted D119688: [RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics..

LGTM. Thanks @khchen !

Feb 16 2022, 11:33 PM · Restricted Project, Restricted Project
rogfer01 accepted D120008: [RISCV][NFC] Add some tail agnostic tests for nomask operations..

LGTM. Thanks @khchen!

Feb 16 2022, 11:20 PM · Restricted Project

Feb 14 2022

rogfer01 added inline comments to D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication.
Feb 14 2022, 8:06 AM · Restricted Project, Restricted Project

Feb 9 2022

rogfer01 added a comment to D118845: [RISCV] Move the creation of VLMaxSentinel to isel. Use X0 during lowering..

To clarify I understand the motivation of this: lowering won't have to special case every constant in the AVL operand just in case it is VLMaxSentinel, right?

Feb 9 2022, 11:29 PM · Restricted Project

Feb 7 2022

rogfer01 added a comment to D119185: [VP] llvm.vp.fma intrinsic and LangRef.

Post-commit review: LGTM

Feb 7 2022, 11:25 PM · Restricted Project

Feb 2 2022

rogfer01 accepted D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub..

Ok thanks for the clarifications!

Feb 2 2022, 2:35 AM · Restricted Project

Jan 27 2022

rogfer01 added a comment to D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub..

Just to confirm, this is not fixed vector specific, is it?

Jan 27 2022, 12:47 AM · Restricted Project

Jan 26 2022

rogfer01 accepted D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics..

Looks reasonable to me. Thans @khchen!

Jan 26 2022, 11:45 PM · Restricted Project, Restricted Project

Jan 20 2022

rogfer01 accepted D117743: [RISCV] Optimize vector_shuffles that are interleaving the lowest elements of two vectors..

LGTM

Jan 20 2022, 8:50 AM · Restricted Project

Jan 7 2022

rogfer01 added inline comments to D116362: [TTI] Support ScalableVectorType in getShuffleCost with SK_Broadcast kind.
Jan 7 2022, 7:14 AM · Restricted Project

Dec 30 2021

rogfer01 added inline comments to D116307: [RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f..
Dec 30 2021, 3:57 AM · Restricted Project

Dec 22 2021

rogfer01 accepted D115978: [RISCV] Use positive 0.0 for the neutral element in fadd reductions if nsz is present..

Though perhaps we can improve the generation of -0.0 in another patch.

Dec 22 2021, 11:32 PM · Restricted Project

Dec 1 2021

rogfer01 accepted D114629: [RISCV][VP] Add RVV codegen for vp.select.

Thanks for the patch @victor-eds!

Dec 1 2021, 11:36 PM · Restricted Project
rogfer01 added inline comments to D114884: [VP] Strided loads/stores.
Dec 1 2021, 10:43 PM · Restricted Project, Restricted Project, Restricted Project

Nov 18 2021

rogfer01 added inline comments to D113439: [RISCV] Add IR intrinsics for reading/write vxrm..
Nov 18 2021, 12:43 AM · Restricted Project

Nov 11 2021

rogfer01 added a comment to D113543: [RISCV] Add inline expansion for vector ftrunc/fceil/ffloor..

Being myself far from an expert in floating-point, the logic and generated code seem correct to me.

Nov 11 2021, 12:00 AM · Restricted Project

Oct 27 2021

rogfer01 added a comment to D112398: [RISCV] Add ABI testing for Float16..

I'm curious about how we handle _Float16 here.

Oct 27 2021, 11:57 PM · Restricted Project

Oct 22 2021

rogfer01 added a comment to D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude..

Looks good to me too. Thanks a lot @craig.topper !

Oct 22 2021, 12:41 PM · Restricted Project, Restricted Project

Oct 20 2021

rogfer01 added a comment to D111617: [RISCV] Lazily add RVV C intrinsics..

Although it reduces the header size, this patch will increase the binary size of clang.

Oct 20 2021, 11:30 PM · Restricted Project, Restricted Project, Restricted Project

Oct 18 2021

rogfer01 added a comment to D111846: [LV] Drop integer poison-generating flags from instructions that need predication.

Thanks @dcaballe for the patch. A bit surprising that we didn't notice this earlier but I guess masking does not get used that often.

Oct 18 2021, 4:17 AM · Restricted Project

Oct 12 2021

rogfer01 added a comment to D111304: [RISCV] Reorder the vector register allocation order..

No objection with this, I guess it is for consistency with GPRs, right?

Oct 12 2021, 2:23 AM · Restricted Project
rogfer01 added inline comments to D111617: [RISCV] Lazily add RVV C intrinsics..
Oct 12 2021, 2:18 AM · Restricted Project, Restricted Project, Restricted Project