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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (145 w, 4 d)

Recent Activity

Tue, Feb 19

rogfer01 added a comment to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

Looks sensible to me.

Tue, Feb 19, 3:50 AM · Restricted Project

Fri, Feb 1

rogfer01 added a reviewer for D57577: Make predefined FLT16 macros conditional on support for the type: SjoerdMeijer.
Fri, Feb 1, 3:36 AM · Restricted Project, Restricted Project

Mon, Jan 28

rogfer01 added a comment to D57163: [DebugInfo][DAG] PR40427: Avoid accidentally re-ordering DBG_VALUEs due to assumptions about inst creation.

@jmorse pr40427.ll uses x86-specific bits in the CHECK lines and is causing failures in builds that do not target by default x86 (e.g. http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/16847 )

Mon, Jan 28, 11:12 PM

Fri, Jan 25

rogfer01 added a comment to D57240: [RISCV] Don't incorrectly force relocation for %pcrel_lo.

Hi @lewis-revill, thanks for the patch.

Fri, Jan 25, 8:55 AM · Restricted Project

Jan 23 2019

rogfer01 added inline comments to D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64 .
Jan 23 2019, 11:23 AM

Jan 16 2019

rogfer01 added inline comments to D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions.
Jan 16 2019, 6:24 AM

Jan 14 2019

rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Ah, I think what happens is that we should not emit such patterns without the presence of the F extension: these patterns are ultimately selected as instructions in F. Does this make sense?

Jan 14 2019, 6:00 AM
rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Hi Alex,

Jan 14 2019, 5:25 AM

Jan 8 2019

rogfer01 added a comment to rL349764: [RISCV] Properly evaluate fixup_riscv_pcrel_lo12.

Hi Alex,

Jan 8 2019, 7:46 AM

Dec 21 2018

rogfer01 added inline comments to D55279: [RISCV] Support assembling %got_pcrel_hi operator.
Dec 21 2018, 2:54 AM · Restricted Project

Dec 14 2018

rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

Rebased and updated to use and expand PseudoLLA for PC-relative addressing.

Dec 14 2018, 12:47 AM · Restricted Project
rogfer01 added a comment to D55303: [RISCV] Add lowering of addressing sequences for PIC.

Minor comment above but other than that this looks good to me too.

Dec 14 2018, 12:34 AM

Dec 10 2018

rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

The build issue was fixed in rL348783

Dec 10 2018, 11:09 PM
rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

Hi all,

Dec 10 2018, 10:00 AM

Dec 7 2018

rogfer01 abandoned D48643: Define LLVM_IS_TRIVIALLY_COPYABLE.

Not needed for now.

Dec 7 2018, 3:18 AM
rogfer01 abandoned D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.

Upstream recently amended the ABI spec so it looks to me this is not going to be needed.

Dec 7 2018, 3:17 AM
rogfer01 committed rL348576: [utils] Use operator "in" instead of bound function "has_key".
[utils] Use operator "in" instead of bound function "has_key"
Dec 7 2018, 1:52 AM
rogfer01 closed D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 7 2018, 1:52 AM
rogfer01 added a comment to D55310: [utils] Use operator "in" instead of bound function "has_key".

Thanks for the review @gbedwell @MaskRay

Dec 7 2018, 1:00 AM

Dec 6 2018

rogfer01 added inline comments to D55341: [RISCV] Support assembling TLS add and associated modifiers.
Dec 6 2018, 5:13 AM · Restricted Project
rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

My only problem with that approach is that it seems wrong to expand PseudoLLA the same way I am expanding PseudoAddrPCRel, IE allowing the AUIPC operand to be decided by codegen.

Dec 6 2018, 3:45 AM · Restricted Project

Dec 5 2018

rogfer01 added a comment to D55335: [RISCV] Support assembling @plt symbol operands.

Ah of course. I hadn't thought of that case. I guess we don't expect symbols to end in @plt as part of their name, do we?

Dec 5 2018, 2:19 PM · Restricted Project
rogfer01 added a comment to D55335: [RISCV] Support assembling @plt symbol operands.

Would it make sense to add an operand that allows a bare symbol or bare symbol + @plt and use it only in CALL and TAIL instead of allowing identifier@plt everywhere?

Dec 5 2018, 12:24 PM · Restricted Project
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Dec 5 2018, 11:29 AM · Restricted Project
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Dec 5 2018, 7:50 AM · Restricted Project
rogfer01 updated subscribers of D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 5 2018, 12:08 AM

Dec 4 2018

rogfer01 created D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 4 2018, 10:45 PM
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Yeah, upstream suggested axing the list of assembly operators from the psABI doc as it's unnecessary duplication that gets out of date. Volunteers?...

Dec 4 2018, 11:42 AM · Restricted Project
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Ah, thanks @asb definitely I was looking at the wrong place!

Dec 4 2018, 11:13 AM · Restricted Project
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

This patch is a very reasonable one: it is a bit weird we can't expand la (under -fPIC) because R_RISCV_GOT_HI20 relocation does not have any associated syntax.

Dec 4 2018, 10:49 AM · Restricted Project
rogfer01 added a comment to D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.

Hi, thanks for the patch. I don't think this usage is wrong so we don't have to change it.

Dec 4 2018, 12:02 AM

Dec 3 2018

rogfer01 added a comment to rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

Thanks both for the prompt answer!

Dec 3 2018, 2:51 AM
rogfer01 updated subscribers of rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

the test MC/Disassembler/RISCV/invalid-instruction.txt contains this case

Dec 3 2018, 1:48 AM

Nov 21 2018

rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

In my downstream I have a single RISCVISD::WRAPPER_PIC and then I use a target flag to remember whether later we want just PCREL (lla) or GOT based on what shouldAssumeDSOLocal returns.

Nov 21 2018, 9:50 AM · Restricted Project

Nov 13 2018

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Nov 13 2018, 1:11 PM

Nov 7 2018

rogfer01 planned changes to D50634: [RISCV] Add support for local PIC addressing.

On hold for now.

Nov 7 2018, 12:36 PM
rogfer01 accepted D54159: [RISCV] Mark FREM as Expand.

Thanks Luis. I merged your earlier change D54034 into my downstream compiler just to find that frem was missing (triggered by a downstream test).

Nov 7 2018, 10:36 AM

Nov 6 2018

rogfer01 added inline comments to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 9:47 AM · Restricted Project
rogfer01 updated subscribers of D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 6:11 AM · Restricted Project

Oct 31 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Here is an example of two dvl invocations, which compute the same result:

a) llvm_dvl_fadd.v256f64(%x, %y, <full mask>, 13)
Since 13 < 32, the hardware will only issue 1 operation to its SIMD execution units. The occupation is thus something like 13/32 ~ 40%.

b`) llvm_dvl_fadd.v256f64(%x, %y, <mask with first 13 bits set>, 256)
Since the DVL is 256, the hardware will issue 8 operations to its SIMD units. However, only the first 13 elements are relevant leading to an occupation of 13/256 ~ 5%.

Oct 31 2018, 3:18 AM
rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I agree with @fpetrogalli here that there is some overlap between a "dynamic vector length" i32 %dvl and a mask of the form %m = <i1 0, ..., i1 0, i1 1, ..., i1 1> (or the reverse, if the lanes are to be interpreted in the other direction) where %dvl = llvm.ctpop(%m). As Francesco, puts it, we can always construct %m from %dvl. Perhaps I'm wrong, but I think in the context of strip-mined loops or whole function vectorisation, more elaborated masks that might arise due to control flow would always be subsumed by %m (i.e. will have a strict subset of the lanes enabled by %dvl).

Oct 31 2018, 1:40 AM

Oct 30 2018

rogfer01 accepted D53848: [ARM] Add missing pseudo-instruction for Thumb1 RSBS..

Hi @efriedma thanks a lot for this improvement.

Oct 30 2018, 12:19 AM

Oct 25 2018

rogfer01 added inline comments to D53235: [RISCV] Add RV64F codegen support.
Oct 25 2018, 8:22 AM

Oct 24 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Yes, the changes in this RFC are compatible with a physical simdlen that is unknown at compile time.

Oct 24 2018, 3:47 AM

Oct 23 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Hi Simon,

Oct 23 2018, 10:49 PM

Oct 22 2018

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Oct 22 2018, 9:41 AM

Oct 15 2018

rogfer01 added inline comments to D53291: add riscv32e to the llvm.
Oct 15 2018, 8:34 AM

Oct 4 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

Sorry I missed the RFC. After having read it I agree with you. Sorry for the noise.

Oct 4 2018, 3:43 AM

Oct 3 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

rv64i has a few specific *w instructions that we probably want to test them too. For instance,

Oct 3 2018, 9:21 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 7:27 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 6:35 AM

Sep 12 2018

rogfer01 committed rL342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 committed rC342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 closed D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 8:56 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

The updated testcase does not fail locally anymore.

Sep 12 2018, 8:35 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks I will do it shortly.

Sep 12 2018, 8:29 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

I can commit it.

Sep 12 2018, 8:23 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks for the review!

Sep 12 2018, 7:53 AM
rogfer01 created D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 3:28 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

on a second thought, "InstalledDir" only appears with -v, and is still too fragile (e.g if installed dir name also contains checked strings)

Sep 12 2018, 2:37 AM

Sep 10 2018

rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Sure, I didn't mean to do that broader change here. Apologies if it read that way.

Sep 10 2018, 10:47 AM
rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Thanks for reopening this @kristina.

Sep 10 2018, 9:45 AM
rogfer01 added inline comments to rL341547: Fix the -print-multi-directory flag to print the selected multilib..
Sep 10 2018, 7:28 AM
rogfer01 added inline comments to rL341655: Differential Revision: https://reviews.llvm.org/D50246.
Sep 10 2018, 6:35 AM

Sep 6 2018

rogfer01 accepted D51733: [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand type.

Oh this is great! Scales much better than my earlier hack. Thanks a lot @asb !

Sep 6 2018, 10:46 PM

Sep 3 2018

rogfer01 added a comment to D50634: [RISCV] Add support for local PIC addressing.

If I'm understanding correctly, the problem here is that the lui has to have the address of the auipc as a parameter.

Sep 3 2018, 3:55 AM

Aug 29 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 29 2018, 9:06 AM

Aug 27 2018

rogfer01 committed rL340722: [RISCV] atomic_store_nn have a different layout to regular store.
[RISCV] atomic_store_nn have a different layout to regular store
Aug 27 2018, 12:09 AM
rogfer01 closed D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 27 2018, 12:09 AM

Aug 26 2018

rogfer01 updated the diff for D51217: [RISCV] atomic_store_nn have a different layout to regular store.

ChangeLog:

  • Align syntax
Aug 26 2018, 11:22 PM
rogfer01 added a comment to D51217: [RISCV] atomic_store_nn have a different layout to regular store.

Thanks for the prompt review @asb!

Aug 26 2018, 11:18 PM

Aug 24 2018

rogfer01 added inline comments to D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 24 2018, 7:39 AM
rogfer01 created D51217: [RISCV] atomic_store_nn have a different layout to regular store.
Aug 24 2018, 7:24 AM

Aug 17 2018

rogfer01 committed rL340024: [RISCV] Remove unused function.
[RISCV] Remove unused function
Aug 17 2018, 6:41 AM
rogfer01 closed D50836: [RISCV] Remove unused function.
Aug 17 2018, 6:41 AM

Aug 16 2018

rogfer01 added a comment to D50836: [RISCV] Remove unused function.

Thanks for the review @asb

Aug 16 2018, 6:48 AM
rogfer01 added a parent revision for D50634: [RISCV] Add support for local PIC addressing: D50836: [RISCV] Remove unused function.
Aug 16 2018, 2:33 AM
rogfer01 added a child revision for D50836: [RISCV] Remove unused function: D50634: [RISCV] Add support for local PIC addressing.
Aug 16 2018, 2:33 AM
rogfer01 created D50836: [RISCV] Remove unused function.
Aug 16 2018, 2:33 AM
rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 16 2018, 1:36 AM

Aug 14 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 14 2018, 5:59 AM
rogfer01 updated the diff for D50634: [RISCV] Add support for local PIC addressing.

ChangeLog

  • Add test for ConstantPools
Aug 14 2018, 5:52 AM
rogfer01 added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Thanks for the update @kito-cheng . Some more comments inline as the change is propagating a mistake of mine I introduced in rL339314 (fixed in rL339654).

Aug 14 2018, 1:43 AM · Restricted Project
rogfer01 committed rL339654: [RISCV] Fix incorrect use of MCInstBuilder.
[RISCV] Fix incorrect use of MCInstBuilder
Aug 14 2018, 1:31 AM

Aug 13 2018

rogfer01 added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:49 AM
rogfer01 retitled D50634: [RISCV] Add support for local PIC addressing from [RISCV] Add support for local PIC accessing to [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:46 AM
rogfer01 created D50634: [RISCV] Add support for local PIC addressing.
Aug 13 2018, 6:46 AM

Aug 9 2018

rogfer01 added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Hi, thanks a lot for the patch. A few comments inline.

Aug 9 2018, 3:57 AM · Restricted Project
rogfer01 committed rL339314: [RISCV] Add "lla" pseudo-instruction to assembler.
[RISCV] Add "lla" pseudo-instruction to assembler
Aug 9 2018, 12:08 AM
rogfer01 closed D49661: [RISCV] Add "lla" pseudo-instruction to assembler.
Aug 9 2018, 12:08 AM

Aug 8 2018

rogfer01 added a comment to D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks for the review @asb . I will commit soon.

Aug 8 2018, 8:29 AM

Aug 3 2018

rogfer01 added inline comments to rC338837: clang-format: [JS] don't break comments before any '{'.
Aug 3 2018, 5:48 AM
rogfer01 added inline comments to rC338837: clang-format: [JS] don't break comments before any '{'.
Aug 3 2018, 5:47 AM
rogfer01 updated the diff for D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks @asb for the review!

Aug 3 2018, 12:55 AM

Jul 30 2018

rogfer01 abandoned D49905: [RISCV] Fix test after new support of "interrupt" attribute landed.

Fixed in rL338341

Jul 30 2018, 11:06 PM

Jul 27 2018

rogfer01 created D49905: [RISCV] Fix test after new support of "interrupt" attribute landed.
Jul 27 2018, 12:03 AM

Jul 26 2018

rogfer01 updated the diff for D49661: [RISCV] Add "lla" pseudo-instruction to assembler.

Thanks a lot for the review @asb !

Jul 26 2018, 11:52 PM

Jul 23 2018

rogfer01 created D49661: [RISCV] Add "lla" pseudo-instruction to assembler.
Jul 23 2018, 3:46 AM

Jul 2 2018

rogfer01 accepted D48846: [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m..

Ah, I didn't notice it was exactly the same. You're right no need to add it again.

Jul 2 2018, 12:50 PM
rogfer01 added a comment to D48846: [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m..

Thanks a lot for the patch @pftbest!

Jul 2 2018, 12:45 PM