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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (171 w, 14 h)

Recent Activity

Fri, Aug 9

rogfer01 added a comment to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

Thanks for the clarification @asb. I've posted D66003 (depending on D66002) for that.

Fri, Aug 9, 3:39 AM · Restricted Project
rogfer01 added parent revisions for D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux: D66002: [RISCV] Move architecture parsing code into its own function, D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Fri, Aug 9, 3:38 AM · Restricted Project
rogfer01 added a child revision for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux: D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Fri, Aug 9, 3:38 AM · Restricted Project
rogfer01 added a child revision for D66002: [RISCV] Move architecture parsing code into its own function: D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Fri, Aug 9, 3:38 AM · Restricted Project
rogfer01 created D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Fri, Aug 9, 3:38 AM · Restricted Project
rogfer01 created D66002: [RISCV] Move architecture parsing code into its own function.
Fri, Aug 9, 3:36 AM · Restricted Project

Thu, Aug 8

rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

Hmm, while there, just to point out the obvious, the another approach here would be to teach DAGCombine/TargetLowering::SimplifySetCC() about these folds.
That is explicitly one of a few valid reasons to add optimizations into backend 'instead' of middle-end.

Thu, Aug 8, 11:44 PM · Restricted Project
rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Combine if-else logic.
  • Adjust subtraction comment to is (non-zero) positive to avoid ambiguity.
Thu, Aug 8, 11:40 PM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Constrain fold to i1.
Thu, Aug 8, 11:13 PM · Restricted Project
rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Thu, Aug 8, 12:03 AM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Tighten even more the condition in which the fold is applied
  • Rephrase comments so they mention brcond.
Thu, Aug 8, 12:03 AM · Restricted Project

Wed, Aug 7

rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Wed, Aug 7, 11:20 PM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Tighten conditions in which the fold is executed
  • Use isBitwiseNot instead of checking for (xor e, 1)
  • Remove TheXor
  • Rephrase comments so they are less confusing by not mentioning br.
Wed, Aug 7, 11:13 PM · Restricted Project
rogfer01 added a comment to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

Thanks @asb @lenary for the review!

Wed, Aug 7, 1:46 AM · Restricted Project
rogfer01 updated the diff for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

ChangeLog:

  • Make ilp32d also the default in 32-bit RISC-V Linux
  • Do not use nested conditional expressions
Wed, Aug 7, 1:42 AM · Restricted Project
rogfer01 abandoned D50634: [RISCV] Add support for local PIC addressing.

Not relevant anymore.

Wed, Aug 7, 12:14 AM
rogfer01 committed rG371bdc9b7f25: [RISCV] Remove duplicated logic when determining the target ABI (authored by rogfer01).
[RISCV] Remove duplicated logic when determining the target ABI
Wed, Aug 7, 12:09 AM
rogfer01 committed rL368128: [RISCV] Remove duplicated logic when determining the target ABI.
[RISCV] Remove duplicated logic when determining the target ABI
Wed, Aug 7, 12:09 AM
rogfer01 closed D48357: [RISCV] Remove duplicated logic when determining the target ABI.
Wed, Aug 7, 12:08 AM · Restricted Project
rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

Thanks @lenary ! I will commit this shortly.

Wed, Aug 7, 12:08 AM · Restricted Project

Tue, Aug 6

rogfer01 added inline comments to rG629273ec0982: [llvm-ar][test] Add tests failing on Darwin.
Tue, Aug 6, 7:28 AM
rogfer01 added a parent revision for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1): D65801: [NFC] Add tests for boolean comparisons.
Tue, Aug 6, 5:49 AM · Restricted Project
rogfer01 added a child revision for D65801: [NFC] Add tests for boolean comparisons: D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Tue, Aug 6, 5:49 AM · Restricted Project
rogfer01 added a reviewer for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1): efriedma.
Tue, Aug 6, 5:49 AM · Restricted Project
rogfer01 created D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Tue, Aug 6, 5:49 AM · Restricted Project
rogfer01 created D65801: [NFC] Add tests for boolean comparisons.
Tue, Aug 6, 5:46 AM · Restricted Project

Mon, Aug 5

rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Update AMDGPU test.
  • Add RISC-V tests to show that we fold the xor in the branch.
Mon, Aug 5, 7:26 AM · Restricted Project
rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

I've committed rL367698 - you should be able to use the update script now

Mon, Aug 5, 7:21 AM · Restricted Project
rogfer01 committed rGf686e56e7d55: Sidestep false positive due to a matching git repository name (authored by rogfer01).
Sidestep false positive due to a matching git repository name
Mon, Aug 5, 3:11 AM
rogfer01 committed rL367826: Sidestep false positive due to a matching git repository name.
Sidestep false positive due to a matching git repository name
Mon, Aug 5, 3:10 AM
rogfer01 closed D65635: Sidestep false positive due to a matching git repository name.
Mon, Aug 5, 3:10 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D65635: Sidestep false positive due to a matching git repository name.

Thanks @efriedma. I will commit this shortly.

Mon, Aug 5, 3:10 AM · Restricted Project, Restricted Project

Fri, Aug 2

rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Remove RISC-V dependent expansions
  • Simplify current target-independent expansion of S{ADD,SUB}O. Not considering U{ADD,SUB}O anymore.
  • Update tests that saw codegen changes after this
Fri, Aug 2, 8:46 AM · Restricted Project

Thu, Aug 1

rogfer01 created D65635: Sidestep false positive due to a matching git repository name.
Thu, Aug 1, 11:52 PM · Restricted Project, Restricted Project
rogfer01 edited reviewers for D65635: Sidestep false positive due to a matching git repository name, added: efriedma; removed: eli.friedman.
Thu, Aug 1, 11:52 PM · Restricted Project, Restricted Project
rogfer01 added a child revision for D48357: [RISCV] Remove duplicated logic when determining the target ABI: D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Thu, Aug 1, 11:35 PM · Restricted Project
rogfer01 added a parent revision for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux: D48357: [RISCV] Remove duplicated logic when determining the target ABI.
Thu, Aug 1, 11:35 PM · Restricted Project
rogfer01 created D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Thu, Aug 1, 11:35 PM · Restricted Project
rogfer01 updated the diff for D48357: [RISCV] Remove duplicated logic when determining the target ABI.

ChangeLog

  • Rebase change
Thu, Aug 1, 11:20 PM · Restricted Project
rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

Hi @lenary, sure I can rebase this.

Thu, Aug 1, 10:44 PM · Restricted Project

Tue, Jul 23

rogfer01 committed rG09e6304440c0: [RISCV] Implement benchmark::cycleclock::Now (authored by rogfer01).
[RISCV] Implement benchmark::cycleclock::Now
Tue, Jul 23, 10:34 PM
rogfer01 committed rL366868: [RISCV] Implement benchmark::cycleclock::Now.
[RISCV] Implement benchmark::cycleclock::Now
Tue, Jul 23, 10:33 PM
rogfer01 closed D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.
Tue, Jul 23, 10:33 PM · Restricted Project
rogfer01 added a comment to D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

Thanks @lenary !

Tue, Jul 23, 10:18 PM · Restricted Project
rogfer01 updated the diff for D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

ChangeLog

  • State on top of which commit of libcxx's copy we are cherry-picking.
Tue, Jul 23, 10:18 PM · Restricted Project
rogfer01 added a comment to D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

Thanks a lot for the guidance @lebedev.ri. I wasn't aware of @lenary change and the other copies.

Tue, Jul 23, 9:56 AM · Restricted Project
rogfer01 updated the diff for D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

ChangeLog:

  • Cherrypick D64237 to other existing copies of cycleclock.h
Tue, Jul 23, 9:53 AM · Restricted Project
rogfer01 created D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.
Tue, Jul 23, 6:56 AM · Restricted Project

Jul 8 2019

rogfer01 added a comment to D60456: [RISCV] Hard float ABI support.

As noted in another comment, it's not entirely clear what zero-width bitfield behaviour to match (see here) as GCC seems buggy and the ABI is under-specified. Ideally I'd like to land this patch and follow-up to adjust the zero-width bitfield behaviour if necessary once that psABI issue is resolved.

Jul 8 2019, 7:43 AM · Restricted Project, Restricted Project

Jul 7 2019

rogfer01 added inline comments to D60456: [RISCV] Hard float ABI support.
Jul 7 2019, 10:44 PM · Restricted Project, Restricted Project

May 23 2019

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
May 23 2019, 12:35 AM · Restricted Project

May 22 2019

rogfer01 updated subscribers of D62266: [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold.
May 22 2019, 12:36 PM · Restricted Project

May 21 2019

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
May 21 2019, 12:40 AM · Restricted Project
rogfer01 accepted D55667: [RISCV] Support assembling TLS LA pseudo instructions.

Thanks @lewis-revill this LGTM.

May 21 2019, 12:23 AM · Restricted Project

May 15 2019

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I have a question about the meaning of the vlen operand so I want to double-check here.

May 15 2019, 2:09 AM · Restricted Project

May 2 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

@rogfer01 Are you still looking into this? My efforts to fix the problem with the debug information would also touch this. How do you want to proceed?

May 2 2019, 10:31 PM · Restricted Project

May 1 2019

rogfer01 added a comment to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.

I've been looking into this and I have some observations, but not a satisfactory solution so far.

May 1 2019, 10:43 AM · Restricted Project

Apr 17 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

James, Alex: Thanks a lot for the comments. I'll look into what I can do here.

Apr 17 2019, 8:41 AM · Restricted Project
Herald added a project to D45181: [RISCV] Add diff relocation support for RISC-V: Restricted Project.

I don't like resurrecting old reviews. This is just a warning in advance of a future issue we will have with the RISC-V backend when exception handling is enabled (it is not yet upstream).

Apr 17 2019, 6:19 AM · Restricted Project

Apr 15 2019

rogfer01 added inline comments to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.
Apr 15 2019, 1:58 AM · Restricted Project

Apr 13 2019

rogfer01 created D60657: [RISCV] Fix evaluation of %pcrel_lo.
Apr 13 2019, 1:09 PM · Restricted Project

Apr 11 2019

rogfer01 committed rGb621f041359b: [RISCV] Diagnose invalid second input register operand when using %tprel_add (authored by rogfer01).
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:12 AM
rogfer01 committed rL358183: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:11 AM
rogfer01 closed D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 added a comment to D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

Thanks a lot for the review Alex!

Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 updated the diff for D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

ChangeLog:

  • Improve comment with wording kindly suggested by Alex Bradbury
Apr 11 2019, 7:30 AM · Restricted Project

Apr 10 2019

rogfer01 retitled D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add from [RISCV] Diagnose invalid second register operand when using %tprel_add to [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project
rogfer01 created D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project

Apr 5 2019

rogfer01 committed rGe011e4f89cce: [RISCV] Implement adding a displacement to a BlockAddress (authored by rogfer01).
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:42 AM
rogfer01 committed rL357752: [RISCV] Implement adding a displacement to a BlockAddress.
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:40 AM
rogfer01 closed D60136: [RISCV] Implement adding a displacement to a BlockAddress.
Apr 5 2019, 1:39 AM · Restricted Project
rogfer01 added a comment to D60136: [RISCV] Implement adding a displacement to a BlockAddress.

Lewis, Alex: thanks for the review.

Apr 5 2019, 12:29 AM · Restricted Project

Apr 3 2019

rogfer01 updated the diff for D60136: [RISCV] Implement adding a displacement to a BlockAddress.

ChangeLog

  • Remove dead phi in the test
Apr 3 2019, 8:26 AM · Restricted Project

Apr 2 2019

rogfer01 created D60136: [RISCV] Implement adding a displacement to a BlockAddress.
Apr 2 2019, 9:04 AM · Restricted Project

Mar 30 2019

rogfer01 accepted D59357: [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs.

Thanks for the update Alex, certainly vararg.ll is a better test to update than my earlier suggestions.

Mar 30 2019, 9:33 AM · Restricted Project

Mar 26 2019

rogfer01 added a comment to rL356990: [RISCV] Improve codegen for icmp {ne,eq} with a constant.

Hi Luis,

Mar 26 2019, 8:19 AM
rogfer01 committed rGe41a74e8d288: [RISCV] Pass -target-abi to -cc1as (authored by rogfer01).
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:01 AM
rogfer01 committed rC356981: [RISCV] Pass -target-abi to -cc1as.
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:00 AM
rogfer01 committed rL356981: [RISCV] Pass -target-abi to -cc1as.
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:00 AM
rogfer01 closed D59298: [RISCV] Pass -target-abi to -cc1as.
Mar 26 2019, 1:00 AM · Restricted Project, Restricted Project

Mar 25 2019

rogfer01 added a comment to D59298: [RISCV] Pass -target-abi to -cc1as.

Thanks Alex. I will commit it shortly.

Mar 25 2019, 11:45 PM · Restricted Project, Restricted Project
rogfer01 added inline comments to D59699: [RISCV] Add seto pattern expansion.
Mar 25 2019, 6:43 AM · Restricted Project

Mar 18 2019

rogfer01 added a comment to D59357: [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs.

Thanks a lot for this Alex.

Mar 18 2019, 6:44 AM · Restricted Project

Mar 14 2019

rogfer01 added a comment to D59355: [RISCV] Optimize emission of SELECT sequences.

Looks good to me, just a minor suggestion above.

Mar 14 2019, 11:46 PM · Restricted Project

Mar 13 2019

rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

@asb in D59298 I call riscv::getRISCVABI for ClangAs, does it make sense to make the same change for Clang here?

Mar 13 2019, 7:14 AM · Restricted Project
rogfer01 created D59298: [RISCV] Pass -target-abi to -cc1as.
Mar 13 2019, 7:03 AM · Restricted Project, Restricted Project

Feb 19 2019

rogfer01 added a comment to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

Looks sensible to me.

Feb 19 2019, 3:50 AM · Restricted Project

Feb 1 2019

rogfer01 added a reviewer for D57577: Make predefined FLT16 macros conditional on support for the type: SjoerdMeijer.
Feb 1 2019, 3:36 AM · Restricted Project, Restricted Project

Jan 28 2019

rogfer01 added a comment to D57163: [DebugInfo][DAG] PR40427: Avoid accidentally re-ordering DBG_VALUEs due to assumptions about inst creation.

@jmorse pr40427.ll uses x86-specific bits in the CHECK lines and is causing failures in builds that do not target by default x86 (e.g. http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/16847 )

Jan 28 2019, 11:12 PM

Jan 25 2019

rogfer01 added a comment to D57240: [RISCV] Don't incorrectly force relocation for %pcrel_lo.

Hi @lewis-revill, thanks for the patch.

Jan 25 2019, 8:55 AM · Restricted Project

Jan 23 2019

rogfer01 added inline comments to D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64 .
Jan 23 2019, 11:23 AM

Jan 16 2019

rogfer01 added inline comments to D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions.
Jan 16 2019, 6:24 AM

Jan 14 2019

rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Ah, I think what happens is that we should not emit such patterns without the presence of the F extension: these patterns are ultimately selected as instructions in F. Does this make sense?

Jan 14 2019, 6:00 AM
rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Hi Alex,

Jan 14 2019, 5:25 AM

Jan 8 2019

rogfer01 added a comment to rL349764: [RISCV] Properly evaluate fixup_riscv_pcrel_lo12.

Hi Alex,

Jan 8 2019, 7:46 AM

Dec 21 2018

rogfer01 added inline comments to D55279: [RISCV] Support assembling %got_pcrel_hi operator.
Dec 21 2018, 2:54 AM · Restricted Project

Dec 14 2018

rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

Rebased and updated to use and expand PseudoLLA for PC-relative addressing.

Dec 14 2018, 12:47 AM · Restricted Project
rogfer01 added a comment to D55303: [RISCV] Add lowering of addressing sequences for PIC.

Minor comment above but other than that this looks good to me too.

Dec 14 2018, 12:34 AM · Restricted Project

Dec 10 2018

rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

The build issue was fixed in rL348783

Dec 10 2018, 11:09 PM
rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

Hi all,

Dec 10 2018, 10:00 AM