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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (178 w, 6 d)

Recent Activity

Fri, Oct 11

rogfer01 updated subscribers of D68685: [RISCV] Scheduler description for Rocket Core.

@javedabsar (or @javed.absar) I seem to recall you have experience with schedulers. If you could give us a hand here that'd be great! :)

Fri, Oct 11, 2:23 AM · Restricted Project

Wed, Oct 9

rogfer01 added inline comments to D68360: PR41162 Implement LKK remainder and divisibility algorithms [urem].
Wed, Oct 9, 12:42 PM · Restricted Project

Mon, Oct 7

rogfer01 closed D20561: Warn when taking address of packed member.
Mon, Oct 7, 6:49 AM · Restricted Project, Restricted Project

Mon, Sep 30

rogfer01 added inline comments to rG61422f96653f: For P0784R7: add support for explicit destructor calls and pseudo-destructor….
Mon, Sep 30, 3:27 AM
rogfer01 committed rG5a2a14db0bc4: [TargetLowering] Simplify expansion of S{ADD,SUB}O (authored by rogfer01).
[TargetLowering] Simplify expansion of S{ADD,SUB}O
Mon, Sep 30, 1:00 AM
rogfer01 committed rL373187: [TargetLowering] Simplify expansion of S{ADD,SUB}O.
[TargetLowering] Simplify expansion of S{ADD,SUB}O
Mon, Sep 30, 1:00 AM
rogfer01 closed D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.
Mon, Sep 30, 1:00 AM · Restricted Project

Fri, Sep 27

rogfer01 accepted D68068: [ScheduleDAG] When a node is cloned, add an edge between the nodes..

Now that you're at it, could you also update the doxygen comments in ScheduleDAGRRList::{AddPredQueued, AddPred, RemovePred} because they don't return a boolean now.

Fri, Sep 27, 2:28 PM · Restricted Project

Mon, Sep 23

rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

IMHO this should land as-is, and setcc folds can be implemented additionally if there are other places where they would be useful. My rationale would be that it is better to directly perform a simpler lowering than a complex lowering that then gets optimized. (Basically: If you can reduce the size of the implementing code and get a better result, then I think we should always be doing that.)

Mon, Sep 23, 11:20 PM · Restricted Project
rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Refresh RISC-V and X86 tests
Mon, Sep 23, 11:17 PM · Restricted Project

Mon, Sep 16

rogfer01 committed rL372073: Request commit access for rogfer01.
Request commit access for rogfer01
Mon, Sep 16, 10:57 PM
rogfer01 added a comment to D60657: [RISCV] Fix evaluation of %pcrel_lo.

Thanks for the review @jrtc27 and apologies for the delay. I had forgotten I had posted this.

Mon, Sep 16, 2:05 AM · Restricted Project
rogfer01 updated the diff for D60657: [RISCV] Fix evaluation of %pcrel_lo.

ChangeLog:

  • Remove unneeded runtime check and turn it into an assertion.
  • Avoid instruction aliases in testcase
  • Strengthen check directives for the NORELAX case.
Mon, Sep 16, 2:05 AM · Restricted Project

Sep 13 2019

rogfer01 added inline comments to rL371806: [RISCV] Support stack offset exceed 32-bit for RV64.
Sep 13 2019, 12:49 AM

Sep 10 2019

rogfer01 committed rG93c4d53b0a57: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux (authored by rogfer01).
[RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux
Sep 10 2019, 1:17 AM
rogfer01 committed rL371496: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
[RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux
Sep 10 2019, 1:16 AM
rogfer01 closed D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Sep 10 2019, 1:16 AM · Restricted Project, Restricted Project
rogfer01 committed rG8e87396307f0: [RISCV] Default to ilp32d/lp64d in RISC-V Linux (authored by rogfer01).
[RISCV] Default to ilp32d/lp64d in RISC-V Linux
Sep 10 2019, 1:02 AM
rogfer01 committed rL371494: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
[RISCV] Default to ilp32d/lp64d in RISC-V Linux
Sep 10 2019, 1:02 AM
rogfer01 closed D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Sep 10 2019, 1:01 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.

Thanks for the review @luismarques

Sep 10 2019, 12:50 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

Thanks for the review @lenary @luismarques

Sep 10 2019, 12:50 AM · Restricted Project, Restricted Project
rogfer01 committed rG60f0a6f6ff99: [RISCV] Move architecture parsing code into its own function (authored by rogfer01).
[RISCV] Move architecture parsing code into its own function
Sep 10 2019, 12:47 AM
rogfer01 committed rL371492: [RISCV] Move architecture parsing code into its own function.
[RISCV] Move architecture parsing code into its own function
Sep 10 2019, 12:46 AM
rogfer01 closed D66002: [RISCV] Move architecture parsing code into its own function.
Sep 10 2019, 12:46 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D66002: [RISCV] Move architecture parsing code into its own function.

Thanks for the review @luismarques

Sep 10 2019, 12:26 AM · Restricted Project, Restricted Project

Aug 30 2019

rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

Yes

Aug 30 2019, 5:54 AM · Restricted Project
rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Aug 30 2019, 5:49 AM · Restricted Project

Aug 9 2019

rogfer01 added a comment to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

Thanks for the clarification @asb. I've posted D66003 (depending on D66002) for that.

Aug 9 2019, 3:39 AM · Restricted Project, Restricted Project
rogfer01 added parent revisions for D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux: D66002: [RISCV] Move architecture parsing code into its own function, D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Aug 9 2019, 3:38 AM · Restricted Project, Restricted Project
rogfer01 added a child revision for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux: D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Aug 9 2019, 3:38 AM · Restricted Project, Restricted Project
rogfer01 added a child revision for D66002: [RISCV] Move architecture parsing code into its own function: D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Aug 9 2019, 3:38 AM · Restricted Project, Restricted Project
rogfer01 created D66003: [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux.
Aug 9 2019, 3:38 AM · Restricted Project, Restricted Project
rogfer01 created D66002: [RISCV] Move architecture parsing code into its own function.
Aug 9 2019, 3:36 AM · Restricted Project, Restricted Project

Aug 8 2019

rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

Hmm, while there, just to point out the obvious, the another approach here would be to teach DAGCombine/TargetLowering::SimplifySetCC() about these folds.
That is explicitly one of a few valid reasons to add optimizations into backend 'instead' of middle-end.

Aug 8 2019, 11:44 PM · Restricted Project
rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Combine if-else logic.
  • Adjust subtraction comment to is (non-zero) positive to avoid ambiguity.
Aug 8 2019, 11:40 PM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Constrain fold to i1.
Aug 8 2019, 11:13 PM · Restricted Project
rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Aug 8 2019, 12:03 AM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Tighten even more the condition in which the fold is applied
  • Rephrase comments so they mention brcond.
Aug 8 2019, 12:03 AM · Restricted Project

Aug 7 2019

rogfer01 added inline comments to D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Aug 7 2019, 11:20 PM · Restricted Project
rogfer01 updated the diff for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).

ChangeLog:

  • Tighten conditions in which the fold is executed
  • Use isBitwiseNot instead of checking for (xor e, 1)
  • Remove TheXor
  • Rephrase comments so they are less confusing by not mentioning br.
Aug 7 2019, 11:13 PM · Restricted Project
rogfer01 added a comment to D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

Thanks @asb @lenary for the review!

Aug 7 2019, 1:46 AM · Restricted Project, Restricted Project
rogfer01 updated the diff for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.

ChangeLog:

  • Make ilp32d also the default in 32-bit RISC-V Linux
  • Do not use nested conditional expressions
Aug 7 2019, 1:42 AM · Restricted Project, Restricted Project
rogfer01 abandoned D50634: [RISCV] Add support for local PIC addressing.

Not relevant anymore.

Aug 7 2019, 12:14 AM
rogfer01 committed rG371bdc9b7f25: [RISCV] Remove duplicated logic when determining the target ABI (authored by rogfer01).
[RISCV] Remove duplicated logic when determining the target ABI
Aug 7 2019, 12:09 AM
rogfer01 committed rL368128: [RISCV] Remove duplicated logic when determining the target ABI.
[RISCV] Remove duplicated logic when determining the target ABI
Aug 7 2019, 12:09 AM
rogfer01 closed D48357: [RISCV] Remove duplicated logic when determining the target ABI.
Aug 7 2019, 12:08 AM · Restricted Project
rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

Thanks @lenary ! I will commit this shortly.

Aug 7 2019, 12:08 AM · Restricted Project

Aug 6 2019

rogfer01 added inline comments to rG629273ec0982: [llvm-ar][test] Add tests failing on Darwin.
Aug 6 2019, 7:28 AM
rogfer01 added a parent revision for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1): D65801: [NFC] Add tests for boolean comparisons.
Aug 6 2019, 5:49 AM · Restricted Project
rogfer01 added a child revision for D65801: [NFC] Add tests for boolean comparisons: D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Aug 6 2019, 5:49 AM · Restricted Project
rogfer01 added a reviewer for D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1): efriedma.
Aug 6 2019, 5:49 AM · Restricted Project
rogfer01 created D65802: [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1).
Aug 6 2019, 5:49 AM · Restricted Project
rogfer01 created D65801: [NFC] Add tests for boolean comparisons.
Aug 6 2019, 5:46 AM · Restricted Project

Aug 5 2019

rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Update AMDGPU test.
  • Add RISC-V tests to show that we fold the xor in the branch.
Aug 5 2019, 7:26 AM · Restricted Project
rogfer01 added a comment to D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

I've committed rL367698 - you should be able to use the update script now

Aug 5 2019, 7:21 AM · Restricted Project
rogfer01 committed rGf686e56e7d55: Sidestep false positive due to a matching git repository name (authored by rogfer01).
Sidestep false positive due to a matching git repository name
Aug 5 2019, 3:11 AM
rogfer01 committed rL367826: Sidestep false positive due to a matching git repository name.
Sidestep false positive due to a matching git repository name
Aug 5 2019, 3:10 AM
rogfer01 closed D65635: Sidestep false positive due to a matching git repository name.
Aug 5 2019, 3:10 AM · Restricted Project, Restricted Project
rogfer01 added a comment to D65635: Sidestep false positive due to a matching git repository name.

Thanks @efriedma. I will commit this shortly.

Aug 5 2019, 3:10 AM · Restricted Project, Restricted Project

Aug 2 2019

rogfer01 updated the diff for D47927: [TargetLowering] Simplify expansion of S{ADD,SUB}O.

ChangeLog:

  • Remove RISC-V dependent expansions
  • Simplify current target-independent expansion of S{ADD,SUB}O. Not considering U{ADD,SUB}O anymore.
  • Update tests that saw codegen changes after this
Aug 2 2019, 8:46 AM · Restricted Project

Aug 1 2019

rogfer01 created D65635: Sidestep false positive due to a matching git repository name.
Aug 1 2019, 11:52 PM · Restricted Project, Restricted Project
rogfer01 edited reviewers for D65635: Sidestep false positive due to a matching git repository name, added: efriedma; removed: eli.friedman.
Aug 1 2019, 11:52 PM · Restricted Project, Restricted Project
rogfer01 added a child revision for D48357: [RISCV] Remove duplicated logic when determining the target ABI: D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Aug 1 2019, 11:35 PM · Restricted Project
rogfer01 added a parent revision for D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux: D48357: [RISCV] Remove duplicated logic when determining the target ABI.
Aug 1 2019, 11:35 PM · Restricted Project, Restricted Project
rogfer01 created D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux.
Aug 1 2019, 11:35 PM · Restricted Project, Restricted Project
rogfer01 updated the diff for D48357: [RISCV] Remove duplicated logic when determining the target ABI.

ChangeLog

  • Rebase change
Aug 1 2019, 11:20 PM · Restricted Project
rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

Hi @lenary, sure I can rebase this.

Aug 1 2019, 10:44 PM · Restricted Project

Jul 23 2019

rogfer01 committed rG09e6304440c0: [RISCV] Implement benchmark::cycleclock::Now (authored by rogfer01).
[RISCV] Implement benchmark::cycleclock::Now
Jul 23 2019, 10:34 PM
rogfer01 committed rL366868: [RISCV] Implement benchmark::cycleclock::Now.
[RISCV] Implement benchmark::cycleclock::Now
Jul 23 2019, 10:33 PM
rogfer01 closed D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.
Jul 23 2019, 10:33 PM · Restricted Project
rogfer01 added a comment to D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

Thanks @lenary !

Jul 23 2019, 10:18 PM · Restricted Project
rogfer01 updated the diff for D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

ChangeLog

  • State on top of which commit of libcxx's copy we are cherry-picking.
Jul 23 2019, 10:18 PM · Restricted Project
rogfer01 added a comment to D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

Thanks a lot for the guidance @lebedev.ri. I wasn't aware of @lenary change and the other copies.

Jul 23 2019, 9:56 AM · Restricted Project
rogfer01 updated the diff for D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.

ChangeLog:

  • Cherrypick D64237 to other existing copies of cycleclock.h
Jul 23 2019, 9:53 AM · Restricted Project
rogfer01 created D65142: [RISCV] Implement benchmark::cycleclock::Now for riscv64-linux.
Jul 23 2019, 6:56 AM · Restricted Project

Jul 8 2019

rogfer01 added a comment to D60456: [RISCV] Hard float ABI support.

As noted in another comment, it's not entirely clear what zero-width bitfield behaviour to match (see here) as GCC seems buggy and the ABI is under-specified. Ideally I'd like to land this patch and follow-up to adjust the zero-width bitfield behaviour if necessary once that psABI issue is resolved.

Jul 8 2019, 7:43 AM · Restricted Project, Restricted Project

Jul 7 2019

rogfer01 added inline comments to D60456: [RISCV] Hard float ABI support.
Jul 7 2019, 10:44 PM · Restricted Project, Restricted Project

May 23 2019

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
May 23 2019, 12:35 AM · Restricted Project

May 22 2019

rogfer01 updated subscribers of D62266: [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold.
May 22 2019, 12:36 PM · Restricted Project

May 21 2019

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
May 21 2019, 12:40 AM · Restricted Project
rogfer01 accepted D55667: [RISCV] Support assembling TLS LA pseudo instructions.

Thanks @lewis-revill this LGTM.

May 21 2019, 12:23 AM · Restricted Project

May 15 2019

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I have a question about the meaning of the vlen operand so I want to double-check here.

May 15 2019, 2:09 AM · Restricted Project

May 2 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

@rogfer01 Are you still looking into this? My efforts to fix the problem with the debug information would also touch this. How do you want to proceed?

May 2 2019, 10:31 PM · Restricted Project

May 1 2019

rogfer01 added a comment to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.

I've been looking into this and I have some observations, but not a satisfactory solution so far.

May 1 2019, 10:43 AM · Restricted Project

Apr 17 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

James, Alex: Thanks a lot for the comments. I'll look into what I can do here.

Apr 17 2019, 8:41 AM · Restricted Project
Herald added a project to D45181: [RISCV] Add diff relocation support for RISC-V: Restricted Project.

I don't like resurrecting old reviews. This is just a warning in advance of a future issue we will have with the RISC-V backend when exception handling is enabled (it is not yet upstream).

Apr 17 2019, 6:19 AM · Restricted Project

Apr 15 2019

rogfer01 added inline comments to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.
Apr 15 2019, 1:58 AM · Restricted Project

Apr 13 2019

rogfer01 created D60657: [RISCV] Fix evaluation of %pcrel_lo.
Apr 13 2019, 1:09 PM · Restricted Project

Apr 11 2019

rogfer01 committed rGb621f041359b: [RISCV] Diagnose invalid second input register operand when using %tprel_add (authored by rogfer01).
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:12 AM
rogfer01 committed rL358183: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:11 AM
rogfer01 closed D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 added a comment to D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

Thanks a lot for the review Alex!

Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 updated the diff for D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

ChangeLog:

  • Improve comment with wording kindly suggested by Alex Bradbury
Apr 11 2019, 7:30 AM · Restricted Project

Apr 10 2019

rogfer01 retitled D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add from [RISCV] Diagnose invalid second register operand when using %tprel_add to [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project
rogfer01 created D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project

Apr 5 2019

rogfer01 committed rGe011e4f89cce: [RISCV] Implement adding a displacement to a BlockAddress (authored by rogfer01).
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:42 AM
rogfer01 committed rL357752: [RISCV] Implement adding a displacement to a BlockAddress.
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:40 AM
rogfer01 closed D60136: [RISCV] Implement adding a displacement to a BlockAddress.
Apr 5 2019, 1:39 AM · Restricted Project
rogfer01 added a comment to D60136: [RISCV] Implement adding a displacement to a BlockAddress.

Lewis, Alex: thanks for the review.

Apr 5 2019, 12:29 AM · Restricted Project