Page MenuHomePhabricator

rogfer01 (Roger Ferrer Ibanez)
User

Projects

User does not belong to any projects.

User Details

User Since
May 10 2016, 6:42 AM (161 w, 6 d)

Recent Activity

Thu, May 23

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
Thu, May 23, 12:35 AM · Restricted Project

Wed, May 22

rogfer01 updated subscribers of D62266: [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold.
Wed, May 22, 12:36 PM · Restricted Project

Tue, May 21

rogfer01 added inline comments to D55305: [RISCV] Add lowering of global TLS addresses.
Tue, May 21, 12:40 AM · Restricted Project
rogfer01 accepted D55667: [RISCV] Support assembling TLS LA pseudo instructions.

Thanks @lewis-revill this LGTM.

Tue, May 21, 12:23 AM · Restricted Project

May 15 2019

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I have a question about the meaning of the vlen operand so I want to double-check here.

May 15 2019, 2:09 AM · Restricted Project

May 2 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

@rogfer01 Are you still looking into this? My efforts to fix the problem with the debug information would also touch this. How do you want to proceed?

May 2 2019, 10:31 PM · Restricted Project

May 1 2019

rogfer01 added a comment to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.

I've been looking into this and I have some observations, but not a satisfactory solution so far.

May 1 2019, 10:43 AM · Restricted Project

Apr 17 2019

rogfer01 added a comment to D45181: [RISCV] Add diff relocation support for RISC-V.

James, Alex: Thanks a lot for the comments. I'll look into what I can do here.

Apr 17 2019, 8:41 AM · Restricted Project
Herald added a project to D45181: [RISCV] Add diff relocation support for RISC-V: Restricted Project.

I don't like resurrecting old reviews. This is just a warning in advance of a future issue we will have with the RISC-V backend when exception handling is enabled (it is not yet upstream).

Apr 17 2019, 6:19 AM · Restricted Project

Apr 15 2019

rogfer01 added inline comments to D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations.
Apr 15 2019, 1:58 AM · Restricted Project

Apr 13 2019

rogfer01 created D60657: [RISCV] Fix evaluation of %pcrel_lo.
Apr 13 2019, 1:09 PM · Restricted Project

Apr 11 2019

rogfer01 committed rGb621f041359b: [RISCV] Diagnose invalid second input register operand when using %tprel_add (authored by rogfer01).
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:12 AM
rogfer01 committed rL358183: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
[RISCV] Diagnose invalid second input register operand when using %tprel_add
Apr 11 2019, 8:11 AM
rogfer01 closed D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 added a comment to D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

Thanks a lot for the review Alex!

Apr 11 2019, 8:11 AM · Restricted Project
rogfer01 updated the diff for D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.

ChangeLog:

  • Improve comment with wording kindly suggested by Alex Bradbury
Apr 11 2019, 7:30 AM · Restricted Project

Apr 10 2019

rogfer01 retitled D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add from [RISCV] Diagnose invalid second register operand when using %tprel_add to [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project
rogfer01 created D60528: [RISCV] Diagnose invalid second input register operand when using %tprel_add.
Apr 10 2019, 12:01 PM · Restricted Project

Apr 5 2019

rogfer01 committed rGe011e4f89cce: [RISCV] Implement adding a displacement to a BlockAddress (authored by rogfer01).
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:42 AM
rogfer01 committed rL357752: [RISCV] Implement adding a displacement to a BlockAddress.
[RISCV] Implement adding a displacement to a BlockAddress
Apr 5 2019, 1:40 AM
rogfer01 closed D60136: [RISCV] Implement adding a displacement to a BlockAddress.
Apr 5 2019, 1:39 AM · Restricted Project
rogfer01 added a comment to D60136: [RISCV] Implement adding a displacement to a BlockAddress.

Lewis, Alex: thanks for the review.

Apr 5 2019, 12:29 AM · Restricted Project

Apr 3 2019

rogfer01 updated the diff for D60136: [RISCV] Implement adding a displacement to a BlockAddress.

ChangeLog

  • Remove dead phi in the test
Apr 3 2019, 8:26 AM · Restricted Project

Apr 2 2019

rogfer01 created D60136: [RISCV] Implement adding a displacement to a BlockAddress.
Apr 2 2019, 9:04 AM · Restricted Project

Mar 30 2019

rogfer01 accepted D59357: [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs.

Thanks for the update Alex, certainly vararg.ll is a better test to update than my earlier suggestions.

Mar 30 2019, 9:33 AM · Restricted Project

Mar 26 2019

rogfer01 added a comment to rL356990: [RISCV] Improve codegen for icmp {ne,eq} with a constant.

Hi Luis,

Mar 26 2019, 8:19 AM
rogfer01 committed rGe41a74e8d288: [RISCV] Pass -target-abi to -cc1as (authored by rogfer01).
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:01 AM
rogfer01 committed rC356981: [RISCV] Pass -target-abi to -cc1as.
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:00 AM
rogfer01 committed rL356981: [RISCV] Pass -target-abi to -cc1as.
[RISCV] Pass -target-abi to -cc1as
Mar 26 2019, 1:00 AM
rogfer01 closed D59298: [RISCV] Pass -target-abi to -cc1as.
Mar 26 2019, 1:00 AM · Restricted Project, Restricted Project

Mar 25 2019

rogfer01 added a comment to D59298: [RISCV] Pass -target-abi to -cc1as.

Thanks Alex. I will commit it shortly.

Mar 25 2019, 11:45 PM · Restricted Project, Restricted Project
rogfer01 added inline comments to D59699: [RISCV] Add seto pattern expansion.
Mar 25 2019, 6:43 AM · Restricted Project

Mar 18 2019

rogfer01 added a comment to D59357: [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs.

Thanks a lot for this Alex.

Mar 18 2019, 6:44 AM · Restricted Project

Mar 14 2019

rogfer01 added a comment to D59355: [RISCV] Optimize emission of SELECT sequences.

Looks good to me, just a minor suggestion above.

Mar 14 2019, 11:46 PM · Restricted Project

Mar 13 2019

rogfer01 added a comment to D48357: [RISCV] Remove duplicated logic when determining the target ABI.

@asb in D59298 I call riscv::getRISCVABI for ClangAs, does it make sense to make the same change for Clang here?

Mar 13 2019, 7:14 AM
rogfer01 created D59298: [RISCV] Pass -target-abi to -cc1as.
Mar 13 2019, 7:03 AM · Restricted Project, Restricted Project

Feb 19 2019

rogfer01 added a comment to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

Looks sensible to me.

Feb 19 2019, 3:50 AM · Restricted Project

Feb 1 2019

rogfer01 added a reviewer for D57577: Make predefined FLT16 macros conditional on support for the type: SjoerdMeijer.
Feb 1 2019, 3:36 AM · Restricted Project, Restricted Project

Jan 28 2019

rogfer01 added a comment to D57163: [DebugInfo][DAG] PR40427: Avoid accidentally re-ordering DBG_VALUEs due to assumptions about inst creation.

@jmorse pr40427.ll uses x86-specific bits in the CHECK lines and is causing failures in builds that do not target by default x86 (e.g. http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/16847 )

Jan 28 2019, 11:12 PM

Jan 25 2019

rogfer01 added a comment to D57240: [RISCV] Don't incorrectly force relocation for %pcrel_lo.

Hi @lewis-revill, thanks for the patch.

Jan 25 2019, 8:55 AM · Restricted Project

Jan 23 2019

rogfer01 added inline comments to D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64 .
Jan 23 2019, 11:23 AM

Jan 16 2019

rogfer01 added inline comments to D56264: [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions.
Jan 16 2019, 6:24 AM

Jan 14 2019

rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Ah, I think what happens is that we should not emit such patterns without the presence of the F extension: these patterns are ultimately selected as instructions in F. Does this make sense?

Jan 14 2019, 6:00 AM
rogfer01 added a comment to D53235: [RISCV] Add RV64F codegen support.

Hi Alex,

Jan 14 2019, 5:25 AM

Jan 8 2019

rogfer01 added a comment to rL349764: [RISCV] Properly evaluate fixup_riscv_pcrel_lo12.

Hi Alex,

Jan 8 2019, 7:46 AM

Dec 21 2018

rogfer01 added inline comments to D55279: [RISCV] Support assembling %got_pcrel_hi operator.
Dec 21 2018, 2:54 AM · Restricted Project

Dec 14 2018

rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

Rebased and updated to use and expand PseudoLLA for PC-relative addressing.

Dec 14 2018, 12:47 AM · Restricted Project
rogfer01 added a comment to D55303: [RISCV] Add lowering of addressing sequences for PIC.

Minor comment above but other than that this looks good to me too.

Dec 14 2018, 12:34 AM · Restricted Project

Dec 10 2018

rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

The build issue was fixed in rL348783

Dec 10 2018, 11:09 PM
rogfer01 added a comment to rL348756: Support clang compiling under windows-gnu and windows-msvc.

Hi all,

Dec 10 2018, 10:00 AM

Dec 7 2018

rogfer01 abandoned D48643: Define LLVM_IS_TRIVIALLY_COPYABLE.

Not needed for now.

Dec 7 2018, 3:18 AM
rogfer01 abandoned D48589: [WIP] [CodeGen] Allow specifying Extend to CoerceAndExpand.

Upstream recently amended the ABI spec so it looks to me this is not going to be needed.

Dec 7 2018, 3:17 AM
rogfer01 committed rL348576: [utils] Use operator "in" instead of bound function "has_key".
[utils] Use operator "in" instead of bound function "has_key"
Dec 7 2018, 1:52 AM
rogfer01 closed D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 7 2018, 1:52 AM
rogfer01 added a comment to D55310: [utils] Use operator "in" instead of bound function "has_key".

Thanks for the review @gbedwell @MaskRay

Dec 7 2018, 1:00 AM

Dec 6 2018

rogfer01 added inline comments to D55341: [RISCV] Support assembling TLS add and associated modifiers.
Dec 6 2018, 5:13 AM · Restricted Project
rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

My only problem with that approach is that it seems wrong to expand PseudoLLA the same way I am expanding PseudoAddrPCRel, IE allowing the AUIPC operand to be decided by codegen.

Dec 6 2018, 3:45 AM · Restricted Project

Dec 5 2018

rogfer01 added a comment to D55335: [RISCV] Support assembling @plt symbol operands.

Ah of course. I hadn't thought of that case. I guess we don't expect symbols to end in @plt as part of their name, do we?

Dec 5 2018, 2:19 PM · Restricted Project
rogfer01 added a comment to D55335: [RISCV] Support assembling @plt symbol operands.

Would it make sense to add an operand that allows a bare symbol or bare symbol + @plt and use it only in CALL and TAIL instead of allowing identifier@plt everywhere?

Dec 5 2018, 12:24 PM · Restricted Project
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Dec 5 2018, 11:29 AM · Restricted Project
rogfer01 added inline comments to D55325: [RISCV] Add assembler support for LA pseudo-instruction.
Dec 5 2018, 7:50 AM · Restricted Project
rogfer01 updated subscribers of D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 5 2018, 12:08 AM

Dec 4 2018

rogfer01 created D55310: [utils] Use operator "in" instead of bound function "has_key".
Dec 4 2018, 10:45 PM
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Yeah, upstream suggested axing the list of assembly operators from the psABI doc as it's unnecessary duplication that gets out of date. Volunteers?...

Dec 4 2018, 11:42 AM · Restricted Project
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

Ah, thanks @asb definitely I was looking at the wrong place!

Dec 4 2018, 11:13 AM · Restricted Project
rogfer01 added a comment to D55279: [RISCV] Support assembling %got_pcrel_hi operator.

This patch is a very reasonable one: it is a bit weird we can't expand la (under -fPIC) because R_RISCV_GOT_HI20 relocation does not have any associated syntax.

Dec 4 2018, 10:49 AM · Restricted Project
rogfer01 added a comment to D55253: [RISCV] Fix incorrect use of MCInstBuilder in RISCVMCCodeEmitter.

Hi, thanks for the patch. I don't think this usage is wrong so we don't have to change it.

Dec 4 2018, 12:02 AM

Dec 3 2018

rogfer01 added a comment to rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

Thanks both for the prompt answer!

Dec 3 2018, 2:51 AM
rogfer01 updated subscribers of rL347988: [RISCV] Add UNIMP instruction (32- and 16-bit forms).

the test MC/Disassembler/RISCV/invalid-instruction.txt contains this case

Dec 3 2018, 1:48 AM

Nov 21 2018

rogfer01 added a comment to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.

In my downstream I have a single RISCVISD::WRAPPER_PIC and then I use a target flag to remember whether later we want just PCREL (lla) or GOT based on what shouldAssumeDSOLocal returns.

Nov 21 2018, 9:50 AM · Restricted Project

Nov 13 2018

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Nov 13 2018, 1:11 PM

Nov 7 2018

rogfer01 planned changes to D50634: [RISCV] Add support for local PIC addressing.

On hold for now.

Nov 7 2018, 12:36 PM
rogfer01 accepted D54159: [RISCV] Mark FREM as Expand.

Thanks Luis. I merged your earlier change D54034 into my downstream compiler just to find that frem was missing (triggered by a downstream test).

Nov 7 2018, 10:36 AM

Nov 6 2018

rogfer01 added inline comments to D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 9:47 AM · Restricted Project
rogfer01 updated subscribers of D54143: [RISCV] Generate address sequences suitable for mcmodel=medium.
Nov 6 2018, 6:11 AM · Restricted Project

Oct 31 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Here is an example of two dvl invocations, which compute the same result:

a) llvm_dvl_fadd.v256f64(%x, %y, <full mask>, 13)
Since 13 < 32, the hardware will only issue 1 operation to its SIMD execution units. The occupation is thus something like 13/32 ~ 40%.

b`) llvm_dvl_fadd.v256f64(%x, %y, <mask with first 13 bits set>, 256)
Since the DVL is 256, the hardware will issue 8 operations to its SIMD units. However, only the first 13 elements are relevant leading to an occupation of 13/256 ~ 5%.

Oct 31 2018, 3:18 AM · Restricted Project
rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

I agree with @fpetrogalli here that there is some overlap between a "dynamic vector length" i32 %dvl and a mask of the form %m = <i1 0, ..., i1 0, i1 1, ..., i1 1> (or the reverse, if the lanes are to be interpreted in the other direction) where %dvl = llvm.ctpop(%m). As Francesco, puts it, we can always construct %m from %dvl. Perhaps I'm wrong, but I think in the context of strip-mined loops or whole function vectorisation, more elaborated masks that might arise due to control flow would always be subsumed by %m (i.e. will have a strict subset of the lanes enabled by %dvl).

Oct 31 2018, 1:40 AM · Restricted Project

Oct 30 2018

rogfer01 accepted D53848: [ARM] Add missing pseudo-instruction for Thumb1 RSBS..

Hi @efriedma thanks a lot for this improvement.

Oct 30 2018, 12:19 AM

Oct 25 2018

rogfer01 added inline comments to D53235: [RISCV] Add RV64F codegen support.
Oct 25 2018, 8:22 AM

Oct 24 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Yes, the changes in this RFC are compatible with a physical simdlen that is unknown at compile time.

Oct 24 2018, 3:47 AM · Restricted Project

Oct 23 2018

rogfer01 added a comment to D53613: RFC: Explicit Vector Length Intrinsics and Attributes.

Hi Simon,

Oct 23 2018, 10:49 PM · Restricted Project

Oct 22 2018

rogfer01 added inline comments to rL344901: Always search sysroot for GCC installs.
Oct 22 2018, 9:41 AM

Oct 15 2018

rogfer01 added inline comments to D53291: add riscv32e to the llvm.
Oct 15 2018, 8:34 AM

Oct 4 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

Sorry I missed the RFC. After having read it I agree with you. Sorry for the noise.

Oct 4 2018, 3:43 AM

Oct 3 2018

rogfer01 added a comment to D52833: [RISCV] Add codegen test for RV64 ALU operations.

rv64i has a few specific *w instructions that we probably want to test them too. For instance,

Oct 3 2018, 9:21 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 7:27 AM
rogfer01 added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Oct 3 2018, 6:35 AM

Sep 12 2018

rogfer01 committed rL342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 committed rC342060: [RISCV] Explicitly set an empty --sysroot in the test.
[RISCV] Explicitly set an empty --sysroot in the test
Sep 12 2018, 8:56 AM
rogfer01 closed D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 8:56 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

The updated testcase does not fail locally anymore.

Sep 12 2018, 8:35 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks I will do it shortly.

Sep 12 2018, 8:29 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

I can commit it.

Sep 12 2018, 8:23 AM
rogfer01 added a comment to D51972: [RISCV] Explicitly set an empty --sysroot in the test.

Thanks for the review!

Sep 12 2018, 7:53 AM
rogfer01 created D51972: [RISCV] Explicitly set an empty --sysroot in the test.
Sep 12 2018, 3:28 AM
rogfer01 added a comment to rL341547: Fix the -print-multi-directory flag to print the selected multilib..

on a second thought, "InstalledDir" only appears with -v, and is still too fragile (e.g if installed dir name also contains checked strings)

Sep 12 2018, 2:37 AM

Sep 10 2018

rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Sure, I didn't mean to do that broader change here. Apologies if it read that way.

Sep 10 2018, 10:47 AM
rogfer01 added a comment to D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf.

Thanks for reopening this @kristina.

Sep 10 2018, 9:45 AM
rogfer01 added inline comments to rL341547: Fix the -print-multi-directory flag to print the selected multilib..
Sep 10 2018, 7:28 AM
rogfer01 added inline comments to rL341655: Differential Revision: https://reviews.llvm.org/D50246.
Sep 10 2018, 6:35 AM