[Clang][RISCV] Define RISC-V V builtin types

[HsiangKai]

Summary

Add the types for the RISC-V V extension builtins.

These types will be used by the RISC-V V intrinsics which require types of the form <vscale x 1 x i64>(LMUL=1 element size=64) or <vscale x 4 x i32>(LMUL=2 element size=32), etc. The vector_size attribute does not work for us as it doesn't create a scalable vector type. We want these types to be opaque and have no operators defined for them. We want them to be sizeless. This makes them similar to the ARM SVE builtin types. But we will have quite a bit more types. This patch adds around 60. Later patches will add another 230 or so types representing tuples of these types similar to the x2/x3/x4 types in ARM SVE. But with extra complexity that these types are combined with the LMUL concept that is unique to RISCV.

For more background see this RFC http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html

Authored-by: Hsiangkai Wang <[e-mail]>

[craig.topper]

Can you re-upload the patch with full context?

[craig.topper]

clang/include/clang/Basic/RISCVVTypes.def

33

NF argument isn't documented. And is always 1.

clang/include/clang/Basic/TargetInfo.h

221

This needs to be initialized to false in TargetInfo::TargetInfo() in TargetInfo.cpp I think. And then set to true from lib/Basic/Targets/RISCV.cpp

clang/lib/AST/ASTContext.cpp

2185

Does this alignment need to be this high? The VMV0 register class in the backend has an alignment of 64 for spills. Just wondering why they aren't consistent.

clang/lib/CodeGen/CGDebugInfo.cpp

779

Is there a function name in DwarfUnt.cpp that would be a better reference here? Line numbers aren't stable.

[HsiangKai]

clang/include/clang/Basic/RISCVVTypes.def

33

NF argument isn't documented. And is always 1.

We could remove it in this patch. The field will be needed when we are going to upstream Zvlsseg implementation.

clang/lib/AST/ASTContext.cpp

2185

Does this alignment need to be this high? The VMV0 register class in the backend has an alignment of 64 for spills. Just wondering why they aren't consistent.

Indeed, it should be 64.

clang/lib/CodeGen/CGDebugInfo.cpp

779

Is there a function name in DwarfUnt.cpp that would be a better reference here? Line numbers aren't stable.

It should be hasVectorBeenPadded(). I have a downstream modification not upstreamed. We could remove the debug info for RVV types from this patch. I think it could be another patch for debug info for scalable vector types.

[liaolucy]

clang/include/clang/Basic/RISCVVTypes.def

68

RISC-V V has too many types, more than 200. All types use builtin types? Is it possible to reduce the number of builtin types?

[jrtc27]

clang/include/clang/Basic/RISCVVTypes.def

68

Indeed this is madness, what's wrong with just using __attribute__((vector_size(n))) on the right type? We should not be encouraging people to write code with architecture-specific types... but if we _really_ need these because RISC-V GCC decided this is how RISC-V V is going to look them can we not just shove them all in a header as typedef's for the architecture-independent attributed types and push that complexity out of the compiler itself?

[craig.topper]

clang/include/clang/Basic/RISCVVTypes.def

68

We are using <vscale x 1 x i64> to specify types in IR. The size of the fixed part is being used to control the LMUL parameter. There is currently no way to spell a scalable vector type in C in a generic way.

Alternatively I guess we could make LMUL a parameter to the intrinsic and create the scalable IR types in the frontend based on it?

[craig.topper]

clang/include/clang/Basic/RISCVVTypes.def

68

I do wonder why we bothered to have signed and unsigned types. The signedness of the operation should be carried in the intrinsic name.

[evandro]

clang/include/clang/Basic/RISCVVTypes.def

33

Perhaps we can just note that NF is going to be used by Zvlsseg instead.

68

Some integer operations distinguish between signed and unsigned.

clang/lib/AST/ASTContext.cpp

2185

Does this alignment need to be this high? The VMV0 register class in the backend has an alignment of 64 for spills. Just wondering why they aren't consistent.

Indeed, it should be 64.

Good catch!

[khchen]

clang/include/clang/Basic/RISCVVTypes.def

68

I do wonder why we bothered to have signed and unsigned types. The signedness of the operation should be carried in the intrinsic name.

I think the only good thing for supporting both signed and unsigned type is that are more readable and compiler can does type checking for programmer.

maybe the alternative way is changing intrinsic naming rule like

vint32m1_t a, b, c;
a = vadd_i32m1(b, c);
vuint32m1_t a, b, c;
a = vadd_u32m1(b, c);
vfloat32m1_t a, b, c;
a = vadd_f32m1(b, c);

[kito-cheng]

clang/include/clang/Basic/RISCVVTypes.def

68

One quick thought about this, if the concern is too much built-in types are introduced in clang, maybe we could add a new attribute like __attribute__((vector_size(n))), maybe named __attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))? and use that to define vector types like typedef int __attribute__((riscv_scaleble_vector("2"))) vintm2_t.

[HsiangKai]

clang/include/clang/Basic/RISCVVTypes.def

68

To have signed and unsigned types, we could do type checking for the builtins. For example, we have vmaxu_vv and vmax_vv. Users could pass signed vector types into unsigned version vmaxu_vv if we only have types without signed/unsigned. How could we tell users they pass values into the wrong builtins?

[liaolucy]

clang/include/clang/Basic/RISCVVTypes.def

69

eg: typedef attribute((riscv_vector_type(16/*EIBits*/, 1/*LMUL*/, ...))) int16_t vint16m1_t;
Please help to consider if this is feasible.

[craig.topper]

clang/include/clang/Basic/RISCVVTypes.def

68

Maybe I've been corrupted by X86 where there is just a single 128-bit integer vector type. Even though there are 8, 16, 32, 64 bit element operations with some being signed/unsigned.

[craig.topper]

Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng @khchen @liaolucy

[asb]

In D92715#2443376, @craig.topper wrote:

Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng @khchen @liaolucy

I've added it to the agenda

[craig.topper]

I think it would be possible to add a new attribute to define these types. But only specific values for parameters would be allowed so that it could only generate the exact types we see here and the future segment load patches. It wouldn't be general purpose like vector_size since the backend design has a contract about how to translate the LMUL value from the scalable type.

This would introduce a new type in the AST or at least new subtype of VectorType. This new type would need to be checked for in multiple places in the compiler to define its behavior. As a datapoint VectorType::SveFixedLengthDataVector appears 20 times. It's not clear that's a reduction in complexity versus following what was already done with AArch64SVEACLETypes.def. But I'm not a frontend expert.

[craig.topper]

@rsmith or @rjmccall do you have any opinions on whether we should use builtin types like SVE or create a new attribute for RISCV?

[craig.topper]

Ping

[erichkeane]

In D92715#2446479, @craig.topper wrote:

I think it would be possible to add a new attribute to define these types. But only specific values for parameters would be allowed so that it could only generate the exact types we see here and the future segment load patches. It wouldn't be general purpose like vector_size since the backend design has a contract about how to translate the LMUL value from the scalable type.

This would introduce a new type in the AST or at least new subtype of VectorType. This new type would need to be checked for in multiple places in the compiler to define its behavior. As a datapoint VectorType::SveFixedLengthDataVector appears 20 times. It's not clear that's a reduction in complexity versus following what was already done with AArch64SVEACLETypes.def. But I'm not a frontend expert.

FWIW, when I went to introduce the predecessor to _ExtInt, @rsmith was very against using an attribute spelling and wanted a declaration keyword (which is partly how _ExtInt ended up how it was).

I don't think it is controversial to be a new AST type however.

[HsiangKai]

@liaolucy RISC-V vector types are sizeless types. Sizeless is kind of characteristic for builtin types. If we use attribute to declare RISC-V vector types, the frontend does not know anything about it. I still think to define RISC-V vector types as builtin types is a better way.

[liaolucy]

In D92715#2495897, @HsiangKai wrote:

@liaolucy RISC-V vector types are sizeless types. Sizeless is kind of characteristic for builtin types. If we use attribute to declare RISC-V vector types, the frontend does not know anything about it. I still think to define RISC-V vector types as builtin types is a better way.

Thanks, It's OK for me.

[HsiangKai]

Refine debug info for RVV types.

[HsiangKai]

Recover comments.

[HsiangKai]

According to "9. Vector Memory Alignment Constraints" in V specification, change the alignment of RVV types to the element size.

[HsiangKai]

Ping. If we all agree to use builtin types to model RVV types, is there any other issues we need to address in this patch?

[craig.topper]

I wonder if these types should be prefixed with "__clang_" like AArch64 tuple types?

clang/lib/AST/ASTContext.cpp

3875

Should this be indented 2 more spaces? to align with the uin64_t above?

3882

Same here

clang/lib/CodeGen/CGDebugInfo.cpp

783

Put this above the "if (FixedSize < 64)" and make that an "else if" so all assignments are in the same if/else structure.
You could pre-initialize Fractional to false and only assign it to true in the if/else chain.

clang/test/CodeGen/RISCV/riscv-v-debuginfo.c

2

This seems to be dependent on the patch that adds the vadd builtins?

[HsiangKai]

Address @craig.topper's comments.

[HsiangKai]

In D92715#2520925, @craig.topper wrote:

I wonder if these types should be prefixed with "__clang_" like AArch64 tuple types?

It seems only AArch64 tuple types have "__clang_" prefix.

[craig.topper]

In D92715#2544178, @HsiangKai wrote:

In D92715#2520925, @craig.topper wrote:

I wonder if these types should be prefixed with "__clang_" like AArch64 tuple types?

It seems only AArch64 tuple types have "__clang_" prefix.

I think the other types don't have it because they are defined by an ARM standard. See the description for https://reviews.llvm.org/D81721

[HsiangKai]

In D92715#2544233, @craig.topper wrote:

In D92715#2544178, @HsiangKai wrote:

In D92715#2520925, @craig.topper wrote:

I wonder if these types should be prefixed with "__clang_" like AArch64 tuple types?

It seems only AArch64 tuple types have "__clang_" prefix.

I think the other types don't have it because they are defined by an ARM standard. See the description for https://reviews.llvm.org/D81721

It seems to use __clang_ to differentiate tuple types and non-tuple types. The mangling rules are different between tuple types and non-tuple types in ARM. We have no mangling rules in our specification. I have a TODO item in this patch to clarify the mangling rules later.

[craig.topper]

LGTM

clang/include/clang/AST/ASTContext.h

#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
   CanQualType Id##Ty;
 #include "clang/Basic/OpenCLExtensionTypes.def"
 #define SVE_TYPE(Name, Id, SingletonId) \
   CanQualType SingletonId;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   CanQualType Id##Ty;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+  CanQualType SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
 
   // Types for deductions in C++0x [stmt.ranged]'s desugaring. Built on demand.
   mutable QualType AutoDeductTy;     // Deduction against 'auto'.
   mutable QualType AutoRRefDeductTy; // Deduction against 'auto &&'.
 
   // Decl used to help define __builtin_va_list for some targets.
   // The decl is built when constructing 'BuiltinVaListDecl'.
   mutable Decl *VaListTagDecl = nullptr;

clang/include/clang/AST/Type.h

 #define EXT_OPAQUE_TYPE(ExtType, Id, Ext) Id,
 #include "clang/Basic/OpenCLExtensionTypes.def"
 // SVE Types
 #define SVE_TYPE(Name, Id, SingletonId) Id,
 #include "clang/Basic/AArch64SVEACLETypes.def"
 // PPC MMA Types
 #define PPC_VECTOR_TYPE(Name, Id, Size) Id,
 #include "clang/Basic/PPCTypes.def"
+// RVV Types
+#define RVV_TYPE(Name, Id, SingletonId) Id,
+#include "clang/Basic/RISCVVTypes.def"
 // All other builtin types
 #define BUILTIN_TYPE(Id, SingletonId) Id,
 #define LAST_BUILTIN_TYPE(Id) LastKind = Id
 #include "clang/AST/BuiltinTypes.def"
   };
 
 private:
   friend class ASTContext; // ASTContext creates these.

clang/include/clang/AST/TypeProperties.td

 #define SVE_TYPE(NAME, ID, SINGLETON_ID) \
       case BuiltinType::ID: return ctx.SINGLETON_ID;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 
 #define PPC_VECTOR_TYPE(NAME, ID, SIZE) \
       case BuiltinType::ID: return ctx.ID##Ty;
 #include "clang/Basic/PPCTypes.def"
 
+#define RVV_TYPE(NAME, ID, SINGLETON_ID) \
+      case BuiltinType::ID: return ctx.SINGLETON_ID;
+#include "clang/Basic/RISCVVTypes.def"
+
 #define BUILTIN_TYPE(ID, SINGLETON_ID) \
       case BuiltinType::ID: return ctx.SINGLETON_ID;
 #include "clang/AST/BuiltinTypes.def"
       }
       llvm_unreachable("unreachable builtin case");
   }]>;
 }
 

clang/include/clang/Basic/RISCVVTypes.def

+//===-- RISCVVTypes.def - Metadata for the RISC-V V types ------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines various RISC-V V builtin types.  The macros are:
+//
+// - RVV_TYPE(Name, Id, SingletonId)
+//   A builtin type that has not been covered by any other #define
+//   Defining this macro covers all the builtins.
+//
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+//   A RISC-V V scalable vector.
+//
+// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
+//   An RISC-V V scalable mask.
+//
+// where:
+//
+// - Name is the name of the builtin type.
+//
+// - Id is the enumerator defining the type.
+//
+// - SingletonId is the global singleton of this type.
+//
+// - NumEls enumerates the number of the elements.
+//
+// - ElBits is the size of one element in bits (SEW).
+//
+// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions
+//   (TODO).
+//
+// - IsSigned is true for vectors of signed integer elements and
+//   for vectors of floating-point elements.
+//
+// - IsFP is true for vectors of floating-point elements.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef RVV_VECTOR_TYPE
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP)\
+  RVV_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef RVV_PREDICATE_TYPE
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)\
+  RVV_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_INT
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned) \
+  RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_FLOAT
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
+  RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#endif
+
+//===- Vector types -------------------------------------------------------===//
+
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t", RvvInt8mf8, RvvInt8mf8Ty, 1,   8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4_t", RvvInt8mf4, RvvInt8mf4Ty, 2,   8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2_t", RvvInt8mf2, RvvInt8mf2Ty, 4,   8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1_t",  RvvInt8m1,  RvvInt8m1Ty,  8,   8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8_t",RvvUint8mf8,RvvUint8mf8Ty,1,   8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4_t",RvvUint8mf4,RvvUint8mf4Ty,2,   8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2_t",RvvUint8mf2,RvvUint8mf2Ty,4,   8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1_t", RvvUint8m1, RvvUint8m1Ty, 8,   8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m2_t", RvvUint8m2, RvvUint8m2Ty, 16,  8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m4_t", RvvUint8m4, RvvUint8m4Ty, 32,  8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m8_t", RvvUint8m8, RvvUint8m8Ty, 64,  8, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4_t",RvvInt16mf4,RvvInt16mf4Ty,1,  16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2_t",RvvInt16mf2,RvvInt16mf2Ty,2,  16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1_t", RvvInt16m1, RvvInt16m1Ty, 4,  16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m2_t", RvvInt16m2, RvvInt16m2Ty, 8,  16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m4_t", RvvInt16m4, RvvInt16m4Ty, 16, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m8_t", RvvInt16m8, RvvInt16m8Ty, 32, 16, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4_t",RvvUint16mf4,RvvUint16mf4Ty,1,  16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2_t",RvvUint16mf2,RvvUint16mf2Ty,2,  16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1_t", RvvUint16m1, RvvUint16m1Ty, 4,  16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m2_t", RvvUint16m2, RvvUint16m2Ty, 8,  16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m4_t", RvvUint16m4, RvvUint16m4Ty, 16, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m8_t", RvvUint16m8, RvvUint16m8Ty, 32, 16, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2_t",RvvInt32mf2,RvvInt32mf2Ty,1,  32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1_t", RvvInt32m1, RvvInt32m1Ty, 2,  32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m2_t", RvvInt32m2, RvvInt32m2Ty, 4,  32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m4_t", RvvInt32m4, RvvInt32m4Ty, 8,  32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m8_t", RvvInt32m8, RvvInt32m8Ty, 16, 32, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2_t",RvvUint32mf2,RvvUint32mf2Ty,1,  32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1_t", RvvUint32m1, RvvUint32m1Ty, 2,  32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m2_t", RvvUint32m2, RvvUint32m2Ty, 4,  32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m4_t", RvvUint32m4, RvvUint32m4Ty, 8,  32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m8_t", RvvUint32m8, RvvUint32m8Ty, 16, 32, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int64m1_t", RvvInt64m1, RvvInt64m1Ty, 1,  64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m2_t", RvvInt64m2, RvvInt64m2Ty, 2,  64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m4_t", RvvInt64m4, RvvInt64m4Ty, 4,  64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m8_t", RvvInt64m8, RvvInt64m8Ty, 8,  64, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1_t",RvvUint64m1,RvvUint64m1Ty,1,  64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m2_t",RvvUint64m2,RvvUint64m2Ty,2,  64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4,  64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8,  64, 1, false)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1,  16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2,  16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4,  16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2, RvvFloat16m2Ty, 8,  16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32, 16, 1)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2_t",RvvFloat32mf2,RvvFloat32mf2Ty,1,  32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1_t", RvvFloat32m1, RvvFloat32m1Ty, 2,  32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2_t", RvvFloat32m2, RvvFloat32m2Ty, 4,  32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m4_t", RvvFloat32m4, RvvFloat32m4Ty, 8,  32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m8_t", RvvFloat32m8, RvvFloat32m8Ty, 16, 32, 1)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1_t", RvvFloat64m1, RvvFloat64m1Ty, 1,  64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2_t", RvvFloat64m2, RvvFloat64m2Ty, 2,  64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4_t", RvvFloat64m4, RvvFloat64m4Ty, 4,  64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m8_t", RvvFloat64m8, RvvFloat64m8Ty, 8,  64, 1)
+
+RVV_PREDICATE_TYPE("__rvv_bool1_t",  RvvBool1,  RvvBool1Ty,  64)
+RVV_PREDICATE_TYPE("__rvv_bool2_t",  RvvBool2,  RvvBool2Ty,  32)
+RVV_PREDICATE_TYPE("__rvv_bool4_t",  RvvBool4,  RvvBool4Ty,  16)
+RVV_PREDICATE_TYPE("__rvv_bool8_t",  RvvBool8,  RvvBool8Ty,  8)
+RVV_PREDICATE_TYPE("__rvv_bool16_t", RvvBool16, RvvBool16Ty, 4)
+RVV_PREDICATE_TYPE("__rvv_bool32_t", RvvBool32, RvvBool32Ty, 2)
+RVV_PREDICATE_TYPE("__rvv_bool64_t", RvvBool64, RvvBool64Ty, 1)
+
+#undef RVV_VECTOR_TYPE_FLOAT
+#undef RVV_VECTOR_TYPE_INT
+#undef RVV_VECTOR_TYPE
+#undef RVV_PREDICATE_TYPE
+#undef RVV_TYPE

clang/include/clang/Basic/TargetInfo.h

protected:
   unsigned ComplexLongDoubleUsesFP2Ret : 1;
 
   unsigned HasBuiltinMSVaList : 1;
 
   unsigned IsRenderScriptTarget : 1;
 
   unsigned HasAArch64SVETypes : 1;
 
+  unsigned HasRISCVVTypes : 1;
+
   unsigned AllowAMDGPUUnsafeFPAtomics : 1;
 
   unsigned ARMCDECoprocMask : 8;
 
   unsigned MaxOpenCLWorkGroupSize;
 
   // TargetInfo Constructor.  Default initializes all fields.
   TargetInfo(const llvm::Triple &T);
public:
 
   /// Returns true for RenderScript.
   bool isRenderScriptTarget() const { return IsRenderScriptTarget; }
 
   /// Returns whether or not the AArch64 SVE built-in types are
   /// available on this target.
   bool hasAArch64SVETypes() const { return HasAArch64SVETypes; }
 
+  /// Returns whether or not the RISC-V V built-in types are
+  /// available on this target.
+  bool hasRISCVVTypes() const { return HasRISCVVTypes; }
+
   /// Returns whether or not the AMDGPU unsafe floating point atomics are
   /// allowed.
   bool allowAMDGPUUnsafeFPAtomics() const { return AllowAMDGPUUnsafeFPAtomics; }
 
   /// For ARM targets returns a mask defining which coprocessors are configured
   /// as Custom Datapath.
   uint32_t getARMCDECoprocMask() const { return ARMCDECoprocMask; }
 

clang/include/clang/Serialization/ASTBitCodes.h

#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
       PREDEF_TYPE_##Id##_ID,
 #include "clang/Basic/OpenCLExtensionTypes.def"
       // \brief SVE types with auto numeration
 #define SVE_TYPE(Name, Id, SingletonId) PREDEF_TYPE_##Id##_ID,
 #include "clang/Basic/AArch64SVEACLETypes.def"
       // \brief  PowerPC MMA types with auto numeration
 #define PPC_VECTOR_TYPE(Name, Id, Size) PREDEF_TYPE_##Id##_ID,
 #include "clang/Basic/PPCTypes.def"
+      // \brief RISC-V V types with auto numeration
+#define RVV_TYPE(Name, Id, SingletonId) PREDEF_TYPE_##Id##_ID,
+#include "clang/Basic/RISCVVTypes.def"
     };
 
     /// The number of predefined type IDs that are reserved for
     /// the PREDEF_TYPE_* constants.
     ///
     /// Type IDs for non-predefined types will start at
     /// NUM_PREDEF_TYPE_IDs.
-    const unsigned NUM_PREDEF_TYPE_IDS = 200;
+    const unsigned NUM_PREDEF_TYPE_IDS = 300;
 
     /// Record codes for each kind of type.
     ///
     /// These constants describe the type records that can occur within a
     /// block identified by DECLTYPES_BLOCK_ID in the AST file. Each
     /// constant describes a record for a specific type class in the
     /// AST. Note that DeclCode values share this code space.
     enum TypeCode {

clang/include/clang/module.modulemap

module Clang_Basic {
   textual header "Basic/MSP430Target.def"
   textual header "Basic/LangOptions.def"
   textual header "Basic/OpenCLExtensions.def"
   textual header "Basic/OpenCLImageTypes.def"
   textual header "Basic/OpenCLExtensionTypes.def"
   textual header "Basic/OpenMPKinds.def"
   textual header "Basic/OperatorKinds.def"
   textual header "Basic/PPCTypes.def"
+  textual header "Basic/RISCVVTypes.def"
   textual header "Basic/Sanitizers.def"
   textual header "Basic/TokenKinds.def"
   textual header "Basic/X86Target.def"
 
   module * { export * }
 }
 
 module Clang_CodeGen { requires cplusplus umbrella "CodeGen" module * { export * } }

clang/lib/AST/ASTContext.cpp

#define PPC_VECTOR_MMA_TYPE(Name, Id, Size) \
       InitBuiltinType(Id##Ty, BuiltinType::Id);
 #include "clang/Basic/PPCTypes.def"
     }
 #define PPC_VECTOR_VSX_TYPE(Name, Id, Size) \
     InitBuiltinType(Id##Ty, BuiltinType::Id);
 #include "clang/Basic/PPCTypes.def"
   }
 
+  if (Target.hasRISCVVTypes()) {
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  InitBuiltinType(SingletonId, BuiltinType::Id);
+#include "clang/Basic/RISCVVTypes.def"
+  }
+
   // Builtin type for __objc_yes and __objc_no
   ObjCBuiltinBoolTy = (Target.useSignedCharForObjCBool() ?
                        SignedCharTy : BoolTy);
 
   ObjCConstantStringType = QualType();
 
   ObjCSuperType = QualType();
 
case BuiltinType::Id:                                                        \
     break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size)                                        \
   case BuiltinType::Id:                                                        \
     Width = Size;                                                              \
     Align = Size;                                                              \
     break;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, NF, IsSigned,   \
+                        IsFP)                                                  \
+  case BuiltinType::Id:                                                        \
+    Width = 0;                                                                 \
+    Align = ElBits;                                                            \
+    break;
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, ElKind)                      \
+  case BuiltinType::Id:                                                        \
+    Width = 0;                                                                 \
+    Align = 8;                                                                 \
+    break;
+#include "clang/Basic/RISCVVTypes.def"
     }
     break;
   case Type::ObjCObjectPointer:
     Width = Target->getPointerWidth(0);
     Align = Target->getPointerAlign(0);
     break;
   case Type::BlockPointer:
     AS = getTargetAddressSpace(cast<BlockPointerType>(T)->getPointeeType());
#define SVE_ELTTY(ELTTY, ELTS, NUMVECTORS)                                     \
   case BuiltinType::SveBFloat16:
     return SVE_ELTTY(BFloat16Ty, 8, 1);
   case BuiltinType::SveBFloat16x2:
     return SVE_ELTTY(BFloat16Ty, 8, 2);
   case BuiltinType::SveBFloat16x3:
     return SVE_ELTTY(BFloat16Ty, 8, 3);
   case BuiltinType::SveBFloat16x4:
     return SVE_ELTTY(BFloat16Ty, 8, 4);
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,         \
+                            IsSigned)                                          \
+  case BuiltinType::Id:                                                        \
+    return {getIntTypeForBitwidth(ElBits, IsSigned),                           \
+            llvm::ElementCount::getScalable(NumEls), NF};
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)       \
+  case BuiltinType::Id:                                                        \
+    return {ElBits == 16 ? HalfTy : (ElBits == 32 ? FloatTy : DoubleTy),       \
+            llvm::ElementCount::getScalable(NumEls), NF};
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)                      \
+  case BuiltinType::Id:                                                        \
+    return {BoolTy, llvm::ElementCount::getScalable(NumEls), 1};
+#include "clang/Basic/RISCVVTypes.def"
   }
 }
 
 /// getScalableVectorType - Return the unique reference to a scalable vector
 /// type of the specified element type and size. VectorType must be a built-in
 /// type.
 QualType ASTContext::getScalableVectorType(QualType EltTy,
                                            unsigned NumElts) const {
if (!EltTy->isBooleanType() &&                                               \
         IsBF && !IsFP)) &&                                                     \
       EltTySize == ElBits && NumElts == NumEls) {                              \
     return SingletonId;                                                        \
   }
 #define SVE_PREDICATE_TYPE(Name, MangledName, Id, SingletonId, NumEls)         \
   if (EltTy->isBooleanType() && NumElts == NumEls)                             \
     return SingletonId;
 #include "clang/Basic/AArch64SVEACLETypes.def"
+  } else if (Target->hasRISCVVTypes()) {
+    uint64_t EltTySize = getTypeSize(EltTy);
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
+                        IsFP)                                                  \
+    if (!EltTy->isBooleanType() &&                                             \
+        ((EltTy->hasIntegerRepresentation() &&                                 \
+          EltTy->hasSignedIntegerRepresentation() == IsSigned) ||              \
+         (EltTy->hasFloatingRepresentation() && IsFP)) &&                      \
+        EltTySize == ElBits && NumElts == NumEls)                              \
+      return SingletonId;
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)                      \
+    if (EltTy->isBooleanType() && NumElts == NumEls)                           \
+      return SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
   }
   return QualType();
 }
 
 /// getVectorType - Return the unique reference to a vector type of
 /// the specified element type and size. VectorType must be a built-in type.
 QualType ASTContext::getVectorType(QualType vecType, unsigned NumElts,
                                    VectorType::VectorKind VecKind) const {
static char getObjCEncodingForPrimitiveType(const ASTContext *C,
     case BuiltinType::SatUFract:
     case BuiltinType::SatULongFract:
       // FIXME: potentially need @encodes for these!
       return ' ';
 
 #define SVE_TYPE(Name, Id, SingletonId) \
     case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
       {
         DiagnosticsEngine &Diags = C->getDiagnostics();
-      unsigned DiagID = Diags.getCustomDiagID(
-          DiagnosticsEngine::Error, "cannot yet @encode type %0");
+        unsigned DiagID = Diags.getCustomDiagID(DiagnosticsEngine::Error,
+                                                "cannot yet @encode type %0");
         Diags.Report(DiagID) << BT->getName(C->getPrintingPolicy());
         return ' ';
       }
 
     case BuiltinType::ObjCId:
     case BuiltinType::ObjCClass:
     case BuiltinType::ObjCSel:
       llvm_unreachable("@encoding ObjC primitive type");
 
     // OpenCL and placeholder types don't need @encodings.
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) \

clang/lib/AST/ASTImporter.cpp

 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id: \
     return Importer.getToContext().SingletonId;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id: \
     return Importer.getToContext().Id##Ty;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  case BuiltinType::Id:                                                        \
+    return Importer.getToContext().SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
 #define SHARED_SINGLETON_TYPE(Expansion)
 #define BUILTIN_TYPE(Id, SingletonId) \
   case BuiltinType::Id: return Importer.getToContext().SingletonId;
 #include "clang/AST/BuiltinTypes.def"
 
   // FIXME: for Char16, Char32, and NullPtr, make sure that the "to"
   // context supports C++.
 

clang/lib/AST/ExprConstant.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
     case BuiltinType::OCLQueue:
     case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) \
     case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
     case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
       return GCCTypeClass::None;
 
     case BuiltinType::Dependent:
       llvm_unreachable("unexpected dependent type");
     };
     llvm_unreachable("unexpected placeholder type");
 
   case Type::Enum:

clang/lib/AST/ItaniumMangle.cpp

case BuiltinType::Id:                                                        \
     break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id: \
     type_name = #Name; \
     Out << 'u' << type_name.size() << type_name; \
     break;
 #include "clang/Basic/PPCTypes.def"
+    // TODO: Check the mangling scheme for RISC-V V.
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  case BuiltinType::Id:                                                        \
+    type_name = Name;                                                          \
+    Out << 'u' << type_name.size() << type_name;                               \
+    break;
+#include "clang/Basic/RISCVVTypes.def"
   }
 }
 
 StringRef CXXNameMangler::getCallingConvQualifierName(CallingConv CC) {
   switch (CC) {
   case CC_C:
     return "";
 

clang/lib/AST/MicrosoftMangle.cpp

case BuiltinType::Half:
     break;
 
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
   case BuiltinType::ShortAccum:
   case BuiltinType::Accum:
   case BuiltinType::LongAccum:
   case BuiltinType::UShortAccum:
   case BuiltinType::UAccum:
   case BuiltinType::ULongAccum:
   case BuiltinType::ShortFract:
   case BuiltinType::Fract:

clang/lib/AST/NSAPI.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
   case BuiltinType::OCLQueue:
   case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
   case BuiltinType::BoundMember:
   case BuiltinType::Dependent:
   case BuiltinType::Overload:
   case BuiltinType::UnknownAny:
   case BuiltinType::ARCUnbridgedCast:
   case BuiltinType::Half:
   case BuiltinType::PseudoObject:
   case BuiltinType::BuiltinFn:

clang/lib/AST/PrintfFormatString.cpp

#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
   case BuiltinType::Id:
 #include "clang/Basic/OpenCLExtensionTypes.def"
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define SIGNED_TYPE(Id, SingletonId)
 #define UNSIGNED_TYPE(Id, SingletonId)
 #define FLOATING_TYPE(Id, SingletonId)
 #define BUILTIN_TYPE(Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/AST/BuiltinTypes.def"
     // Misc other stuff which doesn't make sense here.
     return false;

clang/lib/AST/Type.cpp

 }
 
 bool Type::isSizelessBuiltinType() const {
   if (const BuiltinType *BT = getAs<BuiltinType>()) {
     switch (BT->getKind()) {
       // SVE Types
 #define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
       return true;
     default:
       return false;
     }
   }
   return false;
 }
 

 #define SVE_TYPE(Name, Id, SingletonId) \
   case Id: \
     return Name;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case Id: \
     return #Name;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  case Id:                                                                     \
+    return Name;
+#include "clang/Basic/RISCVVTypes.def"
   }
 
   llvm_unreachable("Invalid builtin type.");
 }
 
 QualType QualType::getNonPackExpansionType() const {
   // We never wrap type sugar around a PackExpansionType.
   if (auto *PET = dyn_cast<PackExpansionType>(getTypePtr()))
#include "clang/Basic/OpenCLExtensionTypes.def"
     case BuiltinType::OCLQueue:
     case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) \
     case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
     case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
     case BuiltinType::BuiltinFn:
     case BuiltinType::NullPtr:
     case BuiltinType::IncompleteMatrixIdx:
     case BuiltinType::OMPArraySection:
     case BuiltinType::OMPArrayShaping:
     case BuiltinType::OMPIterator:
       return false;
     }

clang/lib/AST/TypeLoc.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
   case BuiltinType::OCLQueue:
   case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
   case BuiltinType::BuiltinFn:
   case BuiltinType::IncompleteMatrixIdx:
   case BuiltinType::OMPArraySection:
   case BuiltinType::OMPArrayShaping:
   case BuiltinType::OMPIterator:
     return TST_unspecified;
   }
 

clang/lib/Basic/TargetInfo.cpp

TargetInfo::TargetInfo(const llvm::Triple &T) : TargetOpts(), Triple(T) {
   Float128Format = &llvm::APFloat::IEEEquad();
   MCountName = "mcount";
   RegParmMax = 0;
   SSERegParmMax = 0;
   HasAlignMac68kSupport = false;
   HasBuiltinMSVaList = false;
   IsRenderScriptTarget = false;
   HasAArch64SVETypes = false;
+  HasRISCVVTypes = false;
   AllowAMDGPUUnsafeFPAtomics = false;
   ARMCDECoprocMask = 0;
 
   // Default to no types using fpret.
   RealTypeUsesObjCFPRet = 0;
 
   // Default to not using fp2ret for __Complex long double
   ComplexLongDoubleUsesFP2Ret = false;

clang/lib/Basic/Targets/RISCV.h

public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
     SuitableAlign = 128;
     WCharType = SignedInt;
     WIntType = UnsignedInt;
+    HasRISCVVTypes = true;
   }
 
   bool setCPU(const std::string &Name) override {
     if (!isValidCPUName(Name))
       return false;
     CPU = Name;
     return true;
   }

clang/lib/CodeGen/CGDebugInfo.cpp

#include "clang/Basic/AArch64SVEACLETypes.def"
     }
   // It doesn't make sense to generate debug info for PowerPC MMA vector types.
   // So we return a safe type here to avoid generating an error.
 #define PPC_VECTOR_TYPE(Name, Id, size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
     return CreateType(cast<const BuiltinType>(CGM.getContext().IntTy));
 
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
+    {
+      ASTContext::BuiltinVectorTypeInfo Info =
+          CGM.getContext().getBuiltinVectorTypeInfo(BT);
+
+      unsigned ElementCount = Info.EC.getKnownMinValue();
+      unsigned SEW = CGM.getContext().getTypeSize(Info.ElementType);
+
+      bool Fractional = false;
+      unsigned LMUL;
+      unsigned FixedSize = ElementCount * SEW;
+      if (Info.ElementType == CGM.getContext().BoolTy) {
+        // Mask type only occupies one vector register.
+        LMUL = 1;
+      } else if (FixedSize < 64) {
+        // In RVV scalable vector types, we encode 64 bits in the fixed part.
+        Fractional = true;
+        LMUL = 64 / FixedSize;
+      } else {
+        LMUL = FixedSize / 64;
+      }
+
+      // Element count = (VLENB / SEW) x LMUL
+      SmallVector<int64_t, 9> Expr(
+          // The DW_OP_bregx operation has two operands: a register which is
+          // specified by an unsigned LEB128 number, followed by a signed LEB128
+          // offset.
+          {llvm::dwarf::DW_OP_bregx, // Read the contents of a register.
+           4096 + 0xC22,             // RISC-V VLENB CSR register.
+           0, // Offset for DW_OP_bregx. It is dummy here.
+           llvm::dwarf::DW_OP_constu,
+           SEW / 8, // SEW is in bits.
+           llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL});
+      if (Fractional)
+        Expr.push_back(llvm::dwarf::DW_OP_div);
+      else
+        Expr.push_back(llvm::dwarf::DW_OP_mul);
+
+      auto *LowerBound =
+          llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
+              llvm::Type::getInt64Ty(CGM.getLLVMContext()), 0));
+      auto *UpperBound = DBuilder.createExpression(Expr);
+      llvm::Metadata *Subscript = DBuilder.getOrCreateSubrange(
+          /*count*/ nullptr, LowerBound, UpperBound, /*stride*/ nullptr);
+      llvm::DINodeArray SubscriptArray = DBuilder.getOrCreateArray(Subscript);
+      llvm::DIType *ElemTy =
+          getOrCreateType(Info.ElementType, TheCU->getFile());
+
+      auto Align = getTypeAlignIfRequired(BT, CGM.getContext());
+      return DBuilder.createVectorType(/*Size=*/0, Align, ElemTy,
+                                       SubscriptArray);
+    }
   case BuiltinType::UChar:
   case BuiltinType::Char_U:
     Encoding = llvm::dwarf::DW_ATE_unsigned_char;
     break;
   case BuiltinType::Char_S:
   case BuiltinType::SChar:
     Encoding = llvm::dwarf::DW_ATE_signed_char;
     break;

clang/lib/CodeGen/CodeGenTypes.cpp

case BuiltinType::SveBFloat16x4: {
                                                Info.NumVectors);
     }
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
     case BuiltinType::Id: \
       ResultType = \
         llvm::FixedVectorType::get(ConvertType(Context.BoolTy), Size); \
       break;
 #include "clang/Basic/PPCTypes.def"
-    case BuiltinType::Dependent:
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
+    {
+      ASTContext::BuiltinVectorTypeInfo Info =
+          Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(Ty));
+      return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
+                                           Info.EC.getKnownMinValue() *
+                                           Info.NumVectors);
+    }
 #define BUILTIN_TYPE(Id, SingletonId)
 #define PLACEHOLDER_TYPE(Id, SingletonId) \
     case BuiltinType::Id:
 #include "clang/AST/BuiltinTypes.def"
       llvm_unreachable("Unexpected placeholder builtin type!");
     }
     break;
   }

clang/lib/CodeGen/ItaniumCXXABI.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
     case BuiltinType::OCLQueue:
     case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) \
     case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
     case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
     case BuiltinType::ShortAccum:
     case BuiltinType::Accum:
     case BuiltinType::LongAccum:
     case BuiltinType::UShortAccum:
     case BuiltinType::UAccum:
     case BuiltinType::ULongAccum:
     case BuiltinType::ShortFract:
     case BuiltinType::Fract:

clang/lib/Index/USRGeneration.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
         case BuiltinType::OCLReserveID:
         case BuiltinType::OCLSampler:
 #define SVE_TYPE(Name, Id, SingletonId) \
         case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
         case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
         case BuiltinType::ShortAccum:
         case BuiltinType::Accum:
         case BuiltinType::LongAccum:
         case BuiltinType::UShortAccum:
         case BuiltinType::UAccum:
         case BuiltinType::ULongAccum:
         case BuiltinType::ShortFract:
         case BuiltinType::Fract:

clang/lib/Sema/Sema.cpp

#define PPC_VECTOR_MMA_TYPE(Name, Id, Size) \
       addImplicitTypedef(#Name, Context.Id##Ty);
 #include "clang/Basic/PPCTypes.def"
     }
 #define PPC_VECTOR_VSX_TYPE(Name, Id, Size) \
     addImplicitTypedef(#Name, Context.Id##Ty);
 #include "clang/Basic/PPCTypes.def"
   }
 
+  if (Context.getTargetInfo().hasRISCVVTypes()) {
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  addImplicitTypedef(Name, Context.SingletonId);
+#include "clang/Basic/RISCVVTypes.def"
+  }
+
   if (Context.getTargetInfo().hasBuiltinMSVaList()) {
     DeclarationName MSVaList = &Context.Idents.get("__builtin_ms_va_list");
     if (IdResolver.begin(MSVaList) == IdResolver.end())
       PushOnScopeChains(Context.getBuiltinMSVaListDecl(), TUScope);
   }
 
   DeclarationName BuiltinVaList = &Context.Idents.get("__builtin_va_list");
   if (IdResolver.begin(BuiltinVaList) == IdResolver.end())

clang/lib/Sema/SemaExpr.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
   // In practice we'll never use this, since all SVE types are sugared
   // via TypedefTypes rather than exposed directly as BuiltinTypes.
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define PLACEHOLDER_TYPE(ID, SINGLETON_ID)
 #define BUILTIN_TYPE(ID, SINGLETON_ID) case BuiltinType::ID:
 #include "clang/AST/BuiltinTypes.def"
     return false;
 
   // We cannot lower out overload sets; they might validly be resolved
   // by the call machinery.
   case BuiltinType::Overload:
#define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \
   case BuiltinType::Id:
 #include "clang/Basic/OpenCLExtensionTypes.def"
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define PLACEHOLDER_TYPE(Id, SingletonId)
 #include "clang/AST/BuiltinTypes.def"
     break;
   }
 
   llvm_unreachable("invalid placeholder type!");
 }

clang/lib/Serialization/ASTCommon.cpp

case BuiltinType::Id: \
     ID = PREDEF_TYPE_##Id##_ID; \
     break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
   case BuiltinType::Id: \
     ID = PREDEF_TYPE_##Id##_ID; \
     break;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId)                                        \
+  case BuiltinType::Id:                                                        \
+    ID = PREDEF_TYPE_##Id##_ID;                                                \
+    break;
+#include "clang/Basic/RISCVVTypes.def"
   case BuiltinType::BuiltinFn:
     ID = PREDEF_TYPE_BUILTIN_FN;
     break;
   case BuiltinType::IncompleteMatrixIdx:
     ID = PREDEF_TYPE_INCOMPLETE_MATRIX_IDX;
     break;
   case BuiltinType::OMPArraySection:
     ID = PREDEF_TYPE_OMP_ARRAY_SECTION;

clang/lib/Serialization/ASTReader.cpp

case PREDEF_TYPE_##Id##_ID: \
       T = Context.SingletonId; \
       break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) \
     case PREDEF_TYPE_##Id##_ID: \
       T = Context.Id##Ty; \
       break;
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+    case PREDEF_TYPE_##Id##_ID: \
+      T = Context.SingletonId; \
+      break;
+#include "clang/Basic/RISCVVTypes.def"
     }
 
     assert(!T.isNull() && "Unknown predefined type");
     return T.withFastQualifiers(FastQuals);
   }
 
   Index -= NUM_PREDEF_TYPE_IDS;
   assert(Index < TypesLoaded.size() && "Type index out-of-range");

clang/test/CodeGen/RISCV/riscv-v-debuginfo.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \
+// RUN:   | FileCheck --check-prefix=DEBUGINFO %s
+#include <stdint.h>
+
+__rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) {
+  __rvv_int16m2_t ret;
+  return ret;
+}
+
+// !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+
+__rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) {
+  __rvv_int16mf2_t ret;
+  return ret;
+}
+
+// !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+
+__rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) {
+  __rvv_int32mf2_t ret;
+  return ret;
+}
+
+// !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))

clang/test/Sema/riscv-types.c

+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN:    | FileCheck %s
+
+void bar(void) {
+  // CHECK: __rvv_int64m1_t x0;
+  __rvv_int64m1_t x0;
+
+  // CHECK: __rvv_float64m1_t x1;
+  __rvv_float64m1_t x1;
+
+  // CHECK: __rvv_int64m2_t x2;
+  __rvv_int64m2_t x2;
+
+  // CHECK: __rvv_float64m2_t x3;
+  __rvv_float64m2_t x3;
+
+  // CHECK: __rvv_int64m4_t x4;
+  __rvv_int64m4_t x4;
+
+  // CHECK: __rvv_float64m4_t x5;
+  __rvv_float64m4_t x5;
+
+  // CHECK: __rvv_int64m8_t x6;
+  __rvv_int64m8_t x6;
+
+  // CHECK: __rvv_float64m8_t x7;
+  __rvv_float64m8_t x7;
+
+  // CHECK: __rvv_int32m1_t x8;
+  __rvv_int32m1_t x8;
+
+  // CHECK: __rvv_float32m1_t x9;
+  __rvv_float32m1_t x9;
+
+  // CHECK: __rvv_int32m2_t x10;
+  __rvv_int32m2_t x10;
+
+  // CHECK: __rvv_float32m2_t x11;
+  __rvv_float32m2_t x11;
+
+  // CHECK: __rvv_int32m4_t x12;
+  __rvv_int32m4_t x12;
+
+  // CHECK: __rvv_float32m4_t x13;
+  __rvv_float32m4_t x13;
+
+  // CHECK: __rvv_int32m8_t x14;
+  __rvv_int32m8_t x14;
+
+  // CHECK: __rvv_float32m8_t x15;
+  __rvv_float32m8_t x15;
+
+  // CHECK: __rvv_int16m1_t x16;
+  __rvv_int16m1_t x16;
+
+  // CHECK: __rvv_float16m1_t x17;
+  __rvv_float16m1_t x17;
+
+  // CHECK: __rvv_int16m2_t x18;
+  __rvv_int16m2_t x18;
+
+  // CHECK: __rvv_float16m2_t x19;
+  __rvv_float16m2_t x19;
+
+  // CHECK: __rvv_int16m4_t x20;
+  __rvv_int16m4_t x20;
+
+  // CHECK: __rvv_float16m4_t x21;
+  __rvv_float16m4_t x21;
+
+  // CHECK: __rvv_int16m8_t x22;
+  __rvv_int16m8_t x22;
+
+  // CHECK: __rvv_float16m8_t x23;
+  __rvv_float16m8_t x23;
+
+  // CHECK: __rvv_int8m1_t x24;
+  __rvv_int8m1_t x24;
+
+  // CHECK: __rvv_int8m2_t x25;
+  __rvv_int8m2_t x25;
+
+  // CHECK: __rvv_int8m4_t x26;
+  __rvv_int8m4_t x26;
+
+  // CHECK: __rvv_int8m8_t x27;
+  __rvv_int8m8_t x27;
+
+  // CHECK: __rvv_bool64_t x28;
+  __rvv_bool64_t x28;
+
+  // CHECK: __rvv_bool32_t x29;
+  __rvv_bool32_t x29;
+
+  // CHECK: __rvv_bool16_t x30;
+  __rvv_bool16_t x30;
+
+  // CHECK: __rvv_bool8_t x31;
+  __rvv_bool8_t x31;
+
+  // CHECK: __rvv_bool8_t x32;
+  __rvv_bool8_t x32;
+
+  // CHECK: __rvv_bool8_t x33;
+  __rvv_bool8_t x33;
+
+  // CHECK: __rvv_bool8_t x34;
+  __rvv_bool8_t x34;
+
+  // CHECK: __rvv_int32mf2_t x35;
+  __rvv_int32mf2_t x35;
+
+  // CHECK: __rvv_float32mf2_t x36;
+  __rvv_float32mf2_t x36;
+
+  // CHECK: __rvv_int16mf4_t x37;
+  __rvv_int16mf4_t x37;
+
+  // CHECK: __rvv_float16mf4_t x38;
+  __rvv_float16mf4_t x38;
+
+  // CHECK: __rvv_int16mf2_t x39;
+  __rvv_int16mf2_t x39;
+
+  // CHECK: __rvv_float16mf2_t x40;
+  __rvv_float16mf2_t x40;
+
+  // CHECK: __rvv_int8mf8_t x41;
+  __rvv_int8mf8_t x41;
+
+  // CHECK: __rvv_int8mf4_t x42;
+  __rvv_int8mf4_t x42;
+
+  // CHECK: __rvv_int8mf2_t x43;
+  __rvv_int8mf2_t x43;
+}

clang/tools/libclang/CIndex.cpp

#include "clang/Basic/OpenCLExtensionTypes.def"
   case BuiltinType::OCLEvent:
   case BuiltinType::OCLClkEvent:
   case BuiltinType::OCLQueue:
   case BuiltinType::OCLReserveID:
 #define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
 #include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
 #define BUILTIN_TYPE(Id, SingletonId)
 #define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define FLOATING_TYPE(Id, SingletonId) case BuiltinType::Id:
 #define PLACEHOLDER_TYPE(Id, SingletonId) case BuiltinType::Id:
 #include "clang/AST/BuiltinTypes.def"
     break;