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- User Since
- Sep 17 2020, 7:09 AM (157 w, 2 d)
Wed, Sep 13
If we don't consider inverting the zero_extend placement, it seems that we can also combine on MGATHER. I'll update patch later. Thanks.
Thu, Sep 7
- Rebase.
- Update RISCVISAInfoTest.cpp
Fri, Sep 1
Another solution, enabling the isExtractVecEltCheap when XlenVT == vector_element_type, It's working for pr65068.ll.
Wed, Aug 30
Okay, making sure it's back-end introduced looks like it can be optimized. thanks
I have a question, this ir has been optimized in the opt phase. https://godbolt.org/z/MPvvTG5dT Maybe we don't need another combine in codegen?
Mon, Aug 28
Address comments from Jim, thanks.
Sun, Aug 27
- core-v -> CORE-V to be consistent with other places
- rebase
Fri, Aug 25
address comments, thanks.
Thu, Aug 24
Rebase. Thanks for review.
Address comments, thanks.
Sorry for the late update.
Aug 17 2023
Aug 14 2023
Jul 24 2023
Jul 18 2023
Jul 17 2023
1.skip creating the non-VP node this node if it's a VPOpcode
2.use DAG.getVPZExtOrTrunc
3.rebase
Thanks
Jul 12 2023
Jul 7 2023
Jul 4 2023
Jun 29 2023
Jun 28 2023
I don't find a better way to implement it, I'll create new patch if I have a better idea, thanks for the review.
This patch relies on the D153934.
Otherwise, I tried another method:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ef9e96b6cca4..9a46455017c6 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13020,7 +13020,7 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
Add testcase for riscv.
The testcase is copied from instcombine.
Without this patch:
https://godbolt.org/z/M1nxxf163
Jun 27 2023
Jun 22 2023
address comments, thanks
Jun 19 2023
updated
- Add Verifier.cpp to make sure only legal bits are set.
- Add more testcase
- address more comments
thanks
Jun 16 2023
address comments, use APInt methods, thanks.
Jun 15 2023
- change name to: vp.is.fpclass
- update docs/LangRef.rst, add `llvm.vp.is.fpclass.*`' Intrinsics
Rebase and remove two temporary variables, clearer now.
Jun 14 2023
Jun 6 2023
After I changed it correctly and found that this patch is not needed anymore, thanks for review.
Jun 5 2023
revert the last commit.
[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))
revert the last commit.sorry
[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))
Update, add hasOneUse()
May 31 2023
May 30 2023
Address comments. Thanks.
Using xor to replace setcc.
A DAGCombine patch may be needed here. I can send a new patch.
Deleted two ZERO_EXTEND.
The second ZERO_EXTEND should not be needed either. Setcc and zext are all XLenVT.
If the select true/false are 1.0 and 0.0 we can replace the select with a sint_to_fp.
(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
thanks
May 25 2023
May 24 2023
Reuse RISCVISD::FPCLASS_VL
change the value name to VMSNE
- support scalable vector
- add more testcases
May 23 2023
Thanks Jessica and Craig.
Update try to address comments.
Use AND and SETNE.
Update test case.
May 22 2023
clang-format
May 6 2023
May 5 2023
Here, it looks like there is
let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in def PseudoRV32ZdinxLD : Pseudo<(outs GPRPF64:$dst), (ins GPR:$rs1, simm12:$imm12), []>; defm : LdPat<load, PseudoRV32ZdinxLD, f64>;
Maybe we shouldn't expand the Pseudo in RISCVExpandPseudoInsts.cpp.
It seems that one more MI would get the following error.
llc: /home/liaochunyu/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:83: virtual bool (anonymous namespace)::RISCVExpandPseudo::runOnMachineFunction(llvm::MachineFunction &): Assertion `OldSize >= NewSize' failed.
Maybe we should learn from jrtc27's reference https://github.com/CTSRD-CHERI/llvm-project/pull/635/files
May 4 2023
Apr 27 2023
Apr 25 2023
isnotfinite_fpclasee -> isnotfinite_fpclass
Re-update, I don't know why I didn't modify it correctly just now
update