Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

liaolucy ( Liao Chunyu)
User

Projects

User does not belong to any projects.

User Details

User Since
Sep 17 2020, 7:09 AM (157 w, 2 d)

Recent Activity

Wed, Sep 13

liaolucy added a comment to D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).

If we don't consider inverting the zero_extend placement, it seems that we can also combine on MGATHER. I'll update patch later. Thanks.

Wed, Sep 13, 7:59 AM · Restricted Project, Restricted Project
liaolucy added a comment to D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).

I want to suggest a different approach here. I think this should be a combine on MGATHER (and variants), not a combine on the RISCV specific nodes. It might make sense to have this be a target specific combine, but I don't think it needs to be a combine on custom nodes.

Looking at one of your tests, I see this state immediately before lowering:

    t15: v8i64 = zero_extend t6
    t17: v8i64 = BUILD_VECTOR Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>
  t18: v8i64 = shl t15, t17
t27: v8i16,ch = masked_gather<(load unknown-size, align 2), signed unscaled offset> t0, t12, t9, t2, t18, TargetConstant:i64<1>

The MGATHER node supports scaled offsets, and allows the index type to differ from the native type (i.e. there's implicit extend on the operand). The later seems like it's the right tool here. See refineIndexType in DAGCombine for an example of some code which is related. Basically, we're just inverting the zero_extend placement, and then running that transform. We might even be able to do this in fully generic code.

Wed, Sep 13, 7:03 AM · Restricted Project, Restricted Project

Thu, Sep 7

liaolucy updated the diff for D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.
  1. Rebase.
  2. Update RISCVISAInfoTest.cpp
Thu, Sep 7, 7:44 PM · Restricted Project, Restricted Project, Restricted Project

Fri, Sep 1

liaolucy added a comment to D159190: [RISCV]Combine to make the fixed vector vadd of splats are scalarized.

Another solution, enabling the isExtractVecEltCheap when XlenVT == vector_element_type, It's working for pr65068.ll.

Fri, Sep 1, 6:04 AM · Restricted Project, Restricted Project

Wed, Aug 30

liaolucy added a comment to D159190: [RISCV]Combine to make the fixed vector vadd of splats are scalarized.

Thanks for the patch. Did you take a look at scalarizeBinOpOfSplats in DAGCombiner? I think that might be more generic, it's the combine that kicks in for the scalable vector test case in that issue. I was wondering if it would be possible to get it to work on fixed vectors too.

I have a question, this ir has been optimized in the opt phase. https://godbolt.org/z/MPvvTG5dT Maybe we don't need another combine in codegen?

Good point, I didn't realise opt already took care of this. I guess it depends if this pattern is introduced during codegen at all

I originally noticed this when looking at the code generated whilst expanding ISD::ROT{L,R}, e.g. https://godbolt.org/z/Wh99EPbja
So it can be introduced after the middle-end (but it might not be that common)

Okay, making sure it's back-end introduced looks like it can be optimized. thanks

Wed, Aug 30, 6:01 PM · Restricted Project, Restricted Project
liaolucy added a comment to D159190: [RISCV]Combine to make the fixed vector vadd of splats are scalarized.

Thanks for the patch. Did you take a look at scalarizeBinOpOfSplats in DAGCombiner? I think that might be more generic, it's the combine that kicks in for the scalable vector test case in that issue. I was wondering if it would be possible to get it to work on fixed vectors too.

I have a question, this ir has been optimized in the opt phase. https://godbolt.org/z/MPvvTG5dT Maybe we don't need another combine in codegen?

Wed, Aug 30, 6:57 AM · Restricted Project, Restricted Project
liaolucy requested review of D159190: [RISCV]Combine to make the fixed vector vadd of splats are scalarized.
Wed, Aug 30, 6:00 AM · Restricted Project, Restricted Project

Mon, Aug 28

liaolucy updated the diff for D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.

Address comments from Jim, thanks.

Mon, Aug 28, 6:30 AM · Restricted Project, Restricted Project, Restricted Project

Sun, Aug 27

liaolucy updated the summary of D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.
Sun, Aug 27, 6:14 PM · Restricted Project, Restricted Project, Restricted Project
liaolucy updated the diff for D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.
  1. core-v -> CORE-V to be consistent with other places
  2. rebase
Sun, Aug 27, 6:11 PM · Restricted Project, Restricted Project, Restricted Project

Fri, Aug 25

liaolucy updated the diff for D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.

address comments, thanks.

Fri, Aug 25, 6:48 AM · Restricted Project, Restricted Project, Restricted Project
liaolucy requested review of D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions.
Fri, Aug 25, 1:29 AM · Restricted Project, Restricted Project, Restricted Project
liaolucy committed rG1b12427c0133: [VP][RISCV] Add vp.is.fpclass and RISC-V support (authored by liaolucy).
[VP][RISCV] Add vp.is.fpclass and RISC-V support
Fri, Aug 25, 12:41 AM · Restricted Project, Restricted Project
liaolucy closed D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.
Fri, Aug 25, 12:41 AM · Restricted Project, Restricted Project

Thu, Aug 24

liaolucy updated the diff for D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.

Rebase. Thanks for review.

Thu, Aug 24, 11:59 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).
Thu, Aug 24, 9:10 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).

Address comments, thanks.
Sorry for the late update.

Thu, Aug 24, 9:10 PM · Restricted Project, Restricted Project

Aug 17 2023

liaolucy added inline comments to D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).
Aug 17 2023, 6:32 AM · Restricted Project, Restricted Project
liaolucy requested review of D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C).
Aug 17 2023, 3:08 AM · Restricted Project, Restricted Project

Aug 14 2023

liaolucy added inline comments to D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers.
Aug 14 2023, 3:58 AM · Restricted Project, Restricted Project

Jul 24 2023

liaolucy committed rG620e61c5181d: [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv (authored by liaolucy).
[RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv
Jul 24 2023, 11:21 PM · Restricted Project, Restricted Project
liaolucy closed D155466: [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv.
Jul 24 2023, 11:21 PM · Restricted Project, Restricted Project
liaolucy retitled D155466: [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv from [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra/vnsrl. to [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv.
Jul 24 2023, 7:59 AM · Restricted Project, Restricted Project

Jul 18 2023

liaolucy committed rG65ffcc099c7f: [RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP… (authored by liaolucy).
[RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP…
Jul 18 2023, 12:26 AM · Restricted Project, Restricted Project
liaolucy closed D155150: [RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP and extracting the exponent..
Jul 18 2023, 12:26 AM · Restricted Project, Restricted Project

Jul 17 2023

liaolucy updated the diff for D155150: [RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP and extracting the exponent..

1.skip creating the non-VP node this node if it's a VPOpcode
2.use DAG.getVPZExtOrTrunc
3.rebase
Thanks

Jul 17 2023, 9:50 PM · Restricted Project, Restricted Project
liaolucy requested review of D155466: [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv.
Jul 17 2023, 7:27 AM · Restricted Project, Restricted Project

Jul 12 2023

liaolucy requested review of D155150: [RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP and extracting the exponent..
Jul 12 2023, 8:59 PM · Restricted Project, Restricted Project

Jul 7 2023

liaolucy committed rG1575063db259: [RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl (authored by liaolucy).
[RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl
Jul 7 2023, 5:03 PM · Restricted Project, Restricted Project
liaolucy closed D154726: [RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl.
Jul 7 2023, 5:03 PM · Restricted Project, Restricted Project
liaolucy requested review of D154726: [RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl.
Jul 7 2023, 9:26 AM · Restricted Project, Restricted Project

Jul 4 2023

liaolucy added inline comments to D153748: [RISCV] Add support for XCValu extension in CV32E40P.
Jul 4 2023, 2:21 AM · Restricted Project, Restricted Project

Jun 29 2023

liaolucy added inline comments to D153934: [SelectionDAG][TargetLowering]Add support for nuw/nsw on KnownBits::shl.
Jun 29 2023, 6:34 PM · Restricted Project, Restricted Project

Jun 28 2023

liaolucy abandoned D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg).

I don't find a better way to implement it, I'll create new patch if I have a better idea, thanks for the review.

Jun 28 2023, 8:36 AM · Restricted Project, Restricted Project
liaolucy added a comment to D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg).

This patch relies on the D153934.
Otherwise, I tried another method:

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ef9e96b6cca4..9a46455017c6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13020,7 +13020,7 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
Jun 28 2023, 1:21 AM · Restricted Project, Restricted Project
liaolucy added reviewers for D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg): craig.topper, reames.
Jun 28 2023, 1:20 AM · Restricted Project, Restricted Project
liaolucy retitled D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg) from RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg) to [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg).
Jun 28 2023, 1:00 AM · Restricted Project, Restricted Project
liaolucy requested review of D153947: [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, neg).
Jun 28 2023, 12:59 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D153934: [SelectionDAG][TargetLowering]Add support for nuw/nsw on KnownBits::shl.

Add testcase for riscv.
The testcase is copied from instcombine.
Without this patch:
https://godbolt.org/z/M1nxxf163

Jun 28 2023, 12:54 AM · Restricted Project, Restricted Project

Jun 27 2023

liaolucy requested review of D153934: [SelectionDAG][TargetLowering]Add support for nuw/nsw on KnownBits::shl.
Jun 27 2023, 8:06 PM · Restricted Project, Restricted Project

Jun 22 2023

liaolucy updated the diff for D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.

address comments, thanks

Jun 22 2023, 8:03 AM · Restricted Project, Restricted Project

Jun 19 2023

liaolucy added inline comments to D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.
Jun 19 2023, 7:18 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.
Jun 19 2023, 7:35 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.

updated

  1. Add Verifier.cpp to make sure only legal bits are set.
  2. Add more testcase
  3. address more comments

thanks

Jun 19 2023, 7:35 AM · Restricted Project, Restricted Project

Jun 16 2023

liaolucy committed rG12fee611ca53: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y… (authored by liaolucy).
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y…
Jun 16 2023, 7:10 PM · Restricted Project, Restricted Project
liaolucy closed D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).
Jun 16 2023, 7:10 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

address comments, use APInt methods, thanks.

Jun 16 2023, 7:54 AM · Restricted Project, Restricted Project

Jun 15 2023

liaolucy updated the diff for D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.
  1. change name to: vp.is.fpclass
  2. update docs/LangRef.rst, add `llvm.vp.is.fpclass.*`' Intrinsics
Jun 15 2023, 6:54 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

Rebase and remove two temporary variables, clearer now.

Jun 15 2023, 12:35 AM · Restricted Project, Restricted Project

Jun 14 2023

liaolucy requested review of D152993: [VP][RISCV] Add vp.is.fpclass and RISC-V support.
Jun 14 2023, 11:45 PM · Restricted Project, Restricted Project

Jun 6 2023

liaolucy abandoned D152223: [RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)).

After I changed it correctly and found that this patch is not needed anymore, thanks for review.

Jun 6 2023, 12:35 AM · Restricted Project, Restricted Project

Jun 5 2023

liaolucy added inline comments to D152223: [RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)).
Jun 5 2023, 8:55 PM · Restricted Project, Restricted Project
liaolucy requested review of D152223: [RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)).
Jun 5 2023, 8:52 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

revert the last commit.

Jun 5 2023, 2:38 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

Jun 5 2023, 2:14 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

revert the last commit.sorry

Jun 5 2023, 2:11 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

Jun 5 2023, 2:06 AM · Restricted Project, Restricted Project
liaolucy updated the diff for D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).

Update, add hasOneUse()

Jun 5 2023, 1:41 AM · Restricted Project, Restricted Project
liaolucy requested review of D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt).
Jun 5 2023, 1:22 AM · Restricted Project, Restricted Project

May 31 2023

liaolucy committed rG548fa1d3086f: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT (authored by liaolucy).
[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT
May 31 2023, 12:21 AM · Restricted Project, Restricted Project
liaolucy closed D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.
May 31 2023, 12:21 AM · Restricted Project, Restricted Project

May 30 2023

liaolucy updated the diff for D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.

Address comments. Thanks.

May 30 2023, 10:47 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.

Using xor to replace setcc.
A DAGCombine patch may be needed here. I can send a new patch.

May 30 2023, 10:28 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.
May 30 2023, 9:42 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.
May 30 2023, 9:37 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.

Deleted two ZERO_EXTEND.
The second ZERO_EXTEND should not be needed either. Setcc and zext are all XLenVT.

May 30 2023, 8:36 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.

If the select true/false are 1.0 and 0.0 we can replace the select with a sint_to_fp.
(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
thanks

May 30 2023, 8:17 PM · Restricted Project, Restricted Project
liaolucy retitled D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT from Add special case for (select_cc 0, x, setlt, 0.0, 1.0) to lowerSELECT to [RISCV] Add special case for (select_cc 0, x, setlt, 0.0, 1.0) to lowerSELECT.
May 30 2023, 8:30 AM · Restricted Project, Restricted Project
liaolucy requested review of D151719: [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT.
May 30 2023, 8:29 AM · Restricted Project, Restricted Project

May 25 2023

liaolucy committed rG477d1080cb30: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v (authored by liaolucy).
[RISCV] Custom lower vector llvm.is.fpclass to vfclass.v
May 25 2023, 11:45 PM · Restricted Project, Restricted Project
liaolucy closed D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.
May 25 2023, 11:44 PM · Restricted Project, Restricted Project

May 24 2023

liaolucy updated the diff for D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.

Reuse RISCVISD::FPCLASS_VL
change the value name to VMSNE

May 24 2023, 11:45 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.
  1. support scalable vector
  2. add more testcases
May 24 2023, 7:46 PM · Restricted Project, Restricted Project
liaolucy abandoned D121199: [RISCV] Don't enable loop vectorizer interleaving if the V extension is scalable.
May 24 2023, 5:55 AM · Restricted Project, Restricted Project
liaolucy abandoned D126060: [RISCV] Add basic cost modelling for fixed length vector arithmetic.
May 24 2023, 5:54 AM · Restricted Project, Restricted Project
liaolucy abandoned D151180: [RISCV] select(C0, x, select(C1, x, y)) -> select(C0|C1, x, y).
May 24 2023, 5:53 AM · Restricted Project, Restricted Project

May 23 2023

liaolucy added a comment to D151180: [RISCV] select(C0, x, select(C1, x, y)) -> select(C0|C1, x, y).

Thanks Jessica and Craig.

May 23 2023, 8:46 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.
May 23 2023, 7:28 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.

Update try to address comments.
Use AND and SETNE.
Update test case.

May 23 2023, 7:27 PM · Restricted Project, Restricted Project

May 22 2023

liaolucy updated the summary of D151180: [RISCV] select(C0, x, select(C1, x, y)) -> select(C0|C1, x, y).
May 22 2023, 11:31 PM · Restricted Project, Restricted Project
liaolucy requested review of D151180: [RISCV] select(C0, x, select(C1, x, y)) -> select(C0|C1, x, y).
May 22 2023, 11:31 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.

clang-format

May 22 2023, 8:18 PM · Restricted Project, Restricted Project
liaolucy requested review of D151176: [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v.
May 22 2023, 8:13 PM · Restricted Project, Restricted Project

May 6 2023

liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 6 2023, 5:28 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 6 2023, 12:57 AM · Restricted Project, Restricted Project

May 5 2023

liaolucy added a comment to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.

Maybe we shouldn't expand the Pseudo in RISCVExpandPseudoInsts.cpp.
It seems that one more MI would get the following error.

llc: /home/liaochunyu/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:83: virtual bool (anonymous namespace)::RISCVExpandPseudo::runOnMachineFunction(llvm::MachineFunction &): Assertion `OldSize >= NewSize' failed.

That error means you're missing a let Size = 8 on the pseudo in tablegen.

Maybe I don’t know you meant by one more MI

May 5 2023, 8:31 PM · Restricted Project, Restricted Project
liaolucy added a comment to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.

Maybe we shouldn't expand the Pseudo in RISCVExpandPseudoInsts.cpp.
It seems that one more MI would get the following error.

llc: /home/liaochunyu/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:83: virtual bool (anonymous namespace)::RISCVExpandPseudo::runOnMachineFunction(llvm::MachineFunction &): Assertion `OldSize >= NewSize' failed.

That error means you're missing a let Size = 8 on the pseudo in tablegen.

Here, it looks like there is

let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPF64:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
defm : LdPat<load, PseudoRV32ZdinxLD, f64>;
May 5 2023, 8:10 PM · Restricted Project, Restricted Project
liaolucy added a comment to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.

Maybe we shouldn't expand the Pseudo in RISCVExpandPseudoInsts.cpp.
It seems that one more MI would get the following error.

llc: /home/liaochunyu/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:83: virtual bool (anonymous namespace)::RISCVExpandPseudo::runOnMachineFunction(llvm::MachineFunction &): Assertion `OldSize >= NewSize' failed.

Maybe we should learn from jrtc27's reference https://github.com/CTSRD-CHERI/llvm-project/pull/635/files

May 5 2023, 7:55 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 5 2023, 7:26 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 5 2023, 7:52 AM · Restricted Project, Restricted Project
liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 5 2023, 7:37 AM · Restricted Project, Restricted Project

May 4 2023

liaolucy committed rG8cf768839a8d: [RISCV] Remove unused def simm12_plus1 from RISCVInstrInfo.td. NFC (authored by liaolucy).
[RISCV] Remove unused def simm12_plus1 from RISCVInstrInfo.td. NFC
May 4 2023, 9:54 PM · Restricted Project, Restricted Project
liaolucy closed D149925: [RISCV] Remove unused def simm12_plus1 from RISCVInstrInfo.td. NFC.
May 4 2023, 9:54 PM · Restricted Project, Restricted Project
liaolucy requested review of D149925: [RISCV] Remove unused def simm12_plus1 from RISCVInstrInfo.td. NFC.
May 4 2023, 9:49 PM · Restricted Project, Restricted Project
liaolucy added inline comments to D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen.
May 4 2023, 9:38 PM · Restricted Project, Restricted Project

Apr 27 2023

liaolucy added inline comments to D149063: [RISCV] Custom lowering of llvm.is.fpclass.
Apr 27 2023, 12:38 AM · Restricted Project, Restricted Project

Apr 25 2023

liaolucy committed rG5b869f3e2af4: [RISCV] Custom lowering of llvm.is.fpclass (authored by liaolucy).
[RISCV] Custom lowering of llvm.is.fpclass
Apr 25 2023, 7:17 PM · Restricted Project, Restricted Project
liaolucy closed D149063: [RISCV] Custom lowering of llvm.is.fpclass.
Apr 25 2023, 7:17 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D149063: [RISCV] Custom lowering of llvm.is.fpclass.

isnotfinite_fpclasee -> isnotfinite_fpclass
Re-update, I don't know why I didn't modify it correctly just now

Apr 25 2023, 6:51 PM · Restricted Project, Restricted Project
liaolucy updated the diff for D149063: [RISCV] Custom lowering of llvm.is.fpclass.

update

Apr 25 2023, 6:48 PM · Restricted Project, Restricted Project