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arcbbb (ShihPo Hung)
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User Since
Nov 25 2019, 1:09 AM (135 w, 4 d)

Recent Activity

Thu, Jun 23

arcbbb accepted D128286: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f..

It's great that MinElts can be obtained from RISCV::RVVBitsPerBlock / Subtarget.getELEN()
LGTM. Thanks!

Thu, Jun 23, 1:12 AM · Restricted Project, Restricted Project

May 31 2022

arcbbb added inline comments to D126048: [SplitKit] Handle early clobber + tied to def correctly.
May 31 2022, 6:49 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D126048: [SplitKit] Handle early clobber + tied to def correctly.
May 31 2022, 1:04 AM · Restricted Project, Restricted Project

May 2 2022

arcbbb accepted D123972: [RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ..

As mentioned in spec, For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0
I think FMIN & FMAX is commutative.
LGTM.

May 2 2022, 7:31 PM · Restricted Project, Restricted Project

May 1 2022

arcbbb added a comment to D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.

Thanks @arcbbb.

Just to understand the design principle behind these patches: adding FRM as Use to the v*cvt instructions (like we did in D121087 ) would not help us to implement floor and ceil. I imagine one option could be adding specific pseudos for round up and round down and then a later pass could set the rounding mode and restore it later. However, this would not give great code generation and it adds even more instructions to our already large number of pseudos. So your approach goes by adding a new operand with the rounding mode, similar to the scalar operations, and in D123371 you propose a pass that adjusts the FRM register.

I hope I got it right :)

May 1 2022, 9:31 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.

Address @rogfer01's comments

May 1 2022, 9:28 AM · Restricted Project, Restricted Project

Apr 27 2022

arcbbb accepted D124424: [RISCV] Fix alias printing for vmnot.m.

LGTM. Thanks for the fix!

Apr 27 2022, 10:32 PM · Restricted Project, Restricted Project

Apr 26 2022

arcbbb committed rG6b55f133fb07: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process (authored by arcbbb).
[RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process
Apr 26 2022, 8:15 PM · Restricted Project, Restricted Project
arcbbb committed rGbcb2b86df672: [RISCV] Precommit test for D121881 (authored by arcbbb).
[RISCV] Precommit test for D121881
Apr 26 2022, 8:15 PM · Restricted Project, Restricted Project
arcbbb closed D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 26 2022, 8:15 PM · Restricted Project, Restricted Project
arcbbb closed D123385: [RISCV] Precommit test for D121881.
Apr 26 2022, 8:15 PM · Restricted Project, Restricted Project

Apr 25 2022

arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Address Craig's comments.

Apr 25 2022, 11:40 PM · Restricted Project, Restricted Project
arcbbb added a comment to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

I'm glad we don't need to add dummy pseudos for this to work :)

This is now looking good, thank you: just to check - there's no way to dynamically check whether the TU pseudo exists in TableGen? That would remove the need for HasTU which I'd find a bit cleaner.

Apr 25 2022, 9:33 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Address @frasercrmck 's comments

Apr 25 2022, 9:27 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D123385: [RISCV] Precommit test for D121881.

Address @frasercrmck 's comments.

Apr 25 2022, 9:26 AM · Restricted Project, Restricted Project

Apr 12 2022

arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 12 2022, 9:44 PM · Restricted Project, Restricted Project
arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Address Craig's comments.

Apr 12 2022, 9:43 PM · Restricted Project, Restricted Project

Apr 8 2022

arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 8 2022, 6:46 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Updates

  1. Add a placeholder for pseudos that don't have _TU variants.
Apr 8 2022, 6:44 AM · Restricted Project, Restricted Project
arcbbb requested review of D123385: [RISCV] Precommit test for D121881.
Apr 8 2022, 6:09 AM · Restricted Project, Restricted Project
arcbbb accepted D123291: [RISCV] Select unmasked FP setcc insts via ISel post-process.

LGTM

Apr 8 2022, 5:51 AM · Restricted Project, Restricted Project
arcbbb requested review of D123371: [RISCV][RVV] Add a writefrm insert pass to support vfcvt with static rounding mode.
Apr 8 2022, 2:31 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.

rebased

Apr 8 2022, 12:36 AM · Restricted Project, Restricted Project

Apr 6 2022

arcbbb added inline comments to D120226: [RISCV] Support mask policy for RVV IR intrinsics..
Apr 6 2022, 8:57 PM · Restricted Project, Restricted Project
arcbbb added inline comments to D120226: [RISCV] Support mask policy for RVV IR intrinsics..
Apr 6 2022, 6:55 PM · Restricted Project, Restricted Project
arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 6 2022, 9:00 AM · Restricted Project, Restricted Project
arcbbb accepted D123217: [RISCV] Select unmasked integer setcc insts via ISel post-process.

LGTM

Apr 6 2022, 7:06 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 6 2022, 7:03 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Apr 6 2022, 6:53 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Updates:

  1. Forgot to rename the pass name.
Apr 6 2022, 6:47 AM · Restricted Project, Restricted Project

Apr 3 2022

arcbbb added a comment to D122709: [RISCV] Enable cross basic block aware writevxrm insertion.

I think that's we treating different view for vxrm, ABI was said same as frm, but now we plan to pull that out due to controversial for now, but I still not convinced for that, we pull out that out for prevent making short-sighted ABI decision, but you go this way means we made decision on close the possibility of venv, and that made dynamic rounding mode more unpredictable IMO.

Apr 3 2022, 8:16 AM · Restricted Project, Restricted Project

Apr 2 2022

arcbbb added a comment to D122709: [RISCV] Enable cross basic block aware writevxrm insertion.

Hmm, I think that made the dynamic rounding mode become unexpected/random rounding mode, give following example, the behavior vaddd in foo is unpredictably, vaddd in foo will operated with current rounding mode if the bar is inlined, but it will become rnu once bar inlined, I really think we should restore that for those static rounding mode stuffs.

foo:
  call bar
  vaddd

bar:
  vaadd.rm rnu
Apr 2 2022, 9:41 AM · Restricted Project, Restricted Project
arcbbb added a comment to D122709: [RISCV] Enable cross basic block aware writevxrm insertion.

Hmm, I think that made the dynamic rounding mode become unexpected/random rounding mode, give following example, the behavior vaddd in foo is unpredictably, vaddd in foo will operated with current rounding mode if the bar is inlined, but it will become rnu once bar inlined, I really think we should restore that for those static rounding mode stuffs.

foo:
  call bar
  vaddd

bar:
  vaadd.rm rnu
Apr 2 2022, 9:22 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
Apr 2 2022, 9:16 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Address @khchen 's comment.
Updates:

  1. Rename RISCVVXRMRegister.cpp to RISCVInsertVXRMWrite.cpp
  2. Fix the VCSR restoring.
Apr 2 2022, 9:12 AM · Restricted Project, Restricted Project

Mar 31 2022

arcbbb added a comment to D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.

This patch only creates the interface to specify the round mode in vfcvt pseudos.
How the round mode is changed at MI will be a separate patch.
I think this can make each patch smaller.

Mar 31 2022, 8:36 PM · Restricted Project, Restricted Project
arcbbb requested review of D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions.
Mar 31 2022, 8:20 PM · Restricted Project, Restricted Project
arcbbb committed rG2f1261abe4b7: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions (authored by arcbbb).
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
Mar 31 2022, 1:39 AM · Restricted Project, Restricted Project
arcbbb closed D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.
Mar 31 2022, 1:38 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
Mar 31 2022, 12:19 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Address Craig's comments.
Updates:

  1. Add assertions to check hasVL & hasSEW
  2. Remove RISCVReg 'vcsr'
  3. Do not mask immediate value
  4. Fix inconsistent comments
  5. Update O0 & O3 pipeline tests
Mar 31 2022, 12:17 AM · Restricted Project, Restricted Project

Mar 30 2022

arcbbb requested review of D122709: [RISCV] Enable cross basic block aware writevxrm insertion.
Mar 30 2022, 1:53 AM · Restricted Project, Restricted Project

Mar 29 2022

arcbbb accepted D122637: [RISCV] Trim RVV isel pats matchable via DAG post-process.

LGTM

Mar 29 2022, 12:30 AM · Restricted Project, Restricted Project

Mar 27 2022

arcbbb added inline comments to D122456: [RISCV] Use maskedoff to decide mask policy for masked compare and vmsbf/vmsif/vmsof..
Mar 27 2022, 9:13 AM · Restricted Project, Restricted Project
arcbbb accepted D122512: [RISCV] Add lowering for vp.fptosi and vp.sitofp..

LGTM

Mar 27 2022, 8:54 AM · Restricted Project, Restricted Project

Mar 26 2022

arcbbb added inline comments to D122512: [RISCV] Add lowering for vp.fptosi and vp.sitofp..
Mar 26 2022, 10:13 AM · Restricted Project, Restricted Project

Mar 25 2022

arcbbb added a comment to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8(
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  i64,
  i64);

Sorry I make a wrong example as VAADD doesn't saturate.
I should use VSMUL or VSADD.

Mar 25 2022, 10:13 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Thank @craig.topper and @frasercrmck
Updates:

  1. Reorder intrinsic class definition
  2. Reorder RISCVVXRMRegister in CMakeLists.txt
  3. Use PostISelHook to add VXRM uses to DYN pseudos
  4. Change non-DYN pseudos to DYN pseudos after CSR Write insertion
  5. Update tests
Mar 25 2022, 9:34 AM · Restricted Project, Restricted Project

Mar 24 2022

arcbbb added inline comments to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
Mar 24 2022, 10:55 AM · Restricted Project, Restricted Project

Mar 23 2022

arcbbb planned changes to D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.

I started a discussion on how RVV clang builtins interact with FENV_ACCESS in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/147
I would drop this patch if those builtins are going to be independent of FENV.

Mar 23 2022, 9:45 PM · Restricted Project, Restricted Project, Restricted Project

Mar 22 2022

arcbbb added a comment to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

In case this is relevant to you, I have a proposal to request the psABI to make VXRM non-preserved across calls in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/256
It has not been accepted, but I think it is good to have a discussion.

Mar 22 2022, 12:55 PM · Restricted Project, Restricted Project
arcbbb added inline comments to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
Mar 22 2022, 11:51 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Updates:

  1. Address Craig's comments
  2. Considering VXSAT state, save the value of VCSR instead of the value of VXRM
  3. update test cases
Mar 22 2022, 11:51 AM · Restricted Project, Restricted Project

Mar 21 2022

arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Mar 21 2022, 10:07 PM · Restricted Project, Restricted Project
arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Fixed typo in the test filename.

Mar 21 2022, 9:59 PM · Restricted Project, Restricted Project
arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Updates:

  1. Renames Id to I, and IsTU to IsTA
  2. Makes this patch independent of D120449.
Mar 21 2022, 9:55 PM · Restricted Project, Restricted Project
arcbbb added a comment to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Having RISCVVXRMRegister work per-basic-block is fine for now, but you probably want the capability to hoist the operations out of loops at some point.

Mar 21 2022, 3:10 AM · Restricted Project, Restricted Project

Mar 18 2022

arcbbb added a comment to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

I initiated a discussion https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/144
to talk about whether users of clang builtins would like to stay in option (1).

Mar 18 2022, 10:50 AM · Restricted Project, Restricted Project

Mar 17 2022

arcbbb updated the diff for D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.

Updates:

  1. Addresses @rogfer01's comment. Transforms TU+IMPLICIT_DEF to TA. This can be changed later if we have alternative idea.
  2. Adds TU+IMPLICIT_DEF test cases by
    sed -i '/; CHECK.*/d' $file
    sed -i -e '/define.*@intrinsic_vf.\?cvt_mask/{
           h;
           s/define <vscale.*> @intrinsic_\(vf.\?cvt\)_mask\(.*\)(\(<vscale.*>\) %0, \(<vscale.*>\) %1, <vscale x \(.*\) x i1> %2, iXLen %3) \(.*\)/\
define \3 @intrinsic_allone_\1_mask\2(\4 %1, iXLen %3) \6\
entry:\
  %allone = call <vscale x \5 x i1> @llvm.riscv.vmset.nxv\5i1(\
    iXLen %3);/;
           x;
           n;n;N;N; N;N;N;N;N;
           H;
           x;
           s/%0/undef/g
           s/%1/%0/g
           s/%2/%allone/g
           s/%3/%1/g
           s/iXLen 1/iXLen 0/g
           x;
           G;}
Mar 17 2022, 9:28 AM · Restricted Project, Restricted Project
arcbbb added inline comments to D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Mar 17 2022, 3:17 AM · Restricted Project, Restricted Project

Mar 16 2022

arcbbb retitled D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process from [RISCV][RVV] Select unmaksed TU RVV pseudos in a DAG post-process to [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Mar 16 2022, 11:53 PM · Restricted Project, Restricted Project
arcbbb requested review of D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.
Mar 16 2022, 11:47 PM · Restricted Project, Restricted Project
arcbbb updated the diff for D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

rebase for per-merge checks

Mar 16 2022, 11:41 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.

rebase to main

Mar 16 2022, 11:30 AM · Restricted Project, Restricted Project, Restricted Project

Mar 11 2022

arcbbb added a comment to D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

This generally makes sense.

I'm not sure you want to allow the intrinsics to accept the immediate argument DYN (4). That sort of defeats the point of adding the explicit argument: you can't mark the intrinsic IntrNoMem.

Mar 11 2022, 12:15 AM · Restricted Project, Restricted Project
arcbbb updated the diff for D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.

Updates:

  1. Add isUInt<2> check for timm.
  2. Use 0 as round mode value in tests
  3. Add tu and rv32 test cases.
Mar 11 2022, 12:09 AM · Restricted Project, Restricted Project

Mar 10 2022

arcbbb removed a project from D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction: Restricted Project.
Mar 10 2022, 7:37 AM · Restricted Project, Restricted Project
arcbbb requested review of D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction.
Mar 10 2022, 7:20 AM · Restricted Project, Restricted Project

Mar 9 2022

arcbbb updated the diff for D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

Updates:

  1. Removes FRM use from VFRSQRT7
Mar 9 2022, 6:03 PM · Restricted Project, Restricted Project
arcbbb commandeered D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

VFRSQRT7 do not use FRM.
From v-spec,

The output value is independent of the dynamic rounding mode.

Mar 9 2022, 5:58 PM · Restricted Project, Restricted Project

Mar 7 2022

arcbbb added a comment to D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.

I skip FCVT* because it is defined in D120449

Mar 7 2022, 12:16 AM · Restricted Project, Restricted Project
arcbbb requested review of D121087: [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions.
Mar 7 2022, 12:14 AM · Restricted Project, Restricted Project

Mar 6 2022

arcbbb updated the diff for D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.

Updates:

  1. Fixes indentation in RISCVInstrInfoVVLPatterns.td
  2. Changes variable name Mask to TrueMask in lowerRVVStrictIntrinsics().
  3. Use immediate value 0 in the policy operand for unmasked pseudos.
Mar 6 2022, 8:18 PM · Restricted Project, Restricted Project, Restricted Project

Mar 3 2022

arcbbb added inline comments to D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.
Mar 3 2022, 2:02 AM · Restricted Project, Restricted Project, Restricted Project
arcbbb updated the diff for D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.

Updates:

  1. Adds Uses and mayRaiseFPException to VFCVT* Instruction in RISCVInstrInfoV.td
  2. Drops curly braces in function lowerRVVStrictIntrinsics
Mar 3 2022, 2:01 AM · Restricted Project, Restricted Project, Restricted Project

Mar 2 2022

arcbbb updated the diff for D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.

Update:

  1. Remove Clang changes to make this patch smaller for review
Mar 2 2022, 1:51 AM · Restricted Project, Restricted Project, Restricted Project

Feb 23 2022

arcbbb requested review of D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode.
Feb 23 2022, 7:11 PM · Restricted Project, Restricted Project, Restricted Project

Jan 19 2022

arcbbb accepted D117518: [RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask BUILD_VECTORs..

LGTM. Thanks!

Jan 19 2022, 1:29 AM · Restricted Project

Jan 11 2022

arcbbb accepted D116694: [RISCV] Add strictfp support for compares..

LGTM. Thanks Craig for improving this!

Jan 11 2022, 2:12 AM · Restricted Project

Jan 5 2022

arcbbb accepted D116631: [RISCV] Use macros to reduce repetive switch cases. NFC.

LGTM.

Jan 5 2022, 1:21 AM · Restricted Project

Dec 19 2021

arcbbb accepted D115709: [RISCV] Remove Zvamo Extention.

LGTM too. Thanks.

Dec 19 2021, 6:13 PM · Restricted Project, Restricted Project

Dec 14 2021

arcbbb accepted D115555: [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode..

LGTM

Dec 14 2021, 1:19 AM · Restricted Project
arcbbb accepted D115680: [RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT..

LGTM

Dec 14 2021, 1:11 AM · Restricted Project
arcbbb accepted D115540: [RISCV] Add mayRaiseFPException to RISCV scalar FP instructions..

LGTM

Dec 14 2021, 1:07 AM · Restricted Project

Dec 13 2021

arcbbb added a comment to D113439: [RISCV] Add IR intrinsics for reading/write vxrm..

I agree with the idea that not providing the raw vgetvxrm/vsetvxrm but providing the variants instead.
I see it brings less issues to programmers, LLVM autovectorizer, Halide backend, and optimization passes than the other way.
And since they are target-specific intrinsics, the difference could be understandable.

Dec 13 2021, 7:10 AM · Restricted Project

Oct 13 2021

arcbbb added a reviewer for D111692: [RISCV] Remove Zvamo C intrinsics and builtins.: jrtc27.

@jrtc27 commented to keep it in https://reviews.llvm.org/D105396?id=356342

Oct 13 2021, 1:19 PM · Restricted Project

Jul 21 2021

arcbbb committed rG8d86562e5f1f: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber (authored by arcbbb).
[RegisterCoalescer] Make resolveConflicts aware of earlyclobber
Jul 21 2021, 9:11 PM
arcbbb closed D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Jul 21 2021, 9:11 PM · Restricted Project

Jul 17 2021

arcbbb committed rGbe8159bfa56f: [RISCV][RVV] Precommit a test case for D105684 (authored by arcbbb).
[RISCV][RVV] Precommit a test case for D105684
Jul 17 2021, 9:44 AM
arcbbb closed D105685: [RISCV][RVV] Precommit a test case for D105684.
Jul 17 2021, 9:44 AM · Restricted Project

Jul 13 2021

arcbbb accepted D105417: [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants..

LGTM

Jul 13 2021, 2:03 AM · Restricted Project

Jul 11 2021

arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

Avoid postfix increment operator.

Jul 11 2021, 11:40 PM · Restricted Project

Jul 10 2021

post.kadirselcuk awarded rGf1cbea3e5275: [RISCV] Remove Zvamo implication for v1.0-rc change a Like token.
Jul 10 2021, 9:25 PM
post.kadirselcuk awarded D105396: [RISCV] Remove Zvamo implication for v1.0-rc change a 100 token.
Jul 10 2021, 9:24 PM · Restricted Project, Restricted Project

Jul 9 2021

arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

clang-formatted

Jul 9 2021, 2:46 AM · Restricted Project
arcbbb updated the summary of D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Jul 9 2021, 2:33 AM · Restricted Project
arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

update a test case to show the difference

Jul 9 2021, 2:20 AM · Restricted Project
arcbbb requested review of D105685: [RISCV][RVV] Precommit a test case for D105684.
Jul 9 2021, 2:12 AM · Restricted Project
arcbbb requested review of D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Jul 9 2021, 2:07 AM · Restricted Project

Jul 6 2021

arcbbb accepted D105206: [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno.

LGTM

Jul 6 2021, 10:07 AM · Restricted Project