User Details
- User Since
- Nov 25 2019, 1:09 AM (173 w, 2 d)
Sun, Mar 5
- Update tests
- Address @reames's comments
Jan 21 2023
Jan 20 2023
- Updates
- Address Craig's and Simon's comments a. Labeling the true and false parameters b. Replace TTI::TCK_RecipThroughput with a common CostKind variable.
Jan 19 2023
Jan 18 2023
Nov 30 2022
Nov 2 2022
Updates:
Address Craig's comments.
Updates: Use 1 for fractional LMUL.
Sep 20 2022
LGTM
Sep 5 2022
Look good to me.
LGTM.
It is nice to see vfcvt is used in fceil & ffloor.
Aug 29 2022
Aug 18 2022
LGTM.
Jun 23 2022
It's great that MinElts can be obtained from RISCV::RVVBitsPerBlock / Subtarget.getELEN()
LGTM. Thanks!
May 31 2022
May 2 2022
As mentioned in spec, For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0
I think FMIN & FMAX is commutative.
LGTM.
May 1 2022
Address @rogfer01's comments
Apr 27 2022
LGTM. Thanks for the fix!
Apr 26 2022
Apr 25 2022
Address Craig's comments.
Address @frasercrmck 's comments
Address @frasercrmck 's comments.
Apr 12 2022
Address Craig's comments.
Apr 8 2022
Updates
- Add a placeholder for pseudos that don't have _TU variants.
LGTM
rebased
Apr 6 2022
LGTM
Updates:
- Forgot to rename the pass name.
Apr 3 2022
Apr 2 2022
Address @khchen 's comment.
Updates:
- Rename RISCVVXRMRegister.cpp to RISCVInsertVXRMWrite.cpp
- Fix the VCSR restoring.
Mar 31 2022
This patch only creates the interface to specify the round mode in vfcvt pseudos.
How the round mode is changed at MI will be a separate patch.
I think this can make each patch smaller.
Address Craig's comments.
Updates:
- Add assertions to check hasVL & hasSEW
- Remove RISCVReg 'vcsr'
- Do not mask immediate value
- Fix inconsistent comments
- Update O0 & O3 pipeline tests
Mar 30 2022
Mar 29 2022
LGTM
Mar 27 2022
LGTM
Mar 26 2022
Mar 25 2022
declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8( <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64);
Sorry I make a wrong example as VAADD doesn't saturate.
I should use VSMUL or VSADD.
Thank @craig.topper and @frasercrmck
Updates:
- Reorder intrinsic class definition
- Reorder RISCVVXRMRegister in CMakeLists.txt
- Use PostISelHook to add VXRM uses to DYN pseudos
- Change non-DYN pseudos to DYN pseudos after CSR Write insertion
- Update tests
Mar 24 2022
Mar 23 2022
I started a discussion on how RVV clang builtins interact with FENV_ACCESS in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/147
I would drop this patch if those builtins are going to be independent of FENV.
Mar 22 2022
In case this is relevant to you, I have a proposal to request the psABI to make VXRM non-preserved across calls in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/256
It has not been accepted, but I think it is good to have a discussion.
Updates:
- Address Craig's comments
- Considering VXSAT state, save the value of VCSR instead of the value of VXRM
- update test cases
Mar 21 2022
Fixed typo in the test filename.
Updates:
- Renames Id to I, and IsTU to IsTA
- Makes this patch independent of D120449.
Mar 18 2022
I initiated a discussion https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/144
to talk about whether users of clang builtins would like to stay in option (1).
Mar 17 2022
Updates:
- Addresses @rogfer01's comment. Transforms TU+IMPLICIT_DEF to TA. This can be changed later if we have alternative idea.
- Adds TU+IMPLICIT_DEF test cases by
sed -i '/; CHECK.*/d' $file sed -i -e '/define.*@intrinsic_vf.\?cvt_mask/{ h; s/define <vscale.*> @intrinsic_\(vf.\?cvt\)_mask\(.*\)(\(<vscale.*>\) %0, \(<vscale.*>\) %1, <vscale x \(.*\) x i1> %2, iXLen %3) \(.*\)/\ define \3 @intrinsic_allone_\1_mask\2(\4 %1, iXLen %3) \6\ entry:\ %allone = call <vscale x \5 x i1> @llvm.riscv.vmset.nxv\5i1(\ iXLen %3);/; x; n;n;N;N; N;N;N;N;N; H; x; s/%0/undef/g s/%1/%0/g s/%2/%allone/g s/%3/%1/g s/iXLen 1/iXLen 0/g x; G;}
Mar 16 2022
rebase for per-merge checks
rebase to main
Mar 11 2022
Updates:
- Add isUInt<2> check for timm.
- Use 0 as round mode value in tests
- Add tu and rv32 test cases.
Mar 10 2022
Mar 9 2022
Updates:
- Removes FRM use from VFRSQRT7
Mar 7 2022
I skip FCVT* because it is defined in D120449
Mar 6 2022
Updates:
- Fixes indentation in RISCVInstrInfoVVLPatterns.td
- Changes variable name Mask to TrueMask in lowerRVVStrictIntrinsics().
- Use immediate value 0 in the policy operand for unmasked pseudos.