It's great that MinElts can be obtained from RISCV::RVVBitsPerBlock / Subtarget.getELEN()
LGTM. Thanks!

As mentioned in spec, For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0
I think FMIN & FMAX is commutative.
LGTM.

In D122860#3479271, @rogfer01 wrote:

Thanks @arcbbb.

Just to understand the design principle behind these patches: adding FRM as Use to the v*cvt instructions (like we did in D121087 ) would not help us to implement floor and ceil. I imagine one option could be adding specific pseudos for round up and round down and then a later pass could set the rounding mode and restore it later. However, this would not give great code generation and it adds even more instructions to our already large number of pseudos. So your approach goes by adding a new operand with the rounding mode, similar to the scalar operations, and in D123371 you propose a pass that adjusts the FRM register.

I hope I got it right :)

Address @rogfer01's comments

LGTM. Thanks for the fix!

Address Craig's comments.

In D121881#3447794, @frasercrmck wrote:

I'm glad we don't need to add dummy pseudos for this to work :)

This is now looking good, thank you: just to check - there's no way to dynamically check whether the TU pseudo exists in TableGen? That would remove the need for HasTU which I'd find a bit cleaner.

Address @frasercrmck 's comments

Address @frasercrmck 's comments.

Address Craig's comments.

Updates

1. Add a placeholder for pseudos that don't have _TU variants.

LGTM

rebased

LGTM

Updates:

1. Forgot to rename the pass name.

In D122709#3425094, @kito-cheng wrote:

I think that's we treating different view for vxrm, ABI was said same as frm, but now we plan to pull that out due to controversial for now, but I still not convinced for that, we pull out that out for prevent making short-sighted ABI decision, but you go this way means we made decision on close the possibility of venv, and that made dynamic rounding mode more unpredictable IMO.

In D122709#3419837, @kito-cheng wrote:

Hmm, I think that made the dynamic rounding mode become unexpected/random rounding mode, give following example, the behavior vaddd in foo is unpredictably, vaddd in foo will operated with current rounding mode if the bar is inlined, but it will become rnu once bar inlined, I really think we should restore that for those static rounding mode stuffs.

foo:
  call bar
  vaddd

bar:
  vaadd.rm rnu

In D122709#3419837, @kito-cheng wrote:

Hmm, I think that made the dynamic rounding mode become unexpected/random rounding mode, give following example, the behavior vaddd in foo is unpredictably, vaddd in foo will operated with current rounding mode if the bar is inlined, but it will become rnu once bar inlined, I really think we should restore that for those static rounding mode stuffs.

foo:
  call bar
  vaddd

bar:
  vaadd.rm rnu

Address @khchen 's comment.
Updates:

1. Rename RISCVVXRMRegister.cpp to RISCVInsertVXRMWrite.cpp
2. Fix the VCSR restoring.

This patch only creates the interface to specify the round mode in vfcvt pseudos.
How the round mode is changed at MI will be a separate patch.
I think this can make each patch smaller.

Address Craig's comments.
Updates:

1. Add assertions to check hasVL & hasSEW
2. Remove RISCVReg 'vcsr'
3. Do not mask immediate value
4. Fix inconsistent comments
5. Update O0 & O3 pipeline tests

LGTM

LGTM

declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8(
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  i64,
  i64);

Sorry I make a wrong example as VAADD doesn't saturate.
I should use VSMUL or VSADD.

Thank @craig.topper and @frasercrmck
Updates:

1. Reorder intrinsic class definition
2. Reorder RISCVVXRMRegister in CMakeLists.txt
3. Use PostISelHook to add VXRM uses to DYN pseudos
4. Change non-DYN pseudos to DYN pseudos after CSR Write insertion
5. Update tests

I started a discussion on how RVV clang builtins interact with FENV_ACCESS in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/147
I would drop this patch if those builtins are going to be independent of FENV.

In case this is relevant to you, I have a proposal to request the psABI to make VXRM non-preserved across calls in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/256
It has not been accepted, but I think it is good to have a discussion.

Updates:

1. Address Craig's comments
2. Considering VXSAT state, save the value of VCSR instead of the value of VXRM
3. update test cases

Fixed typo in the test filename.

Updates:

1. Renames Id to I, and IsTU to IsTA
2. Makes this patch independent of D120449.

In D121376#3392981, @efriedma wrote:

Having RISCVVXRMRegister work per-basic-block is fine for now, but you probably want the capability to hoist the operations out of loops at some point.

I initiated a discussion https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/144
to talk about whether users of clang builtins would like to stay in option (1).

Updates:

1. Addresses @rogfer01's comment. Transforms TU+IMPLICIT_DEF to TA. This can be changed later if we have alternative idea.
2. Adds TU+IMPLICIT_DEF test cases by

    sed -i '/; CHECK.*/d' $file
    sed -i -e '/define.*@intrinsic_vf.\?cvt_mask/{
           h;
           s/define <vscale.*> @intrinsic_\(vf.\?cvt\)_mask\(.*\)(\(<vscale.*>\) %0, \(<vscale.*>\) %1, <vscale x \(.*\) x i1> %2, iXLen %3) \(.*\)/\
define \3 @intrinsic_allone_\1_mask\2(\4 %1, iXLen %3) \6\
entry:\
  %allone = call <vscale x \5 x i1> @llvm.riscv.vmset.nxv\5i1(\
    iXLen %3);/;
           x;
           n;n;N;N; N;N;N;N;N;
           H;
           x;
           s/%0/undef/g
           s/%1/%0/g
           s/%2/%allone/g
           s/%3/%1/g
           s/iXLen 1/iXLen 0/g
           x;
           G;}

rebase for per-merge checks

rebase to main

In D121376#3373395, @efriedma wrote:

This generally makes sense.

I'm not sure you want to allow the intrinsics to accept the immediate argument DYN (4). That sort of defeats the point of adding the explicit argument: you can't mark the intrinsic IntrNoMem.

Updates:

1. Add isUInt<2> check for timm.
2. Use 0 as round mode value in tests
3. Add tu and rv32 test cases.

Updates:

1. Removes FRM use from VFRSQRT7

In D121087#3369462, @HanKuanChen wrote:

VFRSQRT7 do not use FRM.
From v-spec,

The output value is independent of the dynamic rounding mode.

I skip FCVT* because it is defined in D120449

Updates:

1. Fixes indentation in RISCVInstrInfoVVLPatterns.td
2. Changes variable name Mask to TrueMask in lowerRVVStrictIntrinsics().
3. Use immediate value 0 in the policy operand for unmasked pseudos.

Updates:

1. Adds Uses and mayRaiseFPException to VFCVT* Instruction in RISCVInstrInfoV.td
2. Drops curly braces in function lowerRVVStrictIntrinsics

Update:

1. Remove Clang changes to make this patch smaller for review

LGTM. Thanks!

LGTM. Thanks Craig for improving this!

LGTM.

LGTM too. Thanks.

LGTM

LGTM

LGTM

I agree with the idea that not providing the raw vgetvxrm/vsetvxrm but providing the variants instead.
I see it brings less issues to programmers, LLVM autovectorizer, Halide backend, and optimization passes than the other way.
And since they are target-specific intrinsics, the difference could be understandable.

@jrtc27 commented to keep it in https://reviews.llvm.org/D105396?id=356342

LGTM

Avoid postfix increment operator.

clang-formatted

update a test case to show the difference

LGTM