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tangxingxin1008 (eric tang)
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Nov 12 2020, 6:10 PM (106 w, 4 d)

Recent Activity

Mar 10 2022

tangxingxin1008 committed rG336c92d5e8ae: [RISCV] Add alias for HFENCE.VVMA (authored by tangxingxin1008).
[RISCV] Add alias for HFENCE.VVMA
Mar 10 2022, 9:35 PM · Restricted Project
tangxingxin1008 closed D120878: [RISCV] Add alias for HFENCE.VVMA.
Mar 10 2022, 9:34 PM · Restricted Project, Restricted Project

Mar 3 2022

tangxingxin1008 added inline comments to D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.
Mar 3 2022, 1:58 AM · Restricted Project, Restricted Project
tangxingxin1008 added a comment to D120878: [RISCV] Add alias for HFENCE.VVMA.

I don't find explicit alias of these instructions(sfence.vma, hfence.gvma, hfence.vvma) from the Privileged spec, but there is a case about hfence.gvma from linux kvm : https://github.com/torvalds/linux/blob/master/arch/riscv/kvm/tlb.S. According to Privileged spec , "HFENCE.VVMA and HFENCE.GVMA,perform a function similar to SFENCE.VMA (Section 4.2.1)", so add alias for hfence.vvma is a necessary.

Mar 3 2022, 1:56 AM · Restricted Project, Restricted Project
tangxingxin1008 added reviewers for D120878: [RISCV] Add alias for HFENCE.VVMA: craig.topper, asb, jrtc27, frasercrmck, kito-cheng.
Mar 3 2022, 1:52 AM · Restricted Project, Restricted Project
tangxingxin1008 requested review of D120878: [RISCV] Add alias for HFENCE.VVMA.
Mar 3 2022, 1:48 AM · Restricted Project, Restricted Project

Feb 27 2022

tangxingxin1008 committed rGb496a172e406: [RISCV] Support hypervisor extention instructions (authored by tangxingxin1008).
[RISCV] Support hypervisor extention instructions
Feb 27 2022, 10:09 PM
tangxingxin1008 committed rG386c5be92a86: [RISCV] Support Sinval extension and hypervisor memory management fence… (authored by tangxingxin1008).
[RISCV] Support Sinval extension and hypervisor memory management fence…
Feb 27 2022, 10:08 PM
tangxingxin1008 committed rGcf80ef139397: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage (authored by tangxingxin1008).
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
Feb 27 2022, 10:08 PM
tangxingxin1008 closed D117733: [RISCV] Support hypervisor extention instructions.
Feb 27 2022, 10:08 PM · Restricted Project
tangxingxin1008 closed D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.
Feb 27 2022, 10:08 PM · Restricted Project, Restricted Project
tangxingxin1008 closed D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage.
Feb 27 2022, 10:08 PM · Restricted Project

Feb 24 2022

tangxingxin1008 updated the diff for D117733: [RISCV] Support hypervisor extention instructions.

Address asb's comment. Add more tests for the RV64-only instructions on RV32.

Feb 24 2022, 9:43 PM · Restricted Project

Feb 18 2022

tangxingxin1008 updated the diff for D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage.

rebase

Feb 18 2022, 1:20 AM · Restricted Project
tangxingxin1008 updated the diff for D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage.

rebase

Feb 18 2022, 12:53 AM · Restricted Project
tangxingxin1008 retitled D117733: [RISCV] Support hypervisor extention instructions from [RISCV] Update Privileged spec to version-20211203: Support Hypervisor Extention to [RISCV] Support hypervisor extention instructions.
Feb 18 2022, 12:38 AM · Restricted Project
tangxingxin1008 updated the diff for D117733: [RISCV] Support hypervisor extention instructions.

Address asb's comment.

Feb 18 2022, 12:35 AM · Restricted Project

Feb 17 2022

tangxingxin1008 added inline comments to D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.
Feb 17 2022, 7:04 PM · Restricted Project, Restricted Project
tangxingxin1008 retitled D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions from [RISCV] Update Privileged spec to version-20211203: Support Sinval Extention to [RISCV] Support Sinval extension and hypervisor memory management fence instructions.
Feb 17 2022, 7:01 PM · Restricted Project, Restricted Project
tangxingxin1008 updated the diff for D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.

Address asb's comment.

Feb 17 2022, 6:59 PM · Restricted Project, Restricted Project
tangxingxin1008 added reviewers for D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage: asb, craig.topper, jrtc27, luismarques, kito.cheng.
Feb 17 2022, 1:10 AM · Restricted Project
tangxingxin1008 added a comment to D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage.

split from D117733

Feb 17 2022, 1:06 AM · Restricted Project
tangxingxin1008 requested review of D120017: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage.
Feb 17 2022, 1:04 AM · Restricted Project

Feb 16 2022

tangxingxin1008 added a comment to D117733: [RISCV] Support hypervisor extention instructions.

Thanks for the patch. Alongside the inline comments, two minor suggestions:

  • There's no need to split it out now I don't think, but the GPRAtomicMemOp->GPRMemZeroOffset is a change that could have been split out to a separate commit and reviewed separately.
  • We don't do enough testing for this in general I don't think, but it would be good to add tests that attempting to use the RV64-only hypervisor instructions on RV32 produces an error.

Once the inline comments are addressed and tests added for using the RV64 instructions on RV32, I think it should be ready to land.

Feb 16 2022, 6:17 PM · Restricted Project
tangxingxin1008 added a comment to D117733: [RISCV] Support hypervisor extention instructions.

@tangxingxin1008: Might you have a chance to look at these review comments soon? I've ended up rebasing D117432 on top of this patch in order to use GPRMemZeroOffset, so that's another reason it would be good to land this. Thanks.

Just a friendly ping on this.

Feb 16 2022, 6:08 PM · Restricted Project

Jan 19 2022

tangxingxin1008 updated the summary of D117733: [RISCV] Support hypervisor extention instructions.
Jan 19 2022, 11:02 PM · Restricted Project
tangxingxin1008 updated the diff for D117733: [RISCV] Support hypervisor extention instructions.

Address jrtc27's comment. Thanks.

Jan 19 2022, 10:58 PM · Restricted Project
tangxingxin1008 added inline comments to D117733: [RISCV] Support hypervisor extention instructions.
Jan 19 2022, 9:01 PM · Restricted Project
tangxingxin1008 requested review of D117733: [RISCV] Support hypervisor extention instructions.
Jan 19 2022, 4:55 PM · Restricted Project
tangxingxin1008 retitled D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions from Update Privileged spec to version-20211203: Support Sinval Extention to [RISCV] Update Privileged spec to version-20211203: Support Sinval Extention.
Jan 19 2022, 2:25 AM · Restricted Project, Restricted Project
tangxingxin1008 updated the diff for D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.

rebase

Jan 19 2022, 2:23 AM · Restricted Project, Restricted Project
tangxingxin1008 requested review of D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions.
Jan 19 2022, 2:16 AM · Restricted Project, Restricted Project
tangxingxin1008 requested review of D117653: [RISCV] Update Privileged spec to version-20211203: Removed the N extension.
Jan 19 2022, 2:11 AM · Restricted Project
tangxingxin1008 abandoned D117652: [RISCV] Update Privileged spec to version-20211203: Removed the N extension.

Sorry, I will recommit these patches

Jan 19 2022, 2:07 AM · Restricted Project
tangxingxin1008 requested review of D117652: [RISCV] Update Privileged spec to version-20211203: Removed the N extension.
Jan 19 2022, 2:05 AM · Restricted Project
tangxingxin1008 abandoned D117651: [RISCV] Update Privileged spec to version-20211203: Support Hypervisor Extention.
Jan 19 2022, 1:59 AM · Restricted Project
tangxingxin1008 requested review of D117651: [RISCV] Update Privileged spec to version-20211203: Support Hypervisor Extention.
Jan 19 2022, 1:59 AM · Restricted Project

Nov 18 2021

tangxingxin1008 added a comment to D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Thank you for all your help! @frasercrmck

Nov 18 2021, 4:55 PM · Restricted Project

Nov 17 2021

tangxingxin1008 added a comment to D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Hi @craig.topper @frasercrmck , I don’t have commit access, can you land this patch for me? Thanks.

Nov 17 2021, 10:14 PM · Restricted Project

Nov 16 2021

tangxingxin1008 added a comment to D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

Sorry, I don't know how to merged this patch, and get a wrong way to close this revision.

To merge a patch you'll need to request commit access to LLVM (see https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access) so that you can do git push. This then closes the revision in Phabricator automatically.

If you don't have commit access yet, I'd be happy to commit the patch for you.

Nov 16 2021, 4:58 PM · Restricted Project
tangxingxin1008 reopened D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

Sorry, I don't know how to merged this patch, and get a wrong way to close this revision. Please forgive me for my mistake.

Nov 16 2021, 2:52 AM · Restricted Project
tangxingxin1008 reopened D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Sorry, I don't know how to merged this patch, and get a wrong way to close this revision. Please forgive me for my mistake.

Nov 16 2021, 2:47 AM · Restricted Project
tangxingxin1008 closed D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.
Nov 16 2021, 2:18 AM · Restricted Project
tangxingxin1008 closed D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.
Nov 16 2021, 2:17 AM · Restricted Project

Sep 26 2021

tangxingxin1008 added a comment to D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

For SetWidenedVector, this change reduced the restrictions. In AArch64 sve, normally, SetWidenedVector only support nxv1i1 -> nxv2i1, after this change, the nxv1i1 -> nxv4i1, nxv1i1 -> nxv8i1, nxv1i1 -> nxv16i1 can also work.

Sep 26 2021, 8:23 PM · Restricted Project, Restricted Project
tangxingxin1008 updated the diff for D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

rebase

Sep 26 2021, 8:10 PM · Restricted Project, Restricted Project

Sep 25 2021

tangxingxin1008 added inline comments to D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.
Sep 25 2021, 6:41 PM · Restricted Project
tangxingxin1008 updated the diff for D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

Address david-arm's comments and add more tests.

Sep 25 2021, 6:40 PM · Restricted Project

Sep 24 2021

tangxingxin1008 updated the diff for D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

rebase

Sep 24 2021, 3:01 AM · Restricted Project
tangxingxin1008 requested review of D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.
Sep 24 2021, 12:38 AM · Restricted Project

Sep 23 2021

tangxingxin1008 added a comment to D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

I know they're both small changes but I think it would be good to split this patch up into separate parts: overflow and select. They're conceptually distinct changes. Then we could have more targeted tests for each operation and each change.

Also RISC-V would benefit from the select change, e.g., adding this sort of test to test/CodeGen/RISCV/rvv/vselect-int-rv32.ll and vselect-int-rv64.ll

define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {
  %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb
  ret <vscale x 3 x i8> %vc
}

thanks, I will be changed according to your advice.

Sep 23 2021, 6:06 PM · Restricted Project, Restricted Project
tangxingxin1008 requested review of D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.
Sep 23 2021, 4:11 AM · Restricted Project, Restricted Project

Sep 22 2021

tangxingxin1008 updated the diff for D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Add AArch64 sve test case. Address Craig Topper's suggestion.

Sep 22 2021, 11:55 PM · Restricted Project
tangxingxin1008 added a comment to D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Does this affect AArch64 too?

Sep 22 2021, 4:21 AM · Restricted Project

Sep 15 2021

tangxingxin1008 requested review of D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.
Sep 15 2021, 12:19 AM · Restricted Project

Apr 11 2021

tangxingxin1008 requested review of D100285: [llvm-mc] List available options for -mcpu=help or -mattr=help more convenience.
Apr 11 2021, 10:37 PM · Restricted Project

Mar 9 2021

tangxingxin1008 added a watcher for lld: tangxingxin1008.
Mar 9 2021, 6:19 PM

Nov 18 2020

tangxingxin1008 abandoned D91668: [RISCV]Add register constraint on riscv vector instruction.

https://reviews.llvm.org/D91712 fix it

Nov 18 2020, 4:35 PM · Restricted Project

Nov 17 2020

tangxingxin1008 added a comment to D91668: [RISCV]Add register constraint on riscv vector instruction.

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

I was wondering the same thing.

Nov 17 2020, 6:36 PM · Restricted Project
tangxingxin1008 requested review of D91668: [RISCV]Add register constraint on riscv vector instruction.
Nov 17 2020, 4:48 PM · Restricted Project