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tangxingxin1008 (eric tang)
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Nov 12 2020, 6:10 PM (49 w, 1 d)

Recent Activity

Sun, Sep 26

tangxingxin1008 added a comment to D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

For SetWidenedVector, this change reduced the restrictions. In AArch64 sve, normally, SetWidenedVector only support nxv1i1 -> nxv2i1, after this change, the nxv1i1 -> nxv4i1, nxv1i1 -> nxv8i1, nxv1i1 -> nxv16i1 can also work.

Sun, Sep 26, 8:23 PM · Restricted Project
tangxingxin1008 updated the diff for D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

rebase

Sun, Sep 26, 8:10 PM · Restricted Project

Sat, Sep 25

tangxingxin1008 added inline comments to D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.
Sat, Sep 25, 6:41 PM · Restricted Project
tangxingxin1008 updated the diff for D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

Address david-arm's comments and add more tests.

Sat, Sep 25, 6:40 PM · Restricted Project

Fri, Sep 24

tangxingxin1008 updated the diff for D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.

rebase

Fri, Sep 24, 3:01 AM · Restricted Project
tangxingxin1008 requested review of D110388: [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors.
Fri, Sep 24, 12:38 AM · Restricted Project

Thu, Sep 23

tangxingxin1008 added a comment to D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.

I know they're both small changes but I think it would be good to split this patch up into separate parts: overflow and select. They're conceptually distinct changes. Then we could have more targeted tests for each operation and each change.

Also RISC-V would benefit from the select change, e.g., adding this sort of test to test/CodeGen/RISCV/rvv/vselect-int-rv32.ll and vselect-int-rv64.ll

define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {
  %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb
  ret <vscale x 3 x i8> %vc
}

thanks, I will be changed according to your advice.

Thu, Sep 23, 6:06 PM · Restricted Project
tangxingxin1008 requested review of D110319: [SelectionDAG] Fixed the scalable vectors issue on WidenVecRes_OverflowOp&WidenVecRes_SELECT.
Thu, Sep 23, 4:11 AM · Restricted Project

Wed, Sep 22

tangxingxin1008 updated the diff for D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Add AArch64 sve test case. Address Craig Topper's suggestion.

Wed, Sep 22, 11:55 PM · Restricted Project

Sep 22 2021

tangxingxin1008 added a comment to D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.

Does this affect AArch64 too?

Sep 22 2021, 4:21 AM · Restricted Project

Sep 15 2021

tangxingxin1008 requested review of D109809: [TargetLowering][RISCV] Fixed a scalable vector issue when lowering [s|u]mul.overflow intrinsics.
Sep 15 2021, 12:19 AM · Restricted Project

Apr 11 2021

tangxingxin1008 requested review of D100285: [llvm-mc] List available options for -mcpu=help or -mattr=help more convenience.
Apr 11 2021, 10:37 PM · Restricted Project

Mar 9 2021

tangxingxin1008 added a watcher for lld: tangxingxin1008.
Mar 9 2021, 6:19 PM

Nov 18 2020

tangxingxin1008 abandoned D91668: [RISCV]Add register constraint on riscv vector instruction.

https://reviews.llvm.org/D91712 fix it

Nov 18 2020, 4:35 PM · Restricted Project

Nov 17 2020

tangxingxin1008 added a comment to D91668: [RISCV]Add register constraint on riscv vector instruction.

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

I was wondering the same thing.

Nov 17 2020, 6:36 PM · Restricted Project
tangxingxin1008 requested review of D91668: [RISCV]Add register constraint on riscv vector instruction.
Nov 17 2020, 4:48 PM · Restricted Project