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HsiangKai (Hsiangkai Wang)
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User Since
May 4 2016, 7:01 PM (246 w, 1 d)

Recent Activity

Today

HsiangKai committed rG5d354220d44f: [RISCV] Correct DWARF number for vector registers. (authored by HsiangKai).
[RISCV] Correct DWARF number for vector registers.
Thu, Jan 21, 7:46 PM
HsiangKai closed D94749: [RISCV] Correct DWARF number for vector registers..
Thu, Jan 21, 7:46 PM · Restricted Project
HsiangKai updated the diff for D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
  • Address @craig.topper's comments.
  • Update the test cases to use v8-v23 as arguments.
Thu, Jan 21, 7:30 PM · Restricted Project
HsiangKai added a comment to D95148: [RISCV] Spilling for RISC-V V extension. (2nd version).

Is this dependent on the frame lowering patch to emit the csrr vlenb?

Thu, Jan 21, 7:27 PM · Restricted Project
HsiangKai added a comment to D95148: [RISCV] Spilling for RISC-V V extension. (2nd version).

Is this patch dependent on https://reviews.llvm.org/D93614?

Yes, D93614 is landed.

Thu, Jan 21, 7:26 PM · Restricted Project
HsiangKai added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Thu, Jan 21, 7:25 PM · Restricted Project
HsiangKai added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Thu, Jan 21, 6:52 PM · Restricted Project
HsiangKai added a comment to D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics..

Put test cases to D95194, D95195, D95196, and D95197.

Thu, Jan 21, 6:50 PM · Restricted Project
HsiangKai updated the diff for D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics..
  • Update to v1.0.
Thu, Jan 21, 6:48 PM · Restricted Project
HsiangKai requested review of D95197: [RISCV] Add test cases for vsuxseg (RV64)..
Thu, Jan 21, 6:47 PM · Restricted Project
HsiangKai requested review of D95196: [RISCV] Add test cases for vsuxseg (RV32)..
Thu, Jan 21, 6:46 PM · Restricted Project
HsiangKai requested review of D95195: [RISCV] Add test cases for vsoxseg (RV64)..
Thu, Jan 21, 6:45 PM · Restricted Project
HsiangKai updated the diff for D94903: [RISCV] Implement vloxseg/vluxseg intrinsics..
Thu, Jan 21, 6:42 PM · Restricted Project
HsiangKai requested review of D95194: [RISCV] Add test cases for vsoxseg (RV32)..
Thu, Jan 21, 6:40 PM · Restricted Project
HsiangKai requested review of D95193: [RISCV] Add test cases for vluxseg (RV32)..
Thu, Jan 21, 6:39 PM · Restricted Project
HsiangKai requested review of D95192: [RISCV] Add test cases for vloxseg (RV64)..
Thu, Jan 21, 6:37 PM · Restricted Project
HsiangKai requested review of D95191: [RISCV] Add test cases for vloxseg (RV32)..
Thu, Jan 21, 6:34 PM · Restricted Project
HsiangKai requested review of D95190: [RISCV] Add test cases for vluxseg (RV64)..
Thu, Jan 21, 6:32 PM · Restricted Project
HsiangKai accepted D94286: [RISCV] Add a VL output to vleff intrinsics..

LGTM.

Thu, Jan 21, 5:02 PM · Restricted Project
HsiangKai committed rG6e360460f14b: [RISCV] Use v8-v23 as argument registers to conform to the proposal. (authored by HsiangKai).
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
Thu, Jan 21, 3:59 PM
HsiangKai closed D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal..
Thu, Jan 21, 3:59 PM · Restricted Project
HsiangKai added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

There are a lot of "Resolve for v1.0" issues open against the spec still. Are we sure we want to brand this as 1.0? It will end up as such in the ELF attributes and thus be deemed compatible with future "real" 1.0 binaries.

Thu, Jan 21, 3:47 PM · Restricted Project
HsiangKai added a comment to D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal..

Add a dedicated test file to demonstrate and verify the ABI would be better.

Thu, Jan 21, 3:36 PM · Restricted Project
HsiangKai committed rGb7ab6726b6de: [RISCV] New vector load/store in V extension v1.0 (authored by HsiangKai).
[RISCV] New vector load/store in V extension v1.0
Thu, Jan 21, 3:30 PM
HsiangKai closed D93614: [RISCV] New vector load/store in V extension v1.0.
Thu, Jan 21, 3:30 PM · Restricted Project
HsiangKai abandoned D93804: [RISCV] Spilling for RISC-V V extension..

Review D95148 instead of this one.

Thu, Jan 21, 9:29 AM · Restricted Project
HsiangKai requested review of D95148: [RISCV] Spilling for RISC-V V extension. (2nd version).
Thu, Jan 21, 9:28 AM · Restricted Project
HsiangKai committed rGb8921af63b0d: [RISCV] Update V instructions constraints to conform to v1.0 (authored by HsiangKai).
[RISCV] Update V instructions constraints to conform to v1.0
Thu, Jan 21, 9:16 AM
HsiangKai closed D93612: [RISCV] Update V instructions constraints to conform to v1.0.
Thu, Jan 21, 9:16 AM · Restricted Project
HsiangKai closed D93613: [RISCV] Add new V instructions and aliases in v1.0-08a0b46..

Landed in 266820be352d5b824cb01c93df1b00184fcc7803.

Thu, Jan 21, 9:15 AM · Restricted Project
HsiangKai closed D93611: [RISCV] Make LMUL field in VTYPE contiguous..

Landed in 9dd5aea1e0397f693a739bffb03fd94dc8e1ec79.

Thu, Jan 21, 9:14 AM · Restricted Project
HsiangKai committed rG266820be352d: [RISCV] Add new V instructions in v1.0-08a0b46. (authored by HsiangKai).
[RISCV] Add new V instructions in v1.0-08a0b46.
Thu, Jan 21, 9:00 AM
HsiangKai committed rG9dd5aea1e039: [RISCV] Make LMUL field in VTYPE continuous. (authored by HsiangKai).
[RISCV] Make LMUL field in VTYPE continuous.
Thu, Jan 21, 8:48 AM
HsiangKai updated the diff for D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

Use v1.0 instead of strange version number. It is under -enable-experimental-extensions. So, I think it should be ok to do this.

Thu, Jan 21, 8:39 AM · Restricted Project
HsiangKai updated the diff for D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics..
Thu, Jan 21, 7:29 AM · Restricted Project
HsiangKai updated the diff for D94903: [RISCV] Implement vloxseg/vluxseg intrinsics..
Thu, Jan 21, 7:28 AM · Restricted Project
HsiangKai requested review of D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal..
Thu, Jan 21, 7:11 AM · Restricted Project

Yesterday

HsiangKai committed rGa8b96eadfd93: [RISCV] Implement vssseg intrinsics. (authored by HsiangKai).
[RISCV] Implement vssseg intrinsics.
Wed, Jan 20, 7:53 PM
HsiangKai committed rGe5e329023bb1: [RISCV] Implement vlsseg intrinsics. (authored by HsiangKai).
[RISCV] Implement vlsseg intrinsics.
Wed, Jan 20, 7:53 PM
HsiangKai committed rG47228f785460: [RISCV] Implement vsseg intrinsics. (authored by HsiangKai).
[RISCV] Implement vsseg intrinsics.
Wed, Jan 20, 7:53 PM
HsiangKai closed D94863: [RISCV] Implement vssseg intrinsics..
Wed, Jan 20, 7:53 PM · Restricted Project
HsiangKai closed D94763: [RISCV] Implement vlsseg intrinsics..
Wed, Jan 20, 7:53 PM · Restricted Project
HsiangKai closed D94688: [RISCV] Implement vsseg intrinsics..
Wed, Jan 20, 7:53 PM · Restricted Project
HsiangKai updated the diff for D93614: [RISCV] New vector load/store in V extension v1.0.

Delete redundant test cases.

Wed, Jan 20, 4:54 AM · Restricted Project
HsiangKai updated the diff for D93614: [RISCV] New vector load/store in V extension v1.0.

Update test cases.

Wed, Jan 20, 4:50 AM · Restricted Project

Tue, Jan 19

HsiangKai committed rG8ca4b174d703: [RISCV] Implement vlseg intrinsics. (authored by HsiangKai).
[RISCV] Implement vlseg intrinsics.
Tue, Jan 19, 10:26 PM
HsiangKai closed D94229: [RISCV] Implement vlseg intrinsics..
Tue, Jan 19, 10:26 PM · Restricted Project
HsiangKai updated the diff for D93612: [RISCV] Update V instructions constraints to conform to v1.0.

Rebase.

Tue, Jan 19, 10:20 PM · Restricted Project
HsiangKai updated the diff for D93614: [RISCV] New vector load/store in V extension v1.0.

Rebase.

Tue, Jan 19, 10:20 PM · Restricted Project
HsiangKai updated the diff for D93613: [RISCV] Add new V instructions and aliases in v1.0-08a0b46..

Rebase.

Tue, Jan 19, 10:19 PM · Restricted Project
HsiangKai updated the diff for D93611: [RISCV] Make LMUL field in VTYPE contiguous..

Rebase.

Tue, Jan 19, 10:18 PM · Restricted Project
HsiangKai updated the diff for D94863: [RISCV] Implement vssseg intrinsics..

clang format.

Tue, Jan 19, 7:11 PM · Restricted Project
HsiangKai updated the diff for D94763: [RISCV] Implement vlsseg intrinsics..

clang format.

Tue, Jan 19, 7:10 PM · Restricted Project
HsiangKai updated the diff for D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics..

Add test cases for rv32. It does not contain all combinations for vsxseg due to the revision will be too large to upload.

Tue, Jan 19, 7:03 PM · Restricted Project
HsiangKai updated the diff for D94903: [RISCV] Implement vloxseg/vluxseg intrinsics..

Add test cases for rv32. It does not contain all combinations of vlxseg due to the revision will be too large to upload.

Tue, Jan 19, 7:00 PM · Restricted Project
HsiangKai updated the diff for D94863: [RISCV] Implement vssseg intrinsics..

Add test cases for rv32.

Tue, Jan 19, 6:42 PM · Restricted Project
HsiangKai updated the diff for D94763: [RISCV] Implement vlsseg intrinsics..
  • Add test cases for rv32.
  • Fix typo.
Tue, Jan 19, 6:41 PM · Restricted Project
HsiangKai updated the diff for D94688: [RISCV] Implement vsseg intrinsics..

Add test cases for rv32.

Tue, Jan 19, 6:35 PM · Restricted Project
HsiangKai updated the diff for D94229: [RISCV] Implement vlseg intrinsics..

Fix typo.

Tue, Jan 19, 6:34 PM · Restricted Project
HsiangKai updated the diff for D94229: [RISCV] Implement vlseg intrinsics..

Add test cases for rv32.

Tue, Jan 19, 6:31 PM · Restricted Project
HsiangKai accepted D94594: [RISCV] Extend RVV VType info with the type's AVL (NFC).

LGTM.

Tue, Jan 19, 7:35 AM · Restricted Project
HsiangKai added inline comments to D94286: [RISCV] Add a VL output to vleff intrinsics..
Tue, Jan 19, 6:14 AM · Restricted Project
HsiangKai accepted D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver.

LGTM.

Tue, Jan 19, 12:55 AM · Restricted Project
HsiangKai abandoned D91314: [RISCV] ELF attribute for Zfh extension..

D94931 is more complete.

Tue, Jan 19, 12:53 AM · Restricted Project
HsiangKai abandoned D91319: [RISCV] ELF attribute for B and V extension..

D94931 is more complete.

Tue, Jan 19, 12:51 AM · Restricted Project
HsiangKai added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

Do you consider to modify ELFObjectFileBase::getRISCVFeatures() in llvm/lib/Object/ELFObjectFile.cpp?

Tue, Jan 19, 12:48 AM · Restricted Project

Mon, Jan 18

HsiangKai requested review of D94940: [RISCV] Implement vsoxseg/vsuxseg intrinsics..
Mon, Jan 18, 7:25 PM · Restricted Project
HsiangKai requested review of D94903: [RISCV] Implement vloxseg/vluxseg intrinsics..
Mon, Jan 18, 3:04 AM · Restricted Project
HsiangKai updated the diff for D94863: [RISCV] Implement vssseg intrinsics..

Add test cases for floating point types.

Mon, Jan 18, 1:59 AM · Restricted Project
HsiangKai updated the diff for D94763: [RISCV] Implement vlsseg intrinsics..

Add test cases for floating point types.

Mon, Jan 18, 1:59 AM · Restricted Project
HsiangKai updated the diff for D94688: [RISCV] Implement vsseg intrinsics..

Add test cases for floating point types.

Mon, Jan 18, 1:58 AM · Restricted Project
HsiangKai updated the diff for D94229: [RISCV] Implement vlseg intrinsics..

Add test cases for floating point types.

Mon, Jan 18, 1:57 AM · Restricted Project

Sun, Jan 17

HsiangKai added a comment to D92715: [Clang][RISCV] Define RISC-V V builtin types.

Ping. If we all agree to use builtin types to model RVV types, is there any other issues we need to address in this patch?

Sun, Jan 17, 9:42 PM · Restricted Project

Sat, Jan 16

HsiangKai updated the diff for D94863: [RISCV] Implement vssseg intrinsics..

Rebase.

Sat, Jan 16, 6:09 PM · Restricted Project
HsiangKai updated the diff for D94763: [RISCV] Implement vlsseg intrinsics..

Rebase.

Sat, Jan 16, 6:08 PM · Restricted Project
HsiangKai updated the diff for D94688: [RISCV] Implement vsseg intrinsics..

Rebase.

Sat, Jan 16, 6:08 PM · Restricted Project
HsiangKai updated the diff for D94229: [RISCV] Implement vlseg intrinsics..

Rebase.

Sat, Jan 16, 6:02 PM · Restricted Project
HsiangKai committed rG098dbf190a55: [RISCV] Correct alignment settings for vector registers. (authored by HsiangKai).
[RISCV] Correct alignment settings for vector registers.
Sat, Jan 16, 7:22 AM
HsiangKai closed D94751: [RISCV] Correct alignment settings for vector registers..
Sat, Jan 16, 7:21 AM · Restricted Project
HsiangKai requested review of D94863: [RISCV] Implement vssseg intrinsics..
Sat, Jan 16, 5:43 AM · Restricted Project

Fri, Jan 15

HsiangKai committed rG619eb1477599: [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td. (authored by HsiangKai).
[NFC][RISCV] Remove useless code in RISCVRegisterInfo.td.
Fri, Jan 15, 4:09 AM
HsiangKai closed D94750: [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td..
Fri, Jan 15, 4:09 AM · Restricted Project
HsiangKai requested review of D94763: [RISCV] Implement vlsseg intrinsics..
Fri, Jan 15, 3:52 AM · Restricted Project

Thu, Jan 14

HsiangKai updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.

According to "9. Vector Memory Alignment Constraints" in V specification, change the alignment of RVV types to the element size.

Thu, Jan 14, 11:08 PM · Restricted Project
HsiangKai updated the summary of D94749: [RISCV] Correct DWARF number for vector registers..
Thu, Jan 14, 10:59 PM · Restricted Project
HsiangKai requested review of D94751: [RISCV] Correct alignment settings for vector registers..
Thu, Jan 14, 10:58 PM · Restricted Project
HsiangKai requested review of D94750: [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td..
Thu, Jan 14, 10:57 PM · Restricted Project
HsiangKai requested review of D94749: [RISCV] Correct DWARF number for vector registers..
Thu, Jan 14, 10:56 PM · Restricted Project
HsiangKai requested review of D94688: [RISCV] Implement vsseg intrinsics..
Thu, Jan 14, 7:09 AM · Restricted Project
HsiangKai updated the diff for D94229: [RISCV] Implement vlseg intrinsics..
Thu, Jan 14, 7:05 AM · Restricted Project

Wed, Jan 13

HsiangKai updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.

Recover comments.

Wed, Jan 13, 7:36 PM · Restricted Project
HsiangKai updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.

Refine debug info for RVV types.

Wed, Jan 13, 7:22 PM · Restricted Project
HsiangKai added a comment to D94403: [RISCV] Implement new architecture extension macros.

LGTM.

Wed, Jan 13, 6:03 PM · Restricted Project
HsiangKai accepted D94249: [RISCV] Custom lower ISD::VSCALE..

LGTM.

Wed, Jan 13, 5:05 PM · Restricted Project
HsiangKai commandeered D92715: [Clang][RISCV] Define RISC-V V builtin types.
Wed, Jan 13, 8:08 AM · Restricted Project
HsiangKai added a comment to D92715: [Clang][RISCV] Define RISC-V V builtin types.

@liaolucy RISC-V vector types are sizeless types. Sizeless is kind of characteristic for builtin types. If we use attribute to declare RISC-V vector types, the frontend does not know anything about it. I still think to define RISC-V vector types as builtin types is a better way.

Wed, Jan 13, 7:55 AM · Restricted Project
HsiangKai committed rG350c0552c66b: [NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32. (authored by HsiangKai).
[NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32.
Wed, Jan 13, 7:46 AM
HsiangKai closed D94584: [NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32..
Wed, Jan 13, 7:46 AM · Restricted Project
HsiangKai abandoned D93750: [RISCV] Frame handling for RISC-V V extension..

Let's focus on D94465. If there is anyone oppose it, I could reactivate this commit.

Wed, Jan 13, 7:26 AM · Restricted Project
HsiangKai added a comment to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).

I also think one direct memory access is better than two memory accesses. I abandoned D93750 first. If there is anyone oppose it, I could reactivate it.

Wed, Jan 13, 7:25 AM · Restricted Project