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evandro (Evandro Menezes)
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User Since
Jan 5 2016, 9:21 AM (284 w, 2 d)

Currently working at SiFive.

Recent Activity

Thu, Jun 10

evandro added a comment to D102535: [RISCV] -mno-relax: emit .option norelax.

Methinks that the choice of whether to relax or not should be decided outside of the assembler code. This directive sets the choice in stone and counters any choice done at build time, when optimizations are specified. For instance, when building a debug version, the optimizations may be different from when building a release version. This directive blocks such common practices and may create confusion and non expected results.

Thu, Jun 10, 4:40 PM · Restricted Project

Tue, May 25

evandro added a comment to D103004: [llvm-mc] Add -M to replace -riscv-no-aliases and -riscv-arch-reg-names.

I'm also not sure why the rvv tests use no-aliases. I think the majority were generated by a tool developed before I get here. I'll ask around internally.

Tue, May 25, 1:46 PM · Restricted Project
evandro added a comment to D103004: [llvm-mc] Add -M to replace -riscv-no-aliases and -riscv-arch-reg-names.

So, can we just delete them all?

Tue, May 25, 12:02 PM · Restricted Project

May 11 2021

evandro committed rG3a64b7080d50: [RISCV] Move instruction information into the RISCVII namespace (NFC) (authored by evandro).
[RISCV] Move instruction information into the RISCVII namespace (NFC)
May 11 2021, 2:33 PM
evandro closed D102268: [RISCV] Move instruction information into the namespace RISCVII (NFC).
May 11 2021, 2:33 PM · Restricted Project
evandro updated the diff for D102268: [RISCV] Move instruction information into the namespace RISCVII (NFC).
May 11 2021, 12:48 PM · Restricted Project
evandro added inline comments to D102268: [RISCV] Move instruction information into the namespace RISCVII (NFC).
May 11 2021, 12:34 PM · Restricted Project
evandro requested review of D102268: [RISCV] Move instruction information into the namespace RISCVII (NFC).
May 11 2021, 11:53 AM · Restricted Project

Apr 1 2021

evandro added inline comments to D98936: [RISCV] DAG nodes and pseudo instructions for CSR access.
Apr 1 2021, 8:54 AM · Restricted Project

Mar 29 2021

evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.

Rebase.

Mar 29 2021, 6:46 PM · Restricted Project
evandro added a comment to D98002: [RISCV] Add scheduling resources for V.

Adding those "sched" information into base RVV instructions seems redundant? The scheduler works on PseudoRVV instructions.

Mar 29 2021, 6:45 PM · Restricted Project
evandro committed rGfd94cfeeb5d2: [RISCV] Move scheduling resources for B into a separate file (NFC) (authored by evandro).
[RISCV] Move scheduling resources for B into a separate file (NFC)
Mar 29 2021, 6:38 PM
evandro closed D99557: [RISCV] Move scheduling resources for B into a separate file (NFC).
Mar 29 2021, 6:38 PM · Restricted Project
evandro requested review of D99557: [RISCV] Move scheduling resources for B into a separate file (NFC).
Mar 29 2021, 6:15 PM · Restricted Project
evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.

Rebased.

Mar 29 2021, 5:49 PM · Restricted Project

Mar 26 2021

evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.
Mar 26 2021, 2:35 PM · Restricted Project
evandro added inline comments to D98002: [RISCV] Add scheduling resources for V.
Mar 26 2021, 2:13 PM · Restricted Project
evandro accepted D99040: [RISCV] Add scheduler classes for the Zba and Zbb extensions..
Mar 26 2021, 2:07 PM · Restricted Project

Mar 24 2021

evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.
Mar 24 2021, 9:36 AM · Restricted Project
evandro added inline comments to D98002: [RISCV] Add scheduling resources for V.
Mar 24 2021, 9:19 AM · Restricted Project

Mar 23 2021

evandro added a comment to D99040: [RISCV] Add scheduler classes for the Zba and Zbb extensions..

Add multiclass for unsupported subextensions

Mar 23 2021, 4:29 PM · Restricted Project
evandro added a comment to D99040: [RISCV] Add scheduler classes for the Zba and Zbb extensions..

This seems like a sensible level of granularity and reuse of existing resources.

Mar 23 2021, 1:10 PM · Restricted Project

Mar 22 2021

evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.
Mar 22 2021, 2:43 PM · Restricted Project
evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.
Mar 22 2021, 12:41 PM · Restricted Project
evandro updated the diff for D98002: [RISCV] Add scheduling resources for V.

Add the mask operand.

Mar 22 2021, 12:12 PM · Restricted Project
evandro added inline comments to D98002: [RISCV] Add scheduling resources for V.
Mar 22 2021, 12:09 PM · Restricted Project

Mar 18 2021

evandro accepted D98911: [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg..
Mar 18 2021, 6:19 PM · Restricted Project

Mar 16 2021

evandro added a comment to D98002: [RISCV] Add scheduling resources for V.

I'm curious how instruction scheduling works if you don't add those resource models into the PseudoRVV instructions?

Mar 16 2021, 12:46 PM · Restricted Project

Mar 5 2021

evandro added a comment to D98002: [RISCV] Add scheduling resources for V.

I'm curious about why there is no any load/store scheduling resources?

Mar 5 2021, 10:14 AM · Restricted Project

Mar 4 2021

evandro requested review of D98002: [RISCV] Add scheduling resources for V.
Mar 4 2021, 7:49 PM · Restricted Project

Feb 16 2021

evandro closed D95049: [doc] Use cmake's -S option to simplify the build instructions.
Feb 16 2021, 1:44 PM · Restricted Project
evandro committed rG8eda10ca09c2: [doc] Use cmake's -S option to simplify the build instructions (authored by ebraminio).
[doc] Use cmake's -S option to simplify the build instructions
Feb 16 2021, 12:47 PM

Jan 29 2021

evandro added a comment to D95049: [doc] Use cmake's -S option to simplify the build instructions.

Thanks for the review :) So guess can be merged now?

Jan 29 2021, 1:56 PM · Restricted Project

Jan 25 2021

evandro added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

Also, when the V spec becomes official, it'll be labeled v2.0. Therefore, as long as v0.9 or v1.0 is implemented, V is only available as an experimental feature.

Jan 25 2021, 5:23 PM · Restricted Project, Restricted Project

Jan 22 2021

evandro abandoned D95281: [RISCV] Add the `vfneg` alias test.

Test is already in aliases.s.

Jan 22 2021, 5:56 PM · Restricted Project
evandro updated the diff for D95281: [RISCV] Add the `vfneg` alias test.
Jan 22 2021, 5:53 PM · Restricted Project
evandro updated the diff for D95281: [RISCV] Add the `vfneg` alias test.
Jan 22 2021, 5:51 PM · Restricted Project
evandro retitled D95281: [RISCV] Add the `vfneg` alias test from [RISCV] Add the `vfneg` alias to [RISCV] Add the `vfneg` alias test.
Jan 22 2021, 5:46 PM · Restricted Project
evandro requested review of D95281: [RISCV] Add the `vfneg` alias test.
Jan 22 2021, 5:37 PM · Restricted Project
evandro accepted D95049: [doc] Use cmake's -S option to simplify the build instructions.
Jan 22 2021, 2:07 PM · Restricted Project

Jan 15 2021

evandro requested changes to D73643: [RISCV] Macro Fusion for RISC-V.
Jan 15 2021, 6:34 PM · Restricted Project
evandro accepted D94566: [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF..
Jan 15 2021, 6:32 PM · Restricted Project

Jan 11 2021

evandro committed rG7470017f2472: [RISCV] Define the vfclass RVV intrinsics (authored by evandro).
[RISCV] Define the vfclass RVV intrinsics
Jan 11 2021, 3:40 PM
evandro closed D94356: [RISCV] Define the vfclass RVV intrinsics.
Jan 11 2021, 3:40 PM · Restricted Project

Jan 8 2021

evandro updated the diff for D94356: [RISCV] Define the vfclass RVV intrinsics.
Jan 8 2021, 6:57 PM · Restricted Project
evandro requested review of D94356: [RISCV] Define the vfclass RVV intrinsics.
Jan 8 2021, 6:55 PM · Restricted Project
evandro accepted D94299: [NFC][AsmPrinter] Make comments for spill/reload more precise..

If you happen to have a test case, please, consider adding it.

Jan 8 2021, 7:58 AM · Restricted Project

Jan 7 2021

evandro committed rG946bc50e4cbb: [RISCV] Define the vfsqrt RVV intrinsics (authored by evandro).
[RISCV] Define the vfsqrt RVV intrinsics
Jan 7 2021, 3:42 PM
evandro closed D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Jan 7 2021, 3:42 PM · Restricted Project

Jan 6 2021

evandro added inline comments to D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Jan 6 2021, 1:54 PM · Restricted Project

Jan 5 2021

evandro added inline comments to D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Jan 5 2021, 7:35 AM · Restricted Project

Jan 4 2021

evandro accepted D91834: [SelectionDAG] Use TypeSize for the stack offset..

LGTM

Jan 4 2021, 6:45 PM · Restricted Project
evandro committed rGd51d72bbb91b: [RISCV] Rename RVV intrinsics class (NFC) (authored by evandro).
[RISCV] Rename RVV intrinsics class (NFC)
Jan 4 2021, 6:36 PM
evandro added a comment to D94035: [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'.

LGTM

Jan 4 2021, 5:42 PM · Restricted Project
evandro updated the diff for D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Jan 4 2021, 5:17 PM · Restricted Project

Dec 23 2020

evandro updated the diff for D93745: [RISCV] Define the vfsqrt RVV intrinsics.

Address @HsiangKai's comments.

Dec 23 2020, 6:21 PM · Restricted Project

Dec 22 2020

evandro committed rG4d479443934a: [RISCV] Define the vfmin, vfmax RVV intrinsics (authored by evandro).
[RISCV] Define the vfmin, vfmax RVV intrinsics
Dec 22 2020, 10:29 PM
evandro closed D93673: [RISCV] Define the vfmin, vfmax RVV intrinsics.
Dec 22 2020, 10:28 PM · Restricted Project
evandro requested review of D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Dec 22 2020, 9:57 PM · Restricted Project

Dec 21 2020

evandro requested review of D93673: [RISCV] Define the vfmin, vfmax RVV intrinsics.
Dec 21 2020, 5:45 PM · Restricted Project
evandro committed rGed73a78924a8: [RISCV] Define the vand, vor and vxor RVV intrinsics (authored by evandro).
[RISCV] Define the vand, vor and vxor RVV intrinsics
Dec 21 2020, 2:21 PM
evandro closed D93574: [RISCV] Define the vand, vor and vxor intrinsics.
Dec 21 2020, 2:21 PM · Restricted Project

Dec 18 2020

evandro requested review of D93574: [RISCV] Define the vand, vor and vxor intrinsics.
Dec 18 2020, 6:47 PM · Restricted Project
evandro accepted D93487: [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen..

LGTM

Dec 18 2020, 8:50 AM · Restricted Project

Dec 14 2020

evandro added a comment to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..

RV32 tests are also needed, please.

Dec 14 2020, 7:01 PM · Restricted Project
evandro accepted D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..

LGTM, but, please, see if any of the lint notices can be addressed before committing.

Dec 14 2020, 3:47 PM · Restricted Project

Dec 11 2020

evandro added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 11 2020, 6:03 PM · Restricted Project

Dec 10 2020

evandro added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 10 2020, 6:06 PM · Restricted Project
evandro added a comment to D92973: [RISCV] Add intrinsics for vsetvli instruction.

The default should be ta and mu. The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.

Dec 10 2020, 4:35 PM · Restricted Project
evandro added a comment to D92228: [RISCV] Add MIR tests exposing missed InstAliases.

One of the suggestions made in that thread is teaching RA new tricks, which I don't feel qualified to do :) (I envision that if RA were able to dynamically limit the valid registers, as it assigns registers to operands, by virtue of some target-specific constraints, then, perhaps, this would be doable. But tbh I have no idea such approach is even feasible in the current RA. If we could do that we could also solve the case where v0 can't be used as the destination of masked instructions).

The other suggestion is to amend the instructions after RA in a specific pass. Seems doable at first but I am afraid this is going to be testing hell just to make sure no instruction manages to escape from that pass incorrectly.

Dec 10 2020, 9:24 AM · Restricted Project

Dec 7 2020

evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 3:44 PM · Restricted Project
evandro added inline comments to D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 3:36 PM · Restricted Project

Dec 5 2020

evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 5 2020, 2:16 PM · Restricted Project
evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 5 2020, 2:12 PM · Restricted Project

Dec 4 2020

evandro requested review of D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 4 2020, 9:21 PM · Restricted Project
evandro committed rG3c12307c7a05: [RISCV] Formatting for easier reading (NFC) (authored by HsiangKai).
[RISCV] Formatting for easier reading (NFC)
Dec 4 2020, 9:15 PM
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Dec 4 2020, 7:12 PM · Restricted Project

Nov 25 2020

evandro accepted D91987: [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd.
Nov 25 2020, 2:36 PM · Restricted Project

Nov 24 2020

evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 12:05 PM · Restricted Project
evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 11:04 AM · Restricted Project
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 10:51 AM · Restricted Project

Nov 23 2020

evandro accepted D91977: [RISCV] Remove unused VM register class.
Nov 23 2020, 11:15 AM · Restricted Project

Nov 6 2020

evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 6 2020, 5:41 PM · Restricted Project

Oct 23 2020

evandro committed rGfe9a7d962781: [RISCV] Use the commercial name for scheduling model (NFC) (authored by evandro).
[RISCV] Use the commercial name for scheduling model (NFC)
Oct 23 2020, 2:34 PM

Oct 19 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

Supporting old names without change of function is sensible, but, in this case, the bit fields in satp are different from stpbr. Then, the sensible result should be an error, because the code does need to be ported to the new version of the spec.

Oct 19 2020, 4:58 PM · Restricted Project

Oct 16 2020

evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 6:50 PM · Restricted Project
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 6:09 PM · Restricted Project

Oct 15 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

This is a wider discussion, but I would favor following the ratified specs, with exceptions on specific cases. I would also favor that the toolchain would enforce compliance on its own, even if more currently than an official, yet non compliant, compliance test suite.

Oct 15 2020, 8:59 AM · Restricted Project
evandro added a comment to D78764: [RISCV] Update debug scratch register names.

Note: this patch maintains backwards compatibility with a preliminary spec.

Oct 15 2020, 8:52 AM · Restricted Project

Oct 14 2020

evandro requested review of D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 14 2020, 10:53 PM · Restricted Project
evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

I agree with @jrtc27. What's the motivation to support a register name obsoleted by a ratified spec?

Oct 14 2020, 1:08 PM · Restricted Project

Oct 13 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

It LGTM, but it's better to wait a couple of days before committing in order to give others time to comment.

Oct 13 2020, 4:57 PM · Restricted Project

Oct 5 2020

evandro committed rGa48d480e1f7e: [RISCV] Fix broken test (authored by evandro).
[RISCV] Fix broken test
Oct 5 2020, 5:40 PM
evandro committed rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option (authored by evandro).
[RISCV] Add SiFive cores to the CPU option
Oct 5 2020, 1:58 PM
evandro committed rGed88d962953c: [RISCV] Use the extensions in the canonical order (NFC) (authored by evandro).
[RISCV] Use the extensions in the canonical order (NFC)
Oct 5 2020, 1:58 PM
evandro closed D88759: [RISCV] Add SiFive cores to the CPU option.
Oct 5 2020, 1:58 PM · Restricted Project, Restricted Project

Oct 2 2020

evandro committed rGa0a8f8371845: [PATCH] Fix typo (NFC) (authored by evandro).
[PATCH] Fix typo (NFC)
Oct 2 2020, 7:23 PM
evandro requested review of D88759: [RISCV] Add SiFive cores to the CPU option.
Oct 2 2020, 3:40 PM · Restricted Project, Restricted Project

Sep 29 2020

evandro committed rGc6b18cf9672b: [RISCV] Use the extensions in the canonical order (NFC) (authored by evandro).
[RISCV] Use the extensions in the canonical order (NFC)
Sep 29 2020, 6:03 PM
evandro accepted D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV..

LGTM

Sep 29 2020, 1:26 PM · Restricted Project