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evandro (Evandro Menezes)
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User Since
Jan 5 2016, 9:21 AM (263 w, 2 d)

Currently working at SiFive.

Recent Activity

Fri, Jan 15

evandro requested changes to D73643: [RISCV] Macro Fusion for RISC-V.
Fri, Jan 15, 6:34 PM · Restricted Project
evandro accepted D94566: [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF..
Fri, Jan 15, 6:32 PM · Restricted Project

Mon, Jan 11

evandro committed rG7470017f2472: [RISCV] Define the vfclass RVV intrinsics (authored by evandro).
[RISCV] Define the vfclass RVV intrinsics
Mon, Jan 11, 3:40 PM
evandro closed D94356: [RISCV] Define the vfclass RVV intrinsics.
Mon, Jan 11, 3:40 PM · Restricted Project

Fri, Jan 8

evandro updated the diff for D94356: [RISCV] Define the vfclass RVV intrinsics.
Fri, Jan 8, 6:57 PM · Restricted Project
evandro requested review of D94356: [RISCV] Define the vfclass RVV intrinsics.
Fri, Jan 8, 6:55 PM · Restricted Project
evandro accepted D94299: [NFC][AsmPrinter] Make comments for spill/reload more precise..

If you happen to have a test case, please, consider adding it.

Fri, Jan 8, 7:58 AM · Restricted Project

Thu, Jan 7

evandro committed rG946bc50e4cbb: [RISCV] Define the vfsqrt RVV intrinsics (authored by evandro).
[RISCV] Define the vfsqrt RVV intrinsics
Thu, Jan 7, 3:42 PM
evandro closed D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Thu, Jan 7, 3:42 PM · Restricted Project

Wed, Jan 6

evandro added inline comments to D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Wed, Jan 6, 1:54 PM · Restricted Project

Tue, Jan 5

evandro added inline comments to D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Tue, Jan 5, 7:35 AM · Restricted Project

Mon, Jan 4

evandro accepted D91834: [SelectionDAG] Use TypeSize for the stack offset..

LGTM

Mon, Jan 4, 6:45 PM · Restricted Project
evandro committed rGd51d72bbb91b: [RISCV] Rename RVV intrinsics class (NFC) (authored by evandro).
[RISCV] Rename RVV intrinsics class (NFC)
Mon, Jan 4, 6:36 PM
evandro added a comment to D94035: [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'.

LGTM

Mon, Jan 4, 5:42 PM · Restricted Project
evandro updated the diff for D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Mon, Jan 4, 5:17 PM · Restricted Project

Wed, Dec 23

evandro updated the diff for D93745: [RISCV] Define the vfsqrt RVV intrinsics.

Address @HsiangKai's comments.

Wed, Dec 23, 6:21 PM · Restricted Project

Dec 22 2020

evandro committed rG4d479443934a: [RISCV] Define the vfmin, vfmax RVV intrinsics (authored by evandro).
[RISCV] Define the vfmin, vfmax RVV intrinsics
Dec 22 2020, 10:29 PM
evandro closed D93673: [RISCV] Define the vfmin, vfmax RVV intrinsics.
Dec 22 2020, 10:28 PM · Restricted Project
evandro requested review of D93745: [RISCV] Define the vfsqrt RVV intrinsics.
Dec 22 2020, 9:57 PM · Restricted Project

Dec 21 2020

evandro requested review of D93673: [RISCV] Define the vfmin, vfmax RVV intrinsics.
Dec 21 2020, 5:45 PM · Restricted Project
evandro committed rGed73a78924a8: [RISCV] Define the vand, vor and vxor RVV intrinsics (authored by evandro).
[RISCV] Define the vand, vor and vxor RVV intrinsics
Dec 21 2020, 2:21 PM
evandro closed D93574: [RISCV] Define the vand, vor and vxor intrinsics.
Dec 21 2020, 2:21 PM · Restricted Project

Dec 18 2020

evandro requested review of D93574: [RISCV] Define the vand, vor and vxor intrinsics.
Dec 18 2020, 6:47 PM · Restricted Project
evandro accepted D93487: [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen..

LGTM

Dec 18 2020, 8:50 AM · Restricted Project

Dec 14 2020

evandro added a comment to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..

RV32 tests are also needed, please.

Dec 14 2020, 7:01 PM · Restricted Project
evandro accepted D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..

LGTM, but, please, see if any of the lint notices can be addressed before committing.

Dec 14 2020, 3:47 PM · Restricted Project

Dec 11 2020

evandro added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 11 2020, 6:03 PM · Restricted Project

Dec 10 2020

evandro added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 10 2020, 6:06 PM · Restricted Project
evandro added a comment to D92973: [RISCV] Add intrinsics for vsetvli instruction.

The default should be ta and mu. The compiler is usually agnostic about the tail of the vector, but usually assumes that masked elements are preserved.

Dec 10 2020, 4:35 PM · Restricted Project
evandro added a comment to D92228: [RISCV] Add MIR tests exposing missed InstAliases.

One of the suggestions made in that thread is teaching RA new tricks, which I don't feel qualified to do :) (I envision that if RA were able to dynamically limit the valid registers, as it assigns registers to operands, by virtue of some target-specific constraints, then, perhaps, this would be doable. But tbh I have no idea such approach is even feasible in the current RA. If we could do that we could also solve the case where v0 can't be used as the destination of masked instructions).

The other suggestion is to amend the instructions after RA in a specific pass. Seems doable at first but I am afraid this is going to be testing hell just to make sure no instruction manages to escape from that pass incorrectly.

Dec 10 2020, 9:24 AM · Restricted Project

Dec 7 2020

evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 3:44 PM · Restricted Project
evandro added inline comments to D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 3:36 PM · Restricted Project

Dec 5 2020

evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 5 2020, 2:16 PM · Restricted Project
evandro updated the diff for D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 5 2020, 2:12 PM · Restricted Project

Dec 4 2020

evandro requested review of D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 4 2020, 9:21 PM · Restricted Project
evandro committed rG3c12307c7a05: [RISCV] Formatting for easier reading (NFC) (authored by HsiangKai).
[RISCV] Formatting for easier reading (NFC)
Dec 4 2020, 9:15 PM
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Dec 4 2020, 7:12 PM · Restricted Project

Nov 25 2020

evandro accepted D91987: [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd.
Nov 25 2020, 2:36 PM · Restricted Project

Nov 24 2020

evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 12:05 PM · Restricted Project
evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 11:04 AM · Restricted Project
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 24 2020, 10:51 AM · Restricted Project

Nov 23 2020

evandro accepted D91977: [RISCV] Remove unused VM register class.
Nov 23 2020, 11:15 AM · Restricted Project

Nov 6 2020

evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 6 2020, 5:41 PM · Restricted Project

Oct 23 2020

evandro committed rGfe9a7d962781: [RISCV] Use the commercial name for scheduling model (NFC) (authored by evandro).
[RISCV] Use the commercial name for scheduling model (NFC)
Oct 23 2020, 2:34 PM

Oct 19 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

Supporting old names without change of function is sensible, but, in this case, the bit fields in satp are different from stpbr. Then, the sensible result should be an error, because the code does need to be ported to the new version of the spec.

Oct 19 2020, 4:58 PM · Restricted Project

Oct 16 2020

evandro updated the diff for D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 6:50 PM · Restricted Project
evandro added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 6:09 PM · Restricted Project

Oct 15 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

This is a wider discussion, but I would favor following the ratified specs, with exceptions on specific cases. I would also favor that the toolchain would enforce compliance on its own, even if more currently than an official, yet non compliant, compliance test suite.

Oct 15 2020, 8:59 AM · Restricted Project
evandro added a comment to D78764: [RISCV] Update debug scratch register names.

Note: this patch maintains backwards compatibility with a preliminary spec.

Oct 15 2020, 8:52 AM · Restricted Project

Oct 14 2020

evandro requested review of D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 14 2020, 10:53 PM · Restricted Project
evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

I agree with @jrtc27. What's the motivation to support a register name obsoleted by a ratified spec?

Oct 14 2020, 1:08 PM · Restricted Project

Oct 13 2020

evandro added a comment to D89288: [RISCV] Enable the use of the old sptbr name.

It LGTM, but it's better to wait a couple of days before committing in order to give others time to comment.

Oct 13 2020, 4:57 PM · Restricted Project

Oct 5 2020

evandro committed rGa48d480e1f7e: [RISCV] Fix broken test (authored by evandro).
[RISCV] Fix broken test
Oct 5 2020, 5:40 PM
evandro committed rG5d6d8a2769b3: [RISCV] Add SiFive cores to the CPU option (authored by evandro).
[RISCV] Add SiFive cores to the CPU option
Oct 5 2020, 1:58 PM
evandro committed rGed88d962953c: [RISCV] Use the extensions in the canonical order (NFC) (authored by evandro).
[RISCV] Use the extensions in the canonical order (NFC)
Oct 5 2020, 1:58 PM
evandro closed D88759: [RISCV] Add SiFive cores to the CPU option.
Oct 5 2020, 1:58 PM · Restricted Project, Restricted Project

Oct 2 2020

evandro committed rGa0a8f8371845: [PATCH] Fix typo (NFC) (authored by evandro).
[PATCH] Fix typo (NFC)
Oct 2 2020, 7:23 PM
evandro requested review of D88759: [RISCV] Add SiFive cores to the CPU option.
Oct 2 2020, 3:40 PM · Restricted Project, Restricted Project

Sep 29 2020

evandro committed rGc6b18cf9672b: [RISCV] Use the extensions in the canonical order (NFC) (authored by evandro).
[RISCV] Use the extensions in the canonical order (NFC)
Sep 29 2020, 6:03 PM
evandro accepted D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV..

LGTM

Sep 29 2020, 1:26 PM · Restricted Project

Sep 25 2020

evandro committed rGa000580a8971: [RISCV] Update driver tests (authored by evandro).
[RISCV] Update driver tests
Sep 25 2020, 4:43 PM
evandro committed rG764c1b7a4db1: [RISCV] Scheduler description for Bullet (authored by compilerguy).
[RISCV] Scheduler description for Bullet
Sep 25 2020, 4:43 PM
evandro committed rG0291c471aad4: [RISCV] Fix formatting (NFC) (authored by evandro).
[RISCV] Fix formatting (NFC)
Sep 25 2020, 4:17 PM

Sep 24 2020

evandro committed rG1e66e723eb66: [RISCV] Merge the pipeline models for Rocket (authored by evandro).
[RISCV] Merge the pipeline models for Rocket
Sep 24 2020, 3:36 PM
evandro closed D87873: [RISCV] Merge the pipeline models for Rocket.
Sep 24 2020, 3:36 PM · Restricted Project

Sep 22 2020

evandro closed D85366: [RISCV] Do not mandate scheduling for CSR instructions.
Sep 22 2020, 10:47 AM · Restricted Project

Sep 21 2020

evandro updated the diff for D87873: [RISCV] Merge the pipeline models for Rocket.
Sep 21 2020, 5:38 PM · Restricted Project
evandro added a comment to D87873: [RISCV] Merge the pipeline models for Rocket.

Why not delete RISCVSchedRocket32.td?

Sep 21 2020, 3:14 PM · Restricted Project

Sep 17 2020

evandro requested review of D87873: [RISCV] Merge the pipeline models for Rocket.
Sep 17 2020, 4:58 PM · Restricted Project

Aug 25 2020

evandro updated the diff for D85366: [RISCV] Do not mandate scheduling for CSR instructions.
Aug 25 2020, 1:31 PM · Restricted Project

Aug 13 2020

evandro added a comment to D85366: [RISCV] Do not mandate scheduling for CSR instructions.

hasSideEffects may imply isNotDuplicable, especially when rematerializing, but the latter prevents duplication more extensively in the middle end (e.g., tail end duplication).

But why does that matter? If LLVM decides it's better to fork a code path then let it, whether it's a CSR instruction or not really does not matter, it's just I-cache usage. In fact that's another reason why I _wouldn't_ want this change to go through.

Aug 13 2020, 3:12 PM · Restricted Project

Aug 11 2020

evandro added a comment to D85366: [RISCV] Do not mandate scheduling for CSR instructions.

hasSideEffects may imply isNotDuplicable, especially when rematerializing, but the latter prevents duplication more extensively in the middle end (e.g., tail end duplication).
Indeed, isReMaterializable (default to false) applies here too.

Aug 11 2020, 2:48 PM · Restricted Project

Aug 5 2020

evandro requested review of D85366: [RISCV] Do not mandate scheduling for CSR instructions.
Aug 5 2020, 3:09 PM · Restricted Project

Jul 30 2020

evandro accepted D72031: [Scheduling] Create the missing dependency edges for store cluster.
Jul 30 2020, 4:39 PM · Restricted Project
evandro added a comment to D72031: [Scheduling] Create the missing dependency edges for store cluster.

I'm not familiar with the AMDGPU target, but the changes in these new tests seem harmless, except in CodeGen/AMDGPU/stack-realign.ll, where an instruction disappeared. Again, I'd defer to someone who works in this backend, perhaps @arsenm, to chime in.

Jul 30 2020, 7:12 AM · Restricted Project

Jul 28 2020

evandro accepted D80802: [RISCV] Upgrade RVV MC to v0.9..
Jul 28 2020, 3:19 PM · Restricted Project, Restricted Project

Jul 24 2020

evandro accepted D84139: [Scheduling] Improve group algorithm for store cluster.
Jul 24 2020, 11:48 AM · Restricted Project
evandro accepted D83588: [TableGen][CGS] Print better errors on overlapping InstRW.
Jul 24 2020, 11:27 AM · Restricted Project

Jul 22 2020

evandro added inline comments to D83588: [TableGen][CGS] Print better errors on overlapping InstRW.
Jul 22 2020, 3:31 PM · Restricted Project

Jul 21 2020

evandro added a comment to D84139: [Scheduling] Improve group algorithm for store cluster.

Other than that, it seems sensible.

Jul 21 2020, 12:52 PM · Restricted Project
evandro added a comment to D72031: [Scheduling] Create the missing dependency edges for store cluster.

The AMDGPU test change likely means nothing, but it'd be good if someone who maintains or work that target would ok it. I suggest giving it another week or so. Otherwise, it LGTM.

Jul 21 2020, 12:41 PM · Restricted Project

Jul 20 2020

evandro added inline comments to D83588: [TableGen][CGS] Print better errors on overlapping InstRW.
Jul 20 2020, 9:16 PM · Restricted Project

Jul 17 2020

evandro added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

Just a couple of nits, but otherwise it LGTM.

Jul 17 2020, 1:56 PM · Restricted Project, Restricted Project

Jul 13 2020

evandro added inline comments to D83588: [TableGen][CGS] Print better errors on overlapping InstRW.
Jul 13 2020, 11:41 AM · Restricted Project

Jul 10 2020

evandro added inline comments to D83588: [TableGen][CGS] Print better errors on overlapping InstRW.
Jul 10 2020, 2:26 PM · Restricted Project

Jul 9 2020

evandro accepted D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.
Jul 9 2020, 8:06 AM · Restricted Project

Jul 6 2020

evandro added inline comments to D82713: Improve stack object printing..
Jul 6 2020, 2:07 PM · Restricted Project

Jul 2 2020

evandro added inline comments to D82713: Improve stack object printing..
Jul 2 2020, 3:41 PM · Restricted Project

Jun 30 2020

evandro added inline comments to D82713: Improve stack object printing..
Jun 30 2020, 4:18 PM · Restricted Project

Jun 29 2020

evandro accepted D81213: [RISCV] Support experimental v extension v0.9..

It LGTM after D80802.

Jun 29 2020, 3:32 PM · Restricted Project

Jun 25 2020

evandro added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Jun 25 2020, 8:33 AM · Restricted Project, Restricted Project

Jun 19 2020

evandro added a comment to D81724: [MVT] Add new MVT types for RISC-V vector..

It LGTM, but it's better to wait for an OK from a couple or so of other reviewers to chime in.

Jun 19 2020, 12:32 PM · Restricted Project

Jun 15 2020

evandro added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Jun 15 2020, 12:40 PM · Restricted Project, Restricted Project

Jun 4 2020

evandro added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Jun 4 2020, 3:30 PM · Restricted Project, Restricted Project
evandro added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

Again, the clang part should be split in another patch and be made a child of D81188.

Jun 4 2020, 1:16 PM · Restricted Project, Restricted Project
evandro added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

It looks pretty GTM. At this point, I'd be fine with accepting this patch as the major issues seem to have already been addressed. Should there be any other minor issue, it could be addressed later.

Jun 4 2020, 12:42 PM · Restricted Project, Restricted Project

May 8 2020

evandro added inline comments to D79409: [InstCombine] Remove hasNoInfs check for pow(C,y) -> exp2(log2(C)*y).
May 8 2020, 1:58 PM · Restricted Project

May 6 2020

evandro added a comment to D78129: Add Marvell ThunderX3T110 support.
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, PAUnsupported.F);
May 6 2020, 5:04 PM · Restricted Project, Restricted Project
evandro added a comment to D79409: [InstCombine] Remove hasNoInfs check for pow(C,y) -> exp2(log2(C)*y).

No, the sign of log2(x) depends on whether x is less or greater than 1, not less or greater than 2.

May 6 2020, 5:04 PM · Restricted Project
evandro added a comment to D79409: [InstCombine] Remove hasNoInfs check for pow(C,y) -> exp2(log2(C)*y).

pow(x, -∞) → ∞ if |x| < 1 or 0 if |x| > 1
pow(x, +∞) → 0 if |x| < 1 or ∞ if |x| > 1
exp2(log2(x) * -∞)exp2(±∞) → ∞ if x < 2 or 0 if x > 2
exp2(log2(x) * +∞)exp2(±∞) → 0 if x < 2 or ∞ if x > 2

May 6 2020, 2:10 PM · Restricted Project