- User Since
- Jun 1 2015, 8:58 AM (287 w, 2 d)
Mon, Nov 30
It might be worth mentioning somewhere (the commit message?) why this isn't done by matching (rotl/rotr X, Bitwidth/2) as GREVI and then matching GORCI through that. Presumably we'd like to match GREVI of rotl/rotr too, for instance?
Good catch, thanks. LGTM.
That was next on my TODO list; LGTM.
Fri, Nov 27
I thought I'd put this up for review since it's (somehow) the first RISC-V MIR test, and in case anyone had looked into this before. I know @craig.topper has some experience with InstAlias.
Wed, Nov 25
Tue, Nov 24
Mon, Nov 23
removed ordering & simplified logic. added extra test.
Fri, Nov 20
LGTM. We can always revisit the grev/ror question as it applies both before and after this patch. At any rate, matching rotl/rotr to roli is a more logical default.
Thu, Nov 19
rebase & fix formatting
Wed, Nov 18
- Catch W before legalization; legalize to W
- Catch more GORCs
- Adjust fshl/fshr tests expectations
Tue, Nov 17
Mon, Nov 16
Apart from my nits, this makes sense to me. The only thing I don't fully get it where/why the original code asserted if the shift amount was >= 32.
Fri, Nov 13
The formatting was done by clang-format and it does look a little "off". We can go against it if people like.
Thu, Nov 12
Address Craig's feedback except:
- using macros; that can be a separate patch
- matching 'W before' legalization; will experiment with that
Out of curiosity, can you use anything like computeKnownBits in TableGen patterns or would we have to do something in C++?
Wed, Nov 11
LGTM; from a quick look I can't see anything that would need that glue. Do you have an idea why it was added?
Tue, Nov 10
Mon, Nov 9
Thu, Nov 5
Wed, Nov 4
@foad did you want to look over how codegen is affected by this fix before approving?
Tue, Nov 3
Nov 2 2020
The comment at the top of SelectRORIW says
Oct 30 2020
LGTM. That operand to FMV_W_X_RV64 does indeed look like it should always be i64.
Oct 29 2020
Would you be able to explain how spills & reloads of vector registers work with this method? Namely, LLVM can insert spills and reloads at any point in the instruction sequence (IIRC). I would imagine that this includes right between VSETVLI/PseudoInst pairs:
Oct 27 2020
Aside from my nitpicks, I was wondering if it's possible to add tests for the other strategies. Even if that involved a strategy that you could force on the command-line, since I know we don't have real TTIs just now. It would be nice to see that the pass behaves in the various ways it's meant to.
Oct 26 2020
Update test to show fixed codegen, and test renamed from underscores to hyphens.
Oct 23 2020
Extend the fix to any non-byte-sized vector element
Oct 22 2020
Oct 21 2020
Oct 19 2020
Oct 16 2020
Jun 8 2020
Apr 23 2020
Add a test case
Apr 21 2020
Apr 17 2020
Apr 16 2020
Apr 3 2020
Add documentation for adjustSchedDependency
Mar 31 2020
Updating Hexagon to use Def and Use terminology now seems too an intrusive change to me: there are also private functions updateLatency, restoreLatency`, changeLatency, isBestZeroLatency which all use Src and Dst. So I think I'll leave it be.
Mar 24 2020
Note that the best test I've found so far is this: