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frasercrmck (Fraser Cormack)
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User Since
Jun 1 2015, 8:58 AM (287 w, 2 d)

Recent Activity

Mon, Nov 30

frasercrmck added a comment to D92228: [RISCV] Add MIR tests exposing missed InstAliases.

Adding @arcbbb. Him and I were talking about maybe splitting masked and unmasked into separate instructions. We need to prevent masked instructions from using v0 as a destination. To do that we've been using @earlyclobber, but that prevents any source operand from being the same as the destination. To fix this it might be better to have separate masked and unmasked instructions. Then we won't use @earlyclobber and instead make the masked instruction forbid v0 as a destination with a register class constraint. Not sure how many additional instructions and pseudo instructions that will require. Thoughts?

Initially, I implemented the V instructions using separate classes for masked and unmasked instructions. You could see the difference from
https://reviews.llvm.org/D69987?vs=228607&id=229020#toc

We need to define some additional classes for masked instructions. After that, we could use multiclass to define unmasked/masked instructions at once.

Mon, Nov 30, 2:39 AM · Restricted Project
frasercrmck added a comment to D92286: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X)..

It might be worth mentioning somewhere (the commit message?) why this isn't done by matching (rotl/rotr X, Bitwidth/2) as GREVI and then matching GORCI through that. Presumably we'd like to match GREVI of rotl/rotr too, for instance?

Mon, Nov 30, 2:13 AM · Restricted Project
frasercrmck accepted D92289: [RISCV] Only combine (or (GREVI x, shamt), x) -> GORCI if shamt is a power of 2..

Good catch, thanks. LGTM.

Mon, Nov 30, 2:08 AM · Restricted Project
frasercrmck accepted D92295: [RISCV] Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2)..

That was next on my TODO list; LGTM.

Mon, Nov 30, 2:04 AM · Restricted Project
frasercrmck accepted D92253: [RISCV] Custom legalize bswap/bitreverse to GREVI with Zbp extension to enable them to combine with other GREVI instructions.

LGTM.

Mon, Nov 30, 2:01 AM · Restricted Project

Fri, Nov 27

frasercrmck added a comment to D92228: [RISCV] Add MIR tests exposing missed InstAliases.

I thought I'd put this up for review since it's (somehow) the first RISC-V MIR test, and in case anyone had looked into this before. I know @craig.topper has some experience with InstAlias.

Fri, Nov 27, 7:02 AM · Restricted Project
frasercrmck requested review of D92228: [RISCV] Add MIR tests exposing missed InstAliases.
Fri, Nov 27, 6:40 AM · Restricted Project
frasercrmck committed rG7793db35ca2c: [OpenCL] Check for extension string extension lookup (authored by erik2020).
[OpenCL] Check for extension string extension lookup
Fri, Nov 27, 5:22 AM
frasercrmck closed D90928: [OpenCL] Check for extension string extension lookup.
Fri, Nov 27, 5:22 AM · Restricted Project
frasercrmck accepted D92128: [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target..

Nice. LGTM.

Fri, Nov 27, 1:44 AM · Restricted Project

Wed, Nov 25

frasercrmck added inline comments to D92105: [RISCV] Add pre-emit pass to make more instructions compressible.
Wed, Nov 25, 9:28 AM · Restricted Project
frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Wed, Nov 25, 4:30 AM · Restricted Project
frasercrmck accepted D91479: [RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt..

LGTM.

Wed, Nov 25, 1:33 AM · Restricted Project

Tue, Nov 24

frasercrmck committed rGca1f2f2716b3: [RISCV] Combine GREVI sequences (authored by frasercrmck).
[RISCV] Combine GREVI sequences
Tue, Nov 24, 4:12 AM
frasercrmck closed D91877: [RISCV] Combine GREVI sequences.
Tue, Nov 24, 4:12 AM · Restricted Project

Mon, Nov 23

frasercrmck added reviewers for D91638: [RISCV] Add a proof-of-concept for supporting non-scalable vectors in RVV: evandro, rogfer01, craig.topper.
Mon, Nov 23, 9:30 AM · Restricted Project
frasercrmck updated the diff for D91877: [RISCV] Combine GREVI sequences.

removed ordering & simplified logic. added extra test.

Mon, Nov 23, 8:17 AM · Restricted Project
frasercrmck added inline comments to D91877: [RISCV] Combine GREVI sequences.
Mon, Nov 23, 7:40 AM · Restricted Project
frasercrmck added inline comments to D91479: [RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt..
Mon, Nov 23, 3:23 AM · Restricted Project

Fri, Nov 20

frasercrmck requested review of D91877: [RISCV] Combine GREVI sequences.
Fri, Nov 20, 9:22 AM · Restricted Project
frasercrmck accepted D91449: [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb..

LGTM. We can always revisit the grev/ror question as it applies both before and after this patch. At any rate, matching rotl/rotr to roli is a more logical default.

Fri, Nov 20, 4:04 AM · Restricted Project
frasercrmck added a comment to D91638: [RISCV] Add a proof-of-concept for supporting non-scalable vectors in RVV.

This is along the lines of the patch I was working on. I used a new .td file of patterns and started with 64 bit vector types based on the minimum VLEN from Evandro and Roger's RFC.

Fri, Nov 20, 2:33 AM · Restricted Project
frasercrmck accepted D91457: [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension.

LGTM.

Fri, Nov 20, 1:30 AM · Restricted Project

Thu, Nov 19

frasercrmck committed rGb14ea01f3bfa: [RISCV] Add test cases for missed grevi/greviw opportunities. NFC (authored by frasercrmck).
[RISCV] Add test cases for missed grevi/greviw opportunities. NFC
Thu, Nov 19, 10:49 AM
frasercrmck committed rG1ac9b548310c: [RISCV] Lower GREVI and GORCI as custom nodes (authored by frasercrmck).
[RISCV] Lower GREVI and GORCI as custom nodes
Thu, Nov 19, 10:17 AM
frasercrmck closed D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Thu, Nov 19, 10:17 AM · Restricted Project
frasercrmck updated the diff for D91259: [RISCV] Lower GREVI and GORCI as custom nodes.

rebase & fix formatting

Thu, Nov 19, 10:08 AM · Restricted Project

Wed, Nov 18

frasercrmck updated the diff for D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
  • Rebase
  • Catch W before legalization; legalize to W
  • Catch more GORCs
  • Adjust fshl/fshr tests expectations
Wed, Nov 18, 8:25 AM · Restricted Project

Tue, Nov 17

frasercrmck requested review of D91638: [RISCV] Add a proof-of-concept for supporting non-scalable vectors in RVV.
Tue, Nov 17, 8:55 AM · Restricted Project
frasercrmck added inline comments to D91441: [VP] Build VP SDNodes.
Tue, Nov 17, 3:55 AM · Restricted Project, Restricted Project

Mon, Nov 16

frasercrmck added inline comments to D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Mon, Nov 16, 7:45 AM · Restricted Project
frasercrmck accepted D90961: [RISCV] When matching SROIW, check all 64 bits of the OR mask.

Apart from my nits, this makes sense to me. The only thing I don't fully get it where/why the original code asserted if the shift amount was >= 32.

Mon, Nov 16, 6:48 AM · Restricted Project
frasercrmck committed rGfe9dc2e54a6d: [RISCV] Use a macro to simplify getTargetNodeName (authored by frasercrmck).
[RISCV] Use a macro to simplify getTargetNodeName
Mon, Nov 16, 1:40 AM
frasercrmck closed D91414: [RISCV] Use a macro to simplify getTargetNodeName.
Mon, Nov 16, 1:40 AM · Restricted Project
frasercrmck added a comment to D91414: [RISCV] Use a macro to simplify getTargetNodeName.
In D91414#2393793, @asb wrote:

I think moving NODE_NAME_CASE(foo) to the left so it's aligned where the case statement would be (same as the equivalent in X86ISelLowering and AMDGPUISelLowering) would be slightly better. I wouldn't be opposed to using // clang-format off to stop clang-format from reformatting (though it seems more common in LLVM right now to just ignore clang-format's preference).

But basically this looks good to me, and I leave it to your judgement if you want to further mess with the whitespace as suggested above. Thanks Fraser!

Mon, Nov 16, 1:35 AM · Restricted Project

Fri, Nov 13

frasercrmck added inline comments to D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Fri, Nov 13, 10:11 AM · Restricted Project
frasercrmck added a reviewer for D91414: [RISCV] Use a macro to simplify getTargetNodeName: asb.
Fri, Nov 13, 4:37 AM · Restricted Project
frasercrmck added a comment to D91414: [RISCV] Use a macro to simplify getTargetNodeName.

The formatting was done by clang-format and it does look a little "off". We can go against it if people like.

Fri, Nov 13, 4:36 AM · Restricted Project
frasercrmck requested review of D91414: [RISCV] Use a macro to simplify getTargetNodeName.
Fri, Nov 13, 4:34 AM · Restricted Project
frasercrmck added inline comments to D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Fri, Nov 13, 3:56 AM · Restricted Project

Thu, Nov 12

frasercrmck updated the diff for D91259: [RISCV] Lower GREVI and GORCI as custom nodes.

Address Craig's feedback except:

  • using macros; that can be a separate patch
  • matching 'W before' legalization; will experiment with that
Thu, Nov 12, 9:31 AM · Restricted Project
frasercrmck added inline comments to D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Thu, Nov 12, 9:29 AM · Restricted Project
frasercrmck accepted D90905: [RISCV] Add an ANDI to shift amount of FSL/FSR instructions.

Out of curiosity, can you use anything like computeKnownBits in TableGen patterns or would we have to do something in C++?

Thu, Nov 12, 3:53 AM · Restricted Project

Wed, Nov 11

frasercrmck added reviewers for D91259: [RISCV] Lower GREVI and GORCI as custom nodes: craig.topper, lewis-revill.
Wed, Nov 11, 6:59 AM · Restricted Project
frasercrmck requested review of D91259: [RISCV] Lower GREVI and GORCI as custom nodes.
Wed, Nov 11, 6:57 AM · Restricted Project
frasercrmck accepted D91199: [RISCV] Remove traces of Glue from RISCVISD::SELECT_CC.

LGTM; from a quick look I can't see anything that would need that glue. Do you have an idea why it was added?

Wed, Nov 11, 1:36 AM · Restricted Project

Tue, Nov 10

frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Tue, Nov 10, 11:02 AM · Restricted Project

Mon, Nov 9

frasercrmck accepted D91016: [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked..

LGTM

Mon, Nov 9, 2:16 AM · Restricted Project
frasercrmck accepted D91024: [RISCV] Add isel patterns for using PACK for zext.h and zext.w..

LGTM

Mon, Nov 9, 2:05 AM · Restricted Project
frasercrmck accepted D91023: [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal when Zbb extension is enabled..

LGTM.

Mon, Nov 9, 1:53 AM · Restricted Project

Thu, Nov 5

frasercrmck accepted D90826: [RISCV] Add isel patterns for fshl with immediate to select FSRI/FSRIW.

LGTM.

Thu, Nov 5, 12:27 AM · Restricted Project

Wed, Nov 4

frasercrmck committed rGf99580c1e578: [DAGCombine] Fix bug in load scalarization (authored by frasercrmck).
[DAGCombine] Fix bug in load scalarization
Wed, Nov 4, 11:09 AM
frasercrmck closed D78568: [DAGCombine] Fix bug in load scalarization.
Wed, Nov 4, 11:09 AM · Restricted Project
frasercrmck added a comment to D78568: [DAGCombine] Fix bug in load scalarization.

@foad did you want to look over how codegen is affected by this fix before approving?

Wed, Nov 4, 9:12 AM · Restricted Project
frasercrmck accepted D90668: [RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns..

LGTM

Wed, Nov 4, 6:58 AM · Restricted Project
frasercrmck accepted D90735: [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions..

LGTM

Wed, Nov 4, 3:58 AM · Restricted Project
frasercrmck added inline comments to D90546: [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI.
Wed, Nov 4, 3:17 AM · Restricted Project
frasercrmck added inline comments to D90546: [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI.
Wed, Nov 4, 2:43 AM · Restricted Project

Tue, Nov 3

frasercrmck accepted D90575: [RISCV] Add missing patterns for rotr with immediate for Zbb/Zbp extensions..

LGTM otherwise.

Tue, Nov 3, 12:59 AM · Restricted Project

Nov 2 2020

frasercrmck accepted D90586: [RISCV] Make SelectRORIW handle the commutability of OR..

LGTM.

Nov 2 2020, 3:56 AM · Restricted Project
frasercrmck added a comment to D90580: [RISCV] When matching RORIW, make sure the same input is given to both shifts..

The comment at the top of SelectRORIW says

Nov 2 2020, 2:00 AM · Restricted Project

Oct 30 2020

frasercrmck accepted D90444: [RISCV] Don't use DCI.CombineTo to replace a single result.

LGTM. That operand to FMV_W_X_RV64 does indeed look like it should always be i64.

Oct 30 2020, 2:11 AM · Restricted Project

Oct 29 2020

frasercrmck added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

Would you be able to explain how spills & reloads of vector registers work with this method? Namely, LLVM can insert spills and reloads at any point in the instruction sequence (IIRC). I would imagine that this includes right between VSETVLI/PseudoInst pairs:

Oct 29 2020, 1:01 AM · Restricted Project

Oct 27 2020

frasercrmck abandoned D89955: [ValueTracking] Recognize more integer abs idioms.
Oct 27 2020, 4:26 AM · Restricted Project
frasercrmck added a comment to D89955: [ValueTracking] Recognize more integer abs idioms.

Please can you explain the bigger problem here?
I'm not sure why the solution isn't: "just run the middle-end optimization passes, or don't expect good back-end codegen".

Oct 27 2020, 3:48 AM · Restricted Project
frasercrmck added a comment to D78203: [VP,Integer,#2] ExpandVectorPredication pass.

Aside from my nitpicks, I was wondering if it's possible to add tests for the other strategies. Even if that involved a strategy that you could force on the command-line, since I know we don't have real TTIs just now. It would be nice to see that the pass behaves in the various ways it's meant to.

Oct 27 2020, 3:21 AM · Restricted Project, Restricted Project
frasercrmck abandoned D76682: [LegalizeTypes] Handle gaps in legal vector types while widening loads.
Oct 27 2020, 2:53 AM · Restricted Project
frasercrmck added a comment to D76682: [LegalizeTypes] Handle gaps in legal vector types while widening loads.

This appears to have been committed by @craig.topper in D84463. Great minds, and all that.

Oct 27 2020, 2:48 AM · Restricted Project

Oct 26 2020

frasercrmck updated the diff for D78568: [DAGCombine] Fix bug in load scalarization.

Update test to show fixed codegen, and test renamed from underscores to hyphens.

Oct 26 2020, 7:08 AM · Restricted Project
frasercrmck committed rGffa6d2afa4a6: [DAGCombine] Add test case showing incorrect DAGCombine optimization (authored by frasercrmck).
[DAGCombine] Add test case showing incorrect DAGCombine optimization
Oct 26 2020, 5:44 AM
frasercrmck added a comment to D78568: [DAGCombine] Fix bug in load scalarization.

Looks good to me. You could pre-commit the test case and rebase this diff so we can see the effect on codegen.

Sure, I can do that. Is committing a test that "expects" incorrect codegen the done thing?

Yes, especially if it's only temporary and the checks are generated.

Oct 26 2020, 2:56 AM · Restricted Project
frasercrmck added a comment to D89955: [ValueTracking] Recognize more integer abs idioms.

This pattern already gets canonicalized by InstCombine (and there are no multi-use problems): https://llvm.godbolt.org/z/od9oq4 As such, it shouldn't be reaching the backend in this form.

Oct 26 2020, 2:41 AM · Restricted Project

Oct 23 2020

frasercrmck added a comment to D78568: [DAGCombine] Fix bug in load scalarization.

Looks good to me. You could pre-commit the test case and rebase this diff so we can see the effect on codegen.

Oct 23 2020, 8:19 AM · Restricted Project
frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 23 2020, 5:01 AM · Restricted Project
frasercrmck updated the diff for D78568: [DAGCombine] Fix bug in load scalarization.

Extend the fix to any non-byte-sized vector element

Oct 23 2020, 3:01 AM · Restricted Project

Oct 22 2020

frasercrmck requested review of D89955: [ValueTracking] Recognize more integer abs idioms.
Oct 22 2020, 6:19 AM · Restricted Project
frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 22 2020, 12:48 AM · Restricted Project

Oct 21 2020

frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 21 2020, 2:23 AM · Restricted Project

Oct 19 2020

frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 19 2020, 6:23 AM · Restricted Project

Oct 16 2020

frasercrmck added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 16 2020, 2:27 AM · Restricted Project

Jun 8 2020

frasercrmck added inline comments to D78568: [DAGCombine] Fix bug in load scalarization.
Jun 8 2020, 7:38 AM · Restricted Project

Apr 23 2020

frasercrmck updated the diff for D78568: [DAGCombine] Fix bug in load scalarization.

Add a test case

Apr 23 2020, 4:49 AM · Restricted Project
frasercrmck updated subscribers of D78568: [DAGCombine] Fix bug in load scalarization.
Apr 23 2020, 4:49 AM · Restricted Project

Apr 21 2020

frasercrmck added a comment to D78568: [DAGCombine] Fix bug in load scalarization.

Tests missing

Apr 21 2020, 10:14 AM · Restricted Project
frasercrmck created D78568: [DAGCombine] Fix bug in load scalarization.
Apr 21 2020, 9:10 AM · Restricted Project
frasercrmck committed rGc3a292961d84: Let targets adjust physical output- and anti-deps (authored by frasercrmck).
Let targets adjust physical output- and anti-deps
Apr 21 2020, 5:55 AM
frasercrmck closed D78380: Let the target adjust physical output- and anti-deps.
Apr 21 2020, 5:54 AM · Restricted Project
frasercrmck updated the diff for D78380: Let the target adjust physical output- and anti-deps.

rebase

Apr 21 2020, 2:39 AM · Restricted Project

Apr 17 2020

frasercrmck created D78380: Let the target adjust physical output- and anti-deps.
Apr 17 2020, 9:42 AM · Restricted Project
frasercrmck committed rGc819ef965363: Provide operand indices to adjustSchedDependency (authored by frasercrmck).
Provide operand indices to adjustSchedDependency
Apr 17 2020, 3:46 AM
frasercrmck closed D77135: Provide operand indices to adjustSchedDependency.
Apr 17 2020, 3:45 AM · Restricted Project

Apr 16 2020

frasercrmck added a comment to D76682: [LegalizeTypes] Handle gaps in legal vector types while widening loads.

Ping

Apr 16 2020, 1:33 AM · Restricted Project
frasercrmck added a comment to D77135: Provide operand indices to adjustSchedDependency.

Ping.

Apr 16 2020, 1:33 AM · Restricted Project

Apr 3 2020

frasercrmck added inline comments to D77135: Provide operand indices to adjustSchedDependency.
Apr 3 2020, 3:11 AM · Restricted Project
frasercrmck updated the diff for D77135: Provide operand indices to adjustSchedDependency.

Add documentation for adjustSchedDependency

Apr 3 2020, 3:11 AM · Restricted Project

Mar 31 2020

frasercrmck added a comment to D77135: Provide operand indices to adjustSchedDependency.

Updating Hexagon to use Def and Use terminology now seems too an intrusive change to me: there are also private functions updateLatency, restoreLatency`, changeLatency, isBestZeroLatency which all use Src and Dst. So I think I'll leave it be.

Mar 31 2020, 7:44 AM · Restricted Project
frasercrmck added inline comments to D77135: Provide operand indices to adjustSchedDependency.
Mar 31 2020, 7:44 AM · Restricted Project
frasercrmck set the repository for D76682: [LegalizeTypes] Handle gaps in legal vector types while widening loads to rG LLVM Github Monorepo.
Mar 31 2020, 4:23 AM · Restricted Project
frasercrmck created D77135: Provide operand indices to adjustSchedDependency.
Mar 31 2020, 4:23 AM · Restricted Project

Mar 24 2020

frasercrmck added a comment to D76682: [LegalizeTypes] Handle gaps in legal vector types while widening loads.

Note that the best test I've found so far is this:

Mar 24 2020, 3:43 AM · Restricted Project