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NickHung (PeiHsiangHung)
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User Since
May 17 2018, 7:42 AM (280 w, 3 d)

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Mar 29 2021

NickHung added a comment to D98002: [RISCV] Add scheduling resources for V.

Adding those "sched" information into base RVV instructions seems redundant? The scheduler works on PseudoRVV instructions.
SchedReadWrite needs to consider pseudo instructions with LMUL? Their latency should be different.

Mar 29 2021, 5:58 PM · Restricted Project, Restricted Project

Mar 23 2021

NickHung abandoned D99136: [RISCV] RVV stack needs two emergency stack slots..
Mar 23 2021, 1:19 AM · Restricted Project

Mar 22 2021

NickHung requested review of D99136: [RISCV] RVV stack needs two emergency stack slots..
Mar 22 2021, 8:05 PM · Restricted Project

Mar 16 2021

NickHung abandoned D93006: [RISCV] Initial support for RVV intrinsic.
Mar 16 2021, 11:57 PM · Restricted Project

Mar 8 2021

NickHung added a comment to D98002: [RISCV] Add scheduling resources for V.

I'm curious how instruction scheduling works if you don't add those resource models into the PseudoRVV instructions?

Mar 8 2021, 5:21 PM · Restricted Project, Restricted Project

Dec 10 2020

NickHung added inline comments to D93006: [RISCV] Initial support for RVV intrinsic.
Dec 10 2020, 6:11 PM · Restricted Project
NickHung added a comment to D93006: [RISCV] Initial support for RVV intrinsic.
In D93006#2447513, @craig.topper wrote:

Are you proposing to do custom isel in RISCVISelDAGToDAG.cpp using lookupPseudoByIntrinsicAndLMUL and not using the RISCVGenDAGISel.inc table? Do you have an implementation of that yet?

Dec 10 2020, 5:58 PM · Restricted Project
NickHung added inline comments to D93006: [RISCV] Initial support for RVV intrinsic.
Dec 10 2020, 5:40 PM · Restricted Project
NickHung requested review of D93006: [RISCV] Initial support for RVV intrinsic.
Dec 10 2020, 12:14 AM · Restricted Project

Dec 9 2020

NickHung added inline comments to D92973: [RISCV] Add intrinsics for vsetvli instruction.
Dec 9 2020, 10:28 PM · Restricted Project, Restricted Project
NickHung added inline comments to D92973: [RISCV] Add intrinsics for vsetvli instruction.
Dec 9 2020, 6:46 PM · Restricted Project, Restricted Project

Dec 6 2020

NickHung added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Dec 6 2020, 4:11 PM · Restricted Project

Oct 21 2020

NickHung added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

Could you demonstrate that RVV intrinsic can share the same infrastructure?

Oct 21 2020, 1:13 AM · Restricted Project
NickHung added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Oct 21 2020, 1:08 AM · Restricted Project

Oct 20 2020

NickHung abandoned D51607: [ELF] Fix bugzilla #38748 for option no-rosegment.
Oct 20 2020, 7:32 PM · lld

Sep 25 2018

NickHung added a comment to D52459: [ELF] - Use output section prediction when creating mergeable synthetic sections..

Filename matching seems not to be considered in this patch.

Sep 25 2018, 11:09 PM

Sep 5 2018

NickHung updated the diff for D51607: [ELF] Fix bugzilla #38748 for option no-rosegment.
Sep 5 2018, 4:20 PM · lld
NickHung added a project to D51607: [ELF] Fix bugzilla #38748 for option no-rosegment: lld.
Sep 5 2018, 4:18 PM · lld

Sep 3 2018

NickHung created D51607: [ELF] Fix bugzilla #38748 for option no-rosegment.
Sep 3 2018, 6:39 PM · lld

Aug 10 2018

NickHung added inline comments to D45788: Mitigate relocation overflow [part 1 of 2].
Aug 10 2018, 12:50 AM

Jun 27 2018

NickHung added inline comments to rL327871: [ELF] Add basic support for PPC LE.
Jun 27 2018, 5:50 PM
Herald added a reviewer for D44483: [ELF] Add basic support for PPC LE: • espindola.
Jun 27 2018, 5:45 PM