[RISCV] Add support for the vscale_range attribute

[frasercrmck]

Summary

This patch begins the process of supporting the vscale_range attribute
for RVV.

Most notably, this patch implements the attribute according to the
minimum and maximum values of VLEN according to specific V extensions
being compiled for. The minimum is taken using the minimum-known VLEN
(i.e., specified through the V or zvl*b extensions) and the maximum is
unconditionally taken as 65536. Both values are then divided by our
"bits per block" value, hardcoded to 64.

The backend can still be given more information about VLEN using the
-riscv-v-vector-bits-min and -riscv-v-vector-bits-max flags. This
means that the API it aims to replace,
TargetTransformInfo::getMaxVScale, may still generate better code with
its better knowledge. Those options override the values found in the
vscale_range attribute.

It is unclear whether we want to move those backend options up into the
frontend, whether we are able to allow the backend to infer all
information from the IR attribute, or whether we even want to do that;
that's a wider discussion.

[frasercrmck]

update usage in vein of AArch64:

• use vscale_range attribute to determine RVV vector bits min/max values
• if no attribute is present, use existing backend flags
• sanitize and pass RVV vector bits from RISCVTargetMachine through to RISCVSubtarget
• RISCVSubtarget just stores and reports

[frasercrmck]

This may be as far as we can take this patch without exposing RVV vectors bit control to the user/driver and having to worry about the concerns that spring from that: linking objects compiled with different RVV vector bits options, LTO, etc.

I believe that with the current state of the patch, the default, hard-coded vscale_range with values mandated by the spec, combined with the existing backend options for overrides, mean we're not losing any functionality.

[frasercrmck]

Ah no, my mistake. This would be a drop in functionality if getMaxVScale is removed, since its replacement only checks the IR attribute and will not be affected by our backend flags.

[craig.topper]

clang/lib/Basic/Targets/RISCV.cpp

291

Should we move RVVBitsPerBlock to RISCVTargetParser.def? Or some other place that can be shared between lllvm/lib/Target/RISCV/ and here?

[kito-cheng]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

108

RISC-V require VLEN in power of 2, multiples of 128 is constraint for SVE :p
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters

[frasercrmck]

• rebase
• move V VLEN bits-per-block (64), min (128), max (65536) defines into TargetParser.h
• clean up assertions

[frasercrmck]

clang/lib/Basic/Targets/RISCV.cpp

291

Good idea. I also added the "StdV" min/max values of 128/65536 in there. However, I just put them in TargetParser.h as putting them in the .def file felt a bit odd and you had to account for preprocessor logic. It still feels a little odd but I agree that sharing these values is important. Other targets have specific values in there so it's not unprecedented. It is target-adjacent data, even if it's not (currently) dependent on triples or cpus.

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

108

Yeah to be honest I was just being cheeky/lazy here :) Since our current implementation requires VLEN >= 128 we know that VLEN must always be a multiple of 128. But yes this isn't really the right way of coding it, even if it does the right thing. I've fixed that up now.

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

103

If clang always emits the attribute, are these options effectively dead for clang codegen?

[frasercrmck]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

103

Yes, that's a good point - I'd missed that. I'm not sure the best way of keeping that ability apart from moving the options up to clang and dealing with the fallout from that. Which I'm not even sure we can deal with yet?

Unless we make the options override the attribute, though that might be its own can of worms.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

103

Well we now have zvl which kinda solve the "min" problem at the frontend level.

Thinking about it again, though, maybe it's not such a bad thing to have clang emit min=<zvl>, max=2^16/RVVBitsPerBlock and then allow backend codegen flags to override that. Then the onus is clearly on the user not to do anything wrong. We could assert if the user-provided values are clearly at odds with the attribute?

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

103

I'm fine with that. I think we should consider dropping the riscv-v-vector-bits-min flag and just have a -riscv-v-fixed-width-vectorization-flag until we can prove that vectorization is robust. Bugs like D117663 make me nervous about blindly vectorizing code right now.

[frasercrmck]

rebase
take minimum from zvl extensions
allow backend options to override attribute values
add extra testing

[khchen]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

I'm thinking do we need to test zvl and vscale_range in the same attribute?
ex. attributes #0 = { vscale_range(2,1024) "target-features"="+zvl512b" }

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Perhaps yeah. Just to check - what exactly for? Because we need zvl in the attributes for correctness, or in order to test the combination of zvl architecture and vscale_range to test what happens when they disagree?

[paulwalker-arm]

Does this mean RISCVTTIImpl::getMaxVScale() can be removed?

[khchen]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Just test for they disagree.
Do you know what's expected value for different vscale_range value in two function after function inlining? If they are always have the same minimum value for VLEN, I think we don't need a check.

[frasercrmck]

In D107290#3268949, @paulwalker-arm wrote:

Does this mean RISCVTTIImpl::getMaxVScale() can be removed?

Good question. I'm unsure at this stage. At hinted at in the description, getMaxVScale can make use of backend-specific flags to hone the maximum down a bit, whereas relying on the attribute basically reduces us to the one value which the frontend will ever likely produce. So as it stands, the vscale_range attribute is not at feature parity with this TTI method. I think we'd have to come to a decision that this outcome is okay.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Good idea.

As for inlining, I can't see anything that would prevent inlining of functions with different vscale_range attributes, per se. However, I was looking at TTI::areInlineCompatible and the default implementation checks whether CPU/Feature Strings are equivalent. The frontend should ensure that vscale_range attributes match up 1:1 with our +zvl feature strings so I think in practice we won't inline functions with different zvl values in clang-generated C/C++ code. But users could write IR with different vscale_range attributes and we'd happily inline them, which sounds fishy. What do you think?

[khchen]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

99

Could we have an assertion to prevent RVVBitsMin and Zvl are different?

105

For forward compatibility, if there is no VScaleRangeAttr, maybe we could initialize the RVVBitsMin as zvl*b if it is present?
I guess maybe some exist IRs have zvl with no VScaleRangeAttr?

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Thanks for investigation!!!
I think we can postpone this inline issue until we really need to fix it.
at least the function would keep the feature string, which may include zvl*b, right?

BTW, could you please try the C code in https://godbolt.org/z/6hfTaxTj5 to see what's vscale_range value for function vadd256 and vadd512? Are they expected value?

[frasercrmck]

rebase
check for zvl feature strings alongside vscale_range

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

103

Yeah... I just realised that by taking vscale_range to mean -riscv-v-vector-bits-min, and us now using zvl to dictate vscale_range, we're effectively enabling fixed-length support by default now. I don't really want to introduce such a change in behaviour in this patch.

Maybe we should delay this patch until we have a -riscv-v-fixed-width-vector-support flag, or something, as you suggest. That or we emit vscale_range now but ignore it in the backend until such a change has been made.

105

It's complicated due to us using RVVBitsMin != 0 to also enable fixed-length vectorization. Defaulting that to our zvl*b extension is a change in behaviour. See the discussion with Craig above this one.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Yeah the feature string looks to contain zvl*b as we expect -- in simple cases (see below). I've updated this test to check for them too.

Thanks for the example! I tried it. We have a couple of issues.

Firstly, the vscale_range is not correctly set for the functions. It is taken from whichever zvl*b we set on the command line. If I do -target-feature +zvl128b all functions have vscale_range(2,1024), if I do -target-feature +zvl256b all functions have (4,1024), etc. So something's not being communicated properly.

The second issue is that, because of this (I think) when using the non-CC1 driver, the subtarget initialization crashes if I compile with -march=rv64gcv or any zvl*b up to -march=rv64gcv_zvl512b1p0 because the -march we specify there determines the vscale_range which in turn determines RVVBitsMin, but that's "lower than the Zvl*b limitation" so an assert triggers.

[khchen]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

163

Sorry, I have no idea about what's good way to fix them, or maybe RISC-V has not already supported ifunc then we could ignore this example, I'm not sure.

BTW, I'm wondering why we want to support vscale_range attribute in RISC-V V.
Could we get any benefit after supporting it?
It seems like SVE does not have a way to encode vector length information, so it must introduce a new function attribute vscale_range in IR.
But in RISC-V V, we already have zvl*b target-feature to get the minimum vlen information, and the maximum vlen is always 65536. In addition, we also have default implication rule for zvl*b depend on V/Zve*.

It seem like we are trying to support users's manually IRs which have vscale_range without zvl*b target-feature, is it?
Or am I misunderstanding the intention?

[reames]

Not knowing about this patch, I posted D135894 which addresses a small sub-set of this. If that goes in, I plan to iterative split off some other parts of this into stand alone changes.

[frasercrmck]

Superseded by D139873 amongst others

clang/lib/Basic/Targets/RISCV.h

initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
                  const std::vector<std::string> &FeaturesVec) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  Optional<std::pair<unsigned, unsigned>>
+  getVScaleRange(const LangOptions &LangOpts) const override;
 };
+
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
   RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : RISCVTargetInfo(Triple, Opts) {
     IntPtrType = SignedInt;
     PtrDiffType = SignedInt;
     SizeType = UnsignedInt;
     resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");

clang/lib/Basic/Targets/RISCV.cpp

bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   }
 
   if (ABI.empty())
     ABI = llvm::RISCV::computeDefaultABIFromArch(*ISAInfo).str();
 
   return true;
 }
 
+Optional<std::pair<unsigned, unsigned>>
+RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+  if (ISAInfo->getMinVLen() < llvm::RISCV::RVVVLENBitsMin)
+    return None;
+  // RVV's vscale is defined as VLEN/RVVBitsPerBlock.
+  return std::make_pair(ISAInfo->getMinVLen() / llvm::RISCV::RVVBitsPerBlock,
+                        llvm::RISCV::RVVVLENBitsMax /
+                            llvm::RISCV::RVVBitsPerBlock);
+}
+
 bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
                                    /*Is64Bit=*/false);
 }
 
 void RISCV32TargetInfo::fillValidCPUList(
     SmallVectorImpl<StringRef> &Values) const {
   llvm::RISCV::fillValidCPUArchList(Values, false);
 }
 

clang/test/CodeGen/RISCV/riscv-vscale-range.c

+// RUN: %clang_cc1 -triple riscv64 -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-NO-V
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x -target-feature +zvl32b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL32b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x -target-feature +zvl64b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL64b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-V
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl256b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL256b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL512b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl1024b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL1024b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl2048b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL2048b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl4096b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL4096b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl8192b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL8192b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl16384b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL16384b
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl32768b -S -emit-llvm -o - %s \
+// RUN:  | FileCheck %s --check-prefixes CHECK,CHECK-ZVL32768b
+
+// CHECK-LABEL: @func() #0
+// CHECK-NO-V-NOT: vscale_range
+// CHECK-ZVL32b-NOT: vscale_range
+// CHECK-ZVL64b: attributes #0 = { {{.*}} vscale_range(1,1024) {{.*}} "target-features"="+64bit,+zve32x,+zve64x,+zvl32b,+zvl64b"
+// CHECK-V: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl128b,+zvl32b,+zvl64b"
+// CHECK-ZVL256b: attributes #0 = { {{.*}} vscale_range(4,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl128b,+zvl256b,+zvl32b,+zvl64b"
+// CHECK-ZVL512b: attributes #0 = { {{.*}} vscale_range(8,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b"
+// CHECK-ZVL1024b: attributes #0 = { {{.*}} vscale_range(16,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b"
+// CHECK-ZVL2048b: attributes #0 = { {{.*}} vscale_range(32,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl2048b,+zvl256b,+zvl32b,+zvl512b,+zvl64b"
+// CHECK-ZVL4096b: attributes #0 = { {{.*}} vscale_range(64,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl2048b,+zvl256b,+zvl32b,+zvl4096b,+zvl512b,+zvl64b"
+// CHECK-ZVL8192b: attributes #0 = { {{.*}} vscale_range(128,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl2048b,+zvl256b,+zvl32b,+zvl4096b,+zvl512b,+zvl64b,+zvl8192b"
+// CHECK-ZVL16384b: attributes #0 = { {{.*}} vscale_range(256,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl16384b,+zvl2048b,+zvl256b,+zvl32b,+zvl4096b,+zvl512b,+zvl64b,+zvl8192b"
+// CHECK-ZVL32768b: attributes #0 = { {{.*}} vscale_range(512,1024) {{.*}} "target-features"="+64bit,+d,+f,+v,+zvl1024b,+zvl128b,+zvl16384b,+zvl2048b,+zvl256b,+zvl32768b,+zvl32b,+zvl4096b,+zvl512b,+zvl64b,+zvl8192b"
+void func() {}

llvm/include/llvm/Support/TargetParser.h

 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
 StringRef getMArchFromMcpu(StringRef CPU);
 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
 StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo);
 
+// We use 64 bits as the known part in the scalable vector types.
+static constexpr unsigned RVVBitsPerBlock = 64;
+// The specification-defined lower- and upper-bounds on VLEN supported by LLVM,
+// in bits. Note that Zvl* extensions may raise the minimum.
+// FIXME: The absolute minimum is technically 32 but we don't support it.
+static constexpr unsigned RVVVLENBitsMin = 64;
+static constexpr unsigned RVVVLENBitsMax = 65536;
+
 } // namespace RISCV
 
 namespace ARM {
 struct ParsedBranchProtection {
   StringRef Scope;
   StringRef Key;
   bool BranchTargetEnforcement;
 };

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
   /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
   /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
   /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
     return false;
   };
 };
 
-namespace RISCV {
-// We use 64 bits as the known part in the scalable vector types.
-static constexpr unsigned RVVBitsPerBlock = 64;
-} // namespace RISCV
-
 namespace RISCVVIntrinsicsTable {
 
 struct RISCVVIntrinsicInfo {
   unsigned IntrinsicID;
   uint8_t SplatOperand;
   uint8_t VLOperand;
   bool hasSplatOperand() const {
     // 0xF is not valid. See NoSplatOperand in IntrinsicsRISCV.td.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-lower"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   ExtZvl ZvlLen = ExtZvl::NotSet;
   MVT XLenVT = MVT::i32;
+  unsigned RVVVectorBitsMin;
+  unsigned RVVVectorBitsMax;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   BitVector UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
                                                   StringRef CPU,
                                                   StringRef TuneCPU,
                                                   StringRef FS,
                                                   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
-                 StringRef FS, StringRef ABIName, const TargetMachine &TM);
+                 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
+                 unsigned RVVVectorLMULMax, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
   const RISCVFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
public:
 
   // Maximum cost used for building integers, integers will be put into constant
   // pool if exceeded.
   unsigned getMaxBuildIntsCost() const;
 
   // Return the known range for the bit length of RVV data registers. A value
   // of 0 means nothing is known about that particular limit beyond what's
   // implied by the architecture.
-  unsigned getMaxRVVVectorSizeInBits() const;
-  unsigned getMinRVVVectorSizeInBits() const;
+  unsigned getMaxRVVVectorSizeInBits() const {
+    assert(hasVInstructions() &&
+           "Tried to get vector length without Zve or V extension support!");
+    // ZvlLen specifies the minimum required vlen. The upper bound provided by
+    // riscv-v-vector-bits-max should be no less than it.
+    if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
+      report_fatal_error("riscv-v-vector-bits-max specified is lower "
+                         "than the Zvl*b limitation");
+    return RVVVectorBitsMax;
+  }
+  unsigned getMinRVVVectorSizeInBits() const {
+    assert(hasVInstructions() &&
+           "Tried to get vector length without Zve or V extension support!");
+    // ZvlLen specifies the minimum required vlen. The lower bound provided by
+    // riscv-v-vector-bits-min should be no less than it.
+    if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
+      report_fatal_error("riscv-v-vector-bits-min specified is lower "
+                         "than the Zvl*b limitation");
+    return RVVVectorBitsMin;
+  }
   unsigned getMaxLMULForFixedLengthVectors() const;
   unsigned getMaxELENForFixedLengthVectors() const;
   bool useRVVForFixedLengthVectors() const;
 };
 } // End llvm namespace
 
 #endif

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
 
-static cl::opt<unsigned> RVVVectorBitsMax(
-    "riscv-v-vector-bits-max",
-    cl::desc("Assume V extension vector registers are at most this big, "
-             "with zero meaning no maximum size is assumed."),
-    cl::init(0), cl::Hidden);
-
-static cl::opt<unsigned> RVVVectorBitsMin(
-    "riscv-v-vector-bits-min",
-    cl::desc("Assume V extension vector registers are at least this big, "
-             "with zero meaning no minimum size is assumed."),
-    cl::init(0), cl::Hidden);
-
 static cl::opt<unsigned> RVVVectorLMULMax(
     "riscv-v-fixed-length-vector-lmul-max",
     cl::desc("The maximum LMUL value to use for fixed length vectors. "
              "Fractional LMUL values are not supported."),
     cl::init(8), cl::Hidden);
 
 static cl::opt<unsigned> RVVVectorELENMax(
     "riscv-v-fixed-length-vector-elen-max",
RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
 
   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
   RISCVFeatures::validate(TT, getFeatureBits());
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
                                StringRef TuneCPU, StringRef FS,
-                               StringRef ABIName, const TargetMachine &TM)
+                               StringRef ABIName, unsigned RVVVectorBitsMin,
+                               unsigned RVVVectorBitsMax,
+                               const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
+      RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
       UserReservedRegister(RISCV::NUM_TARGET_REGS),
-      FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
+      FrameLowering(
+          initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
   RegBankInfo.reset(RBI);
   InstSelector.reset(createRISCVInstructionSelector(
       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
   // instruction. Usually, address calculation and instructions used for
   // building integers (addi, slli, etc.) can be done in one cycle, so here we
   // set the default cost to (LoadLatency + 1) if no threshold is provided.
   return RISCVMaxBuildIntsCost == 0
              ? getSchedModel().LoadLatency + 1
              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
 }
 
-unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
-  assert(hasVInstructions() &&
-         "Tried to get vector length without Zve or V extension support!");
-  if (RVVVectorBitsMax == 0)
-    return 0;
-
-  // ZvlLen specifies the minimum required vlen. The upper bound provided by
-  // riscv-v-vector-bits-max should be no less than it.
-  if (RVVVectorBitsMax < ZvlLen)
-    report_fatal_error("riscv-v-vector-bits-max specified is lower "
-                       "than the Zvl*b limitation");
-
-  // FIXME: Change to >= 32 when VLEN = 32 is supported
-  assert(
-      RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
-      isPowerOf2_32(RVVVectorBitsMax) &&
-      "V or Zve* extension requires vector length to be in the range of 64 to "
-      "65536 and a power of 2!");
-  assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
-         "Minimum V extension vector length should not be larger than its "
-         "maximum!");
-  unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
-}
-
-unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
-  // ZvlLen specifies the minimum required vlen. The lower bound provided by
-  // riscv-v-vector-bits-min should be no less than it.
-  if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
-    report_fatal_error("riscv-v-vector-bits-min specified is lower "
-                       "than the Zvl*b limitation");
-
-  assert(hasVInstructions() &&
-         "Tried to get vector length without Zve or V extension support!");
-  // FIXME: Change to >= 32 when VLEN = 32 is supported
-  assert(
-      (RVVVectorBitsMin == 0 ||
-       (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
-        isPowerOf2_32(RVVVectorBitsMin))) &&
-      "V or Zve* extension requires vector length to be in the range of 64 to "
-      "65536 and a power of 2!");
-  assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
-         "Minimum V extension vector length should not be larger than its "
-         "maximum!");
-  unsigned Min = RVVVectorBitsMin;
-  if (RVVVectorBitsMax != 0)
-    Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
-  return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
-}
-
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
          "V extension requires a LMUL to be at most 8 and a power of 2!");
   return PowerOf2Floor(
       std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
 }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
+static cl::opt<unsigned> RVVVectorBitsMaxOpt(
+    "riscv-v-vector-bits-max",
+    cl::desc("Assume V extension vector registers are at most this big, "
+             "with zero meaning no maximum size is assumed."),
+    cl::init(0), cl::Hidden);
+
+static cl::opt<unsigned> RVVVectorBitsMinOpt(
+    "riscv-v-vector-bits-min",
+    cl::desc("Assume V extension vector registers are at least this big, "
+             "with zero meaning no minimum size is assumed."),
+    cl::init(0), cl::Hidden);
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVSExtWRemovalPass(*PR);

 }
 
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
+  unsigned RVVBitsMin = 0;
+  unsigned RVVBitsMax = 0;
+  Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
+  if (VScaleRangeAttr.isValid()) {
+    RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
+    if (VScaleRangeAttr.getVScaleRangeMax().hasValue())
+      RVVBitsMax =
+          *VScaleRangeAttr.getVScaleRangeMax() * RISCV::RVVBitsPerBlock;
+    else
+      RVVBitsMax = RISCV::RVVVLENBitsMax;
+  }
+  // Allow user options to override these.
+  if (RVVVectorBitsMinOpt)
+    RVVBitsMin = RVVVectorBitsMinOpt;
+  if (RVVVectorBitsMaxOpt)
+    RVVBitsMax = RVVVectorBitsMaxOpt;
+
+  assert((RVVBitsMin == 0 || isPowerOf2_32(RVVBitsMin)) &&
+         "RVV requires vector length to be a power of two!");
+  assert((RVVBitsMax == 0 || isPowerOf2_32(RVVBitsMax)) &&
+         "RVV requires vector length to be a power of two!");
+  assert((RVVBitsMin == 0 || RVVBitsMin >= RISCV::RVVVLENBitsMin) &&
+         "RVV vector size must be no smaller than the minimum allowed by the "
+         "specification!");
+  assert(RVVBitsMax <= RISCV::RVVVLENBitsMax &&
+         "RVV vector size must be no larger than the maximum allowed by the "
+         "specification!");
+  assert((RVVBitsMax == 0 || RVVBitsMax >= RVVBitsMin) &&
+         "Minimum RVV vector size should not be larger than its maximum!");
+
+  // Sanitize user input in case of no asserts.
+  if (RVVBitsMax != 0)
+    RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
+  RVVBitsMin = PowerOf2Floor(
+      (RVVBitsMin < RISCV::RVVVLENBitsMin || RVVBitsMin > RISCV::RVVVLENBitsMax)
+          ? 0
+          : RVVBitsMin);
+
+  RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
+  RVVBitsMax = PowerOf2Floor(
+      (RVVBitsMax < RISCV::RVVVLENBitsMin || RVVBitsMax > RISCV::RVVVLENBitsMax)
+          ? 0
+          : RVVBitsMax);
+
   std::string CPU =
       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
   std::string TuneCPU =
       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
+
   std::string Key = CPU + TuneCPU + FS;
+  Key += "RVVMin";
+  Key += std::to_string(RVVBitsMin);
+  Key += "RVVMax";
+  Key += std::to_string(RVVBitsMax);
+
   auto &I = SubtargetMap[Key];
   if (!I) {
     // This needs to be done before we create a new subtarget since any
     // creation will depend on the TM and the code generation flags on the
     // function that reside in TargetOptions.
     resetTargetOptions(F);
     auto ABIName = Options.MCOptions.getABIName();
     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
             F.getParent()->getModuleFlag("target-abi"))) {
       auto TargetABI = RISCVABI::getTargetABI(ABIName);
       if (TargetABI != RISCVABI::ABI_Unknown &&
           ModuleTargetABI->getString() != ABIName) {
         report_fatal_error("-target-abi option != target-abi module flag");
       }
       ABIName = ModuleTargetABI->getString();
     }
-    I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
+    I = std::make_unique<RISCVSubtarget>(
+        TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
   }
   return I.get();
 }
 
 TargetTransformInfo
 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(RISCVTTIImpl(this, F));
 }

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

 #define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
 
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/Analysis/IVDescriptors.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/BasicTTIImpl.h"
 #include "llvm/IR/Function.h"
+#include "llvm/Support/TargetParser.h"
 
 namespace llvm {
 
 class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
   using BaseT = BasicTTIImplBase<RISCVTTIImpl>;
   using TTI = TargetTransformInfo;
 
   friend BaseT;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
+
+define <512 x i8> @vadd_v512i8_zvl128(<512 x i8> %a, <512 x i8> %b) #0 {
+; CHECK-LABEL: vadd_v512i8_zvl128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    csrr a2, vlenb
+; CHECK-NEXT:    li a4, 40
+; CHECK-NEXT:    mul a2, a2, a4
+; CHECK-NEXT:    sub sp, sp, a2
+; CHECK-NEXT:    csrr a2, vlenb
+; CHECK-NEXT:    li a4, 24
+; CHECK-NEXT:    mul a2, a2, a4
+; CHECK-NEXT:    add a2, sp, a2
+; CHECK-NEXT:    addi a2, a2, 16
+; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
+; CHECK-NEXT:    csrr a2, vlenb
+; CHECK-NEXT:    slli a2, a2, 5
+; CHECK-NEXT:    add a2, sp, a2
+; CHECK-NEXT:    addi a2, a2, 16
+; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
+; CHECK-NEXT:    li a2, 128
+; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, mu
+; CHECK-NEXT:    addi a2, a3, 128
+; CHECK-NEXT:    addi a4, a3, 384
+; CHECK-NEXT:    vle8.v v8, (a4)
+; CHECK-NEXT:    csrr a4, vlenb
+; CHECK-NEXT:    slli a4, a4, 4
+; CHECK-NEXT:    add a4, sp, a4
+; CHECK-NEXT:    addi a4, a4, 16
+; CHECK-NEXT:    vs8r.v v8, (a4) # Unknown-size Folded Spill
+; CHECK-NEXT:    addi a4, a1, 128
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 3
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    addi a1, a3, 256
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vle8.v v16, (a4)
+; CHECK-NEXT:    vle8.v v24, (a2)
+; CHECK-NEXT:    vle8.v v0, (a3)
+; CHECK-NEXT:    addi a1, sp, 16
+; CHECK-NEXT:    vs8r.v v0, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 3
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vl8re8.v v0, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vadd.vv v8, v0, v8
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 3
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 4
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vl8re8.v v8, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vadd.vv v16, v16, v8
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    li a2, 24
+; CHECK-NEXT:    mul a1, a1, a2
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vl8re8.v v8, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vadd.vv v8, v8, v24
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    slli a1, a1, 5
+; CHECK-NEXT:    add a1, sp, a1
+; CHECK-NEXT:    addi a1, a1, 16
+; CHECK-NEXT:    vl8re8.v v24, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    addi a1, sp, 16
+; CHECK-NEXT:    vl8re8.v v0, (a1) # Unknown-size Folded Reload
+; CHECK-NEXT:    vadd.vv v0, v24, v0
+; CHECK-NEXT:    vse8.v v0, (a0)
+; CHECK-NEXT:    addi a1, a0, 384
+; CHECK-NEXT:    vse8.v v16, (a1)
+; CHECK-NEXT:    addi a1, a0, 256
+; CHECK-NEXT:    csrr a2, vlenb
+; CHECK-NEXT:    slli a2, a2, 3
+; CHECK-NEXT:    add a2, sp, a2
+; CHECK-NEXT:    addi a2, a2, 16
+; CHECK-NEXT:    vl8re8.v v16, (a2) # Unknown-size Folded Reload
+; CHECK-NEXT:    vse8.v v16, (a1)
+; CHECK-NEXT:    addi a0, a0, 128
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    li a1, 40
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+define <512 x i8> @vadd_v512i8_zvl256(<512 x i8> %a, <512 x i8> %b) #1 {
+; CHECK-LABEL: vadd_v512i8_zvl256:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a1, a0, 256
+; CHECK-NEXT:    li a2, 256
+; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, mu
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vle8.v v0, (a1)
+; CHECK-NEXT:    vadd.vv v8, v8, v24
+; CHECK-NEXT:    vadd.vv v16, v16, v0
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+define <512 x i8> @vadd_v512i8_zvl512(<512 x i8> %a, <512 x i8> %b) #2 {
+; CHECK-LABEL: vadd_v512i8_zvl512:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+define <512 x i8> @vadd_v512i8_zvl1024(<512 x i8> %a, <512 x i8> %b) #3 {
+; CHECK-LABEL: vadd_v512i8_zvl1024:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+define <512 x i8> @vadd_v512i8_zvl2048(<512 x i8> %a, <512 x i8> %b) #4 {
+; CHECK-LABEL: vadd_v512i8_zvl2048:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+define <512 x i8> @vadd_v512i8_zvl4096(<512 x i8> %a, <512 x i8> %b) #5 {
+; CHECK-LABEL: vadd_v512i8_zvl4096:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 512
+; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+  %c = add <512 x i8> %a, %b
+  ret <512 x i8> %c
+}
+
+attributes #0 = { vscale_range(2,1024) }
+attributes #1 = { vscale_range(4,1024) }
+attributes #2 = { vscale_range(8,1024) }
+attributes #3 = { vscale_range(16,1024) }
+attributes #4 = { vscale_range(32,1024) }
+attributes #5 = { vscale_range(64,1024) }