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- User Since
- Apr 9 2019, 6:59 AM (199 w, 3 d)
Yesterday
Wed, Feb 1
Update commit message, didn't realize that arc diff overwrote it
Tue, Jan 31
Mon, Jan 30
Fix commit message typo
Address comments, redo description
Fri, Jan 27
@qcolombet Apologies if I'm pinging the wrong person here, I'm looking for some advice on some register coalescer behaviour, let me know if this question is better directed towards someone else.
On RISC-V we're seeing some unexpected extra COPYs being left around with these $x0 registers, which is both a reserved and constant physical register.
Add another test that should be fixed
Simplify test
Thu, Jan 26
Address comments
Fix llc invocation
Wed, Jan 25
Update RISCVInstrInfoVSDPatterns.td too
Superseded by D142551
Tue, Jan 24
Update release notes
Mon, Jan 23
Remove unnecessary changes
The codegen changes seem fine to me but perhaps I'm missing something.
Mention GitHub issue in commit message
Don't suppress misc.highlighting_failure warning
Rendered PDF
Sat, Jan 21
Remove erroneous include
Fri, Jan 20
Thu, Jan 19
Address comment
Wed, Jan 18
Mon, Jan 16
Only scalarize if scalar type is legal
Split out webassembly test into pre-commit test
Fri, Jan 13
Check for legal types and equal int/float bit sizes
Add missing checks in half case
Expand to include halfs and conversions to other integer types
Update affected tests
Limit to cases where the shuffle is not just a single non-undef mask element
Thu, Jan 12
Don't include test case commit
Update AMDGPU tests with D140537
Rebase and update comments
Wed, Jan 11
Tue, Jan 10
Mon, Jan 9
Address review comments
Fri, Jan 6
Rework the approach