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apazos (Ana Pazos)
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User Since
Jan 24 2014, 10:03 AM (286 w, 1 d)

Recent Activity

Mar 28 2019

apazos added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Mar 28 2019, 5:01 PM · Restricted Project

Mar 27 2019

apazos added inline comments to D57497: [RISCV] Passing small data limitation value to RISCV backend.
Mar 27 2019, 1:59 PM · Restricted Project

Mar 20 2019

apazos added inline comments to D59592: [RISCV] support ilp32e Calling Convention.
Mar 20 2019, 3:33 PM · Restricted Project
apazos added a comment to D59470: [RISCV] Add basic RV32E definitions and MC layer support.

Thanks Alex, LGTM

Mar 20 2019, 2:56 PM · Restricted Project
apazos added inline comments to D59470: [RISCV] Add basic RV32E definitions and MC layer support.
Mar 20 2019, 2:52 PM · Restricted Project
apazos added inline comments to D57497: [RISCV] Passing small data limitation value to RISCV backend.
Mar 20 2019, 2:05 PM · Restricted Project
apazos added inline comments to D57493: [RISCV] Put data smaller than eight bytes to small data section.
Mar 20 2019, 1:47 PM · Restricted Project

Mar 8 2019

apazos committed rG5254d1baae63: [RISCV] Allow access to FP CSRs without F extension (authored by apazos).
[RISCV] Allow access to FP CSRs without F extension
Mar 8 2019, 3:01 PM
apazos committed rL355753: [RISCV] Allow access to FP CSRs without F extension.
[RISCV] Allow access to FP CSRs without F extension
Mar 8 2019, 3:01 PM
apazos closed D58932: [RISCV] Allow access to FP CSRs without F extension.
Mar 8 2019, 3:01 PM · Restricted Project
apazos added a comment to D59023: [RISCV] Support -target-abi at the MC layer and for codegen.

Thanks Alex, LGTM.

Mar 8 2019, 1:49 PM · Restricted Project
apazos added inline comments to D59023: [RISCV] Support -target-abi at the MC layer and for codegen.
Mar 8 2019, 10:00 AM · Restricted Project

Mar 7 2019

apazos updated the diff for D58932: [RISCV] Allow access to FP CSRs without F extension.

Leaving pseudo instructions that access FP CSRs untouched for now.

Mar 7 2019, 1:25 PM · Restricted Project
apazos added a comment to D58932: [RISCV] Allow access to FP CSRs without F extension.

OK, I can restrict the patch to access CSR names and value range without F extension, while we wait GCC and the RISC-V specs to be updated.

Mar 7 2019, 8:56 AM · Restricted Project

Mar 6 2019

apazos added a comment to D58943: [RISCV][MC] Find matching pcrel_hi fixup in more cases..

LGTM, I have verified the patch with some workloads and found no new issue.

Mar 6 2019, 6:33 PM · Restricted Project
apazos added inline comments to D59023: [RISCV] Support -target-abi at the MC layer and for codegen.
Mar 6 2019, 6:27 PM · Restricted Project
apazos abandoned D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

We are going with the alternative in https://reviews.llvm.org/D58943

Mar 6 2019, 4:56 PM

Mar 4 2019

apazos added a comment to D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

Hi Eli, this current patch as it is fails for the test case you highlighted. Thanks for clarifying and pushing an alternative solution.

Mar 4 2019, 8:33 PM
apazos created D58932: [RISCV] Allow access to FP CSRs without F extension.
Mar 4 2019, 3:39 PM · Restricted Project
apazos added a comment to D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

Hi Eli,

Mar 4 2019, 1:43 PM
apazos retitled D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi from Fixed error: could not find corresponding %pcrel_hi to [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.
Mar 4 2019, 10:15 AM

Mar 1 2019

apazos abandoned D58485: [WIP] Experimenting with aligning with GCC LIR behavior at Os.

Not profitable

Mar 1 2019, 5:09 PM
apazos updated subscribers of D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.
Mar 1 2019, 2:09 PM
apazos updated the diff for D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

Updated triple in test case

Mar 1 2019, 1:27 PM
apazos retitled D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi from [RISCV] (WIP) Fixed error: could not find corresponding %pcrel_hi to Fixed error: could not find corresponding %pcrel_hi.
Mar 1 2019, 1:25 PM
apazos edited reviewers for D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi, added: eli.friedman; removed: lewis-revill.
Mar 1 2019, 1:11 PM
apazos updated subscribers of D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.
Mar 1 2019, 1:10 PM
apazos updated the diff for D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

Reduced code changes, added test case

Mar 1 2019, 1:09 PM
apazos added a comment to D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.

Hi Lewis, yes it is possible to reduce the code changes. I will push an update.
The concern I have is that for pseudo instructions it was enough to change RISCVAsmParser.cpp to fix the problem. But for the expanded instructions I have to modify AsmParser.cpp.
So maybe instead of adding a new EmitLabel we change the current api.

Mar 1 2019, 1:03 PM

Feb 27 2019

apazos added a reviewer for D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi: lewis-revill.

Lewis, is this what you had in mind, I only changed RISC-V parser path.

Feb 27 2019, 8:56 PM
apazos created D58759: [RISCV][MC] Fixed error: could not find corresponding %pcrel_hi.
Feb 27 2019, 8:50 PM
apazos added a comment to D54029: [RISCV] Properly evaluate fixup_riscv_pcrel_lo12.

Thanks for the analysis and suggestion Lewis.

Feb 27 2019, 8:48 PM · Restricted Project

Feb 20 2019

apazos created D58485: [WIP] Experimenting with aligning with GCC LIR behavior at Os.
Feb 20 2019, 6:11 PM
Herald added a project to D54029: [RISCV] Properly evaluate fixup_riscv_pcrel_lo12: Restricted Project.

Hi James, I encountered another case not handled yet in this patch. It produces the error: could not find corresponding %pcrel_hi

Feb 20 2019, 1:01 PM · Restricted Project

Feb 14 2019

apazos committed rG6dbe86597a8f: Fixed failure on Darwin due to r354064 (authored by apazos).
Fixed failure on Darwin due to r354064
Feb 14 2019, 4:21 PM
apazos committed rC354089: Fixed failure on Darwin due to r354064.
Fixed failure on Darwin due to r354064
Feb 14 2019, 4:21 PM
apazos committed rL354089: Fixed failure on Darwin due to r354064.
Fixed failure on Darwin due to r354064
Feb 14 2019, 4:21 PM
apazos closed D58259: Fixed failure on Darwin due to r354064.
Feb 14 2019, 4:21 PM · Restricted Project
apazos created D58259: Fixed failure on Darwin due to r354064.
Feb 14 2019, 3:27 PM · Restricted Project
apazos committed rGbbb8129b2cdd: Set hidden attribute on lprofMergeValueProfData (authored by apazos).
Set hidden attribute on lprofMergeValueProfData
Feb 14 2019, 1:38 PM
apazos committed rCRT354064: Set hidden attribute on lprofMergeValueProfData.
Set hidden attribute on lprofMergeValueProfData
Feb 14 2019, 1:38 PM
apazos committed rL354064: Set hidden attribute on lprofMergeValueProfData.
Set hidden attribute on lprofMergeValueProfData
Feb 14 2019, 1:38 PM
apazos closed D55893: Set hidden attribute on lprofMergeValueProfData.
Feb 14 2019, 1:38 PM · Restricted Project

Feb 12 2019

apazos updated the diff for D55893: Set hidden attribute on lprofMergeValueProfData.

I added a test case to verify the fix prevents lprofMergeValueProfData from another module from being accessed.

Feb 12 2019, 5:26 PM · Restricted Project

Feb 11 2019

apazos committed rG9a3dc3e60bf0: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types (authored by apazos).
[LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types
Feb 11 2019, 2:10 PM
apazos committed rL353757: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.
[LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types
Feb 11 2019, 2:10 PM
apazos closed D57875: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.
Feb 11 2019, 2:10 PM · Restricted Project

Feb 8 2019

apazos added a comment to D57875: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.

Without the patch, the fneg use in the given test case becomes a sub lib call in the targets I checked when using soft abi (riscv, arm)

Feb 8 2019, 2:56 PM · Restricted Project
apazos resigned from D25634: Fix replacedSelectWithOperand in InstCombiner to handle branch having two same successors..
Feb 8 2019, 10:40 AM
apazos resigned from D8371: Allow code generation of ARM usat/ssat instructions.
Feb 8 2019, 10:39 AM
apazos resigned from D3476: Fix use_iterator in ARM64AddressTypePromotion.
Feb 8 2019, 10:38 AM

Feb 7 2019

apazos added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

The patch is not applying cleanly due to the added test/MC/RISCV/rv64i-pseudos.s which was first added in https://reviews.llvm.org/D55325

Feb 7 2019, 10:31 AM · Restricted Project

Feb 6 2019

apazos added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

If this is a target flag in GCC, shouldn't we make it a LLVM Target feature and pass it as -mattr, just like done for mrelax?

Feb 6 2019, 10:23 PM · Restricted Project
apazos added a comment to D57875: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.

For the cases it does not transform, we still do not need to make lib calls.

Feb 6 2019, 9:50 PM · Restricted Project
apazos updated subscribers of D57875: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.
Feb 6 2019, 8:17 PM · Restricted Project
apazos created D57875: [LegalizeTypes] Expand FNEG to bitwise op for IEEE FP types.
Feb 6 2019, 8:16 PM · Restricted Project

Feb 5 2019

apazos added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

So Eli is concerned we might end up with many globals in the small data section or not picking the best candidates if we pass -G to all files in LTO.
I don’t know if anyone has experimented with a heuristic to selectively pick which globals and of which size will be allowed to go into the small data section.
Simon, do you have any insight?
Shiva, maybe for now we don’t pass the flag to LTO. But I think you got the correct mechanism. The only other suggestion I have is to add a RISC-V specific function to avoid too much RISC-V specific code in gnutools::Linker::constructJob. You just check the triple and call something like toolchains::RISCVToolChain::AddGoldPluginAdditionalFlags.

Feb 5 2019, 3:34 PM · Restricted Project

Feb 3 2019

apazos added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

I don't see -plugin-opt=-riscv-ssection-threshold=.. being passed.
tools::gnutools::Linker::ConstructJob is being invoked with target riscv32-unknown-linux-gnu
It has to work for riscv32-unknown-linux-gnu and riscv32-unknown-elf

Feb 3 2019, 8:12 AM · Restricted Project
apazos added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Hi Shiva, I will check, but I think you need to also modify gnutools:Linker because riscv::Linker is called for baremetal. I think you need in both places.
The way I check is by invoking -flto -v from clang and look at the arguments passed to the compiler and linker

Feb 3 2019, 7:46 AM · Restricted Project

Feb 2 2019

apazos added a comment to D57497: [RISCV] Passing small data limitation value to RISCV backend.

Hi Shiva, I think you need to check for and pass along the -G option to the linker (gnutools::Linker and RISCV::Linker) and will be available for LTO. Check Hexagon, it passes the threshold value to the assembler (via -gpsize) and linker (via -G).

Feb 2 2019, 6:45 PM · Restricted Project

Feb 1 2019

Herald added a project to D57493: [RISCV] Put data smaller than eight bytes to small data section: Restricted Project.
Feb 1 2019, 4:48 PM · Restricted Project

Jan 25 2019

apazos committed rL352237: Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
Jan 25 2019, 12:24 PM

Jan 24 2019

apazos added a comment to D57141: [RISCV] Add implied zero offset load/store alias patterns.

Yes James, please post your patch and tests. Kito quickly posted this one to unblock me.

Jan 24 2019, 2:39 PM · Restricted Project

Jan 23 2019

apazos committed rL352014: Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI".
Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"
Jan 23 2019, 7:02 PM
apazos committed rL352010: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
Jan 23 2019, 6:42 PM
apazos closed D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 23 2019, 6:42 PM
apazos committed rL352008: [RISCV] Set isReMaterializable for ORI, XORI.
[RISCV] Set isReMaterializable for ORI, XORI
Jan 23 2019, 6:32 PM
apazos closed D57069: [RISCV] Set isReMaterializable for ORI, XORI.
Jan 23 2019, 6:32 PM
apazos retitled D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI from Fixed isAsCheapAsAMove settings to [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 23 2019, 6:05 PM
apazos retitled D57069: [RISCV] Set isReMaterializable for ORI, XORI from [RISCV] Fixed isReMaterializable setting for ORI, XORI to [RISCV] Set isReMaterializable for ORI, XORI.
Jan 23 2019, 6:04 PM

Jan 22 2019

apazos updated the diff for D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 22 2019, 4:08 PM
apazos added a comment to D57069: [RISCV] Set isReMaterializable for ORI, XORI.

I meant to comment https://reviews.llvm.org/D56526

Jan 22 2019, 3:31 PM
apazos added a comment to D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.

Sure, will update this patch and I have pushed the other changes to separate patches:
R351895 - Fixed isReMaterializable setting for LUI instruction.
https://reviews.llvm.org/D57069 [RISCV] Fixed isReMaterializable setting for ORI, XORI

Jan 22 2019, 3:31 PM
apazos added a comment to D57069: [RISCV] Set isReMaterializable for ORI, XORI.

Sure, will update this patch and I have pushed the other changes to separate patches:
R351895 - Fixed isReMaterializable setting for LUI instruction.
https://reviews.llvm.org/D57069 [RISCV] Fixed isReMaterializable setting for ORI, XORI

Jan 22 2019, 3:30 PM
apazos created D57069: [RISCV] Set isReMaterializable for ORI, XORI.
Jan 22 2019, 3:29 PM
apazos committed rL351895: Fixed isReMaterializable setting for LUI instruction..
Fixed isReMaterializable setting for LUI instruction.
Jan 22 2019, 3:01 PM

Jan 15 2019

apazos added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Just noted that this is failing:

Jan 15 2019, 11:54 AM · Restricted Project

Jan 11 2019

apazos updated the diff for D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 11 2019, 1:12 PM
apazos updated the diff for D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 11 2019, 1:07 PM

Jan 9 2019

apazos created D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI.
Jan 9 2019, 6:14 PM

Dec 19 2018

apazos added a comment to D55893: Set hidden attribute on lprofMergeValueProfData.

I observed the issue with instrumented libs in Android. I have not been successful in reducing a test case that would fail on x86 linux.
I can write a test case that shows I can do a dlopen/dlsym of lprofMergeValueProfData from a different library, but with the hidden attribute set on the function, the dlsym call will fail.
Shouldn't we prevent lprofMergeValueProfData from being accessed outside a module?

Dec 19 2018, 10:08 PM · Restricted Project
apazos added a comment to D55893: Set hidden attribute on lprofMergeValueProfData.

A test would need to dump the contents of the symbol table and verify the hidden attribute for that symbol. Do you have something else in mind?

Dec 19 2018, 11:28 AM · Restricted Project
apazos created D55893: Set hidden attribute on lprofMergeValueProfData.
Dec 19 2018, 11:16 AM · Restricted Project
apazos updated the diff for D55644: Emitting MCInstruction from Protocol Buffer Message.
Dec 19 2018, 10:57 AM

Dec 12 2018

apazos created D55644: Emitting MCInstruction from Protocol Buffer Message.
Dec 12 2018, 9:31 PM

Nov 29 2018

apazos added a comment to D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I.

Thanks Alex, LGTM. I did not detect missing predicate around the 64 bit instructions and patterns.

Nov 29 2018, 1:09 PM
apazos added a comment to D54574: [SelectionDAG] Support promotion of the FPOWI integer operand.

can you rebase this one as well, patch not applying cleanly

Nov 29 2018, 10:29 AM · Restricted Project
apazos added a comment to D53820: [SelectionDAG] Support result type promotion for FLT_ROUNDS_.

Alex, can you rebase this one, it does not apply cleanly.

Nov 29 2018, 10:25 AM

Oct 12 2018

apazos updated the diff for D51144: Implemented Protobuf fuzzer for LLVM RISC-V MC Assembler.

Some cleanup.
Removed bracket field from Register Message. The Statement types add the brackets when needed.
Added PCREL_HI/LO modifiers.
Fixed mesage Label definition, added suffix to numeric label.
Added Label to Immediate Message handling in proto-to-asm-fuzz-opnd-values.

Oct 12 2018, 5:10 PM
apazos updated the diff for D51710: Implemented Protobuf fuzzer for LLVM RISC-V MC Disassembler.

Small fix in README.txt

Oct 12 2018, 1:31 PM
apazos updated the diff for D51710: Implemented Protobuf fuzzer for LLVM RISC-V MC Disassembler.

Small fix in mcfuzzer.py

Oct 12 2018, 11:28 AM

Oct 11 2018

apazos updated the diff for D51710: Implemented Protobuf fuzzer for LLVM RISC-V MC Disassembler.

Removed PBM_FUZZ_PATH and PBM_REPO from build steps.
Relying on building these fuzzers with the latest version of libprotobuf (and libprotobuf-mutator), which should be installed in the system.

Oct 11 2018, 7:16 PM
apazos updated the diff for D51144: Implemented Protobuf fuzzer for LLVM RISC-V MC Assembler.

Removed PBM_FUZZ_PATH and PBM_REPO from build steps.
Relying on building these fuzzers with the latest version of libprotobuf (and libprotobuf-mutator), which should be installed in the system.

Oct 11 2018, 6:03 PM
apazos retitled D51710: Implemented Protobuf fuzzer for LLVM RISC-V MC Disassembler from Implemented Protobuf fuzzer for LLVM MC Disassembler to Implemented Protobuf fuzzer for LLVM RISC-V MC Disassembler.
Oct 11 2018, 4:06 PM
apazos retitled D51144: Implemented Protobuf fuzzer for LLVM RISC-V MC Assembler from Implemented Protobuf fuzzer for LLVM MC Assembler to Implemented Protobuf fuzzer for LLVM RISC-V MC Assembler.
Oct 11 2018, 4:05 PM
apazos committed rL344309: [RISCV] Fix disassembling of fence instruction with invalid field.
[RISCV] Fix disassembling of fence instruction with invalid field
Oct 11 2018, 3:52 PM
apazos closed D51828: [RISCV] Fix disassembling of fence instruction with invalid field.
Oct 11 2018, 3:52 PM
apazos updated the diff for D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Updated patch based on review comment.

Oct 11 2018, 3:48 PM
apazos added a comment to D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Good comments, will make the updates.

Oct 11 2018, 3:19 PM

Oct 4 2018

apazos updated the diff for D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Printing unknown when disassembling instruction with 0 field.

Oct 4 2018, 3:13 PM