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luke957 (Luke)
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Jan 26 2021, 7:22 PM (111 w, 5 d)

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Mar 30 2022

luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.
rebase and update
Mar 30 2022, 9:13 AM · Restricted Project, Restricted Project

Mar 10 2022

luke957 added a comment to D119834: [RISCV] Add fixed-length vector instrinsics for segment load.

Comments addressed before commit. Thanks.

Mar 10 2022, 1:27 AM · Restricted Project, Restricted Project
luke957 committed rG0803dba7dd99: [RISCV] Add fixed-length vector instrinsics for segment load (authored by luke957).
[RISCV] Add fixed-length vector instrinsics for segment load
Mar 10 2022, 12:34 AM · Restricted Project
luke957 closed D119834: [RISCV] Add fixed-length vector instrinsics for segment load.
Mar 10 2022, 12:33 AM · Restricted Project, Restricted Project

Mar 2 2022

Herald added a project to D119834: [RISCV] Add fixed-length vector instrinsics for segment load: Restricted Project.

Gently ping.

Mar 2 2022, 8:46 PM · Restricted Project, Restricted Project

Feb 24 2022

luke957 updated the diff for D119834: [RISCV] Add fixed-length vector instrinsics for segment load.
Feb 24 2022, 7:28 AM · Restricted Project, Restricted Project
luke957 updated the diff for D119834: [RISCV] Add fixed-length vector instrinsics for segment load.

Address comments

Feb 24 2022, 7:16 AM · Restricted Project, Restricted Project

Feb 22 2022

luke957 added a comment to D119834: [RISCV] Add fixed-length vector instrinsics for segment load.

Hi, any comments? :)

Feb 22 2022, 11:08 PM · Restricted Project, Restricted Project

Feb 15 2022

luke957 updated the summary of D119834: [RISCV] Add fixed-length vector instrinsics for segment load.
Feb 15 2022, 5:23 AM · Restricted Project, Restricted Project
luke957 requested review of D119834: [RISCV] Add fixed-length vector instrinsics for segment load.
Feb 15 2022, 5:12 AM · Restricted Project, Restricted Project

Nov 8 2021

luke957 abandoned D112829: [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV.

See https://reviews.llvm.org/D107432

Nov 8 2021, 4:27 AM · Restricted Project
luke957 added a comment to D112829: [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV.
In D112829#3113118, @HsiangKai wrote:

I have a patch to fix the problem. https://reviews.llvm.org/D107432

Nov 8 2021, 2:36 AM · Restricted Project

Nov 5 2021

luke957 added a comment to D107210: [RISCV] Support interleaved load lowering.

Gently ping.

Nov 5 2021, 7:34 AM · Restricted Project, Restricted Project

Oct 29 2021

luke957 added reviewers for D112829: [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV: asb, luismarques, HsiangKai.
Oct 29 2021, 10:00 PM · Restricted Project
luke957 retitled D112829: [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV from [RISCV][DebugInfo] fix crash to [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV.
Oct 29 2021, 9:51 PM · Restricted Project
luke957 requested review of D112829: [RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV.
Oct 29 2021, 9:30 AM · Restricted Project

Oct 28 2021

luke957 resigned from D111285: Fix invalid Kill on callee save on RISC-V.

So sorry for my bad herald script.

Oct 28 2021, 7:33 AM · Restricted Project
luke957 resigned from D111519: [WIP] [RISCV] Emit cfi directives for function epilogue.

So sorry for my bad herald script.

Oct 28 2021, 7:32 AM · Restricted Project
luke957 resigned from D111939: [RISCV] Add missing e_flag EF_RISCV_TSO.

So sorry for my bad herald script.

Oct 28 2021, 7:31 AM · Restricted Project
luke957 resigned from D112359: [RISCV] Unify depedency check and extension implication parsing logics.

So sorry for my bad herald script.

Oct 28 2021, 7:31 AM · Restricted Project, Restricted Project
luke957 resigned from D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0..

So sorry for my bad herald script.

Oct 28 2021, 7:30 AM · Restricted Project, Restricted Project
luke957 resigned from D112534: [PoC][RISCV] Use an attribute to declare C intrinsics with different policy..

So sorry for my bad herald script.

Oct 28 2021, 7:29 AM · Restricted Project, Restricted Project
luke957 added a comment to D112692: [RISCV] Generate pseudo instruction li.

So sorry for my bad herald script.

Oct 28 2021, 7:28 AM · Restricted Project, Restricted Project
luke957 resigned from D112692: [RISCV] Generate pseudo instruction li.
Oct 28 2021, 7:28 AM · Restricted Project, Restricted Project
luke957 added a comment to D110527: [llvm-reduce] Add MIR support..

So sorry for my bad herald script.

Oct 28 2021, 7:26 AM · Restricted Project
luke957 resigned from D110527: [llvm-reduce] Add MIR support..
Oct 28 2021, 7:23 AM · Restricted Project

Oct 27 2021

luke957 added inline comments to D112598: [WIP][RISCV][CostModel] Add cost model for shuffle.
Oct 27 2021, 4:09 AM · Restricted Project
luke957 requested review of D112598: [WIP][RISCV][CostModel] Add cost model for shuffle.
Oct 27 2021, 12:47 AM · Restricted Project

Oct 26 2021

luke957 added inline comments to D107210: [RISCV] Support interleaved load lowering.
Oct 26 2021, 12:23 AM · Restricted Project, Restricted Project
luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.

Update

Oct 26 2021, 12:02 AM · Restricted Project, Restricted Project

Oct 4 2021

luke957 added a comment to D99142: [RISCV] Add basic cost modelling for fixed vector gather/scatter..

@craig.topper It seems for intrinsic llvm.masked.gather.xxx, the backend will produce similar assembly instructions.
Eg, llvm.masked.gather.v8f64.v8p0f64 will get

vsetivli    zero, 8, e64, m4, tu, mu
vluxei64.v  v12, (zero), v8, v0.t
vmv4r.v     v8, v12

, and llvm.masked.gather.v4f64.v4p0f64 will get

vsetivli    zero, 4, e64, m2, tu, mu
vluxei64.v  v10, (zero), v8, v0.t
vmv2r.v     v8, v10

So why the cost is calculated by element number? I'm not quite clear about this. Can you give some reference or clue? Thanks.

Oct 4 2021, 3:28 AM · Restricted Project

Sep 28 2021

luke957 added a comment to D107945: [RISCV] Use RISCV::RVVBitsPerBlock for RGK_ScalableVector in getRegisterBitWidth..

May I ask a question, why is RISCV::RVVBitsPerBlock set to 64? Any clue(RFC) to this concept? Thanks.

Sep 28 2021, 12:06 AM · Restricted Project

Sep 27 2021

luke957 added inline comments to D107210: [RISCV] Support interleaved load lowering.
Sep 27 2021, 9:57 PM · Restricted Project, Restricted Project
luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.

Update

Sep 27 2021, 9:37 PM · Restricted Project, Restricted Project
luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.

Clang tidy

Sep 27 2021, 8:08 PM · Restricted Project, Restricted Project

Sep 6 2021

luke957 added a comment to D107210: [RISCV] Support interleaved load lowering.

ping

Sep 6 2021, 7:19 PM · Restricted Project, Restricted Project

Aug 31 2021

luke957 committed rGa78dd726f46d: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV (authored by luke957).
[SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV
Aug 31 2021, 11:25 PM
luke957 closed D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV.
Aug 31 2021, 11:25 PM · Restricted Project
luke957 added a comment to D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV.
In D108973#2976094, @craig.topper wrote:
In D108973#2976093, @luke957 wrote:
In D108973#2974682, @craig.topper wrote:

Tests?

Em, I haven't got a proper test case for this. Without this methed being implemented, the mothed in super class will be called and got a return value of 128.

In D108973#2974808, @craig.topper wrote:

Is this function just picking the minimum size of vector SLP will use? Do we want that to follow getRegisterBitWidth() or should it be allowed to be lower?

Oh, I get your point. For RVV, we can use a vector registor fractionally, so minimum size of vector could be less than MinVectorRegisterBitWidth. But I'm not sure whether it is appropriate for a methed naming getMinVectorRegisterBitWidth.

There was a vague suggestion about possibly adding a new getMinVectorizationBitWidth mentioned here https://reviews.llvm.org/D103925

Anyway this patch is probably good as a starting point. LGTM

Aug 31 2021, 9:55 PM · Restricted Project
luke957 added a comment to D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV.
In D108973#2974682, @craig.topper wrote:

Tests?

Aug 31 2021, 9:32 PM · Restricted Project
luke957 added reviewers for D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV: craig.topper, frasercrmck, HsiangKai.
Aug 31 2021, 1:23 AM · Restricted Project
luke957 added a comment to D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV.

Should we implement method unsigned getMinVectorRegisterBitWidth() to avoid potential errors?

Aug 31 2021, 1:21 AM · Restricted Project
luke957 requested review of D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV.
Aug 31 2021, 1:19 AM · Restricted Project

Aug 28 2021

luke957 added inline comments to D107210: [RISCV] Support interleaved load lowering.
Aug 28 2021, 8:44 PM · Restricted Project, Restricted Project
luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.

Update

Aug 28 2021, 8:42 PM · Restricted Project, Restricted Project

Aug 18 2021

luke957 added a comment to D107210: [RISCV] Support interleaved load lowering.

ping

Aug 18 2021, 8:22 PM · Restricted Project, Restricted Project

Aug 11 2021

luke957 added a comment to D107210: [RISCV] Support interleaved load lowering.
In D107210#2918081, @craig.topper wrote:

Don't you need to add the InterleavedAccess pass to RISCVTargetMachine?

Aug 11 2021, 4:50 AM · Restricted Project, Restricted Project
luke957 updated the summary of D107210: [RISCV] Support interleaved load lowering.
Aug 11 2021, 4:41 AM · Restricted Project, Restricted Project
luke957 updated the diff for D107210: [RISCV] Support interleaved load lowering.

Update

Aug 11 2021, 4:36 AM · Restricted Project, Restricted Project

Jul 30 2021

luke957 requested review of D107210: [RISCV] Support interleaved load lowering.
Jul 30 2021, 8:57 PM · Restricted Project, Restricted Project

Jul 29 2021

luke957 added a comment to D105130: [RISCV] Enable interleaved access vectorization.
In D105130#2909219, @craig.topper wrote:
In D105130#2902226, @luke957 wrote:
In D105130#2847617, @craig.topper wrote:

Please upload patches with full context using -U999999 has documented here https://releases.llvm.org/11.0.0/docs/Phabricator.html#requesting-a-review-via-the-web-interface

Do you plan to map these to segment load/store instructions in the future?

Yeah, segment load/store instructions are naturally suitable for mapping these. Do we need to create a new RISCVISD?

I believe we need to run the InterleavedAccessPass and and and implement TargetLowering::LowerInterleavedLoad/Store to create IR intrinsics. That's how it is done on ARM for their vldX and vstX intstructions.

Jul 29 2021, 8:05 AM · Restricted Project
luke957 added a comment to D105130: [RISCV] Enable interleaved access vectorization.
In D105130#2909217, @craig.topper wrote:

If we aren't using segment load/store, what does the backend codegen for this look like?

Jul 29 2021, 8:02 AM · Restricted Project

Jul 27 2021

luke957 added a comment to D105130: [RISCV] Enable interleaved access vectorization.

ping

Jul 27 2021, 6:47 PM · Restricted Project

Jul 24 2021

luke957 added inline comments to D105130: [RISCV] Enable interleaved access vectorization.
Jul 24 2021, 1:52 AM · Restricted Project
luke957 added a comment to D105130: [RISCV] Enable interleaved access vectorization.
In D105130#2847617, @craig.topper wrote:

Please upload patches with full context using -U999999 has documented here https://releases.llvm.org/11.0.0/docs/Phabricator.html#requesting-a-review-via-the-web-interface

Do you plan to map these to segment load/store instructions in the future?

Jul 24 2021, 1:51 AM · Restricted Project
luke957 updated the diff for D105130: [RISCV] Enable interleaved access vectorization.

Update

Jul 24 2021, 1:40 AM · Restricted Project

Jun 29 2021

luke957 requested review of D105130: [RISCV] Enable interleaved access vectorization.
Jun 29 2021, 9:31 AM · Restricted Project

Jun 17 2021

luke957 closed D104364: [RISCV] Don't enable Interleaved Access Vectorization.
Jun 17 2021, 9:46 PM · Restricted Project
luke957 committed rGc2e97ba85e46: [RISCV] Don't enable Interleaved Access Vectorization (authored by luke957).
[RISCV] Don't enable Interleaved Access Vectorization
Jun 17 2021, 9:39 PM

Jun 16 2021

luke957 updated the summary of D104393: [RISCV] Update test case.
Jun 16 2021, 8:56 AM · Restricted Project
luke957 added a reviewer for D104393: [RISCV] Update test case: jrtc27.
Jun 16 2021, 8:55 AM · Restricted Project
luke957 requested review of D104393: [RISCV] Update test case.
Jun 16 2021, 8:54 AM · Restricted Project
luke957 added inline comments to D101469: [RISCV] Enable interleaved vectorization for RVV.
Jun 16 2021, 2:29 AM · Restricted Project, Restricted Project
luke957 added inline comments to D101469: [RISCV] Enable interleaved vectorization for RVV.
Jun 16 2021, 2:24 AM · Restricted Project, Restricted Project
luke957 requested review of D104364: [RISCV] Don't enable Interleaved Access Vectorization.
Jun 16 2021, 1:39 AM · Restricted Project
luke957 added inline comments to D101469: [RISCV] Enable interleaved vectorization for RVV.
Jun 16 2021, 1:21 AM · Restricted Project, Restricted Project

Jun 7 2021

luke957 added a comment to D101469: [RISCV] Enable interleaved vectorization for RVV.
In D101469#2801793, @luke957 wrote:
In D101469#2801767, @craig.topper wrote:

I just noticed that this enabled interleaving in the loop vectorizer even when the V extension isn't enabled. So we now generate interleaved scalar code in some cases. Was that intentional?

Thanks for reminding me. Sorry for my carelessness.

Jun 7 2021, 7:33 PM · Restricted Project, Restricted Project

Jun 6 2021

luke957 accepted D103787: [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled..
Jun 6 2021, 11:48 PM · Restricted Project
luke957 added a comment to D103787: [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled..

LGTM

Jun 6 2021, 11:47 PM · Restricted Project
luke957 added a comment to D101469: [RISCV] Enable interleaved vectorization for RVV.
In D101469#2801767, @craig.topper wrote:

I just noticed that this enabled interleaving in the loop vectorizer even when the V extension isn't enabled. So we now generate interleaved scalar code in some cases. Was that intentional?

Jun 6 2021, 11:45 PM · Restricted Project, Restricted Project

May 28 2021

luke957 committed rGc4c3869554a6: [RISCV] Enable interleaved vectorization for RVV (authored by luke957).
[RISCV] Enable interleaved vectorization for RVV
May 28 2021, 8:29 PM
luke957 closed D101469: [RISCV] Enable interleaved vectorization for RVV.
May 28 2021, 8:28 PM · Restricted Project, Restricted Project
luke957 added a comment to D101469: [RISCV] Enable interleaved vectorization for RVV.

ping

May 28 2021, 9:36 AM · Restricted Project, Restricted Project

May 20 2021

luke957 added inline comments to D101469: [RISCV] Enable interleaved vectorization for RVV.
May 20 2021, 10:27 AM · Restricted Project, Restricted Project
luke957 updated the diff for D101469: [RISCV] Enable interleaved vectorization for RVV.

Rebase and update.

May 20 2021, 10:15 AM · Restricted Project, Restricted Project
luke957 committed rG1595994b2825: [RISCV] Add legality check for vectorizing reduction (authored by luke957).
[RISCV] Add legality check for vectorizing reduction
May 20 2021, 2:46 AM
luke957 closed D99509: [RISCV] Add legality check for vectoring reduction.
May 20 2021, 2:46 AM · Restricted Project

May 19 2021

luke957 updated the diff for D99509: [RISCV] Add legality check for vectoring reduction.

rebase

May 19 2021, 9:37 AM · Restricted Project

May 18 2021

luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
May 18 2021, 9:11 AM · Restricted Project
luke957 updated the diff for D99509: [RISCV] Add legality check for vectoring reduction.
May 18 2021, 9:02 AM · Restricted Project
luke957 added a comment to D101469: [RISCV] Enable interleaved vectorization for RVV.
In D101469#2766122, @frasercrmck wrote:

Do you still need to update the diff to address the previous comments?

May 18 2021, 8:12 AM · Restricted Project, Restricted Project
luke957 added a comment to D101469: [RISCV] Enable interleaved vectorization for RVV.

ping

May 18 2021, 7:05 AM · Restricted Project, Restricted Project

Apr 29 2021

luke957 added inline comments to D101469: [RISCV] Enable interleaved vectorization for RVV.
Apr 29 2021, 9:06 AM · Restricted Project, Restricted Project
luke957 updated the diff for D101469: [RISCV] Enable interleaved vectorization for RVV.
Apr 29 2021, 8:55 AM · Restricted Project, Restricted Project

Apr 28 2021

luke957 added reviewers for D101469: [RISCV] Enable interleaved vectorization for RVV: craig.topper, frasercrmck, HsiangKai.
Apr 28 2021, 9:19 AM · Restricted Project, Restricted Project
luke957 requested review of D101469: [RISCV] Enable interleaved vectorization for RVV.
Apr 28 2021, 9:17 AM · Restricted Project, Restricted Project
luke957 added a comment to D99509: [RISCV] Add legality check for vectoring reduction.

ping

Apr 28 2021, 12:32 AM · Restricted Project

Apr 22 2021

luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
Apr 22 2021, 9:35 AM · Restricted Project
luke957 updated the diff for D99509: [RISCV] Add legality check for vectoring reduction.
Apr 22 2021, 8:58 AM · Restricted Project

Apr 15 2021

luke957 added a reviewer for D99509: [RISCV] Add legality check for vectoring reduction: dmgreen.
Apr 15 2021, 6:23 AM · Restricted Project
luke957 added a comment to D99509: [RISCV] Add legality check for vectoring reduction.

ping

Apr 15 2021, 3:17 AM · Restricted Project

Apr 13 2021

luke957 abandoned D99492: [RISCV] "V" Extention coming with "F" "D" "Zfh" Extentions.
Apr 13 2021, 7:59 PM · Restricted Project

Apr 8 2021

luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
Apr 8 2021, 1:36 AM · Restricted Project
luke957 updated the diff for D99509: [RISCV] Add legality check for vectoring reduction.
Apr 8 2021, 1:25 AM · Restricted Project

Apr 7 2021

luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
Apr 7 2021, 8:38 AM · Restricted Project
luke957 updated the diff for D99509: [RISCV] Add legality check for vectoring reduction.
Apr 7 2021, 8:34 AM · Restricted Project

Apr 5 2021

luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
Apr 5 2021, 9:32 AM · Restricted Project
luke957 added inline comments to D99509: [RISCV] Add legality check for vectoring reduction.
Apr 5 2021, 9:23 AM · Restricted Project

Mar 30 2021

luke957 added inline comments to D99492: [RISCV] "V" Extention coming with "F" "D" "Zfh" Extentions.
Mar 30 2021, 3:36 AM · Restricted Project
luke957 added a comment to D99492: [RISCV] "V" Extention coming with "F" "D" "Zfh" Extentions.
In D99492#2655701, @HsiangKai wrote:

There is no such implication in the V specification. See https://github.com/riscv/riscv-v-spec/issues/608.

Mar 30 2021, 3:34 AM · Restricted Project