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paulwalker-arm (Paul Walker)
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Nov 24 2016, 5:21 AM (216 w, 4 d)

Recent Activity

Sat, Jan 16

paulwalker-arm added inline comments to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.
Sat, Jan 16, 4:18 AM · Restricted Project
paulwalker-arm added a comment to D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic.

In D94444, @paulwalker-arm proposed a more generic extract vector intrinsic that accepts an index and stride. Now I'm wondering if we should just have a generic scalable shuffle vector intrinsic to handle all these operations under one intrinsic.

That idea doesn't need to hold up this Diff, but it might be something to consider...

Sat, Jan 16, 4:08 AM · Restricted Project

Fri, Jan 15

paulwalker-arm committed rG2b8db40c9218: [SVE] Restrict the usage of REINTERPRET_CAST. (authored by paulwalker-arm).
[SVE] Restrict the usage of REINTERPRET_CAST.
Fri, Jan 15, 3:34 AM
paulwalker-arm closed D94593: [SVE] Restrict the usage of REINTERPRET_CAST..
Fri, Jan 15, 3:34 AM · Restricted Project

Thu, Jan 14

paulwalker-arm added a comment to D94444: [RFC][Scalable] Add scalable shuffle intrinsic to extract evens from a pair of vectors.

A bit of a flyby review as I'm still on holidays but to my mind many of the restrictions being proposed for the new intrinsic seem purely down to the design decision of splitting the input vector across two operands. I understand this is how the underlying instructions work for SVE but that does not seem like a good enough reason to compromise the IR.

Thu, Jan 14, 3:36 AM · Restricted Project

Wed, Jan 13

paulwalker-arm added reviewers for D94593: [SVE] Restrict the usage of REINTERPRET_CAST.: kmclaughlin, david-arm, c-rhodes.
Wed, Jan 13, 5:26 AM · Restricted Project
paulwalker-arm requested review of D94593: [SVE] Restrict the usage of REINTERPRET_CAST..
Wed, Jan 13, 5:09 AM · Restricted Project

Thu, Jan 7

paulwalker-arm accepted D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

Thanks @david-arm . FYI the CHECK-DAGs within sve-fixed-length-int-arith.ll don't need to be DAGs but I'm going to restructure these tests anyway so there's not point changing them.

Thu, Jan 7, 2:00 AM · Restricted Project
paulwalker-arm added a comment to D94193: [SVE] Unpacked scalable floating point ZIP/UZP/TRN.

Please can you add entries for nxv2f16 as well? That way all the legal fp types are covered.

Thu, Jan 7, 1:51 AM · Restricted Project
paulwalker-arm added inline comments to D94069: [NFC][InstructionCost]Migrate VectorCombine.cpp to use InstructionCost.
Thu, Jan 7, 1:40 AM · Restricted Project

Wed, Jan 6

paulwalker-arm added a comment to D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

I'm just keeping things ticking over. It doesn't have to be this patch, I just did wanted to know if it's something I can take off my TODO list. If you're support eager then FABS also requires fixed length support :)

Wed, Jan 6, 3:49 AM · Restricted Project
paulwalker-arm accepted D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic.

Do you plan to add support for fixed length vectors?

Wed, Jan 6, 3:12 AM · Restricted Project

Tue, Jan 5

paulwalker-arm committed rGeba6deab22b5: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations. (authored by paulwalker-arm).
[SVE] Lower vector CTLZ, CTPOP and CTTZ operations.
Tue, Jan 5, 2:57 AM
paulwalker-arm closed D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Tue, Jan 5, 2:57 AM · Restricted Project
paulwalker-arm added a comment to D91834: [SelectionDAG] Use TypeSize for the stack offset..

As before I still believe there should be a test to protect this fix as presumably you're doing it for a reason.

Tue, Jan 5, 2:29 AM · Restricted Project

Sun, Dec 27

paulwalker-arm accepted D93825: [AArch64] Fix legalization of i128 ctpop without neon.
Sun, Dec 27, 2:24 AM · Restricted Project
paulwalker-arm added inline comments to D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Sun, Dec 27, 2:17 AM · Restricted Project

Tue, Dec 22

paulwalker-arm committed rGbe85b3e4324b: Fix some misnamed variables in sve-fixed-length-int-minmax.ll. (authored by paulwalker-arm).
Fix some misnamed variables in sve-fixed-length-int-minmax.ll.
Tue, Dec 22, 9:12 AM
paulwalker-arm committed rG8eec7294fea8: [SVE] Lower vector BITREVERSE and BSWAP operations. (authored by paulwalker-arm).
[SVE] Lower vector BITREVERSE and BSWAP operations.
Tue, Dec 22, 8:51 AM
paulwalker-arm closed D93606: [SVE] Lower vector BITREVERSE and BSWAP operations..
Tue, Dec 22, 8:51 AM · Restricted Project

Mon, Dec 21

paulwalker-arm updated the diff for D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..

Fixed incorrect variable naming within ctlz_v64i8, ctpop_v64i8, cttz_v64i8.

Mon, Dec 21, 8:23 AM · Restricted Project
paulwalker-arm updated the diff for D93606: [SVE] Lower vector BITREVERSE and BSWAP operations..

Fixed incorrect variable naming with bitreverse_v64i8 test.
Made test function names consistent.

Mon, Dec 21, 8:15 AM · Restricted Project

Sun, Dec 20

paulwalker-arm added reviewers for D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations.: cameron.mcinally, david-arm, kmclaughlin.
Sun, Dec 20, 5:09 PM · Restricted Project
paulwalker-arm added reviewers for D93606: [SVE] Lower vector BITREVERSE and BSWAP operations.: cameron.mcinally, david-arm, kmclaughlin.
Sun, Dec 20, 5:09 PM · Restricted Project
paulwalker-arm requested review of D93607: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations..
Sun, Dec 20, 5:08 PM · Restricted Project
paulwalker-arm requested review of D93606: [SVE] Lower vector BITREVERSE and BSWAP operations..
Sun, Dec 20, 5:04 PM · Restricted Project

Dec 18 2020

paulwalker-arm added a comment to D91092: [SVE][CodeGen] Lower scalable masked gathers.

Is that not a bug in WidenVecRes_MGATHER? I would have thought there's an expectation that the element count of MGATHER would match the element count of it's MemVT. That's to say that these nodes allow loads with element extension rather than loads where the vector is packed into a larger container.

Dec 18 2020, 5:49 AM · Restricted Project
paulwalker-arm accepted D93292: [AArch64][SVE] Add optimization to remove redundant ptest instructions.
Dec 18 2020, 5:43 AM · Restricted Project
paulwalker-arm committed rGfc712eb7aa00: [AArch64] Fix Copy Elemination for negative values (authored by tmatheson).
[AArch64] Fix Copy Elemination for negative values
Dec 18 2020, 5:33 AM
paulwalker-arm closed D93100: [AArch64] Fix Copy Elemination for negative values.
Dec 18 2020, 5:33 AM · Restricted Project
paulwalker-arm committed rGc0bc169cb173: [NFC][SVE] Clean up bfloat isel patterns that emit non-bfloat instructions. (authored by paulwalker-arm).
[NFC][SVE] Clean up bfloat isel patterns that emit non-bfloat instructions.
Dec 18 2020, 5:25 AM
paulwalker-arm closed D93404: [NFC][SVE] Clean up bfloat isel patterns that emit non-bfloat instructions..
Dec 18 2020, 5:25 AM · Restricted Project

Dec 17 2020

paulwalker-arm added a comment to D93100: [AArch64] Fix Copy Elemination for negative values.

I'll wait to give other reviewers a chance to comment, but otherwise I'll commit it for you tomorrow.

Dec 17 2020, 6:31 AM · Restricted Project
paulwalker-arm accepted D93100: [AArch64] Fix Copy Elemination for negative values.
Dec 17 2020, 5:53 AM · Restricted Project
paulwalker-arm added inline comments to D93292: [AArch64][SVE] Add optimization to remove redundant ptest instructions.
Dec 17 2020, 4:07 AM · Restricted Project
paulwalker-arm added a comment to D93292: [AArch64][SVE] Add optimization to remove redundant ptest instructions.

Other than some missing tests this looks reasonable to me.

Dec 17 2020, 4:02 AM · Restricted Project

Dec 16 2020

paulwalker-arm added a comment to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..

Just making a note here that I've push D90093 so that we follow the same principle shown here for the lowering of i1 based int_to_fp conversions. This also means getPromotedVTForPredicate is now useable for this patch also.

Dec 16 2020, 4:36 PM · Restricted Project
paulwalker-arm added a comment to D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering..
Dec 16 2020, 4:35 PM · Restricted Project
paulwalker-arm added reviewers for D93404: [NFC][SVE] Clean up bfloat isel patterns that emit non-bfloat instructions.: fpetrogalli, c-rhodes, kmclaughlin.
Dec 16 2020, 9:35 AM · Restricted Project
paulwalker-arm requested review of D93404: [NFC][SVE] Clean up bfloat isel patterns that emit non-bfloat instructions..
Dec 16 2020, 9:33 AM · Restricted Project

Dec 15 2020

paulwalker-arm committed rG632f4d2747f0: [NFC] Fix a few SVEInstrInfo related stylistic issues. (authored by paulwalker-arm).
[NFC] Fix a few SVEInstrInfo related stylistic issues.
Dec 15 2020, 8:13 AM
paulwalker-arm committed rGb74c4dbb9634: [SVE] Move INT_TO_FP i1 promotion into custom lowering. (authored by paulwalker-arm).
[SVE] Move INT_TO_FP i1 promotion into custom lowering.
Dec 15 2020, 4:03 AM
paulwalker-arm closed D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering..
Dec 15 2020, 4:03 AM · Restricted Project
paulwalker-arm committed rG6d35bd1d48e9: [CodeGenPrepare] Update optimizeGatherScatterInst for scalable vectors. (authored by paulwalker-arm).
[CodeGenPrepare] Update optimizeGatherScatterInst for scalable vectors.
Dec 15 2020, 3:56 AM
paulwalker-arm closed D92572: [CodeGenPrepare] Update optimizeGatherScatterInst for scalable vectors..
Dec 15 2020, 3:55 AM · Restricted Project

Dec 11 2020

paulwalker-arm added inline comments to D93050: [SVE][CodeGen] Lower scalable floating-point vector reductions.
Dec 11 2020, 5:55 AM · Restricted Project
paulwalker-arm added inline comments to D93050: [SVE][CodeGen] Lower scalable floating-point vector reductions.
Dec 11 2020, 5:06 AM · Restricted Project

Dec 10 2020

paulwalker-arm added inline comments to D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.
Dec 10 2020, 7:11 AM · Restricted Project
paulwalker-arm accepted D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.

A few stylistic things to consider (I'm only really bothered about loosing the v32 tests) but otherwise looks good.

Dec 10 2020, 5:04 AM · Restricted Project

Dec 9 2020

paulwalker-arm added inline comments to D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.
Dec 9 2020, 7:35 AM · Restricted Project
paulwalker-arm added inline comments to D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.
Dec 9 2020, 3:27 AM · Restricted Project
paulwalker-arm added inline comments to D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.
Dec 9 2020, 3:19 AM · Restricted Project
paulwalker-arm added a comment to D92760: [SelectionDAG] Implement SplitVecOp_INSERT_SUBVECTOR.

If you can find a test that exposes the need for this split function with generic IR that would be really helpful I think - LLVM has managed for a long time without needing this split function so something has changed. I suspect it's probably just the new intrinsic that now exposes this code path.

Dec 9 2020, 2:41 AM · Restricted Project

Dec 3 2020

paulwalker-arm added reviewers for D92572: [CodeGenPrepare] Update optimizeGatherScatterInst for scalable vectors.: kmclaughlin, david-arm, craig.topper.
Dec 3 2020, 4:48 AM · Restricted Project
paulwalker-arm requested review of D92572: [CodeGenPrepare] Update optimizeGatherScatterInst for scalable vectors..
Dec 3 2020, 4:45 AM · Restricted Project

Nov 30 2020

paulwalker-arm added inline comments to D91957: [Support] Migrate more high level cost functions to using InstructionCost.
Nov 30 2020, 5:15 AM · Restricted Project

Nov 26 2020

paulwalker-arm added a comment to D91174: [Support] Introduce a new InstructionCost class.

I agree with @david-arm because this unsigned->class conversion has a different rational than TypeSize. Here we want to have the ability to allow natural maths when computing a cost but also be able to reflect the state where the cost is special, one example of which is "the cost is meaningless", rather than trying to second guess the callers intention and say "just returning a big number in the hope the user does what we need".

Nov 26 2020, 3:00 AM · Restricted Project

Nov 20 2020

paulwalker-arm added a comment to D91834: [SelectionDAG] Use TypeSize for the stack offset..

Change looks sensible but please add a test.

Nov 20 2020, 4:45 AM · Restricted Project

Nov 18 2020

paulwalker-arm added a comment to D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors.

As I see it there are a bunch of pragmas that all enable vectorisation, with each pragma providing a unit of information. One component of this information is the vectorisation factor hint provided by vectorize_width.

Nov 18 2020, 4:48 AM · Restricted Project
paulwalker-arm added a comment to D88962: [SVE] Add support for scalable vectors with vectorize.scalable.enable loop attribute.

Thanks for the info @david-arm. I just figured we'd support vector_width(2), vector_width(2, fixed), vector_width(2, scalable), vector_width(fixed), vector_width(scalable) so I still say splitting the width property across multiple pragmas is against our goal of moving away from fixed length only representations. That said, if this is the consensus then so be it.

Nov 18 2020, 3:49 AM · Restricted Project
paulwalker-arm added a comment to D88962: [SVE] Add support for scalable vectors with vectorize.scalable.enable loop attribute.

Hi @david-arm, can you document the reasons for the change?

Nov 18 2020, 2:54 AM · Restricted Project

Nov 17 2020

paulwalker-arm added inline comments to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.
Nov 17 2020, 10:40 AM · Restricted Project

Nov 13 2020

paulwalker-arm added a comment to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.

Thanks @lebedev.ri, I incorrectly assumed exposing existing functionality wouldn't require an RFC. I'm putting together an RFC to cover support for other scalable vector shuffles so I'll include these within that.

Nov 13 2020, 8:33 AM · Restricted Project

Nov 12 2020

paulwalker-arm added a comment to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.

@lebedev.ri: shufflevector only has minimal support for scalable vectors with only the splat case covered (and even that has its quirks). With the recent change to force the mask to be an ArrayRef there is no way to represent arbitrary shuffles and at the same time the implementation forced a requirement that scalable vector data inputs imply a scalable vector result.

Nov 12 2020, 9:20 AM · Restricted Project
paulwalker-arm added a comment to D91362: [SelectionDAG] Add llvm.vector.{extract,insert} intrinsics.

Presumably you're planning to add some tests?

Nov 12 2020, 9:01 AM · Restricted Project

Nov 4 2020

paulwalker-arm accepted D90710: [UBSan] Cannot negate smallest negative signed integer.
Nov 4 2020, 4:06 AM · Restricted Project

Oct 29 2020

paulwalker-arm accepted D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Oct 29 2020, 7:26 AM · Restricted Project

Oct 28 2020

paulwalker-arm added a comment to D89576: [SVE][CodeGen] Lower scalable masked scatters.

Just a couple of general observations as I'm not sure if I'll get chance to properly review before the patch is accepted. I'm not expecting any changes based on these comments as they're effectively refactoring and thus getting to a state where MGATHER/MSCATTER works for SVE is a better starting point for such refactoring.

Oct 28 2020, 5:42 AM · Restricted Project
paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Oct 28 2020, 5:28 AM · Restricted Project

Oct 24 2020

paulwalker-arm abandoned D89950: [SVE] Implement extractelement of i1 from scalable vectors..
Oct 24 2020, 10:11 AM · Restricted Project
paulwalker-arm added a reviewer for D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering.: kmclaughlin.

I've created this patch so as to be consistent with D87651.

Oct 24 2020, 3:36 AM · Restricted Project
paulwalker-arm requested review of D90093: [SVE] Move INT_TO_FP i1 promotion into custom lowering..
Oct 24 2020, 3:32 AM · Restricted Project

Oct 23 2020

paulwalker-arm accepted D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

With this patch[1] landed I believe operation legalisation is now a solved problem for SVE (well for fixed length vectors). I think it's worth tackling the type legalisation side of things rather than overcomplicating shouldExpandReduction. Of course that's easy for me to say given it's your time :) but you've already done part of the work based on the older patch.

Oct 23 2020, 11:53 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@cameron.mcinally: I'm sure you know this but just in case it saves some time I can confirm you will not hit the splitting code until after you relax shouldExpandReduction. So I think your current patch is complete so it really comes down to whether adding the support this way round (i.e. only allow legal types for SVE, then allow all types and implement the legalisation) is acceptable to @nikic .

Oct 23 2020, 9:29 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@paulwalker-arm There is no need to implement any target-specific support. The legalization outcome will be a simple chain of extracts and fadd/fmuls. It does not need to generate good code, just not assert for any VTs.

Oct 23 2020, 8:51 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

@nikic Why does wanting to implement VECREDUCE_SEQ_FADD for SVE necessitate having to implement full support for NEON (AArch64 and Arm)?

Oct 23 2020, 8:22 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

The new tests would be broken without the legalisation changes, so I'm assuming that those are enough coverage. Maybe I'm missing something though...

Oct 23 2020, 7:50 AM · Restricted Project
paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Oct 23 2020, 5:12 AM · Restricted Project
paulwalker-arm accepted D87651: [AArch64][SVE] Implement extractelement of i1 vectors..

I just don't buy this argument. You're saying that we must force all target's to perform custom lowering for promotable illegal operations on i1 vectors because somebody in the future might try to "fix" LegalizeDAG when they should implement custom lowering for extend/truncate operations. This is the situation Target/AArch64 is in and we never considered "fixing" LegalizeDAG so I don't see why others wouldn't just follow our example.

Oct 23 2020, 4:31 AM · Restricted Project

Oct 22 2020

paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Sorry @cameron.mcinally I've not had much time for code reviews this week although will take proper look tomorrow. I have a question though. You've added extra legalisation support but I don't see any explicit tests (or at least ones with matching check lines) for it. Is this something you need for this patch? (I'm guessing sve-fixed-length-fp-reduce.ll's stock NEON run line triggers the cases?) If so then there really should be a neon specific test file that verifies the widening and scalarisation changes as the NEON run line for the "fixed-length" tests is more about ensuring no SVE instructions slip through.

Oct 22 2020, 9:37 AM · Restricted Project
paulwalker-arm added a comment to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..

Perhaps I'm missing something but I've created D89950 to show what I mentioned in my previous comment. To me it's preferable to have this as target independent code as it seems a common enough solution. I know it results in "Pomote" having multiple meanings but that boat has sailed because different nodes have already chosen different meanings and I think it's pretty clear from the old and new VTs what's being asked for.

Oct 22 2020, 4:26 AM · Restricted Project
paulwalker-arm requested review of D89950: [SVE] Implement extractelement of i1 from scalable vectors..
Oct 22 2020, 4:17 AM · Restricted Project

Oct 20 2020

paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Oct 20 2020, 3:44 PM · Restricted Project

Oct 16 2020

paulwalker-arm accepted D88654: [SVE][CodeGen] Replace uses of TypeSize comparison operators with calls to isKnownXY.
Oct 16 2020, 4:42 AM · Restricted Project

Oct 15 2020

paulwalker-arm added a comment to D88654: [SVE][CodeGen] Replace uses of TypeSize comparison operators with calls to isKnownXY.

I guess most of my comments relate to minimising direct uses of TypeSize.

Oct 15 2020, 8:49 AM · Restricted Project
paulwalker-arm added inline comments to D89382: [SVE][CodeGen] Lower scalable integer vector reductions.
Oct 15 2020, 6:10 AM · Restricted Project

Oct 14 2020

paulwalker-arm accepted D89263: [SVE] Lower fixed length VECREDUCE_FADD operation.

Not lowering to SVE for v2f## MVTs makes sense for now but as before when we have proper support for v#i1 our hands will be tied.

Oct 14 2020, 4:27 AM · Restricted Project

Oct 13 2020

paulwalker-arm committed rG981b31c282ea: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0" (authored by paulwalker-arm).
[SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0"
Oct 13 2020, 2:55 AM
paulwalker-arm closed D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".
Oct 13 2020, 2:55 AM · Restricted Project

Oct 12 2020

paulwalker-arm added a comment to D89246: [SVE] Remove aarch64_sve_vector_pcs attribute.

I think we should keep this because it gives us the possibility to attach it to functions where the function signature wouldn't use it otherwise.

Oct 12 2020, 9:22 AM · Restricted Project
paulwalker-arm added a comment to D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".

Looking at the testing I think there are some holes regarding general vector inserts, but I'll investigate that under a different patch.

Oct 12 2020, 4:48 AM · Restricted Project
paulwalker-arm added a comment to D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation.

Are you planning to add support for the normal VECREDUCE_FADD? I ask because that's likely to see more initial use upstream than the SEQ variant.

Oct 12 2020, 4:47 AM · Restricted Project
paulwalker-arm added reviewers for D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0": cameron.mcinally, david-arm, kmclaughlin.
Oct 12 2020, 4:41 AM · Restricted Project
paulwalker-arm requested review of D89235: [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0".
Oct 12 2020, 4:40 AM · Restricted Project

Oct 8 2020

paulwalker-arm accepted D88974: [SVE] Lower fixed length VECREDUCE_XOR operation.
Oct 8 2020, 4:18 AM · Restricted Project

Oct 6 2020

paulwalker-arm committed rG8bb702a8ad30: [SVE] Lower fixed length vector floating point rounding operations. (authored by paulwalker-arm).
[SVE] Lower fixed length vector floating point rounding operations.
Oct 6 2020, 2:57 AM
paulwalker-arm committed rG27f3d51b4ef9: [SVE] Lower fixed length vector fneg and fsqrt operations. (authored by paulwalker-arm).
[SVE] Lower fixed length vector fneg and fsqrt operations.
Oct 6 2020, 2:57 AM
paulwalker-arm closed D88683: [SVE] Lower fixed length vector fneg and fsqrt operations..
Oct 6 2020, 2:57 AM · Restricted Project
paulwalker-arm closed D88671: [SVE] Lower fixed length vector floating point rounding operations..
Oct 6 2020, 2:57 AM · Restricted Project
paulwalker-arm accepted D88847: [SVE] Lower fixed length VECREDUCE_OR operation.
Oct 6 2020, 2:46 AM · Restricted Project