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paulwalker-arm (Paul Walker)
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User Since
Nov 24 2016, 5:21 AM (238 w, 4 d)

Recent Activity

Today

paulwalker-arm added inline comments to D104573: [AArch64] Optimize SVE bitcasts of unpacked types..
Mon, Jun 21, 4:27 AM · Restricted Project
paulwalker-arm accepted D104468: [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics.
Mon, Jun 21, 3:24 AM · Restricted Project

Fri, Jun 18

paulwalker-arm added inline comments to D104468: [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics.
Fri, Jun 18, 9:37 AM · Restricted Project
paulwalker-arm added inline comments to D104468: [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics.
Fri, Jun 18, 6:26 AM · Restricted Project
paulwalker-arm accepted D103702: [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries.
Fri, Jun 18, 5:35 AM · Restricted Project, Restricted Project

Thu, Jun 17

paulwalker-arm added inline comments to D102842: [Verifier] Fail on invalid indices for {insert,extract} vector intrinsics.
Thu, Jun 17, 4:08 AM · Restricted Project
paulwalker-arm added inline comments to D102842: [Verifier] Fail on invalid indices for {insert,extract} vector intrinsics.
Thu, Jun 17, 3:44 AM · Restricted Project

Tue, Jun 15

paulwalker-arm added inline comments to D104217: [AArch64][SVE] Add support for fixed length MSCATTER/MGATHER.
Tue, Jun 15, 4:57 AM · Restricted Project

Mon, Jun 14

paulwalker-arm added inline comments to D103702: [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries.
Mon, Jun 14, 10:27 AM · Restricted Project, Restricted Project

Thu, Jun 10

paulwalker-arm added inline comments to D103702: [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries.
Thu, Jun 10, 5:07 AM · Restricted Project, Restricted Project

Wed, Jun 9

paulwalker-arm added a comment to D103170: [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory.

I'll take a more detailed look later but structurally it looks fine to me. I've added a comment that hopefully means we don't need the frame index limitation.

Wed, Jun 9, 11:51 AM · Restricted Project
paulwalker-arm added a comment to D103882: [CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> expensive..

My feeling is that the vectoriser should never try to vectorise a loop that is impossible to vectorise, with the act of costing a vectorisation candidate effectively saying the loop is safe to vectorise. So a way to guard this is to ensure that when costing a vectorisation candidate we force the need for a real cost. It's just unfortunate that when it comes to scalable vectorisation there are more scenarios that lead to loops that are not vectorisable (or rather, loops where scalable VFs must be pulled from the list of candidate VFs).

Wed, Jun 9, 2:32 AM · Restricted Project

Tue, Jun 8

paulwalker-arm accepted D103882: [CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> expensive..

Personally, for the testing I'd pick a different element type than i128 given that is already problematic.

Tue, Jun 8, 9:28 AM · Restricted Project

Thu, Jun 3

paulwalker-arm accepted D103168: [AArch64][SVE] Add support for using reverse forms of SVE2 shifts.
Thu, Jun 3, 2:40 AM · Restricted Project

Tue, Jun 1

paulwalker-arm accepted D98722: [LV] Build and cost VPlans for scalable VFs..
Tue, Jun 1, 4:07 AM · Restricted Project

May 21 2021

paulwalker-arm added inline comments to D102842: [Verifier] Fail on invalid indices for {insert,extract} vector intrinsics.
May 21 2021, 9:06 AM · Restricted Project
paulwalker-arm accepted D102607: [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND.
May 21 2021, 7:52 AM · Restricted Project
paulwalker-arm added inline comments to D102765: [SelectionDAG] Add stub implementation of ReplaceInsertSubVectorResults.
May 21 2021, 6:31 AM · Restricted Project

May 20 2021

paulwalker-arm added inline comments to D102765: [SelectionDAG] Add stub implementation of ReplaceInsertSubVectorResults.
May 20 2021, 10:47 AM · Restricted Project
paulwalker-arm added inline comments to D102766: [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR.
May 20 2021, 10:42 AM · Restricted Project
paulwalker-arm added inline comments to D102607: [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND.
May 20 2021, 10:28 AM · Restricted Project
paulwalker-arm accepted D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 20 2021, 10:03 AM · Restricted Project
paulwalker-arm accepted D102699: [InstSimplify] Properly constrain {insert,extract}_subvector intrinsic fold.
May 20 2021, 9:44 AM · Restricted Project

May 19 2021

paulwalker-arm added inline comments to D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 19 2021, 10:32 AM · Restricted Project
paulwalker-arm added a comment to D102607: [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND.

I've added a recommendation that I believe will also simplify D102777.

May 19 2021, 9:29 AM · Restricted Project

May 18 2021

paulwalker-arm added inline comments to D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 18 2021, 8:58 AM · Restricted Project
paulwalker-arm added inline comments to D101986: [InstSimplify] Remove redundant {insert,extract}_vector intrinsic chains.
May 18 2021, 8:35 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 18 2021, 8:12 AM · Restricted Project
paulwalker-arm added inline comments to D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 18 2021, 3:08 AM · Restricted Project

May 17 2021

paulwalker-arm added inline comments to D101945: [LV] Add -scalable-vectorization=<option> flag..
May 17 2021, 4:01 AM · Restricted Project
paulwalker-arm added inline comments to D101945: [LV] Add -scalable-vectorization=<option> flag..
May 17 2021, 3:46 AM · Restricted Project
paulwalker-arm accepted D101945: [LV] Add -scalable-vectorization=<option> flag..
May 17 2021, 2:37 AM · Restricted Project
paulwalker-arm added inline comments to D102498: [AArch64][SVE] Improve codegen for fixed length vector concat.
May 17 2021, 2:18 AM · Restricted Project

May 16 2021

paulwalker-arm added a comment to D101945: [LV] Add -scalable-vectorization=<option> flag..

A few stylistic things to consider that I'll not hold you to, but the change to validate is the main thing stopping me from accepting the patch.

May 16 2021, 4:15 AM · Restricted Project

May 13 2021

paulwalker-arm accepted D101831: [AArch64][SVE] Add unpredicated vector BIC ISD node.
May 13 2021, 3:14 AM · Restricted Project
paulwalker-arm accepted D102077: [AArch64][SVE] Combine cntp intrinsics with add/sub to produce incp/decp.
May 13 2021, 3:10 AM · Restricted Project

May 12 2021

paulwalker-arm added inline comments to D101945: [LV] Add -scalable-vectorization=<option> flag..
May 12 2021, 9:48 AM · Restricted Project
paulwalker-arm added inline comments to D102330: [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs for RDFFR_P.
May 12 2021, 8:17 AM · Restricted Project
paulwalker-arm accepted D101357: [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr.
May 12 2021, 7:03 AM · Restricted Project
paulwalker-arm added inline comments to D101357: [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr.
May 12 2021, 4:52 AM · Restricted Project

May 11 2021

paulwalker-arm accepted D101544: [AArch64][SVE] Improve sve.convert.to.svbool lowering.
May 11 2021, 9:47 AM · Restricted Project
paulwalker-arm added inline comments to D101831: [AArch64][SVE] Add unpredicated vector BIC ISD node.
May 11 2021, 7:44 AM · Restricted Project
paulwalker-arm accepted D101357: [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr.

Looks good to me. I've a few comments that you're free to ignore.

May 11 2021, 4:51 AM · Restricted Project

May 10 2021

paulwalker-arm added inline comments to D102077: [AArch64][SVE] Combine cntp intrinsics with add/sub to produce incp/decp.
May 10 2021, 11:39 AM · Restricted Project

May 2 2021

paulwalker-arm added inline comments to D101357: [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr.
May 2 2021, 3:37 AM · Restricted Project
paulwalker-arm added inline comments to D101544: [AArch64][SVE] Improve sve.convert.to.svbool lowering.
May 2 2021, 3:07 AM · Restricted Project
paulwalker-arm accepted D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes.

If you think it's worth addressing, I can try messing with the matcher.

May 2 2021, 2:34 AM · Restricted Project

Apr 30 2021

paulwalker-arm accepted D101642: [AArch64][SVE] Remove unused function missed from D101302.
Apr 30 2021, 8:36 AM · Restricted Project
paulwalker-arm accepted D101593: [AArch64][SVE] Remove index_vector node..

Please can you also remove INDEX_VECTOR from the AArch64ISD enum.

Apr 30 2021, 5:09 AM · Restricted Project
paulwalker-arm accepted D101574: [AArch64] Fix lowering for fshl/fshr with SVE types..

I'm not against adding the extra tests, which could also include the legal i8, i16 & i32 vector types, but for my money there's little new code here so I'm happy to assume the common expand/legalisation code is already well tested.

Apr 30 2021, 3:24 AM · Restricted Project
paulwalker-arm accepted D100816: [AArch64][SVE] Lower index_vector to step_vector.
Apr 30 2021, 3:17 AM · Restricted Project
paulwalker-arm added a comment to D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes.

Are we concerned about the reduced code quality shown by the splice tests? Is there a way to know if the basic block is, or within, a loop body? so that we can restrict the patterns to instances where we're confident the extra instructions are likely to be hoisted. I guess for the PTRUE case we already know there is a need for some kind of machine pass to remove larger element PTRUEs when a smaller element one is safe to use.

Apr 30 2021, 3:12 AM · Restricted Project

Apr 29 2021

paulwalker-arm added a comment to D100816: [AArch64][SVE] Lower index_vector to step_vector.

Assuming you agree I think you can just delete a bit of code and then the patch is good to go.

Apr 29 2021, 10:07 AM · Restricted Project

Apr 28 2021

paulwalker-arm added inline comments to D101369: [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N.
Apr 28 2021, 2:11 AM · Restricted Project

Apr 27 2021

paulwalker-arm added inline comments to D101062: [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics.
Apr 27 2021, 7:31 AM · Restricted Project
paulwalker-arm added inline comments to D101076: [SVE][LoopVectorize] Add support for scalable vectorization of first-order recurrences.
Apr 27 2021, 6:08 AM · Restricted Project
paulwalker-arm accepted D101042: [AArch64] Add missing UINT_TO_FP promotions for v16i8.

Looks fine to me given this is more a "compiler shouldn't crash" test that will be updated once we have support to custom lower these nodes.

Apr 27 2021, 5:10 AM · Restricted Project
paulwalker-arm added inline comments to D100816: [AArch64][SVE] Lower index_vector to step_vector.
Apr 27 2021, 5:07 AM · Restricted Project

Apr 26 2021

paulwalker-arm added inline comments to D101042: [AArch64] Add missing UINT_TO_FP promotions for v16i8.
Apr 26 2021, 3:42 AM · Restricted Project

Apr 23 2021

paulwalker-arm added inline comments to D101076: [SVE][LoopVectorize] Add support for scalable vectorization of first-order recurrences.
Apr 23 2021, 4:14 AM · Restricted Project

Apr 22 2021

paulwalker-arm accepted D100370: [AArch64][SVE] Fix bug in lowering of fixed-length integer vector divides.

The non-power-of-two RUN lines should be extended to allow maximum testing (see comments) but otherwise looks good.

Apr 22 2021, 9:59 AM · Restricted Project
paulwalker-arm accepted D100812: [DAGCombiner] Allow operand of step_vector to be negative..

A couple of minor requests plus it's worth adding a "step-vector has more than one use" test but otherwise looks good to me. Thanks for your efforts @junparser, also thanks @frasercrmck and @craig.topper for the assists.

Apr 22 2021, 3:14 AM · Restricted Project

Apr 21 2021

paulwalker-arm added inline comments to D100812: [DAGCombiner] Allow operand of step_vector to be negative..
Apr 21 2021, 8:48 AM · Restricted Project
paulwalker-arm added inline comments to D100858: [AArch64][SVE] Allow generation of MOVPRFX for intrinsic nodes.
Apr 21 2021, 5:56 AM · Restricted Project
paulwalker-arm added inline comments to D100812: [DAGCombiner] Allow operand of step_vector to be negative..
Apr 21 2021, 5:17 AM · Restricted Project
paulwalker-arm added inline comments to D100812: [DAGCombiner] Allow operand of step_vector to be negative..
Apr 21 2021, 2:58 AM · Restricted Project

Apr 20 2021

paulwalker-arm accepted D100851: [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines.
Apr 20 2021, 7:14 AM · Restricted Project
paulwalker-arm added inline comments to D100487: [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions.
Apr 20 2021, 5:59 AM · Restricted Project
paulwalker-arm added a comment to D100812: [DAGCombiner] Allow operand of step_vector to be negative..

I've nothing against the change but it is more involved than updating the comment and assert. There are places where STEP_VECTOR's operand is treated as unsigned, based on the original requirement, that will need to be updated. For example DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR. Ideally we'd want to add/update tests to show the signedness is properly protected during type legalisation.

Apr 20 2021, 1:58 AM · Restricted Project

Apr 19 2021

paulwalker-arm added inline comments to D100370: [AArch64][SVE] Fix bug in lowering of fixed-length integer vector divides.
Apr 19 2021, 10:12 AM · Restricted Project
paulwalker-arm resigned from D91512: [AArch64][Isel] Avoid implicit zext for SIGN_EXTEND_INREG ( TRUNCATE ).
Apr 19 2021, 5:02 AM · Restricted Project
paulwalker-arm accepted D100564: [TTI] NFC: Change getScalingFactorCost to return InstructionCost.

One comment about preexisting possibly redundant code so the patch looks good to me.

Apr 19 2021, 5:01 AM · Restricted Project
paulwalker-arm accepted D100660: [SelectionDAG] Relax constraints on STEP_VECTOR step operand.
Apr 19 2021, 4:12 AM · Restricted Project
paulwalker-arm accepted D100487: [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions.
Apr 19 2021, 4:06 AM · Restricted Project
paulwalker-arm added a comment to D100527: [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes.

Sounds sensible to me but wonder if there's a nicer way to create the patterns as it seems we're likely to have a significant number of patterns targeting the same instructions. Do you think it's possible to have something like load_8 match all things where LD1_B (reg+reg) can be used?

Apr 19 2021, 3:41 AM · Restricted Project
paulwalker-arm added inline comments to D99074: [llvm][AArch64][SVE] Fold literals into math instructions.
Apr 19 2021, 3:37 AM · Restricted Project
paulwalker-arm accepted D100107: [AArch64][SVE] Combine add and index_vector.
Apr 19 2021, 3:18 AM · Restricted Project
paulwalker-arm added inline comments to D100370: [AArch64][SVE] Fix bug in lowering of fixed-length integer vector divides.
Apr 19 2021, 2:55 AM · Restricted Project
paulwalker-arm added a comment to D100476: [AArch64][SVEIntrinsicOpts] Replace last{a,b} intrinsic calls with extracts....

Looks fine to me with a couple of issues that can be resolved before committing.

Apr 19 2021, 2:30 AM · Restricted Project
paulwalker-arm accepted D100476: [AArch64][SVEIntrinsicOpts] Replace last{a,b} intrinsic calls with extracts....
Apr 19 2021, 2:28 AM · Restricted Project
paulwalker-arm accepted D100463: [AArch64][SVEIntrinsicOpts] Fold sve_convert_from_svbool(zero) to zero.
Apr 19 2021, 2:11 AM · Restricted Project

Apr 16 2021

paulwalker-arm added inline comments to D100476: [AArch64][SVEIntrinsicOpts] Replace last{a,b} intrinsic calls with extracts....
Apr 16 2021, 5:02 AM · Restricted Project

Apr 15 2021

paulwalker-arm added inline comments to D100487: [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions.
Apr 15 2021, 7:58 AM · Restricted Project

Apr 14 2021

paulwalker-arm added a comment to D100107: [AArch64][SVE] Combine add and index_vector.
Apr 14 2021, 2:58 AM · Restricted Project

Apr 6 2021

paulwalker-arm added inline comments to D99699: [AArch64][SVE] Lowering sve.dot to DOT node.
Apr 6 2021, 4:48 AM · Restricted Project

Apr 1 2021

paulwalker-arm accepted D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Apr 1 2021, 6:44 AM · Restricted Project
paulwalker-arm added inline comments to D99699: [AArch64][SVE] Lowering sve.dot to DOT node.
Apr 1 2021, 4:00 AM · Restricted Project

Mar 31 2021

paulwalker-arm added a reviewer for D99657: [AArch64][SVE] SVE functions should use the SVE calling convention for fast calls: sdesmalen.
Mar 31 2021, 5:53 AM · Restricted Project
paulwalker-arm added inline comments to D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Mar 31 2021, 2:53 AM · Restricted Project
paulwalker-arm accepted D99584: [AArch64][SVE] Remove redundant PTEST of MATCH/NMATCH results.
Mar 31 2021, 2:41 AM · Restricted Project

Mar 30 2021

paulwalker-arm added a comment to D97299: [IR][SVE] Add new llvm.experimental.stepvector intrinsic.

I'm still struggling with how best to represent STEPVECTOR's scale operand. The patch as it currently stands is probably good enough but I do wonder how long we'll get by without needing to implement PromoteIntOp_STEP_VECTOR. I also wonder if we can take a similar approach as done for INSERT_SUBVECTOR's index operand.

Hey. Sorry to raise a closed thread but this exact issue is making it difficult to support STEP_VECTOR on RISC-V. On RV32 we don't have legal i64 but do have legal i64 vectors. So we're hitting an assert during visitStepVector where we try and create a nxvXi64 STEP_VECTOR with an i32 operand. Are you aware of anything that stops us from changing the requirements to be an integer pointer type? It might limit optimizations but we can always not perform DAG combines if it's not safe to do so?

Mar 30 2021, 7:59 AM · Restricted Project
paulwalker-arm added inline comments to D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types.
Mar 30 2021, 2:32 AM · Restricted Project

Mar 29 2021

paulwalker-arm added a comment to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).

Just wanted to add that the patch summary no longer matches the intent of the patch.

Mar 29 2021, 7:48 AM · Restricted Project
paulwalker-arm accepted D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).
Mar 29 2021, 7:45 AM · Restricted Project
paulwalker-arm accepted D99502: [InstructionCost] Don't conflate Invalid costs with Unknown costs..

I agree, InstructionCost::Invalid is solving a specific problem which is different to "Did not bother computing a real cost".

Mar 29 2021, 7:30 AM · Restricted Project
paulwalker-arm accepted D98939: [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps.
Mar 29 2021, 7:22 AM · Restricted Project
paulwalker-arm accepted D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT.
Mar 29 2021, 7:08 AM · Restricted Project
paulwalker-arm accepted D99412: [AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement.
Mar 29 2021, 5:08 AM · Restricted Project
paulwalker-arm added inline comments to D99324: [AArch64][SVE] Codegen dup_lane for dup(vector_extract).
Mar 29 2021, 4:43 AM · Restricted Project
paulwalker-arm added inline comments to D99412: [AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement.
Mar 29 2021, 4:20 AM · Restricted Project