Page MenuHomePhabricator

paulwalker-arm (Paul Walker)
User

Projects

User does not belong to any projects.

User Details

User Since
Nov 24 2016, 5:21 AM (200 w, 6 d)

Recent Activity

Today

paulwalker-arm updated the diff for D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction..

Don't suggest promotion for 'vscale x 16' lane floating point operations.

Wed, Sep 30, 6:17 AM · Restricted Project
paulwalker-arm added reviewers for D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction.: efriedma, sdesmalen, david-arm, kmclaughlin.
Wed, Sep 30, 3:58 AM · Restricted Project
paulwalker-arm requested review of D88552: [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction..
Wed, Sep 30, 3:56 AM · Restricted Project

Yesterday

paulwalker-arm accepted D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

@cameron.mcinally No worries, I clearly didn't do the best job reviewing that patch either.

Tue, Sep 29, 9:45 AM · Restricted Project
paulwalker-arm added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Tue, Sep 29, 9:03 AM · Restricted Project
paulwalker-arm added inline comments to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.
Tue, Sep 29, 3:50 AM · Restricted Project
paulwalker-arm added a comment to D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable.

Also, while I have everyone's attention, there are a number of unhandled vector reduction intrinsics with SVE support. Do we want to add lowerings for those? E.g. ANDV.

Tue, Sep 29, 3:05 AM · Restricted Project
paulwalker-arm accepted D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations.

FP_ROUND's extra operand is a tad inconvenient but that's not your fault and you're following the naming rules for _MERGE_PASSTHRU so this LGTM. I'll note there's no illegal to illegal test for fptrunc like there is for fpext but then I don't know what those tests are verifying that's not already covered by the illegal<->legal tests.

Tue, Sep 29, 2:46 AM · Restricted Project

Mon, Sep 28

paulwalker-arm added a comment to D88317: [SVE] Lower fixed length VECREDUCE_[UMAX|UMIN] to Scalable.

Or, if @kmclaughlin would like, I can add the Scalable lowerings while I'm here. Assuming you don't have downstream changes prepared already...

Mon, Sep 28, 7:50 AM · Restricted Project
paulwalker-arm accepted D88317: [SVE] Lower fixed length VECREDUCE_[UMAX|UMIN] to Scalable.

Just a heads up that @kmclaughlin is starting to look at legalisation/lowering for scalable vector types. From an operation legalisation point of view you've done most of the plumbing so hopefully any toe treading will be minimal.

Mon, Sep 28, 4:28 AM · Restricted Project

Fri, Sep 25

paulwalker-arm accepted D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

Formatting issues aside this LGTM.

Fri, Sep 25, 11:06 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations.
Fri, Sep 25, 10:59 AM · Restricted Project
paulwalker-arm accepted D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.

LGTM assuming the potential compiler warning is removed.

Fri, Sep 25, 6:24 AM · Restricted Project
paulwalker-arm added inline comments to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.
Fri, Sep 25, 3:42 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

@david-arm The main priority is to remove the operator overloads so if universally using divideCoefficientBy pleases the most people then let's just do that.

Fri, Sep 25, 3:41 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.

Other than a quibble related to singleton DAG checks this patch LGTM.

Fri, Sep 25, 2:51 AM · Restricted Project

Thu, Sep 24

paulwalker-arm added inline comments to D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.
Thu, Sep 24, 6:21 PM · Restricted Project
paulwalker-arm added inline comments to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Thu, Sep 24, 4:16 PM · Restricted Project
paulwalker-arm added inline comments to D88259: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable.
Thu, Sep 24, 4:05 PM · Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

I think the precedent has already been set as VectorType and ValueType already deem doubling and halving to be special enough to have explicit operations, albeit they save more effort that what's being saved here. Personally I just think

ElementCount.halve()

is more meaningful/readable than

assert(ElementCount.isKnownMultiple(2));
ElementCount.coefficientDiv(2);

Whereas ElementCount * 2 is already meaningful enough.

Thu, Sep 24, 9:39 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88186: [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base..
Thu, Sep 24, 4:10 AM · Restricted Project

Wed, Sep 23

paulwalker-arm added inline comments to D88098: [SVE] Add new isKnownXX comparison functions to TypeSize.
Wed, Sep 23, 9:04 AM · Restricted Project
paulwalker-arm added a comment to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.

LGTM

Alternatively, we could make CONCAT_VECTOR "legal", and lower it using an isel pattern. But I'm not sure that's actually an improvement.

Wed, Sep 23, 5:37 AM · Restricted Project
paulwalker-arm added a comment to D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy.

I'm not a great fan of the coefficientDiv name but once in I doubt I'll give it a second thought. That said, because by far the most common usage is coefficientDiv(2), whose intent is clearly to knowingly split something into two equal parts I'm wondering if adding a halve() utility function will keep the main usage short and meaningful and then there's even less reason to care about the name of coefficientDiv.

Wed, Sep 23, 5:06 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D88098: [SVE] Add new isKnownXX comparison functions to TypeSize.

My preference would be to follow the clang-format advice for TypeSize.h.

Wed, Sep 23, 4:06 AM · Restricted Project
paulwalker-arm accepted D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.
Wed, Sep 23, 3:41 AM · Restricted Project
paulwalker-arm accepted D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Wed, Sep 23, 2:22 AM · Restricted Project

Tue, Sep 22

paulwalker-arm added inline comments to D88033: [SVE][CodeGen] Legalisation of integer -> floating point conversions.
Tue, Sep 22, 3:16 AM · Restricted Project
paulwalker-arm accepted D88032: [AArch64][SVE] Add lowering for llvm frecpx.
Tue, Sep 22, 3:02 AM · Restricted Project
paulwalker-arm added inline comments to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.
Tue, Sep 22, 3:00 AM · Restricted Project

Mon, Sep 21

paulwalker-arm committed rGf3fa954b5b19: [SVE] Change definition of reduction ISD nodes to have an SVE vector result… (authored by paulwalker-arm).
[SVE] Change definition of reduction ISD nodes to have an SVE vector result…
Mon, Sep 21, 5:23 AM
paulwalker-arm closed D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type..
Mon, Sep 21, 5:23 AM · Restricted Project
paulwalker-arm committed rG6457455248d5: [SVE] Use NEON for extract_vector_elt when the index is in range. (authored by paulwalker-arm).
[SVE] Use NEON for extract_vector_elt when the index is in range.
Mon, Sep 21, 5:16 AM
paulwalker-arm closed D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Mon, Sep 21, 5:15 AM · Restricted Project

Fri, Sep 18

paulwalker-arm added inline comments to D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Fri, Sep 18, 9:43 AM · Restricted Project
paulwalker-arm updated the diff for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..

Replaced custom selection with isel patterns. Since we're going the isel route I figures I may was well add the missing patterns for unpacked floating point types.

Fri, Sep 18, 9:29 AM · Restricted Project

Thu, Sep 17

paulwalker-arm updated the diff for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..

Remove block that is incorrectly reporting unpacked and predicate EXTRACT_VECTOR_ELT as legal.

Thu, Sep 17, 12:30 PM · Restricted Project
paulwalker-arm added inline comments to D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Thu, Sep 17, 12:26 PM · Restricted Project
paulwalker-arm added a comment to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.

D87843 fixes the issue. Its dependence on D87842 is purely to maintain current code quality.

Thu, Sep 17, 10:30 AM · Restricted Project
paulwalker-arm added reviewers for D87842: [SVE] Use NEON for extract_vector_elt when the index is in range.: kmclaughlin, david-arm.
Thu, Sep 17, 10:27 AM · Restricted Project
paulwalker-arm added reviewers for D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.: cameron.mcinally, sdesmalen, c-rhodes.
Thu, Sep 17, 10:27 AM · Restricted Project
paulwalker-arm requested review of D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type..
Thu, Sep 17, 10:25 AM · Restricted Project
paulwalker-arm requested review of D87842: [SVE] Use NEON for extract_vector_elt when the index is in range..
Thu, Sep 17, 10:23 AM · Restricted Project
paulwalker-arm added a comment to D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable.

Oh, I hadn't realised we are handling reduction in this way upstream (although it does match an old design we had downstream). This is certainly not the expected behaviour so I'll get it fixed. The expectation is for the SVE reduction ISD nodes to reflect the underlying instructions behaviour, which is they set the whole vector register. The reason for this is that we don't want the element extraction to be done during isel because it introduces needless vpr-gpr transitions and there are also use cases that make use of the implicit zeroing of the upper lanes.

Thu, Sep 17, 3:31 AM · Restricted Project

Wed, Sep 16

paulwalker-arm added a comment to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.

Oh and the commit message should reference the lowering of FP_TO_SINT/FP_TO_UINT.

Wed, Sep 16, 8:28 AM · Restricted Project
paulwalker-arm accepted D87232: [SVE][CodeGen] Lower floating point -> integer conversions.

LGTM assuming adding the missing tests don't throw up anything unexpected.

Wed, Sep 16, 8:27 AM · Restricted Project
paulwalker-arm added inline comments to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..
Wed, Sep 16, 2:55 AM · Restricted Project

Tue, Sep 15

paulwalker-arm added inline comments to D87707: [AArch64][SVE] Add lowering for llvm fsqrt.
Tue, Sep 15, 10:21 AM · Restricted Project
paulwalker-arm accepted D87707: [AArch64][SVE] Add lowering for llvm fsqrt.

@paulwalker-arm: I couldn't find out the corresponding ISD Node for FRECPX.

Tue, Sep 15, 10:20 AM · Restricted Project
paulwalker-arm added inline comments to D87651: [AArch64][SVE] Implement extractelement of i1 vectors..
Tue, Sep 15, 3:17 AM · Restricted Project

Thu, Sep 10

paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Thu, Sep 10, 2:41 PM · Restricted Project
paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Thu, Sep 10, 12:35 PM · Restricted Project

Wed, Sep 9

paulwalker-arm accepted D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors.

Looks good assuming the new test doesn't throw up any surprises.

Wed, Sep 9, 5:39 AM · Restricted Project

Tue, Sep 8

paulwalker-arm added a comment to D86078: [AArch64] Improved lowering for saturating float to int..

I'm afraid some of my comments are probably conflicting. I would have experimented a little to understand better how things work, but I'm guessing the patch is based on other work because I couldn't some of the affected functions/nodes.

Tue, Sep 8, 7:27 AM · Restricted Project

Mon, Sep 7

paulwalker-arm added a comment to D86078: [AArch64] Improved lowering for saturating float to int..

Sorry I had hoped to look at this patch properly today but that hasn't worked out. I've got a general comment below as I think it would be nicer to abstract the NativeSaturation into a TLI hook that other targets can implement when useful to them.

Mon, Sep 7, 10:46 AM · Restricted Project
paulwalker-arm added inline comments to D87232: [SVE][CodeGen] Lower floating point -> integer conversions.
Mon, Sep 7, 6:55 AM · Restricted Project
paulwalker-arm added inline comments to D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors.
Mon, Sep 7, 5:51 AM · Restricted Project

Thu, Sep 3

paulwalker-arm accepted D86793: [AArch64][SVE] Add lowering for rounding operations.

Other than adding the missing test before landing that patch, this LGTM.

Thu, Sep 3, 8:25 AM · Restricted Project

Wed, Sep 2

paulwalker-arm abandoned D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2]..

With the exception of VSELECT lowering, which is being worked under D85364, everything else is available in master.

Wed, Sep 2, 4:22 AM · Restricted Project, Restricted Project
paulwalker-arm abandoned D71760: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 1/2]..

The intention of this patch is now complete. All work is available in master with the exception of the hook into -msve-vector-bits which is not necessarily the direction we'll use once function attributes are available.

Wed, Sep 2, 4:20 AM · Restricted Project, Restricted Project
paulwalker-arm updated subscribers of D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors.
Wed, Sep 2, 4:15 AM · Restricted Project
paulwalker-arm committed rGf72121254da4: [SVE] Don't reorder subvector/binop sequences when the resulting binop is not… (authored by paulwalker-arm).
[SVE] Don't reorder subvector/binop sequences when the resulting binop is not…
Wed, Sep 2, 3:05 AM
paulwalker-arm closed D86450: [SVE] Don't reorder subvector/binop sequences when the resulting binop is not legal..
Wed, Sep 2, 3:04 AM · Restricted Project

Tue, Sep 1

paulwalker-arm updated subscribers of D70800: Fix AArch64 AAPCS frame record chain.

Fair enough, thanks for the information Owen.

Tue, Sep 1, 12:00 PM · Restricted Project
paulwalker-arm added a comment to D70800: Fix AArch64 AAPCS frame record chain.

Sure, but that means there need to be a way to detect when FP is displaced (hence my original question). If such data is available (and it needs to be for SVE code generation to function correctly) then I don't see why the assert cannot use it to assert Bytes is correctly aligned and displaced.

Tue, Sep 1, 10:36 AM · Restricted Project
paulwalker-arm updated subscribers of D70800: Fix AArch64 AAPCS frame record chain.

But doesn't that mean the assert is now protecting less than it was? Without the knowledge of FP's displacement, you cannot know if Bytes % 8 == 0 is safe or not. Is the knowledge of FP's displacement recorded anyway so the original intent of the assert is not compromised? From an SVE point of view, FP displacement will either need to be prevented or undone if it's used to access SVE stack slots. This is because SVE offsets are implicitly scaled and thus any byte based displacement cannot be encoded into its instructions.

Tue, Sep 1, 10:07 AM · Restricted Project
paulwalker-arm added a comment to D70800: Fix AArch64 AAPCS frame record chain.

I've had to revert this patch because it caused runtime failures when building spec2k/eon with -march=armv8-a+sve -mllvm -aarch64-sve-vector-bits-min=256.

Tue, Sep 1, 8:13 AM · Restricted Project
paulwalker-arm added a reverting change for rGe9d9a612084b: Reapply D70800: Fix AArch64 AAPCS frame record chain: rGbc9a29b9ee6a: Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain".
Tue, Sep 1, 8:11 AM
paulwalker-arm committed rGbc9a29b9ee6a: Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain" (authored by paulwalker-arm).
Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"
Tue, Sep 1, 8:11 AM
paulwalker-arm added a reverting change for D70800: Fix AArch64 AAPCS frame record chain: rGbc9a29b9ee6a: Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain".
Tue, Sep 1, 8:11 AM · Restricted Project

Aug 28 2020

paulwalker-arm added a comment to D85225: [Target][AArch64] Allow for char as int8_t in AArch64AsmParser.cpp.

@ro Is it worth specifying an end date for votes/opinions?

Aug 28 2020, 11:30 AM · Restricted Project
paulwalker-arm added a comment to D85225: [Target][AArch64] Allow for char as int8_t in AArch64AsmParser.cpp.

My vote hasn't changed, I mean I already accepted the tweaked Option1 so you could have been done and dusted by now :) I just don't see what's gained from Option3's refactoring. It does the same as Option1 but in a less type safe/flexible/c++ way. Furthermore, the new interface is needlessly different to the other functions that handle SVE immediate values when the vector element type plays a role.

Aug 28 2020, 10:26 AM · Restricted Project
paulwalker-arm added inline comments to D86793: [AArch64][SVE] Add lowering for rounding operations.
Aug 28 2020, 9:55 AM · Restricted Project
paulwalker-arm added a comment to D86065: [SVE] Make ElementCount members private.

To be more clear, I'm happy to defer the divide conversation for if/when we run into issues so my previous acceptance still stands. It'll be good to get the intent of the patch in (i.e. stoping access to internal class members) asap, plus any follow up work will be a smaller more manageable patch. It's worth talking this through during the next sync call to see it we can get some consensus regarding what maths is and isn't allowed.

Aug 28 2020, 5:20 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D86065: [SVE] Make ElementCount members private.

I'm retracting my operator% request. After thinking about it and speaking with Dave I just cannot see how allowing a total divide is safe for scalable vectors. If you are relying on a truncating divide then special handling is require anyway, which is likely to be different between fixed-length and scalable vectors.

Aug 28 2020, 3:59 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D86065: [SVE] Make ElementCount members private.

Can't say I agree since people are already writing the ugly code, because the result typically demands different handling or they're asserting the divide doesn't truncate in the first place. That said I'm happy for there to be no assert as long as operator% is implemented so users can calculate the remainder in the expected way.

Aug 28 2020, 3:06 AM · Restricted Project, Restricted Project

Aug 27 2020

paulwalker-arm accepted D86065: [SVE] Make ElementCount members private.

There's probably a few .Min to .getKnownMinValue() conversions where the .Min could be dropped (calls to Builder.CreateVectorSplat for example) but they can be tidied up as part of a proper activity to reduce the places where getKnownMinValue is called. So other than my suggested updated to EC::operator/ the patch looks good to my eye. Please give other reviewers a little more time to provide other insights.

Aug 27 2020, 10:34 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D86065: [SVE] Make ElementCount members private.

I cannot say whether such questions make sense without a deeper investigation, but I can say for certain that EC.isPowerOf2 is a question we cannot answer at compile time. Given this is a mechanical change I would just remove the member function and leave the code as is (well change EC.Min to EC.getKnownMinValue()). We already know that we'll need to visit the places where getKnownMinValue() is used to ensure the question makes sense in the face of scalable vectors.

Aug 27 2020, 4:44 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D86065: [SVE] Make ElementCount members private.
Aug 27 2020, 4:19 AM · Restricted Project, Restricted Project
paulwalker-arm committed rG81337c915f15: [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non… (authored by paulwalker-arm).
[SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non…
Aug 27 2020, 3:00 AM
paulwalker-arm closed D86394: [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source..
Aug 27 2020, 3:00 AM · Restricted Project

Aug 26 2020

paulwalker-arm accepted D86633: [MC][SVE] Fix data operand for instruction alias of `st1d`..
Aug 26 2020, 10:42 AM · Restricted Project
paulwalker-arm added inline comments to D86633: [MC][SVE] Fix data operand for instruction alias of `st1d`..
Aug 26 2020, 9:14 AM · Restricted Project
paulwalker-arm added a comment to D85364: [SVE][WIP] Implement lowering for fixed width select.

However, when we go to lower this to AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, that operation expects a half vector type for the operand. Here's a special case -- for illustrative purposes only:

Aug 26 2020, 5:25 AM · Restricted Project
paulwalker-arm accepted D84548: [AArch64][SVE] Add lowering for llvm fceil.

Personally I think it's better to order the FCEIL_MERGE_PASSTHRU enum entry and related code alphabetically relative to FNEG_MERGE_PASSTHRU but it's not a deal breaker. So if you're happy with renaming AArch64fceil_mt before landing the patch then I'm happy.

Aug 26 2020, 3:42 AM · Restricted Project

Aug 25 2020

paulwalker-arm committed rG73ac3c0ede4c: [SVE] Lower scalable vector ISD::FNEG operations. (authored by paulwalker-arm).
[SVE] Lower scalable vector ISD::FNEG operations.
Aug 25 2020, 3:24 AM
paulwalker-arm closed D86415: [SVE] Lower scalable vector ISD::FNEG operations..
Aug 25 2020, 3:24 AM · Restricted Project

Aug 24 2020

paulwalker-arm added a comment to D86078: [AArch64] Improved lowering for saturating float to int..

Given you are making use of the fact that AArch64 fp_to_int already does the saturation part, I'm wondering if the different-width saturation can be moved from the input to the output? Specially I'm thinking this will result in nicer code as the min/max immediate values will be easier to produce in integer form.

Aug 24 2020, 6:32 AM · Restricted Project
paulwalker-arm added reviewers for D86450: [SVE] Don't reorder subvector/binop sequences when the resulting binop is not legal.: david-arm, cameron.mcinally.
Aug 24 2020, 6:01 AM · Restricted Project
paulwalker-arm requested review of D86450: [SVE] Don't reorder subvector/binop sequences when the resulting binop is not legal..
Aug 24 2020, 5:59 AM · Restricted Project

Aug 23 2020

paulwalker-arm added reviewers for D86415: [SVE] Lower scalable vector ISD::FNEG operations.: cameron.mcinally, kmclaughlin.

@Asif & @dancgr : Sorry if you've already started looking at FNEG. It wasn't really my intension to implement support but it turned out to be the nicest way to test the isConstOrConstSplatFP change, which is required to fix an infinite legalisation hang when using fixed length vectors for SVE.

Aug 23 2020, 3:37 AM · Restricted Project
paulwalker-arm requested review of D86415: [SVE] Lower scalable vector ISD::FNEG operations..
Aug 23 2020, 3:29 AM · Restricted Project

Aug 22 2020

paulwalker-arm added reviewers for D86394: [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source.: cameron.mcinally, david-arm.
Aug 22 2020, 4:15 AM · Restricted Project
paulwalker-arm added a comment to D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations.

Perhaps I've misunderstood but based on Cameron's original message I suspect he's hit a bug because I lowered all SIGN_EXTEND_INREG operations regardless of the inreg type. This is wrong because there's no patterns for non-power-of-2 non-byte-based inreg types and thus I guess Cameron has hit a selection failure?

Aug 22 2020, 4:15 AM · Restricted Project
paulwalker-arm requested review of D86394: [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source..
Aug 22 2020, 4:10 AM · Restricted Project

Aug 21 2020

paulwalker-arm added inline comments to D86065: [SVE] Make ElementCount members private.
Aug 21 2020, 5:36 AM · Restricted Project, Restricted Project

Aug 20 2020

paulwalker-arm accepted D86316: [SVE] Lower fixed length UDIV to scalable.
Aug 20 2020, 4:15 PM · Restricted Project
paulwalker-arm accepted D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

The expanding is because we don't yet attempt to lower the subvector and concat_vector operations. As I say, I think today the correct move is to take this patch and then see what the future holds when we have full support for subvec and concat.

Aug 20 2020, 11:25 AM · Restricted Project
paulwalker-arm added a comment to D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable.

The end result is a big uglier than I would have hoped for, but I can't think of any particularly better way given the constraints.

Agreed. I'll wait for Paul to have a look to see if he has any tricks.

Aug 20 2020, 11:04 AM · Restricted Project
paulwalker-arm committed rG0015b8db8e5e: [SVE] Add ISEL patterns for predicated shifts by an immediate. (authored by paulwalker-arm).
[SVE] Add ISEL patterns for predicated shifts by an immediate.
Aug 20 2020, 3:53 AM