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paulwalker-arm (Paul Walker)
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Nov 24 2016, 5:21 AM (292 w, 1 d)

Recent Activity

Today

paulwalker-arm added inline comments to D128065: [AArch64][SVE] Fold target specific ext/trunc nodes into loads/stores.
Fri, Jul 1, 7:59 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D128665: [AArch64] Make nxv1i1 types a legal type for SVE..

One potential nit but otherwise this and the other i1 work is looking really good.

Fri, Jul 1, 5:57 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D128926: [AArch64] NFC: Move safe predicate casting to a separate function..
Fri, Jul 1, 4:14 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127126: [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST..

Discussed offline but for completeness.

Fri, Jul 1, 3:15 AM · Restricted Project, Restricted Project

Yesterday

paulwalker-arm committed rG43f8a6b74931: [SVE] Use CPY to zero active lanes of a floating point vector. (authored by paulwalker-arm).
[SVE] Use CPY to zero active lanes of a floating point vector.
Thu, Jun 30, 5:15 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128669: [SVE] Use CPY to zero active lanes of a floating point vector..
Thu, Jun 30, 5:15 PM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128159: [DAG] Enable scalable vectors handling in computeKnownBits.

Reading through the comments, has anything changed since my first comment? The main response seems to be "but hay it works". I'm sure that's true, but we've had several such moments when adding scalable support and each time we've been told to implement things properly. Hence the new vector type, element count, type size and instruction cost. I'm not hearing good reasons why demanded elements is any different.

Thu, Jun 30, 5:11 PM · Restricted Project, Restricted Project
paulwalker-arm committed rG2be4a7a2097e: [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an… (authored by paulwalker-arm).
[SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an…
Thu, Jun 30, 4:58 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128479: [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate..
Thu, Jun 30, 4:57 PM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128926: [AArch64] NFC: Move safe predicate casting to a separate function..
Thu, Jun 30, 10:33 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128926: [AArch64] NFC: Move safe predicate casting to a separate function..
Thu, Jun 30, 10:31 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128665: [AArch64] Make nxv1i1 types a legal type for SVE..

Sorry for the incremental review. This was not intentional, just how my code review time worked out for this patch.

Thu, Jun 30, 10:16 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128642: [AArch64][SVE] Use SVE for VLS fcopysign for wide vectors.
Thu, Jun 30, 9:48 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128926: [AArch64] NFC: Move safe predicate casting to a separate function..
Thu, Jun 30, 9:24 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

A few comment related issues but otherwise looks good to me.

Thu, Jun 30, 5:58 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D128902: [AArch64][SVE] Create AArch64ISD node for DUPQLANE128.

A potential code placement improvement but otherwise looks good.

Thu, Jun 30, 4:27 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128902: [AArch64][SVE] Create AArch64ISD node for DUPQLANE128.
Thu, Jun 30, 3:27 AM · Restricted Project, Restricted Project

Wed, Jun 29

paulwalker-arm added inline comments to D128665: [AArch64] Make nxv1i1 types a legal type for SVE..
Wed, Jun 29, 4:24 PM · Restricted Project, Restricted Project

Tue, Jun 28

paulwalker-arm added a comment to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

Out of interest are the test output produced manually or via an update script. I ask because I cannot see any of the normal headers and am wondering why.

Tue, Jun 28, 10:55 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128503: [AArch64][SVE] Lower aarch64_sve_dupq_lane to ld1rq.
Tue, Jun 28, 7:36 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128606: [WIP][AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx.

Is this optimisation valid? The merging SVE intrinsics have strict rules about what happens to inactive lanes. For the llvm.aarch64.sve.and the inactive lanes are set to the matching lanes of the first operand. This means that the inactive lanes of the second operand play no role in the operation and thus the example in and_i64_zero_comm is not a zeroing and.

Tue, Jun 28, 5:19 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128642: [AArch64][SVE] Use SVE for VLS fcopysign for wide vectors.

When checking the output for SVE2 I see no difference, which means we're missing out on the BSL optimisation we get for scalable vectors. I think this is because you're handling the fixed->scalable lowering too late. I think you really need to edit LowerFCOPYSIGN to first convert the fixed length ISD::FCOPYSIGN to a scalable one, then let the existing scalable vector code decide how best to lower it.

Tue, Jun 28, 4:32 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D128447: [AArch64][SVE] Match (add x (urshr/srshr y c)) -> ursra/srsra x y c.
Tue, Jun 28, 3:11 AM · Restricted Project, Restricted Project

Mon, Jun 27

paulwalker-arm added reviewers for D128669: [SVE] Use CPY to zero active lanes of a floating point vector.: kmclaughlin, bsmith.
Mon, Jun 27, 10:29 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D128669: [SVE] Use CPY to zero active lanes of a floating point vector..
Mon, Jun 27, 10:24 AM · Restricted Project, Restricted Project
paulwalker-arm committed rG049e107139a3: [NFC][SVE] Add more tests of vector compares and selects taking an immediate… (authored by paulwalker-arm).
[NFC][SVE] Add more tests of vector compares and selects taking an immediate…
Mon, Jun 27, 10:24 AM · Restricted Project, Restricted Project

Sun, Jun 26

paulwalker-arm committed rGfadea4413ecb: [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests. (authored by paulwalker-arm).
[NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests.
Sun, Jun 26, 4:08 PM · Restricted Project, Restricted Project

Fri, Jun 24

paulwalker-arm added reviewers for D128479: [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate.: david-arm, c-rhodes.
Fri, Jun 24, 3:31 AM · Restricted Project, Restricted Project

Thu, Jun 23

paulwalker-arm requested review of D128479: [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate..
Thu, Jun 23, 4:33 PM · Restricted Project, Restricted Project
paulwalker-arm accepted D127976: [IR] Move vector.insert/vector.extract out of experimental namespace.
Thu, Jun 23, 7:33 AM · Restricted Project, Restricted Project, Restricted Project

Wed, Jun 22

paulwalker-arm committed rGe8716179eb0b: [SVE] Make ISD::SPLAT_VECTOR a legal operation. (authored by paulwalker-arm).
[SVE] Make ISD::SPLAT_VECTOR a legal operation.
Wed, Jun 22, 4:44 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128265: [SVE] Make ISD::SPLAT_VECTOR a legal operation..
Wed, Jun 22, 4:44 PM · Restricted Project, Restricted Project
paulwalker-arm accepted D128045: [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c.
Wed, Jun 22, 7:24 AM · Restricted Project, Restricted Project

Tue, Jun 21

paulwalker-arm committed rG696169a35d5c: [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR. (authored by paulwalker-arm).
[SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR.
Tue, Jun 21, 4:14 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128200: [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR..
Tue, Jun 21, 4:14 PM · Restricted Project, Restricted Project
paulwalker-arm committed rG84f486cfab17: [NFC][SVE] Simplify SUBR_ZI isel patterns. (authored by paulwalker-arm).
[NFC][SVE] Simplify SUBR_ZI isel patterns.
Tue, Jun 21, 4:11 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128199: [NFC][SVE] Simplify SUBR_ZI isel patterns..
Tue, Jun 21, 4:10 PM · Restricted Project, Restricted Project
paulwalker-arm committed rG7b285ae0e8e6: [SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U. (authored by paulwalker-arm).
[SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U.
Tue, Jun 21, 4:04 PM · Restricted Project, Restricted Project
paulwalker-arm closed D128198: [SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U..
Tue, Jun 21, 4:04 PM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128283: [AArch64][SVE] Support optimized lowered selection with small SVE bits.

Hi @Allen, typically the SVE intrinsics only support legal types. This is a conscience choice because otherwise it will be very difficult to offer universal type support for all these target specific operations (i.e. where would we draw the line). Is there a reason not to use llvm.vector.reduce.and instead?

Tue, Jun 21, 8:16 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D128265: [SVE] Make ISD::SPLAT_VECTOR a legal operation.: dmgreen, david-arm, sdesmalen.
Tue, Jun 21, 5:26 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D128265: [SVE] Make ISD::SPLAT_VECTOR a legal operation..
Tue, Jun 21, 5:25 AM · Restricted Project, Restricted Project

Mon, Jun 20

paulwalker-arm accepted D128217: [ValueTracking] Teach isKnownNonZero that a vscale is never 0..
Mon, Jun 20, 11:43 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D126201: [WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors..
Mon, Jun 20, 8:32 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D127655: [AArch64] Define __FP_FAST_FMA[F].
Mon, Jun 20, 8:26 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR..
Mon, Jun 20, 8:22 AM · Restricted Project, Restricted Project
paulwalker-arm updated the diff for D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR..

Extended to allow an arbitrary start index.

Mon, Jun 20, 8:21 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D128200: [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR.: DavidTruby, kmclaughlin.
Mon, Jun 20, 6:40 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D128199: [NFC][SVE] Simplify SUBR_ZI isel patterns.: sdesmalen, peterwaller-arm.
Mon, Jun 20, 6:40 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D128200: [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR..
Mon, Jun 20, 6:39 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D128199: [NFC][SVE] Simplify SUBR_ZI isel patterns..
Mon, Jun 20, 6:38 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D128198: [SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U.: bsmith, david-arm, MattDevereau.
Mon, Jun 20, 6:31 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D128198: [SVE] Lower "unpredicated" sabd/uabd intrinsics to ISD::ABDS/U..
Mon, Jun 20, 6:30 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128045: [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c.

We may well have other sra related patterns so what about naming the test just sve-sra.ll?

Mon, Jun 20, 4:46 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D128045: [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c.
Mon, Jun 20, 4:41 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128159: [DAG] Enable scalable vectors handling in computeKnownBits.

I don't like the path this patch is taking. In it current form it is changing what the current interface means without documenting such, nor paying much heed to what all the code paths might do. This is why during initial scalable vector bring up, we decided to go the safest route and essentially bail for scalable vectors. Sure this means we implicitly changed the meaning of the "all known" value but there was little else we could do.

Mon, Jun 20, 3:52 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D128144: [AArch64] Known bits for AArch64ISD::DUP.

I'll take a look. In the long run I think I would like to remove AArch64ISD::DUP and just use ISD::SPLAT_VECTOR for all vectors across AArch64. That would take some time though, and would hit the same problem of canonicalising into a BUILD_VECTOR.

Mon, Jun 20, 3:33 AM · Restricted Project, Restricted Project

Fri, Jun 17

paulwalker-arm added inline comments to D127655: [AArch64] Define __FP_FAST_FMA[F].
Fri, Jun 17, 6:40 AM · Restricted Project, Restricted Project
paulwalker-arm committed rG0e21f1d56a50: [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases. (authored by paulwalker-arm).
[SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases.
Fri, Jun 17, 5:41 AM · Restricted Project, Restricted Project
paulwalker-arm closed D127508: [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases..
Fri, Jun 17, 5:41 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D127976: [IR] Move vector.insert/vector.extract out of experimental namespace.
Fri, Jun 17, 5:06 AM · Restricted Project, Restricted Project, Restricted Project

Thu, Jun 16

paulwalker-arm committed rGfcd058acc95c: [SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks. (authored by paulwalker-arm).
[SVE][CodeGen] Restructure SVE fixed length tests to use update_llc_test_checks.
Thu, Jun 16, 4:32 PM · Restricted Project, Restricted Project

Tue, Jun 14

paulwalker-arm added inline comments to D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR..
Tue, Jun 14, 5:24 AM · Restricted Project, Restricted Project

Mon, Jun 13

paulwalker-arm retitled D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR. from [WIP][SVE] Use INDEX to generate matching instances of BUILD_VECTOR. to [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR..
Mon, Jun 13, 10:47 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR.: bsmith, cameron.mcinally, david-arm.
Mon, Jun 13, 10:46 AM · Restricted Project, Restricted Project
paulwalker-arm updated the diff for D125194: [SVE][SelectionDAG] Use INDEX to generate matching instances of BUILD_VECTOR..

Rebased.
Changed isConstantSequence to return and optional.
Added tests.

Mon, Jun 13, 10:45 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D127508: [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases..
Mon, Jun 13, 10:42 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

I see :)

Mon, Jun 13, 7:28 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

@deadalnix @paulwalker-arm Should sve-fixed-length-fp-vselect.ll be updated to match as well?

Mon, Jun 13, 7:06 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127596: [WIP][AArch64][CodeGen] Support select address mode load/store.

I don't believe we want this functionality. We originally added it but then it got removed by D88994 as unsound because there's no instruction available to load/store predicates that are smaller than <vscale x 16 x i1>. At the C/C++ level we don't expose these "smaller" predicate types and so there shouldn't really be a route needed to load/store them. @Allen Do you have a real world use case where loading/storing them is required?

Mon, Jun 13, 4:00 AM · Restricted Project, Restricted Project
paulwalker-arm accepted D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

@paulwalker-arm Would that work or do you think the test refactor is imminent?

Mon, Jun 13, 3:47 AM · Restricted Project, Restricted Project

Sat, Jun 11

paulwalker-arm committed rG10d55c4634fa: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST. (authored by paulwalker-arm).
[SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST.
Sat, Jun 11, 3:58 AM · Restricted Project, Restricted Project
paulwalker-arm closed D127322: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST..
Sat, Jun 11, 3:57 AM · Restricted Project, Restricted Project

Fri, Jun 10

paulwalker-arm added reviewers for D127508: [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases.: efriedma, david-arm, kmclaughlin, sdesmalen.
Fri, Jun 10, 9:23 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D127508: [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover more cases..
Fri, Jun 10, 9:19 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127322: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST..

Thanks for the information @efriedma. I'll likely need to do a fuller <vscale x 1 x investigation to close out the remaining legalisation issues as I think the current strategy may well not be a good fit.

Fri, Jun 10, 4:57 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D127209: [SVE][AArch64] Refine hasSVEArgsOrReturn.
Fri, Jun 10, 4:13 AM · Restricted Project, Restricted Project

Thu, Jun 9

paulwalker-arm added a comment to D126505: [AArch64][SVE] Don't crash on pre-legalized types in extload combine..

@ab What's your plans for submitting this fix. I only ask because others have hit the same issue, as shown by https://github.com/llvm/llvm-project/issues/55866.

Thu, Jun 9, 5:55 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

To be honest these tests are just not a good fit for auto-generation, which is why we didn't use update_llc_test_checks.py originally. The best I could come up with is to disable the NO_SVE run line when running the script and then enable it afterwards. I do have the workings of a patch to add a --ignored-check-prefixes option to update_llc_test_checks.py but even then the decision as to which CHECK lines are emitted doesn't really match what we wanted to achieve. If autogeneration is preferable and you're happy to wait a week or two I think it'll be better if I just restructure all the SVE fixed length tests (essentially split them based on register size) and enable auto-generation at the same time. I think this is worth doing anyway to increase our test coverage and test parallelism as the existing layout means these tests are the most time consuming ones with the AArch64 directory.

Thu, Jun 9, 4:40 AM · Restricted Project, Restricted Project

Wed, Jun 8

paulwalker-arm added reviewers for D127322: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST.: bsmith, CarolineConcatto, david-arm, efriedma.

For full disclosure, I'm not 100% sure but believe the nxv1#64 output is likely wrong. This is true for the existing and new tests. I don't think this is the fault of this or previous bitcast work but rather an issue with how we're lowering ISD::INSERT_SUBVECTOR for these types. It looks suspiciously like we're treating ISD::INSERT_SUBVECTOR nxv2i64 undef, nxv1i64 data, i32 0 as a NOP.

Wed, Jun 8, 10:25 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D127322: [SelectionDAG] Remove invalid TypeSize conversion from WidenVecOp_BITCAST..
Wed, Jun 8, 10:20 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D127210: [AArch64][SME] Add load/store intrinsics.
Wed, Jun 8, 5:20 AM · Restricted Project, Restricted Project
paulwalker-arm committed rGd88354213cbb: [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST. (authored by paulwalker-arm).
[SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST.
Wed, Jun 8, 2:32 AM · Restricted Project, Restricted Project
paulwalker-arm closed D127126: [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST..
Wed, Jun 8, 2:31 AM · Restricted Project, Restricted Project
paulwalker-arm committed rGa1121c31d840: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types. (authored by paulwalker-arm).
[SVE] Fix incorrect code generation for bitcasts of unpacked vector types.
Wed, Jun 8, 2:31 AM · Restricted Project, Restricted Project
paulwalker-arm closed D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types..
Wed, Jun 8, 2:31 AM · Restricted Project, Restricted Project

Tue, Jun 7

paulwalker-arm added a comment to D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

Have you had chance to see if the extra NO_SVE lines can be removed. I really don't want these tests to require updates when SVE is not being used, whilst at the same time validating no SVE is used, which is what the current single NO_SVE-NOT lines verifies.

Tue, Jun 7, 5:00 PM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D127210: [AArch64][SME] Add load/store intrinsics.
Tue, Jun 7, 7:32 AM · Restricted Project, Restricted Project

Mon, Jun 6

paulwalker-arm added reviewers for D127126: [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST.: bsmith, CarolineConcatto, david-arm, sdesmalen, efriedma.
Mon, Jun 6, 9:42 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D127126: [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST..
Mon, Jun 6, 9:41 AM · Restricted Project, Restricted Project
paulwalker-arm added a comment to D127118: [AArch64] Autogenerate sve-fixed-length tests. NFC.

For most of these tests we don't care about the exact "no sve" output and thus have a single CHECK for the whole file. Is there a parameter that can be passed to update_llc_test_checks.py so those CHECK lines are not generated?

Mon, Jun 6, 8:43 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D126532: [SVE] Add a DAG combiner fold to visitADD for vscale with truncate.
Mon, Jun 6, 5:58 AM · Restricted Project, Restricted Project
paulwalker-arm added inline comments to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.
Mon, Jun 6, 5:31 AM · Restricted Project, Restricted Project

Sun, Jun 5

paulwalker-arm updated the diff for D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types..

Add assert to getSVESafeBitCast to detect original failure case.

Sun, Jun 5, 5:03 PM · Restricted Project, Restricted Project

Sat, Jun 4

paulwalker-arm added a comment to D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types..

@efriedma I'd still rather have the improved code generation as a separate patch, mainly because this patch forces the need to remove an invalid type size conversion from SelectionDAGLegalize::EmitStackConvert and I'd like there to be a window (however small) that validates the code now works for fixed and scalable vector types.

Sat, Jun 4, 3:04 AM · Restricted Project, Restricted Project

Fri, Jun 3

paulwalker-arm added a comment to D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types..

For this patch I'm just playing it safe and using common expansion via the stack rather than anything more exotic.

Fri, Jun 3, 4:18 AM · Restricted Project, Restricted Project
paulwalker-arm added reviewers for D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types.: sdesmalen, CarolineConcatto, david-arm, bsmith.
Fri, Jun 3, 4:17 AM · Restricted Project, Restricted Project
paulwalker-arm requested review of D126957: [SVE] Fix incorrect code generation for bitcasts of unpacked vector types..
Fri, Jun 3, 4:13 AM · Restricted Project, Restricted Project
paulwalker-arm committed rG2dde272db767: [SVE] Refactor sve-bitcast.ll to include all combinations for legal types. (authored by paulwalker-arm).
[SVE] Refactor sve-bitcast.ll to include all combinations for legal types.
Fri, Jun 3, 4:12 AM · Restricted Project, Restricted Project

Thu, Jun 2

paulwalker-arm committed rG48ea26a3878f: [SVE] Fixed custom lowering of ISD::INSERT_SUBVECTOR. (authored by paulwalker-arm).
[SVE] Fixed custom lowering of ISD::INSERT_SUBVECTOR.
Thu, Jun 2, 7:07 AM · Restricted Project, Restricted Project