[SelectionDAG] Add Target-Independent Compiler Barrier

[lenary]

Summary

Several different target backends end up implementing compiler-only
barrier pseudo-instructions which eventually expand into an assembly
comment.

These come from for example C's atomic_signal_fence, C++'s
std::atomic_signal_fence, or Rust's compiler_barrier which are all
documented to not result in assembly instructions. While emitting a
fence instruction (or equivalent) is not incorrect within usual memory
models, it is inefficient. Depending on the target configuration, these
usually turn into atomic_fence before SelectionDAG (with syncscope of
"singlethread"), where they are then turned first into a target-specific
ISD node, and then into a pseudo-instruction which prints as a comment.

Most LLVM Target backends seem to have copied a MEMBARRIER
target-specific ISD node, so every new LLVM target needs to replicate
all these parts to get the same behaviour. Some targets don't do this,
and end up emitting fence instructions without paying attention to the
syncscope fence argument.

LLVM, however, has target-independent machine opcodes, which have a
variety of uses in LLVM's backend code. This patch adds a
COMPILER_BARRIER target-independent opcode to represent a compiler-only
barrier, which does not generate instructions. This opcode still
contains information about the syncscope and ordering of the original
atomic_fence, so that backend-specific optimisations still have this
information.

This patch also refactors existing instances of target-specific
MEMBARRIERs to use the new target-independent COMPILER_BARRIER.

[lenary]

RFC Thread on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2020-December/147318.html

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

29204

Would it make sense to have a SelectionDAG::getCompilerBarrier method that would hide most of the boilerplate for creating these nodes?

[lenary]

llvm/lib/Target/X86/X86ISelLowering.cpp

29204

Almost certainly.

One thing I did run into was I wanted to keep the ordering in the barrier around for later passes - but I ran into issues on x86 where the immediate I was using to represent it was getting allocated into a register and that caused instruction verification to fail. I could look at bringing that back if people thought it was useful (for instance, later Machine Passes may want to know if they can hoist/sink loads and stores past a barrier with more granularity than just "No").

[arsenm]

llvm/include/llvm/Support/TargetOpcodes.def

220–223

I think the scope should also be parameterized. This also does not match the description of the defined instruction which is missing the ordering operand

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

29204

Can you use getTargetConstant? That should never end up in a register.

[lenary]

llvm/include/llvm/Support/TargetOpcodes.def

220–223

The documentation about ordering is out of date, I did include it before, but then ran into x86 issues, so removed it. I'm looking at bringing it back with @craig.topper's suggestions.

Because this barrier explicitly does not translate to machine code (that would be a place where you used a target-dependent fence or similar), I don't want to suggest this has any syncscope that is not singlethread, but maybe that's wrong?

llvm/lib/Target/X86/X86ISelLowering.cpp

29204

I'll try again, I cannot remember exactly what I used for that version of the code.

[lenary]

• Include Ordering Again (using getTargetConstant)
• Add Helper for creating DAG nodes

[jrtc27]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

286–287

I don't think this should be reached any more?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

610–611

The change to emitFunctionBody should render this dead?

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

What's up with this change?

[craig.topper]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I'm guessing that TargetOpcode::COMPILER_BARRIER is giving a different value from TargetSchedMode::computeInstrLatency() that X86::MEMBARRIER did which changed how X86PadShortFunctions.cpp computed how many NOPs to add before the return.

[jrtc27]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I guess the question then is "which is better?".

[craig.topper]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I think we were counting a "compiler barrier" that doesn't generate code as having a non-zero or multiple cycle latency before. So this change is probably better.

[lenary]

• Address Minor Review Comments, Method Naming issues.

[jrtc27]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

612

"both" no longer applies

[lenary]

• Comments and Whitespace

[lenary]

Ping

@arsenm Please may you clarify why you think the scope is still useful to represent this late?

[skan]

FYI, this patch also fix the bug that "X86::Int_MemBarrier should be a MetaInstruction".

[skan]

@lenary Do you need to update something? There are three tests fail according to the log.

[lenary]

In D92842#2533053, @skan wrote:

@lenary Do you need to update something? There are three tests fail according to the log.

I'm waiting for some confirmation that people are happy with the approach. I've had a little feedback but not much, and hardly any actual code review.

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

[skan]

In D92842#2561721, @lenary wrote:

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

The failed LIT tests in the remote tests are "x64 debian > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/XCore::threads.ll", I think you can see them on this page.

The bug "X86::Int_MemBarrier should be a MetaInstruction" is an internal bug, I found it when I was doing some development work about debug info personally. Although I could not give a failed test, here is a way to trigger that:

define dso_local i32 @main() !dbg !7 {
entry:
  fence acquire, !dbg !9
  fence release, !dbg !9
  %retval = alloca i32, align 4
  store i32 0, i32* %retval, align 4
  ret i32 0, !dbg !9
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
!llvm.ident = !{!6}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: DebugDirectivesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "none.c", directory: "/temp")
!2 = !{}
!3 = !{i32 2, !"PersonalFlag", i32 1}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
!6 = !{!"clang version 11.0.0"}
!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
!8 = !DISubroutineType(types: !2)
!9 = !DILocation(line: 1, column: 14, scope: !7)

llc -O0 -mtriple x86_64-linux-gnu  test.ll

IR fence acquire and fence release is lowered to X86::Int_MemBarrier, and the interface bool isMetaInstruction() const returns false for it. So if you add an assert
for this, the program will crash.

[lenary]

Updated based on review feedback:

• Migrated more targets to COMPILER_BARRIER
• Added syncscope argument to COMPILER_BARRIER

[lenary]

llvm/include/llvm/Support/TargetOpcodes.def

220

Sorry, I missed this comment

[lenary]

I'm looking for reviewers from the following targets for this change:

• VE - @simoll would you be willing to?
• XCore - @nigelp-xmos would you be willing to?

[nigelp-xmos]

Yes, I will look at this for the XCore target.

[nigelp-xmos]

XCore change LGTM. (Commenting on XCore only.)

[nigelp-xmos]

llvm/include/llvm/Target/TargetSelectionDAG.td defines SDTMemBarrier. This seems to have been introduced in 9b254eed32028 for ISD::MEMBARRIER, which was removed some time ago. I can't find a use of it and I can build without it. Could SDTMemBarrier be removed and would it belong in this patch?

[lenary]

In D92842#2821463, @nigelp-xmos wrote:

llvm/include/llvm/Target/TargetSelectionDAG.td defines SDTMemBarrier. This seems to have been introduced in 9b254eed32028 for ISD::MEMBARRIER, which was removed some time ago. I can't find a use of it and I can build without it. Could SDTMemBarrier be removed and would it belong in this patch?

Yes, that makes sense to me, I think I removed some target-specific TypeProfiles which were now unused, so it makes sense to remove this too.

[pengfei]

Reverse ping. Is there any blocker issue for this patch landing?

[skan]

In D92842#2570304, @skan wrote:

In D92842#2561721, @lenary wrote:

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

The failed LIT tests in the remote tests are "x64 debian > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/XCore::threads.ll", I think you can see them on this page.

The bug "X86::Int_MemBarrier should be a MetaInstruction" is an internal bug, I found it when I was doing some development work about debug info personally. Although I could not give a failed test, here is a way to trigger that:

define dso_local i32 @main() !dbg !7 {
entry:
  fence acquire, !dbg !9
  fence release, !dbg !9
  %retval = alloca i32, align 4
  store i32 0, i32* %retval, align 4
  ret i32 0, !dbg !9
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
!llvm.ident = !{!6}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: DebugDirectivesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "none.c", directory: "/temp")
!2 = !{}
!3 = !{i32 2, !"PersonalFlag", i32 1}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
!6 = !{!"clang version 11.0.0"}
!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
!8 = !DISubroutineType(types: !2)
!9 = !DILocation(line: 1, column: 14, scope: !7)

llc -O0 -mtriple x86_64-linux-gnu  test.ll

IR fence acquire and fence release is lowered to X86::Int_MemBarrier, and the interface bool isMetaInstruction() const returns false for it. So if you add an assert
for this, the program will crash.

A LIT test is provided at D121879.

[lenary]

In D92842#3388199, @pengfei wrote:

Reverse ping. Is there any blocker issue for this patch landing?

iirc, I have some planned changes and haven't got back to them recently. In the meantime, hopefully @skan's patch tides you over.

[pengfei]

In D92842#3388658, @lenary wrote:

In D92842#3388199, @pengfei wrote:

Reverse ping. Is there any blocker issue for this patch landing?

iirc, I have some planned changes and haven't got back to them recently. In the meantime, hopefully @skan's patch tides you over.

Thanks! I personally prefer this patch. But yes, we can land @skan's patch first.

[lenary]

Superseded by work from @reames

[reames]

Replying here mostly so I can find the information later.

Over the last few days, I have submitted a couple of changes which factor out a target independent MEMBARRIER node. At this point, all targets except ARM, AArch64, AMDGPU, and WebAssembly have been migrated. The former two are on review, the third I don't plan to touch as it uses a late expansion of atomic_fence instead, and has some target specific logic based on that which is hard to follow without architecture context I don't have. The fourth I haven't looked at closely as I just found the alternate spelling of the barrier name it uses.

The choice of MEMBARRIER vs COMPILER_BARRIER naming was arbitrary. I went with what more targets seemed to have used to minimize test churn.

I didn't find an in tree example which required the ordering on the generic instruction. Given that, I left it out. I am not opposed to adding it, but would like to see a justification before we add complexity.

As far as I can tell, the scope argument in this patch is purely spurious. A MEMBARRIER can only have a single scope - SingleThread. This is definitely true for all the targets I've looked at closely. AMDGPU *might* be a counter example, but I don't understand the semantics of it's scopes closely well enough to know for sure.

Finally, this patch contains two functional changes to the x86 backend. I did not include those. Separating those out - with tests! - would likely be valuable. I'd be happy to review if you wanted to do that.

llvm/include/llvm/CodeGen/MachineInstr.h

bool isMetaInstruction() const {
     case TargetOpcode::DBG_VALUE:
     case TargetOpcode::DBG_VALUE_LIST:
     case TargetOpcode::DBG_INSTR_REF:
     case TargetOpcode::DBG_PHI:
     case TargetOpcode::DBG_LABEL:
     case TargetOpcode::LIFETIME_START:
     case TargetOpcode::LIFETIME_END:
     case TargetOpcode::PSEUDO_PROBE:
+    case TargetOpcode::COMPILER_BARRIER:
       return true;
     }
   }
 
   /// Return true if this is a transient instruction that is either very likely
   /// to be eliminated during register allocation (such as copy-like
   /// instructions), or if this instruction doesn't have an execution-time cost.
   bool isTransient() const {

llvm/include/llvm/CodeGen/SelectionDAG.h

#endif
   /// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
   SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
                                  SDValue Operand);
 
   /// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
   SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
                                 SDValue Operand, SDValue Subreg);
 
+  /// A convenience function for creating TargetOpCode::COMPILER_BARRIER nodes.
+  SDValue getCompilerBarrier(const SDLoc &DL, AtomicOrdering Ordering,
+                             SyncScope::ID Scope, SDValue Chain);
+
   /// Get the specified node if it's already available, or else return NULL.
   SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
                           ArrayRef<SDValue> Ops, const SDNodeFlags Flags);
   SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
                           ArrayRef<SDValue> Ops);
 
   /// Check if a node exists without modifying its flags.
   bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef<SDValue> Ops);

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
 
 /// Wraps a typed logging call and its argument with nop sleds. At runtime, this
 /// can be patched to insert instrumentation instructions.
 HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL)
 
 HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
 
+// This is a fence with the singlethread scope. It has a single operand, which
+// is the ordering requested. This instruction has `mayLoad` and `mayStore`, so
+// that memory operations are not moved around it.
+HANDLE_TARGET_OPCODE(COMPILER_BARRIER)
+
 /// The following generic opcodes are not supposed to appear after ISel.
 /// This is something we might want to relax, but for now, this is convenient
 /// to produce diagnostics.
 
 /// Instructions which should not exist past instruction selection, but do not
 /// generate code. These instructions only act as optimization hints.
 HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
 HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)

llvm/include/llvm/Target/Target.td

def FENTRY_CALL : StandardPseudoInstruction {
   let hasSideEffects = true;
 }
 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
   let hasSideEffects = true;
 }
+def COMPILER_BARRIER : StandardPseudoInstruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins i32imm:$ordering, i32imm:$scope);
+  let AsmString = "";
+  let hasSideEffects = true;
+  let Size = 0;
+}
 
 // Generic opcodes used in GlobalISel.
 include "llvm/Target/GenericOpcodes.td"
 
 //===----------------------------------------------------------------------===//
 // AsmParser - This class can be implemented by targets that wish to implement
 // .s file parsing.
 //

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
   raw_svector_ostream OS(Str);
   OS << "implicit-def: "
      << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
 
   OutStreamer->AddComment(OS.str());
   OutStreamer->AddBlankLine();
 }
 
+static void emitCompilerBarrierComment(const MachineInstr *MI, AsmPrinter &AP) {
+  auto Ordering = static_cast<AtomicOrdering>(MI->getOperand(0).getImm());
+  auto Scope = static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
+
+  SmallVector<StringRef> SSNames;
+  LLVMContext &Ctx = AP.MMI->getModule()->getContext();
+  Ctx.getSyncScopeNames(SSNames);
+
+  SmallString<128> Str;
+  raw_svector_ostream OS(Str);
+  OS << " Compiler Barrier: " << toIRString(Ordering);
+  if (Scope != SyncScope::System) {
+    OS << " syncscope(" << SSNames[Scope] << ")";
+  }
+
+  AP.OutStreamer->emitRawComment(OS.str());
+}
+
 static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
   std::string Str;
   raw_string_ostream OS(Str);
   OS << "kill:";
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &Op = MI->getOperand(i);
     assert(Op.isReg() && "KILL instruction must have only register operands");
     OS << ' ' << (Op.isDef() ? "def " : "killed ")
for (auto &MI : MBB) {
         if (isVerbose()) emitImplicitDef(&MI);
         break;
       case TargetOpcode::KILL:
         if (isVerbose()) emitKill(&MI, *this);
         break;
       case TargetOpcode::PSEUDO_PROBE:
         emitPseudoProbe(MI);
         break;
+      case TargetOpcode::COMPILER_BARRIER:
+        emitCompilerBarrierComment(&MI, *this);
+        break;
       default:
         emitInstruction(&MI);
         if (CanDoExtraAnalysis) {
           MCInst MCI;
           MCI.setOpcode(MI.getOpcode());
           auto Name = OutStreamer->getMnemonic(MCI);
           auto I = MnemonicCounts.insert({Name, 0u});
           I.first->second++;

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
                                             SDValue Operand, SDValue Subreg) {
   SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
   SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
                                   VT, Operand, Subreg, SRIdxVal);
   return SDValue(Result, 0);
 }
 
+SDValue SelectionDAG::getCompilerBarrier(const SDLoc &DL,
+                                         AtomicOrdering Ordering,
+                                         SyncScope::ID Scope, SDValue Chain) {
+  SDValue OrderingVal = getTargetConstant((uint64_t)Ordering, DL, MVT::i32);
+  SDValue ScopeVal = getTargetConstant((uint64_t)Scope, DL, MVT::i32);
+  SDNode *Result = getMachineNode(TargetOpcode::COMPILER_BARRIER, DL,
+                                  MVT::Other, {OrderingVal, ScopeVal, Chain});
+  return SDValue(Result, 0);
+}
+
 /// getNodeIfExists - Get the specified node if it's already available, or
 /// else return NULL.
 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
                                       ArrayRef<SDValue> Ops) {
   SDNodeFlags Flags;
   if (Inserter)
     Flags = Inserter->getFlags();
   return getNodeIfExists(Opcode, VTList, Ops, Flags);

llvm/lib/Target/AArch64/AArch64InstrAtomics.td

 //=- AArch64InstrAtomics.td - AArch64 Atomic codegen support -*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Atomic operand code-gen constructs.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------
 // Atomic fences
 //===----------------------------------
-let AddedComplexity = 15, Size = 0 in
-def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering),
-                             [(atomic_fence timm:$ordering, 0)]>, Sched<[]>;
+let AddedComplexity = 15 in
+def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering, (i32 0))>;
 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
 
 //===----------------------------------
 // Atomic loads
 //===----------------------------------
 
 // When they're actually atomic, only one addressing mode (GPR64sp) is

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
     uint64_t Value = AArch64_AM::decodeLogicalImmediate(
         MI->getOperand(2).getImm(), RegWidth);
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
       O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
         << formatImm(SignExtend64(Value, RegWidth));
       return;
     }
   }
 
-  if (Opcode == AArch64::CompilerBarrier) {
-    O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
-    printAnnotation(O, Annot);
-    return;
-  }
-
   if (Opcode == AArch64::SPACE) {
     O << '\t' << MAI.getCommentString() << " SPACE "
       << MI->getOperand(1).getImm();
     printAnnotation(O, Annot);
     return;
   }
 
   // Instruction TSB is specified as a one operand instruction, but 'csync' is
   // not encoded, so for printing it is treated as a special case here:

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

if (MI.getOpcode() == AArch64::TLSDESCCALL) {
     auto Reloc = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32
                      ? ELF::R_AARCH64_P32_TLSDESC_CALL
                      : ELF::R_AARCH64_TLSDESC_CALL;
     Fixups.push_back(
         MCFixup::create(0, MI.getOperand(0).getExpr(),
                         MCFixupKind(FirstLiteralRelocationKind + Reloc)));
     return;
   }
 
-  if (MI.getOpcode() == AArch64::CompilerBarrier ||
-      MI.getOpcode() == AArch64::SPACE) {
-    // CompilerBarrier just prevents the compiler from reordering accesses, and
+  if (MI.getOpcode() == AArch64::SPACE) {
     // SPACE just increases basic block size, in both cases no actual code.
     return;
   }
 
   uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
   support::endian::write<uint32_t>(OS, Binary, support::little);
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 }
 

llvm/lib/Target/ARM/ARMInstrInfo.td

def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
                              (ins GPR:$addr, GPR:$desired, GPR:$new),
                              NoItinerary, []>, Sched<[]>;
 
 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
                              (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
                              NoItinerary, []>, Sched<[]>;
 }
 
-def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
-                                 [(atomic_fence timm:$ordering, 0)]> {
-  let hasSideEffects = 1;
-  let Size = 0;
-  let AsmString = "@ COMPILER BARRIER";
-  let hasNoSchedulingInfo = 1;
-}
+def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering, (i32 0))>;

llvm/lib/Target/ARM/ARMScheduleA57.td

 
 // To have "CompleteModel = 1", support of pseudos and special instructions
 def : InstRW<[WriteNoop], (instregex "(t)?BKPT$", "(t2)?CDP(2)?$",
   "(t2)?CLREX$", "CONSTPOOL_ENTRY$", "COPY_STRUCT_BYVAL_I32$",
   "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
   "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
   "(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE",
   "(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG",
-  "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier",
-  "t__brkdiv0")>;
+  "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "t__brkdiv0")>;
 
 def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
 
 // Specific memory instrs
 def : InstRW<[WriteNoop, WriteNoop], (instregex "(t2)?LDA", "(t2)?LDC", "(t2)?STC",
   "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY")>;
 
 // coprocessor moves

 def : SchedAlias<WriteBrTbl, A57Write_1cyc_1B_1I>;
 def : SchedAlias<WritePreLd, A57Write_4cyc_1L>;
 
 def : SchedAlias<WriteLd, A57Write_4cyc_1L>;
 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
 def : ReadAdvance<ReadALU, 0>;
 
 } // SchedModel = CortexA57Model
-

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 defm : StPat<truncstorei16, SH, GPR, XLenVT>;
 defm : StPat<store, SW, GPR, i32>, Requires<[IsRV32]>;
 
 /// Fences
 
 // Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set
 // Manual: Volume I.
 
+// Scope of 0 is for singlethread fences, which are not generated into instructions.
+def : Pat<(atomic_fence (timm:$ordering), 0), (COMPILER_BARRIER i32:$ordering, (i32 0))>;
+
 // fence acquire -> fence r, rw
 def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>;
 // fence release -> fence rw, w
 def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>;
 // fence acq_rel -> fence.tso
 def : Pat<(atomic_fence (XLenVT 6), (timm)), (FENCE_TSO)>;
 // fence seq_cst -> fence rw, rw
 def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>;

llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp

case SystemZ::Serialize:
     if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
       LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
         .addImm(14).addReg(SystemZ::R0D);
     else
       LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
         .addImm(15).addReg(SystemZ::R0D);
     break;
 
-  // Emit nothing here but a comment if we can.
-  case SystemZ::MemBarrier:
-    OutStreamer->emitRawComment("MEMBARRIER");
-    return;
-
   // We want to emit "j .+2" for traps, jumping to the relative immediate field
   // of the jump instruction, which is an illegal instruction. We cannot emit a
   // "." symbol, so create and emit a temp label before the instruction and use
   // that instead.
   case SystemZ::Trap: {
     MCSymbol *DotSym = OutContext.createTempSymbol();
     OutStreamer->emitLabel(DotSym);
 

llvm/lib/Target/SystemZ/SystemZISelLowering.h

enum NodeType : unsigned {
   // operand is the end address, the second is the start, and the third
   // is the character to search for.  CC is set to 1 on success and 2
   // on failure.
   SEARCH_STRING,
 
   // Store the CC value in bits 29 and 28 of an integer.
   IPM,
 
-  // Compiler barrier only; generate a no-op.
-  MEMBARRIER,
-
   // Transaction begin.  The first operand is the chain, the second
   // the TDB pointer, and the third the immediate control field.
   // Returns CC value and chain.
   TBEGIN,
   TBEGIN_NOFLOAT,
 
   // Transaction end.  Just the chain operand.  Returns CC value and chain.
   TEND,

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
   // cross-thread fence.
   if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
       FenceSSID == SyncScope::System) {
     return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
                                       Op.getOperand(0)),
                    0);
   }
 
-  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-  return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
+  return DAG.getCompilerBarrier(DL, FenceOrdering, FenceSSID, Op.getOperand(0));
 }
 
 // Op is an atomic load.  Lower it into a normal volatile load.
 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
                                                 SelectionDAG &DAG) const {
   auto *Node = cast<AtomicSDNode>(Op.getNode());
   return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
                         Node->getChain(), Node->getBasePtr(),
switch ((SystemZISD::NodeType)Opcode) {
     OPCODE(XC);
     OPCODE(XC_LOOP);
     OPCODE(CLC);
     OPCODE(CLC_LOOP);
     OPCODE(STPCPY);
     OPCODE(STRCMP);
     OPCODE(SEARCH_STRING);
     OPCODE(IPM);
-    OPCODE(MEMBARRIER);
     OPCODE(TBEGIN);
     OPCODE(TBEGIN_NOFLOAT);
     OPCODE(TEND);
     OPCODE(BYTE_MASK);
     OPCODE(ROTATE_MASK);
     OPCODE(REPLICATE);
     OPCODE(JOIN_DWORDS);
     OPCODE(SPLAT);

llvm/lib/Target/SystemZ/SystemZInstrInfo.td

 // Atomic operations
 //===----------------------------------------------------------------------===//
 
 // A serialization instruction that acts as a barrier for all memory
 // accesses, which expands to "bcr 14, 0".
 let hasSideEffects = 1 in
 def Serialize : Alias<2, (outs), (ins), []>;
 
-// A pseudo instruction that serves as a compiler barrier.
-let hasSideEffects = 1, hasNoSchedulingInfo = 1 in
-def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
-
 let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
   def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
   def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
   def LAAL  : LoadAndOpRSY<"laal",  0xEBFA, null_frag, GR32>;
   def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
   def LAN   : LoadAndOpRSY<"lan",   0xEBF4, atomic_load_and_32, GR32>;
   def LANG  : LoadAndOpRSY<"lang",  0xEBE4, atomic_load_and_64, GR64>;
   def LAO   : LoadAndOpRSY<"lao",   0xEBF6, atomic_load_or_32, GR32>;

llvm/lib/Target/SystemZ/SystemZOperators.td

 def z_udivrem           : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
 def z_saddo             : SDNode<"SystemZISD::SADDO", SDT_ZBinaryWithFlags>;
 def z_ssubo             : SDNode<"SystemZISD::SSUBO", SDT_ZBinaryWithFlags>;
 def z_uaddo             : SDNode<"SystemZISD::UADDO", SDT_ZBinaryWithFlags>;
 def z_usubo             : SDNode<"SystemZISD::USUBO", SDT_ZBinaryWithFlags>;
 def z_addcarry_1        : SDNode<"SystemZISD::ADDCARRY", SDT_ZBinaryWithCarry>;
 def z_subcarry_1        : SDNode<"SystemZISD::SUBCARRY", SDT_ZBinaryWithCarry>;
 
-def z_membarrier        : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
-                                 [SDNPHasChain, SDNPSideEffect]>;
-
 def z_loadbswap        : SDNode<"SystemZISD::LRV", SDTLoad,
                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def z_storebswap       : SDNode<"SystemZISD::STRV", SDTStore,
                                  [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def z_loadeswap        : SDNode<"SystemZISD::VLER", SDTLoad,
                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def z_storeeswap       : SDNode<"SystemZISD::VSTER", SDTStore,
                                  [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;

llvm/lib/Target/VE/VEISelLowering.h

enum NodeType : unsigned {
   EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
   GETFUNPLT,              // Load function address through %plt insturction.
   GETTLSADDR,             // Load address for TLS access.
   GETSTACKTOP,            // Retrieve address of stack top (first address of
                           // locals and temporaries).
   GLOBAL_BASE_REG,        // Global base reg for PIC.
   Hi,                     // Hi/Lo operations, typically on a global address.
   Lo,                     // Hi/Lo operations, typically on a global address.
-  MEMBARRIER,             // Compiler barrier only; generate a no-op.
   RET_FLAG,               // Return with a flag operand.
   TS1AM,                  // A TS1AM instruction used for 1/2 bytes swap.
   VEC_BROADCAST,          // A vector broadcast instruction.
                           //   0: scalar value, 1: VL
 
 // VVP_* nodes.
 #define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
 #include "VVPNodes.def"

llvm/lib/Target/VE/VEISelLowering.cpp

case VEISD::FIRST_NUMBER:
     TARGET_NODE_CASE(EH_SJLJ_SETJMP)
     TARGET_NODE_CASE(EH_SJLJ_SETUP_DISPATCH)
     TARGET_NODE_CASE(GETFUNPLT)
     TARGET_NODE_CASE(GETSTACKTOP)
     TARGET_NODE_CASE(GETTLSADDR)
     TARGET_NODE_CASE(GLOBAL_BASE_REG)
     TARGET_NODE_CASE(Hi)
     TARGET_NODE_CASE(Lo)
-    TARGET_NODE_CASE(MEMBARRIER)
     TARGET_NODE_CASE(RET_FLAG)
     TARGET_NODE_CASE(TS1AM)
     TARGET_NODE_CASE(VEC_BROADCAST)
 
     // Register the VVP_* SDNodes.
 #define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
 #include "VVPNodes.def"
   }
case AtomicOrdering::SequentiallyConsistent:
       //        so  seq_cst may require more instruction for them.
       return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
                                         DAG.getTargetConstant(3, DL, MVT::i32),
                                         Op.getOperand(0)),
                      0);
     }
   }
 
-  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-  return DAG.getNode(VEISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
+  return DAG.getCompilerBarrier(DL, FenceOrdering, FenceSSID, Op.getOperand(0));
 }
 
 TargetLowering::AtomicExpansionKind
 VETargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
   // We have TS1AM implementation for i8/i16/i32/i64, so use it.
   if (AI->getOperation() == AtomicRMWInst::Xchg) {
     return AtomicExpansionKind::None;
   }

llvm/lib/Target/VE/VEInstrInfo.td

 def GetTLSAddr : SDNode<"VEISD::GETTLSADDR", SDT_SPCall,
                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                          SDNPVariadic]>;
 
 // GETSTACKTOP
 def GetStackTop : SDNode<"VEISD::GETSTACKTOP", SDTNone,
                         [SDNPHasChain, SDNPSideEffect]>;
 
-// MEMBARRIER
-def MemBarrier : SDNode<"VEISD::MEMBARRIER", SDTNone,
-                        [SDNPHasChain, SDNPSideEffect]>;
-
 // TS1AM
 def SDT_TS1AM : SDTypeProfile<1, 3, [SDTCisSameAs<0, 3>, SDTCisPtrTy<1>,
                                      SDTCisVT<2, i32>, SDTCisInt<3>]>;
 def ts1am     : SDNode<"VEISD::TS1AM", SDT_TS1AM,
                        [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
                         SDNPMemOperand]>;
 
 //===----------------------------------------------------------------------===//

 // These calls are needed to probe the stack when allocating more over
 // %s8 (%sl - stack limit).
 
 let Uses = [SX11], hasSideEffects = 1 in
 def GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),
                          "# GET STACK TOP",
                          [(set iPTR:$dst, (GetStackTop))]>;
 
-// MEMBARRIER
-let hasSideEffects = 1 in
-def MEMBARRIER : Pseudo<(outs), (ins), "# MEMBARRIER", [(MemBarrier)] >;
-
 //===----------------------------------------------------------------------===//
 // Other patterns
 //===----------------------------------------------------------------------===//
 
 // SETCC pattern matches
 //
 //   CMP  %tmp, lhs, rhs     ; compare lhs and rhs
 //   or   %res, 0, (0)1      ; initialize by 0

llvm/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
     // falls back to heap allocation if not.
     SEG_ALLOCA,
 
     // For allocating stack space when using stack clash protector.
     // Allocation is performed by block, and each block is probed.
     PROBED_ALLOCA,
 
     // Memory barriers.
-    MEMBARRIER,
     MFENCE,
 
     // Get a random integer and indicate whether it is valid in CF.
     RDRAND,
 
     // Get a NIST SP800-90B & C compliant random integer and
     // indicate whether it is valid in CF.
     RDSEED,

llvm/lib/Target/X86/X86ISelLowering.cpp

if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
       FenceSSID == SyncScope::System) {
     if (Subtarget.hasMFence())
       return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
 
     SDValue Chain = Op.getOperand(0);
     return emitLockedStackOp(DAG, Subtarget, Chain, dl);
   }
 
-  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-  return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
+  // COMPILER_BARRIER codegens to a 0-byte instruction.
+  return DAG.getCompilerBarrier(dl, FenceOrdering, FenceSSID, Op.getOperand(0));
 }
 
 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget &Subtarget,
                              SelectionDAG &DAG) {
   MVT T = Op.getSimpleValueType();
   SDLoc DL(Op);
   unsigned Reg = 0;
   unsigned size = 0;
if (AN->getOrdering() == AtomicOrdering::SequentiallyConsistent &&
       // traffic.  This assumes that stack locations are very likely to be
       // accessed only by the owning thread.
       SDValue NewChain = emitLockedStackOp(DAG, Subtarget, Chain, DL);
       assert(!N->hasAnyUseOfValue(0));
       // NOTE: The getUNDEF is needed to give something for the unused result 0.
       return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
                          DAG.getUNDEF(VT), NewChain);
     }
-    // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-    SDValue NewChain = DAG.getNode(X86ISD::MEMBARRIER, DL, MVT::Other, Chain);
+
+    // COMPILER_BARRIER is a compiler barrier; it codegens to a no-op.
+    SDValue NewChain = DAG.getCompilerBarrier(DL, AN->getOrdering(), AN->getSyncScopeID(), Chain);
     assert(!N->hasAnyUseOfValue(0));
     // NOTE: The getUNDEF is needed to give something for the unused result 0.
     return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
                        DAG.getUNDEF(VT), NewChain);
   }
 
   SDValue LockOp = lowerAtomicArithWithLOCK(N, DAG, Subtarget);
   // RAUW the chain, but don't worry about the result, as it's unused.
#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
   NODE_NAME_CASE(PMULUDQ)
   NODE_NAME_CASE(PMULDQ)
   NODE_NAME_CASE(PSADBW)
   NODE_NAME_CASE(DBPSADBW)
   NODE_NAME_CASE(VASTART_SAVE_XMM_REGS)
   NODE_NAME_CASE(VAARG_64)
   NODE_NAME_CASE(VAARG_X32)
   NODE_NAME_CASE(WIN_ALLOCA)
-  NODE_NAME_CASE(MEMBARRIER)
   NODE_NAME_CASE(MFENCE)
   NODE_NAME_CASE(SEG_ALLOCA)
   NODE_NAME_CASE(PROBED_ALLOCA)
   NODE_NAME_CASE(RDRAND)
   NODE_NAME_CASE(RDSEED)
   NODE_NAME_CASE(RDPKRU)
   NODE_NAME_CASE(WRPKRU)
   NODE_NAME_CASE(VPMADDUBSW)

llvm/lib/Target/X86/X86InstrCompiler.td

 // Memory barriers
 
 let isCodeGenOnly = 1, Defs = [EFLAGS] in
 def OR32mi8Locked  : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero),
                          "or{l}\t{$zero, $dst|$dst, $zero}", []>,
                          Requires<[Not64BitMode]>, OpSize32, LOCK,
                          Sched<[WriteALURMW]>;
 
-let hasSideEffects = 1 in
-def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
-                     "#MEMBARRIER",
-                     [(X86MemBarrier)]>, Sched<[WriteLoad]>;
-
 // RegOpc corresponds to the mr version of the instruction
 // ImmOpc corresponds to the mi version of the instruction
 // ImmOpc8 corresponds to the mi8 version of the instruction
 // ImmMod corresponds to the instruction format of the mi and mi8 versions
 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
                            Format ImmMod, SDNode Op, string mnemonic> {
 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
     SchedRW = [WriteALURMW] in {

llvm/lib/Target/X86/X86InstrInfo.cpp

default:
     // By default, assume that the instruction is not data invariant.
     return false;
 
     // Some target-independent operations that trivially lower to data-invariant
     // instructions.
   case TargetOpcode::COPY:
   case TargetOpcode::INSERT_SUBREG:
   case TargetOpcode::SUBREG_TO_REG:
+  case TargetOpcode::COMPILER_BARRIER:
     return true;
 
   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
   // However, they set flags and are perhaps the most surprisingly constant
   // time operations so we call them out here separately.
   case X86::IMUL16rr:
   case X86::IMUL16rri8:
   case X86::IMUL16rri:
outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
   unsigned SequenceSize =
       std::accumulate(RepeatedSequenceLocs[0].front(),
                       std::next(RepeatedSequenceLocs[0].back()), 0,
                       [](unsigned Sum, const MachineInstr &MI) {
                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
                         // we can't tell the cost.  Just assume each instruction
                         // is one byte.
-                        if (MI.isDebugInstr() || MI.isKill())
+                        if (MI.isMetaInstruction())
                           return Sum;
                         return Sum + 1;
                       });
 
   // We check to see if CFI Instructions are present, and if they are
   // we find the number of CFI Instructions in the candidates.
   unsigned CFICount = 0;
   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();

llvm/lib/Target/X86/X86InstrInfo.td

 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 
 def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
 
-def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
+def SDT_X86MFENCE : SDTypeProfile<0, 0, []>;
 
 def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
                                          SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>;
 
 def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>,
                                               SDTCisVT<1, i32>,
                                               SDTCisVT<2, v2i64>,
                                               SDTCisPtrTy<3>]>;
 
-def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
-                            [SDNPHasChain,SDNPSideEffect]>;
-def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
+def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MFENCE,
                         [SDNPHasChain]>;
 
 
 def X86bsf     : SDNode<"X86ISD::BSF",      SDTUnaryArithWithFlags>;
 def X86bsr     : SDNode<"X86ISD::BSR",      SDTUnaryArithWithFlags>;
 def X86fshl    : SDNode<"X86ISD::FSHL",     SDTIntShiftDOp>;
 def X86fshr    : SDNode<"X86ISD::FSHR",     SDTIntShiftDOp>;
 

llvm/lib/Target/X86/X86MCInstLower.cpp

void X86AsmPrinter::emitInstruction(const MachineInstr *MI) {
   // Add comments for values loaded from constant pool.
   if (OutStreamer->isVerboseAsm())
     addConstantComments(MI, *OutStreamer);
 
   switch (MI->getOpcode()) {
   case TargetOpcode::DBG_VALUE:
     llvm_unreachable("Should be handled target independently");
 
-  // Emit nothing here but a comment if we can.
-  case X86::Int_MemBarrier:
-    OutStreamer->emitRawComment("MEMBARRIER");
-    return;
-
   case X86::EH_RETURN:
   case X86::EH_RETURN64: {
     // Lower these as normal, but add some comments.
     Register Reg = MI->getOperand(0).getReg();
     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
                             X86ATTInstPrinter::getRegisterName(Reg));
     break;
   }

llvm/lib/Target/XCore/XCoreISelLowering.h

enum NodeType : unsigned {
       BR_JT32,
 
       // Offset from frame pointer to the first (possible) on-stack argument
       FRAME_TO_ARGS_OFFSET,
 
       // Exception handler return. The stack is restored to the first
       // followed by a jump to the second argument.
       EH_RETURN,
-
-      // Memory barrier.
-      MEMBARRIER
     };
   }
 
   //===--------------------------------------------------------------------===//
   // TargetLowering Implementation
   //===--------------------------------------------------------------------===//
   class XCoreTargetLowering : public TargetLowering
   {
private:
     SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
 
     MachineMemOperand::Flags getTargetMMOFlags(
       const Instruction &I) const override;
 
     // Inline asm support
     std::pair<unsigned, const TargetRegisterClass *>

llvm/lib/Target/XCore/XCoreISelLowering.cpp

switch ((XCoreISD::NodeType)Opcode)
     case XCoreISD::LMUL              : return "XCoreISD::LMUL";
     case XCoreISD::MACCU             : return "XCoreISD::MACCU";
     case XCoreISD::MACCS             : return "XCoreISD::MACCS";
     case XCoreISD::CRC8              : return "XCoreISD::CRC8";
     case XCoreISD::BR_JT             : return "XCoreISD::BR_JT";
     case XCoreISD::BR_JT32           : return "XCoreISD::BR_JT32";
     case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
     case XCoreISD::EH_RETURN         : return "XCoreISD::EH_RETURN";
-    case XCoreISD::MEMBARRIER        : return "XCoreISD::MEMBARRIER";
   }
   return nullptr;
 }
 
 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
                                          const XCoreSubtarget &Subtarget)
     : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
 
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 
   // Exception handling
   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
   setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
 
   // Atomic operations
   // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic.
-  // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
-  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
+  // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a compiler
+  // barrier.
+  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
   setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
 
   // TRAMPOLINE is custom lowered.
   setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
   setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
 
   // We want to custom lower some of our intrinsics.
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::ADD:
   case ISD::SUB:                return ExpandADDSUB(Op.getNode(), DAG);
   case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
   case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
   case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
   case ISD::INIT_TRAMPOLINE:    return LowerINIT_TRAMPOLINE(Op, DAG);
   case ISD::ADJUST_TRAMPOLINE:  return LowerADJUST_TRAMPOLINE(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
-  case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
   case ISD::ATOMIC_LOAD:        return LowerATOMIC_LOAD(Op, DAG);
   case ISD::ATOMIC_STORE:       return LowerATOMIC_STORE(Op, DAG);
   default:
     llvm_unreachable("unimplemented operand");
   }
 }
 
 /// ReplaceNodeResults - Replace the results of node with an illegal result
case Intrinsic::xcore_crc8:
       SDValue Crc(Data.getNode(), 1);
       SDValue Results[] = { Crc, Data };
       return DAG.getMergeValues(Results, DL);
   }
   return SDValue();
 }
 
 SDValue XCoreTargetLowering::
-LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
-  SDLoc DL(Op);
-  return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
-}
-
-SDValue XCoreTargetLowering::
 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
   AtomicSDNode *N = cast<AtomicSDNode>(Op);
   assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
   assert((N->getOrdering() == AtomicOrdering::Unordered ||
           N->getOrdering() == AtomicOrdering::Monotonic) &&
          "setInsertFencesForAtomic(true) expects unordered / monotonic");
   if (N->getMemoryVT() == MVT::i32) {
     if (N->getAlignment() < 4)

llvm/lib/Target/XCore/XCoreInstrInfo.td

 def SDT_XCoreCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
                                            SDTCisVT<1, i32> ]>;
 
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
                            [SDNPHasChain, SDNPOutGlue]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_XCoreCallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
-def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>;
-
-def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER,
-                             [SDNPHasChain]>;
-
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
 
 def div4_xform : SDNodeXForm<imm, [{
   // Transformation function: imm/4
   assert(N->getZExtValue() % 4 == 0);
   return getI32Imm(N->getZExtValue()/4, SDLoc(N));

 let usesCustomInserter = 1 in {
   def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
                               (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
                               "# SELECT_CC PSEUDO!",
                               [(set GRRegs:$dst,
                                  (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
 }
 
-let hasSideEffects = 1 in
-def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER",
-                                     [(XCoreMemBarrier)]>;
+// As we are always Sequential Consistent, an ATOMIC_FENCE becomes a compiler
+// barrier (no instruction).
+def : Pat<(atomic_fence (timm:$ordering), (timm:$scope)),
+          (COMPILER_BARRIER i32:$ordering, i32:$scope)>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 // Three operand short
 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;

llvm/test/CodeGen/AArch64/fence-singlethread.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s --check-prefix=LINUX
 ; RUN: llc -mtriple=aarch64-apple-ios %s -o - | FileCheck %s --check-prefix=IOS
 ; RUN: llc -mtriple=aarch64-linux-gnueabihf %s -filetype=obj -o %t
 ; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=OBJ
 
 ; OBJ-NOT: dmb
 
 define void @fence_singlethread() {
 ; LINUX-LABEL: fence_singlethread:
 ; LINUX-NOT: dmb
-; LINUX: // COMPILER BARRIER
+; LINUX: // Compiler Barrier: seq_cst syncscope(singlethread)
 ; LINUX-NOT: dmb
 
 ; IOS-LABEL: fence_singlethread:
 ; IOS-NOT: dmb
-; IOS: ; COMPILER BARRIER
+; IOS: ; Compiler Barrier: seq_cst syncscope(singlethread)
 ; IOS-NOT: dmb
 
   fence syncscope("singlethread") seq_cst
   ret void
 }

llvm/test/CodeGen/ARM/fence-singlethread.ll

 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -filetype=obj -o %t
 ; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=OBJ
 
 ; OBJ-NOT: dmb
 
 define void @fence_singlethread() {
 ; CHECK-LABEL: fence_singlethread:
 ; CHECK-NOT: dmb
-; CHECK: @ COMPILER BARRIER
+; CHECK: @ Compiler Barrier: seq_cst syncscope(singlethread)
 ; CHECK-NOT: dmb
 
   fence syncscope("singlethread") seq_cst
   ret void
 }

llvm/test/CodeGen/RISCV/atomic-fence.ll

 ;
 ; RV64I-LABEL: fence_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fence rw, rw
 ; RV64I-NEXT:    ret
   fence seq_cst
   ret void
 }
+
+define void @fence_st_acquire() nounwind {
+; RV32I-LABEL: fence_st_acquire:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier: acquire syncscope(singlethread)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier: acquire syncscope(singlethread)
+; RV64I-NEXT:    ret
+; RV641-EMPTY:
+  fence syncscope("singlethread") acquire
+  ret void
+}
+
+define void @fence_st_release() nounwind {
+; RV32I-LABEL: fence_st_release:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier: release syncscope(singlethread)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier: release syncscope(singlethread)
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") release
+  ret void
+}
+
+define void @fence_st_acq_rel() nounwind {
+; RV32I-LABEL: fence_st_acq_rel:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier: acq_rel syncscope(singlethread)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier: acq_rel syncscope(singlethread)
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") acq_rel
+  ret void
+}
+
+define void @fence_st_seq_cst() nounwind {
+; RV32I-LABEL: fence_st_seq_cst:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier: seq_cst syncscope(singlethread)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier: seq_cst syncscope(singlethread)
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") seq_cst
+  ret void
+}

llvm/test/CodeGen/SystemZ/atomic-fence-02.ll

 ; Serialization is emitted only for fence seq_cst.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @test() {
-; CHECK: #MEMBARRIER
+; CHECK: # Compiler Barrier: acquire
   fence acquire
-; CHECK: #MEMBARRIER
+; CHECK: # Compiler Barrier: release
   fence release
-; CHECK: #MEMBARRIER
+; CHECK: # Compiler Barrier: acq_rel
   fence acq_rel
   ret void
 }

llvm/test/CodeGen/X86/atomic-idempotent.ll

 ; X86-ATOM-NEXT:    retl
   %1 = atomicrmw and i32* %p, i32 -1 acq_rel
   ret i32 %1
 }
 
 define void @or32_nouse_monotonic(i32* %p) {
 ; X64-LABEL: or32_nouse_monotonic:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier: monotonic
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_monotonic:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier: monotonic
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_monotonic:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier: monotonic
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 monotonic
   ret void
 }
 
 
 define void @or32_nouse_acquire(i32* %p) {
 ; X64-LABEL: or32_nouse_acquire:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier: acquire
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_acquire:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier: acquire
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_acquire:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier: acquire
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 acquire
   ret void
 }
 
 define void @or32_nouse_release(i32* %p) {
 ; X64-LABEL: or32_nouse_release:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier: release
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_release:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier: release
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_release:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier: release
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 release
   ret void
 }
 
 define void @or32_nouse_acq_rel(i32* %p) {
 ; X64-LABEL: or32_nouse_acq_rel:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier: acq_rel
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_acq_rel:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier: acq_rel
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_acq_rel:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier: acq_rel
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 acq_rel

llvm/test/CodeGen/X86/atomic-unordered.ll

; CHECK-NEXT:    retq
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 
 define i64 @nofold_fence_acquire(i64* %p) {
 ; CHECK-LABEL: nofold_fence_acquire:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    # Compiler Barrier: acquire
 ; CHECK-NEXT:    addq $15, %rax
 ; CHECK-NEXT:    retq
   %v = load atomic i64, i64* %p unordered, align 8
   fence acquire
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 
 
 define i64 @nofold_stfence(i64* %p) {
 ; CHECK-LABEL: nofold_stfence:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    # Compiler Barrier: seq_cst syncscope(singlethread)
 ; CHECK-NEXT:    addq $15, %rax
 ; CHECK-NEXT:    retq
   %v = load atomic i64, i64* %p unordered, align 8
   fence syncscope("singlethread") seq_cst
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 

llvm/test/CodeGen/X86/barrier-sse.ll

 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
 
 define void @test() {
+; CHECK-LABEL: test
   fence acquire
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier: acquire
 
   fence release
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier: release
 
   fence acq_rel
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier: acq_rel
 
   ret void
 }

llvm/test/CodeGen/X86/implicit-null-check.ll

 ;; TODO: We could handle this case as we can lift the fence into the
 ;; previous block before the conditional without changing behavior.
 define i32 @imp_null_check_load_fence1(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_fence1:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    testq %rdi, %rdi
 ; CHECK-NEXT:    je LBB16_1
 ; CHECK-NEXT:  ## %bb.2: ## %not_null
-; CHECK-NEXT:    ##MEMBARRIER
+; CHECK-NEXT:    ## Compiler Barrier: acquire
 ; CHECK-NEXT:    movl (%rdi), %eax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  LBB16_1: ## %is_null
 ; CHECK-NEXT:    movl $42, %eax
 ; CHECK-NEXT:    retq
 
 entry:
   %c = icmp eq i32* %x, null

llvm/test/CodeGen/XCore/atomic.ll

 ; RUN: llc < %s -march=xcore | FileCheck %s
 
 ; CHECK-LABEL: atomic_fence
-; CHECK: #MEMBARRIER
-; CHECK: #MEMBARRIER
-; CHECK: #MEMBARRIER
-; CHECK: #MEMBARRIER
+; CHECK: # Compiler Barrier: acquire
+; CHECK: # Compiler Barrier: release
+; CHECK: # Compiler Barrier: acq_rel
+; CHECK: # Compiler Barrier: seq_cst
 ; CHECK: retsp 0
 define void @atomic_fence() nounwind {
 entry:
   fence acquire
   fence release
   fence acq_rel
   fence seq_cst
   ret void
 }
 
 @pool = external global i64
 
 define void @atomicloadstore() nounwind {
 entry:
 ; CHECK-LABEL: atomicloadstore
 
 ; CHECK: ldw r[[R0:[0-9]+]], dp[pool]
 ; CHECK-NEXT: ldaw r[[R1:[0-9]+]], dp[pool]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: ldc r[[R2:[0-9]+]], 0
   %0 = load atomic i32, i32* bitcast (i64* @pool to i32*) acquire, align 4
 
 ; CHECK-NEXT: ld16s r3, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   %1 = load atomic i16, i16* bitcast (i64* @pool to i16*) acquire, align 2
 
 ; CHECK-NEXT: ld8u r11, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   %2 = load atomic i8, i8* bitcast (i64* @pool to i8*) acquire, align 1
 
 ; CHECK-NEXT: ldw r4, dp[pool]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   %3 = load atomic i32, i32* bitcast (i64* @pool to i32*) seq_cst, align 4
 
 ; CHECK-NEXT: ld16s r5, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   %4 = load atomic i16, i16* bitcast (i64* @pool to i16*) seq_cst, align 2
 
 ; CHECK-NEXT: ld8u r6, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   %5 = load atomic i8, i8* bitcast (i64* @pool to i8*) seq_cst, align 1
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: stw r[[R0]], dp[pool]
   store atomic i32 %0, i32* bitcast (i64* @pool to i32*) release, align 4
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: st16 r3, r[[R1]][r[[R2]]]
   store atomic i16 %1, i16* bitcast (i64* @pool to i16*) release, align 2
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: st8 r11, r[[R1]][r[[R2]]]
   store atomic i8 %2, i8* bitcast (i64* @pool to i8*) release, align 1
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: stw r4, dp[pool]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   store atomic i32 %3, i32* bitcast (i64* @pool to i32*) seq_cst, align 4
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: st16 r5, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   store atomic i16 %4, i16* bitcast (i64* @pool to i16*) seq_cst, align 2
 
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
 ; CHECK-NEXT: st8 r6, r[[R1]][r[[R2]]]
-; CHECK-NEXT: #MEMBARRIER
+; CHECK-NEXT: # Compiler Barrier:
   store atomic i8 %5, i8* bitcast (i64* @pool to i8*) seq_cst, align 1
 
 ; CHECK-NEXT: ldw r[[R0]], dp[pool]
 ; CHECK-NEXT: stw r[[R0]], dp[pool]
 ; CHECK-NEXT: ld16s r[[R0]], r[[R1]][r[[R2]]]
 ; CHECK-NEXT: st16 r[[R0]], r[[R1]][r[[R2]]]
 ; CHECK-NEXT: ld8u r[[R0]], r[[R1]][r[[R2]]]
 ; CHECK-NEXT: st8 r[[R0]], r[[R1]][r[[R2]]]