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lenary (Sam Elliott)
Compiler Developer at lowRISC CIC

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User Since
Nov 21 2016, 2:12 PM (164 w, 6 d)

Recent Activity

Wed, Jan 15

lenary added a comment to D71774: [RISCV] Optimize seteq/setne pattern expansions for better code size.

This seems like a fun issue:

  • addi is compressible
  • xor is almost certainly easier to analyse (from the view of KnownBits and the like).
Wed, Jan 15, 6:48 AM · Restricted Project
lenary added a comment to D72755: [RISCV] Pass target-abi via module flag metadata.

Please can you also add code for ensuring that the target-abi module flag matches the -target-abi command line flag in llvm?

Wed, Jan 15, 3:51 AM · Restricted Project
lenary reopened D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

@s.egerton Thank you. Sorry again for the confusion.

Wed, Jan 15, 3:15 AM · Restricted Project
lenary added inline comments to D68685: [RISCV] Scheduler description for Rocket Core.
Wed, Jan 15, 1:14 AM · Restricted Project
lenary accepted D70837: [RISCV] Support ABI checking with per function target-features.

LGTM!

Wed, Jan 15, 12:45 AM · Restricted Project

Tue, Jan 14

lenary added a comment to D72624: [WIP] TargetMachine Hook for Module Metadata.

One thing to note about my patch, above: I have not made the TargetMachine DataLayout non-const, but I wanted to ensure that this might be possible in future, which is why calling initializeOptionsWithModuleMetadata must be done before the first call to createDataLayout. At the moment, the RISC-V ABI data layouts are based only on riscv32 vs riscv64, not the target-abi metadata (all riscv32 ABIs use the same data layout, all riscv64 ABIs use the same data layout), but I know Mips has more complex logic for computing their data layout based on their ABI.

Tue, Jan 14, 3:14 PM · Restricted Project, Restricted Project, Restricted Project
lenary added a comment to D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

@efriedma To keep you in the loop, D72624 is the patch to add a target hook for setting the TargetMachine options based on module metadata. That patch does not add any RISC-V specific functionality, it only lays the groundwork for it.

Tue, Jan 14, 3:04 PM · Restricted Project
lenary updated the diff for D72624: [WIP] TargetMachine Hook for Module Metadata.

Address some review feedback.

Tue, Jan 14, 11:32 AM · Restricted Project, Restricted Project, Restricted Project
lenary added a comment to D72624: [WIP] TargetMachine Hook for Module Metadata.
Tue, Jan 14, 11:32 AM · Restricted Project, Restricted Project, Restricted Project
lenary added a comment to D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

@s.egerton Please can you revert rG57cf6ee9c84434161088c39a6f8dd2aae14eb12d - this patch has open dependencies, including on the LLVM support for RISC-V B extension. It would be confusing to users if clang 10.0 contained frontend support for the B extension, but LLVM 10.0 did not contain backend support for it.

Tue, Jan 14, 10:32 AM · Restricted Project
lenary added inline comments to D70837: [RISCV] Support ABI checking with per function target-features.
Tue, Jan 14, 5:56 AM · Restricted Project
lenary committed rGdee6e39c7561: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions (authored by lenary).
[RISCV][NFC] Deduplicate Atomic Intrinsic Definitions
Tue, Jan 14, 5:26 AM
lenary closed D71777: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions.
Tue, Jan 14, 5:26 AM · Restricted Project
lenary added inline comments to D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Tue, Jan 14, 3:30 AM · Restricted Project, Restricted Project

Mon, Jan 13

lenary added inline comments to D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Mon, Jan 13, 8:59 AM · Restricted Project, Restricted Project
lenary created D72624: [WIP] TargetMachine Hook for Module Metadata.
Mon, Jan 13, 8:50 AM · Restricted Project, Restricted Project, Restricted Project
lenary added inline comments to D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.
Mon, Jan 13, 8:22 AM · Restricted Project, Restricted Project
lenary accepted D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types.

@jrtc27 It would be good to get this in for LLVM 10.0.

Mon, Jan 13, 6:07 AM · Restricted Project
lenary accepted D72134: [RISCV] Fix test for inline asm z constraint modifier.

LGTM. Please wait for @jrtc27 to approve this before landing.

Mon, Jan 13, 5:48 AM · Restricted Project
lenary committed rGc9babcbda77e: [RISCV] Collect Statistics on Compressed Instructions (authored by lenary).
[RISCV] Collect Statistics on Compressed Instructions
Mon, Jan 13, 2:07 AM
lenary closed D67495: [RISCV] Collect Statistics on Compressed Instructions.
Mon, Jan 13, 2:07 AM · Restricted Project
lenary added a comment to D71777: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions.

@jrtc27 I'm going to wait for the ok from you before I merge this, given you had feedback before.

Mon, Jan 13, 2:07 AM · Restricted Project

Fri, Jan 10

lenary accepted D72471: [RISCV] Check register class for AMO memory operands.

LGTM. Nice fix!

Fri, Jan 10, 3:11 AM · Restricted Project

Thu, Jan 9

lenary added a comment to D67495: [RISCV] Collect Statistics on Compressed Instructions.

LGTM. My only concern was if it made sense to use the same statistic to count in both places, and if we could end up double counting the instructions emitted (now, or in a future LLVM version). After a quick look I didn't really see other targets using the same approach, but I also can't think of a way where this ends up actually being problematic.

Thu, Jan 9, 3:40 AM · Restricted Project
lenary updated the diff for D67495: [RISCV] Collect Statistics on Compressed Instructions.

Rebase

Thu, Jan 9, 3:26 AM · Restricted Project

Tue, Jan 7

lenary added a comment to D71777: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions.

TableGen is an officially supported language for clang-format, which is why I hoped it wouldn't be so bad to use to format this file. I really wanted a nice way to avoid having to manually wrap the comments.

Tue, Jan 7, 9:55 AM · Restricted Project
lenary updated the diff for D71777: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions.

Address review comments

Tue, Jan 7, 9:55 AM · Restricted Project
lenary accepted D72275: [RISCV] Handle globals and block addresses in asm operands.

LGTM! Thanks!

Tue, Jan 7, 4:46 AM · Restricted Project

Mon, Jan 6

lenary added inline comments to D67495: [RISCV] Collect Statistics on Compressed Instructions.
Mon, Jan 6, 7:11 AM · Restricted Project

Dec 20 2019

lenary created D71778: [RISCV] Add Clang Builtins for Accessing CSRs.
Dec 20 2019, 11:01 AM · Restricted Project, Restricted Project
lenary created D71777: [RISCV][NFC] Deduplicate Atomic Intrinsic Definitions.
Dec 20 2019, 11:01 AM · Restricted Project
lenary added a comment to D71683: [ORC][EH] Deregister EH frames in MemoryManager dtor.

@myhsu Now that you have three accepted commits to LLVM, you can ask for commit access! Follow these instructions

Dec 20 2019, 6:59 AM · Restricted Project
lenary added a comment to D67661: [RISCV] Headers: Add Bitmanip extension Clang header files and rvintrin.h.

Selfishly, I would like to see the addition of rvintrin.h separated from the bit-manipulation-specific headers. I'm looking at landing some additions to clang/LLVM that include builtins, and don't want to cause merge issues with this PR.

Dec 20 2019, 3:56 AM · Restricted Project, Restricted Project
lenary accepted D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

LGTM!

Dec 20 2019, 3:27 AM · Restricted Project

Dec 16 2019

lenary committed rGce3d1c6d61dc: [libunwind][RISCV] Add 64-bit RISC-V support (authored by lenary).
[libunwind][RISCV] Add 64-bit RISC-V support
Dec 16 2019, 8:43 AM
lenary closed D68362: [libunwind][RISCV] Add 64-bit RISC-V support.
Dec 16 2019, 8:43 AM · Restricted Project
lenary added a comment to D68362: [libunwind][RISCV] Add 64-bit RISC-V support.

Yeah, will do.

Dec 16 2019, 8:34 AM · Restricted Project
lenary added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Dec 16 2019, 8:34 AM · Restricted Project, Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Update Comments
Dec 16 2019, 8:15 AM · Restricted Project, Restricted Project
lenary added a reviewer for D67495: [RISCV] Collect Statistics on Compressed Instructions: luismarques.
Dec 16 2019, 7:22 AM · Restricted Project
lenary accepted D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO.

Nice! I think this is the correct way of implementing this, and I don't think it will have any issue with other backends.

Dec 16 2019, 5:35 AM · Restricted Project
lenary accepted D70116: [RISCV] add subtargets initialized with target feature.
Dec 16 2019, 4:55 AM · Restricted Project

Dec 13 2019

lenary committed rGa0f43b004358: [RISCV] Move DebugLoc Copy into CompressInstEmitter (authored by lenary).
[RISCV] Move DebugLoc Copy into CompressInstEmitter
Dec 13 2019, 12:06 PM
lenary closed D67493: [RISCV] Move DebugLoc Copy into CompressInstEmitter.
Dec 13 2019, 12:05 PM · Restricted Project
lenary accepted D68362: [libunwind][RISCV] Add 64-bit RISC-V support.

LGTM! Thanks for correcting the preprocessor issues!

Dec 13 2019, 8:24 AM · Restricted Project

Dec 11 2019

lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Ran clang-format
Dec 11 2019, 7:31 AM · Restricted Project, Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Correct typo
Dec 11 2019, 6:45 AM · Restricted Project, Restricted Project
lenary added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Dec 11 2019, 6:45 AM · Restricted Project, Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Update vararg.ll test to add ILP32E tests
  • Address code duplication review comments.
Dec 11 2019, 6:40 AM · Restricted Project, Restricted Project

Dec 10 2019

lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Clang support for ilp32e
Dec 10 2019, 8:01 AM · Restricted Project, Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Update CSR definition comments
Dec 10 2019, 7:43 AM · Restricted Project, Restricted Project
lenary added inline comments to D71124: [RISCV] support clang driver to select cpu.
Dec 10 2019, 7:42 AM · Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Test Updates
Dec 10 2019, 7:09 AM · Restricted Project, Restricted Project
lenary updated the diff for D70401: [WIP][RISCV] Implement ilp32e ABI.
  • Address ILP32E / rv32d frame pointer issue. I didn't manage to find a reasonable way to query for defined fpr64s, so I'm just enabling the FP if the D extension is enabled.
Dec 10 2019, 6:56 AM · Restricted Project, Restricted Project
lenary added reviewers for D71124: [RISCV] support clang driver to select cpu: lenary, asb.
Dec 10 2019, 5:16 AM · Restricted Project

Dec 9 2019

lenary updated the diff for D67493: [RISCV] Move DebugLoc Copy into CompressInstEmitter.

Rebased and added a test to ensure debug info is preserved.

Dec 9 2019, 9:28 AM · Restricted Project
lenary added a comment to D70666: [RISCV] Machine Operand Flag Serialization.

This broke the build and I had to add rGcb664baf50f069cb844d69cd6b8952cb22a3e7c2 to fix it.

Dec 9 2019, 5:56 AM · Restricted Project
lenary committed rGcb664baf50f0: [RISCV] Fix mir-target-flags.ll (authored by lenary).
[RISCV] Fix mir-target-flags.ll
Dec 9 2019, 5:54 AM
lenary committed rGc20930a724f9: [RISCV] Machine Operand Flag Serialization (authored by lenary).
[RISCV] Machine Operand Flag Serialization
Dec 9 2019, 5:19 AM
lenary closed D70666: [RISCV] Machine Operand Flag Serialization.
Dec 9 2019, 5:19 AM · Restricted Project

Dec 4 2019

lenary added a reviewer for D68290: [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes(): lewis-revill.
Dec 4 2019, 3:30 AM · Restricted Project
lenary added reviewers for D68290: [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes(): lenary, asb, luismarques.
Dec 4 2019, 3:30 AM · Restricted Project

Nov 27 2019

lenary added a comment to D70116: [RISCV] add subtargets initialized with target feature.

We definitely want to support rv32imafc/ilp32 and combinations like that.

Nov 27 2019, 2:17 PM · Restricted Project
lenary added a comment to D70116: [RISCV] add subtargets initialized with target feature.

So am I right in thinking that neither foo nor foo2 will trigger the ABI_Unknown issue, and the issue is only coming from hand-written assembly files?

Actually, you may need to specify -target-abi in the top of the subtarget-features-std-ext.ll file.

Sorry I didn't explain clearly,
The problem is caused by when I try to enable LTO and it need to pass mabi to LTO code generator (mabi is not encoded in bitcode)
like we compile below case with llc example.c -mtriple=riscv32 -mabi=ilp32f.

define float @foo(i32 %a) nounwind #0 {
  %conv = sitofp i32 %a to float
  ret float %conv
}

define float @foo2(i32 %a) nounwind #1{
  %conv = sitofp i32 %a to float
  ret float %conv
}

attributes #0 = { "target-features"="+f"}
attributes #1 = { "target-features"="+f"}

and they will show two error messages Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension.
so there is no any issue in subtarget-features-std-ext.ll without -target-abi.

when I started to fix this error, I found backend shares the ABI parsing/checking function (computeTargetABI) in codegen and MC layer when instance RISCVAsmBackend (note: IR function is not available at this point)
ref. https://github.com/llvm/llvm-project/commit/fea4957177315f83746dca90cb4c9013eb465c46

so this patch is workable, but it's not useful for LTO, not useful enough to support per function feature in backend, and then I'm not sure it's worth to upstream this patch.

Nov 27 2019, 5:49 AM · Restricted Project
lenary added a comment to D70116: [RISCV] add subtargets initialized with target feature.

So am I right in thinking that neither foo nor foo2 will trigger the ABI_Unknown issue, and the issue is only coming from hand-written assembly files?

Nov 27 2019, 3:07 AM · Restricted Project

Nov 26 2019

lenary abandoned D70670: [RISCV] Implement canRealignStack.

With the patch, double load/store instructions may unaligned-access with -mabi=ilp32e -mattr=+d flags. Could the load/store support unaligned-access?

Nov 26 2019, 2:53 AM · Restricted Project
lenary retitled D70666: [RISCV] Machine Operand Flag Serialization from [WIP][RISCV] Machine Operand Flag Serialization to [RISCV] Machine Operand Flag Serialization.
Nov 26 2019, 2:53 AM · Restricted Project
lenary added reviewers for D70666: [RISCV] Machine Operand Flag Serialization: jrtc27, luismarques.
Nov 26 2019, 2:44 AM · Restricted Project
lenary added inline comments to D70666: [RISCV] Machine Operand Flag Serialization.
Nov 26 2019, 2:44 AM · Restricted Project
lenary updated the diff for D70666: [RISCV] Machine Operand Flag Serialization.
  • Increase Testcase Coverage
Nov 26 2019, 2:44 AM · Restricted Project

Nov 25 2019

lenary updated the diff for D70666: [RISCV] Machine Operand Flag Serialization.
  • Serialization Testcase
Nov 25 2019, 11:23 AM · Restricted Project
lenary accepted D70678: [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32).

Sure, LGTM

Nov 25 2019, 9:56 AM · Restricted Project
lenary added a comment to D70670: [RISCV] Implement canRealignStack.

This might have to be backported to 9.0.1 as stack realignment has got into 9.0.1.

Nov 25 2019, 6:42 AM · Restricted Project
lenary added a child revision for D70670: [RISCV] Implement canRealignStack: D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 25 2019, 5:53 AM · Restricted Project
lenary created D70670: [RISCV] Implement canRealignStack.
Nov 25 2019, 5:53 AM · Restricted Project
lenary added a parent revision for D70401: [WIP][RISCV] Implement ilp32e ABI: D70670: [RISCV] Implement canRealignStack.
Nov 25 2019, 5:53 AM · Restricted Project, Restricted Project
lenary created D70666: [RISCV] Machine Operand Flag Serialization.
Nov 25 2019, 5:29 AM · Restricted Project
lenary added a comment to D62190: [RISCV] Allow shrink wrapping for RISC-V.
In D62190#1755159, @asb wrote:

I note that the TargetFrameLowering hooks canUseAsPrologue and canUseAsEpilogue are both called by the shrink wrapper. They default to true, but targets may need to override this for correctness. Looking at e.g. AArch64, I see it overrides canUseAsPrologue and returns false in the case that the function needs stack realignment and there are no scratch registers available. Are you certain that no such case is needed for RISC-V?

So I see that the stack realignment implementation for larger values does indeed require the use of a scratch register, so that implies we should attempt to prevent the situation where we don't have one available. However the scratch register is created as a virtual GPR register, rather than attempting to scavenge a real free register. I can imagine that if this was changed, we could directly perform the same check in canUseAsPrologue to guarantee a register being available in a much more transparent and obvious way. EG the way in which AArch64 uses the function findScratchNonCalleeSaveRegister.

Nov 25 2019, 3:29 AM · Restricted Project

Nov 21 2019

lenary added inline comments to D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 21 2019, 11:27 AM · Restricted Project, Restricted Project
lenary retitled D70401: [WIP][RISCV] Implement ilp32e ABI from [RISCV] Implement ilp32e ABI to [WIP][RISCV] Implement ilp32e ABI.
Nov 21 2019, 11:27 AM · Restricted Project, Restricted Project
lenary added a comment to D67508: [RISCV] support mutilib in baremetal environment.

Re-applied with typo fix in rGdf876a026981.

Nov 21 2019, 5:02 AM · Restricted Project

Nov 20 2019

lenary added inline comments to D70477: [Clang] Enable RISC-V support for Fuchsia.
Nov 20 2019, 11:07 AM · Restricted Project
lenary accepted D68407: [RISCV] Use compiler-rt if no GCC installation detected.

Nice, LGTM! Thanks for fixing this in the presence of CLANG_DEFAULT_RTLIB.

Nov 20 2019, 3:27 AM · Restricted Project
lenary added inline comments to D70426: [DAGCombiner][RISCV] Avoid FCOPYSIGN folding of legalizing operand casts.
Nov 20 2019, 3:16 AM · Restricted Project
lenary accepted D69899: [RISCV] Improve assembler missing feature warnings.

LGTM! This is a really nice improvement, thanks!

Nov 20 2019, 3:16 AM · Restricted Project
lenary added inline comments to rGb6d7bbfa0043: [RISCV] Support mutilib in baremetal environment.
Nov 20 2019, 2:52 AM

Nov 18 2019

lenary added a comment to D70401: [WIP][RISCV] Implement ilp32e ABI.

Some notes and queries about this patch.

Nov 18 2019, 8:44 AM · Restricted Project, Restricted Project
lenary created D70401: [WIP][RISCV] Implement ilp32e ABI.
Nov 18 2019, 8:35 AM · Restricted Project, Restricted Project
lenary added a comment to D69741: [Codegen] Both sides of '&&' are same; fixed.

There is no official riscv buildbot? I think it is mandatory to have a buildbot for official (non experimental) target.

Nov 18 2019, 5:45 AM · Restricted Project

Nov 15 2019

lenary added a comment to D67508: [RISCV] support mutilib in baremetal environment.

Do rebase this patch now that D69383 has landed, and check that it is still working correctly. If so, you can land this patch.

Nov 15 2019, 7:42 AM · Restricted Project
lenary committed rGe3d5ff5a0b10: [RISCV] Match GCC `-march`/`-mabi` driver defaults (authored by lenary).
[RISCV] Match GCC `-march`/`-mabi` driver defaults
Nov 15 2019, 7:16 AM
lenary closed D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults.
Nov 15 2019, 7:16 AM · Restricted Project
lenary updated the diff for D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults.

Rebase and update comments and release notes

Nov 15 2019, 7:15 AM · Restricted Project
lenary updated the summary of D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults.
Nov 15 2019, 7:15 AM · Restricted Project
lenary accepted D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

LGTM, Let's get this merged!

Nov 15 2019, 3:39 AM · Restricted Project
lenary added a comment to D67794: [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation.

The RISC-V test changes look good. (I do not intend to review the optimisation implementation or other backend test changes).

Nov 15 2019, 3:29 AM · Restricted Project

Nov 14 2019

lenary committed rG32d840d29179: [RISCV] Use addi rather than add x0 (authored by lenary).
[RISCV] Use addi rather than add x0
Nov 14 2019, 10:52 AM
lenary closed D70124: [RISCV] Use addi rather than add x0.
Nov 14 2019, 10:52 AM · Restricted Project
lenary added a comment to D68979: [RISCV] Handle variable sized objects with the stack need to be realigned.

Please can you rebase this on top of master? @luismarques has removed CFI directives from function epilogs (because they were sometimes buggy), which should make this code simpler.

Nov 14 2019, 10:24 AM · Restricted Project

Nov 12 2019

lenary created D70124: [RISCV] Use addi rather than add x0.
Nov 12 2019, 7:31 AM · Restricted Project