- User Since
- Mar 22 2017, 6:01 PM (148 w, 1 d)
Tue, Jan 14
If this is changing the user visible defaults then the processor table in AMDGPUUsage also needs to be updated and the change of compiler needs to be mentioned in the release notes.
Dec 12 2019
Dec 11 2019
Split non-DWARF changes into D71392.
Dec 5 2019
Dec 4 2019
Nov 25 2019
@scott.linder can answer about the -g question, but I would expect that the CFI is capable of describing the address of the CFA regardless of whether there is a frame pointer by simply knowing the constant offset from the stack pointer.
Nov 23 2019
Move note on supporting any integral value to be implcitly converted
to a location description.
[AMDGPU] Update AMDGPUUsage with DWARF proposal and other fixes
Nov 21 2019
Nov 20 2019
Oct 17 2019
Oct 8 2019
Oct 7 2019
Jul 24 2019
How does this work for EXEC mask?
Mar 25 2019
Do we know the state of split DWARF and DWARF compression for DWARF 5 (compared to DWARF 2)?
Mar 7 2019
LGTM with comment update.
Feb 28 2019
Feb 21 2019
To clarify, I am saying that the stub does have a different name since it is conceptually part of the implementation of doing the call to the device function implementation, and is not in fact the the device function being called itself. However, when we generate code for a function that is present on both the host and device, both copies of the code are for the same source level function and so can have the same symbol name (which was a question that was asked).
Yes this relates to supporting the debugger.
Nov 19 2018
Nov 15 2018
Nov 9 2018
Nov 7 2018
This is sufficient, because whenever only one event of a count type is
pending, its last time point is naturally the upper bound of all time
points of this count type, and when multiple event types are pending,
the count type has gone out of order and an s_waitcnt to 0 is required
to clear any pending event type (and will then clear all pending event
types for that count type).
Nov 6 2018
Nov 5 2018
Summary needs updating as now only being done for kernels and not namespace scope variables.
Should the v2 version of the metadata be moved to a separate section rather than be deleted since it is still generated when the v2 code object format is requested?
LGTM (scheduler can be done in separate change list)
Does the assembler need any support for this? For example, does the .amdgcn_target directive need to accept the +sramecc and ensure the e_flag is set accordingly?
Oct 23 2018
Oct 22 2018
Oct 17 2018
Oct 16 2018
Oct 7 2018
Another word commonly used across languages is "offload".
Jul 20 2018
Jul 17 2018
Jul 10 2018
Jul 9 2018
Jun 21 2018
Now this is implemented it may be worth converting the memorylegalizer tests from MIR to IR tests.
Jun 14 2018
Jun 13 2018
Abandon as duplicate of D47549.
Rename note record enmerator from NT_AMD_AMDGPU_* to NT_AMDGPU_* to match the vendor name change from "AMD" to "AMDGPU".
Jun 12 2018
Jun 8 2018
Jun 7 2018
Add MIR tests for local and region address spaces.
Jun 4 2018
Jun 1 2018
Further minimize MIR tests (thanks @rampitec ).
May 31 2018
Reduced size of mir tests.
Update for @rampitec review comments.
May 30 2018
May 29 2018
May 25 2018
May 18 2018
May 17 2018
LGTM except for minor suggestions.
May 16 2018
May 15 2018