RISC-V big-endian support implementation

[gbenyei]

Summary

Implement riscv32be and riscv64be targets.
The RISC-V big- and bi-endian targets are discussed in the RISC-V spec Version 20191213, but some aspects, like ABI are still unclear.
The instruction encoding is little endian in both big- and little-endian modes. ISA spec Volume 1 1.15: "Instructions are stored in memory as a sequence
of 16-bit little-endian parcels, regardless of memory system endianness".

RISC-V Big-endian cores are already supported by GCC. Where spec is unclear, we aim to be compatible with GCC.

[craig.topper]

clang/lib/Basic/Targets/RISCV.h

111

Instead of creating new classes, could we have a branch on the Arch or isLittleEndian portion of the triple to decide what to pass to resetDataLayout? That's what PPC32TargetInfo does for example.

lld/ELF/Arch/RISCV.cpp

160 ↗

(On Diff #440067)

Is it possible to use write64 instead of write64le/be? It looks like it checks the endianness internally.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

628

Capitalize swapValue

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

32–33

Is this longer than 80 columns?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp

24

Could we do IsLittleEndian = TT.isLittleEndian()?

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

64

No else after return

[jhenderson]

llvm/include/llvm/ADT/Triple.h

864

Perhaps worth updating to mention big and little endian here, like isPPC64 above?

llvm/tools/llvm-objcopy/ObjcopyOptions.cpp

304–305

We need llvm-objcopy testing for these new targets.

[gbenyei]

Thanks, Craig. Updated the patch with your remarks.

[jrtc27]

clang/lib/Basic/Targets/RISCV.h

113

And please avoid repeating the whole data layout, just make the e/E a variable

clang/lib/Driver/ToolChains/FreeBSD.cpp

235

-X to match LE. Or ditch these (and I can ditch riscv32...) since FreeBSD only supports riscv64.

clang/lib/Driver/ToolChains/Gnu.cpp

1701–1702

Just shove a + Be + in the middle of these two rather than introducing a whole new set and picking between them?

llvm/cmake/config-ix.cmake

463 ↗

(On Diff #440196)

I believe these need to come before the unsuffixed versions to do anything, but also the unsuffixed versions already handle the suffixed versions correctly so this isn't needed?

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

554 ↗

(On Diff #440196)

Why switch to this order when before you've used 32, 64, 32be, 64be as the order

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

65

As with Clang

[jhenderson]

Objcopy aspects look good, thanks.

[MaskRay]

lld/ELF change should be dropped from this change. Don't use config->endianness.
I feel sad that for little-endian users who don't use big-endian, every write now is slightly slower due to a check ;-)

clang/lib/Basic/Targets/RISCV.cpp

123–124

The convention doesn't add () in such an assignment.

218

This can be simplified with something like isRISCV64()

clang/lib/Basic/Targets/RISCV.h

142

You may use a char and possibly fold this into the expression below.

143

delete blank line

[gbenyei]

In D128612#3617906, @jhenderson wrote:

Objcopy aspects look good, thanks.

Thanks

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

554 ↗

(On Diff #440196)

The order in the code before my changes is 64, 32. I guess for no good reason, but I prefer not to re-order code while implementing a feature - it trashes git history.

[gbenyei]

In D128612#3617955, @MaskRay wrote:

lld/ELF change should be dropped from this change. Don't use config->endianness.
I feel sad that for little-endian users who don't use big-endian, every write now is slightly slower due to a check ;-)

Hi, I'm not sure I get it. How will we have a fully functional toolchain, if I don't implement the lld/ELF part?
In LLVM, unlike in GCC, target related decisions happen in runtime. I think it's a high level design decision. While I can understand the pain of LE developers getting a slightly slower linker due to endianness checking, I sure will feel the pain of a BE developer not having a linker...

Please explain why I shouldn't use config->endianness?

[MaskRay]

In D128612#3618167, @gbenyei wrote:

In D128612#3617955, @MaskRay wrote:

lld/ELF change should be dropped from this change. Don't use config->endianness.
I feel sad that for little-endian users who don't use big-endian, every write now is slightly slower due to a check ;-)

Hi, I'm not sure I get it. How will we have a fully functional toolchain, if I don't implement the lld/ELF part?
In LLVM, unlike in GCC, target related decisions happen in runtime. I think it's a high level design decision. While I can understand the pain of LE developers getting a slightly slower linker due to endianness checking, I sure will feel the pain of a BE developer not having a linker...

Please explain why I shouldn't use config->endianness?

See PPC64.cpp. See D96188 how I added aarch64_be support. A set of representative tests should be picked with be tests.
If llvm-project consensus is that we will add big-endian support, I can handle lld/ELF part. I am mostly concerned with this scenarios that some RISC-V folks click LGTM, and the change lands with no test in some areas, or the code somewhat breaks local convention.

Many of the changes in this patch probably should be split. llvm-objcopy and JIT changes definitely needs appropriate tests and the suitable domain reviewers.

[gbenyei]

In D128612#3620911, @MaskRay wrote:

In D128612#3618167, @gbenyei wrote:

In D128612#3617955, @MaskRay wrote:

lld/ELF change should be dropped from this change. Don't use config->endianness.
I feel sad that for little-endian users who don't use big-endian, every write now is slightly slower due to a check ;-)

Hi, I'm not sure I get it. How will we have a fully functional toolchain, if I don't implement the lld/ELF part?
In LLVM, unlike in GCC, target related decisions happen in runtime. I think it's a high level design decision. While I can understand the pain of LE developers getting a slightly slower linker due to endianness checking, I sure will feel the pain of a BE developer not having a linker...

Please explain why I shouldn't use config->endianness?

See PPC64.cpp. See D96188 how I added aarch64_be support. A set of representative tests should be picked with be tests.
If llvm-project consensus is that we will add big-endian support, I can handle lld/ELF part. I am mostly concerned with this scenarios that some RISC-V folks click LGTM, and the change lands with no test in some areas, or the code somewhat breaks local convention.

Many of the changes in this patch probably should be split. llvm-objcopy and JIT changes definitely needs appropriate tests and the suitable domain reviewers.

Thanks, it makes more sense now. I'll split the LLD changes, and remove the JIT related stuff.

clang/lib/Basic/Targets/RISCV.h

142

Concatenating a conditional char and a string literal might be tricky, I'm not sure there is a cleaner solution.

[MaskRay]

clang/lib/Basic/Targets/RISCV.h

142

There is a constructor Twine(char)

[gbenyei]

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

554 ↗

(On Diff #440196)

Removed this part anyway - JIT is out of scope for this commit. Thanks.

[gbenyei]

Removed LLD and JIT related parts - JIT is out of my scope, and LLD will be in an additional patch.
Fixed additional remarks.

[asb]

Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it would be helpful from a review perspective to write down at least a simple plain-text description of the changes to the psABI doc needed to reflect the BE ABI implemented by GCC (and soon LLVM), perhaps in an issue.

I think this patch is lacking some test coverage around things like fixup handling (e.g. the logic to swap fixups).

[djtodoro]

Hi! I am wondering if someone knows what is the status of this.

[asb]

In D128612#4337037, @djtodoro wrote:

Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against the psABI doc for big endian that we can review against.

[djtodoro]

In D128612#4345912, @asb wrote:

In D128612#4337037, @djtodoro wrote:

Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against the psABI doc for big endian that we can review against.

OK. Can you please share with me the GCC PR, so I can take a look how it should be done :)

[asb]

In D128612#4349259, @djtodoro wrote:

In D128612#4345912, @asb wrote:

In D128612#4337037, @djtodoro wrote:

Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against the psABI doc for big endian that we can review against.

OK. Can you please share with me the GCC PR, so I can take a look how it should be done :)

Based on comments here it sounds like GCC merged some level of support without submitting corresponding changes to the psABI. I don't have those patches to hand, but you can probably find them on the GCC patches list. I think we've had enough unexpected compatibility issues by now that it's not really justifiable to merge something that's meant to be a standard ABI without having the corresponding psABI patch (even if it appears simple). I don't think anyone has posted such a psABI patch but there is/was a tracking issue for it on the psABI repo.

@kito-cheng is the bigendian RISC-V work in GCC still active at all? I'm wondering if there's a connection you could help make for Djordje.

[djtodoro]

In D128612#4349291, @asb wrote:

In D128612#4349259, @djtodoro wrote:

In D128612#4345912, @asb wrote:

In D128612#4337037, @djtodoro wrote:

Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against the psABI doc for big endian that we can review against.

OK. Can you please share with me the GCC PR, so I can take a look how it should be done :)

Based on comments here it sounds like GCC merged some level of support without submitting corresponding changes to the psABI. I don't have those patches to hand, but you can probably find them on the GCC patches list. I think we've had enough unexpected compatibility issues by now that it's not really justifiable to merge something that's meant to be a standard ABI without having the corresponding psABI patch (even if it appears simple). I don't think anyone has posted such a psABI patch but there is/was a tracking issue for it on the psABI repo.

Yeah, if the https://github.com/riscv-non-isa/riscv-elf-psabi-doc is the repo, I was not able to find the PR for GCC. And I think the support within GCC is somewhat finished.

@kito-cheng is the bigendian RISC-V work in GCC still active at all? I'm wondering if there's a connection you could help make for Djordje.

clang/include/clang/Basic/Attr.td

 def TargetAArch64 : TargetArch<["aarch64"]>;
 def TargetAnyArm : TargetArch<!listconcat(TargetARM.Arches, TargetAArch64.Arches)>;
 def TargetAVR : TargetArch<["avr"]>;
 def TargetBPF : TargetArch<["bpfel", "bpfeb"]>;
 def TargetMips32 : TargetArch<["mips", "mipsel"]>;
 def TargetAnyMips : TargetArch<["mips", "mipsel", "mips64", "mips64el"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetM68k : TargetArch<["m68k"]>;
-def TargetRISCV : TargetArch<["riscv32", "riscv64"]>;
+def TargetRISCV : TargetArch<["riscv32", "riscv64", "riscv32be", "riscv64be"]>;
 def TargetX86 : TargetArch<["x86"]>;
 def TargetAnyX86 : TargetArch<["x86", "x86_64"]>;
 def TargetWebAssembly : TargetArch<["wasm32", "wasm64"]>;
 def TargetHasDLLImportExport : TargetSpec {
   let CustomCode = [{ Target.getTriple().hasDLLImportExport() }];
 }
 def TargetItaniumCXXABI : TargetSpec {
   let CustomCode = [{ Target.getCXXABI().isItaniumFamily() }];

clang/lib/Basic/Targets.cpp

TargetInfo *AllocateTarget(const llvm::Triple &Triple,
   case llvm::Triple::nvptx64:
     return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64);
 
   case llvm::Triple::amdgcn:
   case llvm::Triple::r600:
     return new AMDGPUTargetInfo(Triple, Opts);
 
   case llvm::Triple::riscv32:
+  case llvm::Triple::riscv32be:
     // TODO: add cases for NetBSD, RTEMS once tested.
     switch (os) {
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<RISCV32TargetInfo>(Triple, Opts);
     case llvm::Triple::Linux:
       return new LinuxTargetInfo<RISCV32TargetInfo>(Triple, Opts);
     default:
       return new RISCV32TargetInfo(Triple, Opts);
     }
 
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv64be:
     // TODO: add cases for NetBSD, RTEMS once tested.
     switch (os) {
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<RISCV64TargetInfo>(Triple, Opts);
     case llvm::Triple::OpenBSD:
       return new OpenBSDTargetInfo<RISCV64TargetInfo>(Triple, Opts);
     case llvm::Triple::Fuchsia:
       return new FuchsiaTargetInfo<RISCV64TargetInfo>(Triple, Opts);

clang/lib/Basic/Targets/OSTargets.h

FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     case llvm::Triple::ppc64le:
       this->MCountName = "_mcount";
       break;
     case llvm::Triple::arm:
       this->MCountName = "__mcount";
       break;
     case llvm::Triple::riscv32:
     case llvm::Triple::riscv64:
+    case llvm::Triple::riscv32be:
+    case llvm::Triple::riscv64be:
       break;
     }
   }
 };
 
 // GNU/kFreeBSD Target
 template <typename Target>
 class LLVM_LIBRARY_VISIBILITY KFreeBSDTargetInfo : public OSTargetInfo<Target> {
OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     case llvm::Triple::ppc:
     case llvm::Triple::ppc64:
     case llvm::Triple::ppc64le:
     case llvm::Triple::sparcv9:
       this->MCountName = "_mcount";
       break;
     case llvm::Triple::riscv32:
     case llvm::Triple::riscv64:
+    case llvm::Triple::riscv32be:
+    case llvm::Triple::riscv64be:
       break;
     }
   }
 };
 
 // PSP Target
 template <typename Target>
 class LLVM_LIBRARY_VISIBILITY PSPTargetInfo : public OSTargetInfo<Target> {

clang/lib/Basic/Targets/RISCV.h

 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
   RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : RISCVTargetInfo(Triple, Opts) {
     IntPtrType = SignedInt;
     PtrDiffType = SignedInt;
     SizeType = UnsignedInt;
-    resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
+    resetDataLayout((Twine(Triple.isLittleEndian() ? "e" : "E") +
+      "-m:e-p:32:32-i64:64-n32-S128").str());
   }
 
   bool setABI(const std::string &Name) override {
     if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
       ABI = Name;
       return true;
     }
     return false;
   }
public:
   }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
 public:
   RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : RISCVTargetInfo(Triple, Opts) {
     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
     IntMaxType = Int64Type = SignedLong;
-    resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128");
+    resetDataLayout((Twine(Triple.isLittleEndian() ? "e" : "E") +
+      "-m:e-p:64:64-i64:64-i128:128-n64-S128").str());
   }
 
   bool setABI(const std::string &Name) override {
     if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
       ABI = Name;
       return true;
     }
     return false;
   }

clang/lib/Basic/Targets/RISCV.cpp

default:
     break;
   }
   return R;
 }
 
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
-  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
-  Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
+  Builder.defineMacro("__riscv_xlen", getTriple().isRISCV64() ? "64" : "32");
   StringRef CodeModel = getTargetOpts().CodeModel;
   unsigned FLen = ISAInfo->getFLen();
   unsigned MinVLen = ISAInfo->getMinVLen();
   unsigned MaxELen = ISAInfo->getMaxELen();
   unsigned MaxELenFp = ISAInfo->getMaxELenFp();
   if (CodeModel == "default")
     CodeModel = "small";
 
if (ISAInfo->hasExtension("m")) {
     Builder.defineMacro("__riscv_muldiv");
   }
 
   if (ISAInfo->hasExtension("a")) {
     Builder.defineMacro("__riscv_atomic");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-    if (Is64Bit)
+    if (getTriple().isRISCV64())
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
 
   if (FLen) {
     Builder.defineMacro("__riscv_flen", Twine(FLen));
     Builder.defineMacro("__riscv_fdiv");
     Builder.defineMacro("__riscv_fsqrt");
   }

 }
 
 bool RISCVTargetInfo::initFeatureMap(
     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
     const std::vector<std::string> &FeaturesVec) const {
 
   unsigned XLen = 32;
 
-  if (getTriple().getArch() == llvm::Triple::riscv64) {
+  if (getTriple().isRISCV64()) {
     Features["64bit"] = true;
     XLen = 64;
   }
 
   auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
   if (!ParseResult) {
     std::string Buffer;
     llvm::raw_string_ostream OutputErrMsg(Buffer);
for (const std::string &Feature : FeaturesVec)
     if (!llvm::is_contained(ImpliedFeatures, Feature))
       ImpliedFeatures.push_back(Feature);
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
-  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+  bool Is64Bit = getTriple().isRISCV64();
   auto Result = llvm::StringSwitch<Optional<bool>>(Feature)
                     .Case("riscv", true)
                     .Case("riscv32", !Is64Bit)
                     .Case("riscv64", Is64Bit)
                     .Case("64bit", Is64Bit)
                     .Default(None);
   if (Result)
     return Result.getValue();

clang/lib/CodeGen/CGBuiltin.cpp

case llvm::Triple::nvptx64:
     return CGF->EmitNVPTXBuiltinExpr(BuiltinID, E);
   case llvm::Triple::wasm32:
   case llvm::Triple::wasm64:
     return CGF->EmitWebAssemblyBuiltinExpr(BuiltinID, E);
   case llvm::Triple::hexagon:
     return CGF->EmitHexagonBuiltinExpr(BuiltinID, E);
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue);
   default:
     return nullptr;
   }
 }
 
 Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID,
                                               const CallExpr *E,

clang/lib/CodeGen/CodeGenModule.cpp

if (   Arch == llvm::Triple::arm
       || Arch == llvm::Triple::armeb
       || Arch == llvm::Triple::thumb
       || Arch == llvm::Triple::thumbeb) {
     // The minimum width of an enum in bytes
     uint64_t EnumWidth = Context.getLangOpts().ShortEnums ? 1 : 4;
     getModule().addModuleFlag(llvm::Module::Error, "min_enum_size", EnumWidth);
   }
 
-  if (Arch == llvm::Triple::riscv32 || Arch == llvm::Triple::riscv64) {
+  if (Arch == llvm::Triple::riscv32 || Arch == llvm::Triple::riscv64 ||
+      Arch == llvm::Triple::riscv32be || Arch == llvm::Triple::riscv64be) {
     StringRef ABIStr = Target.getABI();
     llvm::LLVMContext &Ctx = TheModule.getContext();
     getModule().addModuleFlag(llvm::Module::Error, "target-abi",
                               llvm::MDString::get(Ctx, ABIStr));
   }
 
   if (CodeGenOpts.SanitizeCfiCrossDso) {
     // Indicate that we want cross-DSO control flow integrity checks.

 
 void CodeGenModule::EmitBackendOptionsMetadata(
     const CodeGenOptions CodeGenOpts) {
   switch (getTriple().getArch()) {
   default:
     break;
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     getModule().addModuleFlag(llvm::Module::Error, "SmallDataLimit",
                               CodeGenOpts.SmallDataLimit);
     break;
   }
 }
 
 void CodeGenModule::UpdateCompletedType(const TagDecl *TD) {
   // Make sure that this type is translated.

clang/lib/CodeGen/TargetInfo.cpp

const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
   case llvm::Triple::nvptx:
   case llvm::Triple::nvptx64:
     return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
 
   case llvm::Triple::msp430:
     return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
 
   case llvm::Triple::riscv32:
-  case llvm::Triple::riscv64: {
+  case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be: {
     StringRef ABIStr = getTarget().getABI();
     unsigned XLen = getTarget().getPointerWidth(0);
     unsigned ABIFLen = 0;
     if (ABIStr.endswith("f"))
       ABIFLen = 32;
     else if (ABIStr.endswith("d"))
       ABIFLen = 64;
     return SetCGInfo(new RISCVTargetCodeGenInfo(Types, XLen, ABIFLen));

clang/lib/Driver/Driver.cpp

if (A && Target.isMIPS()) {
     }
   }
 
   // If target is RISC-V adjust the target triple according to
   // provided architecture name
   A = Args.getLastArg(options::OPT_march_EQ);
   if (A && Target.isRISCV()) {
     StringRef ArchName = A->getValue();
-    if (ArchName.startswith_insensitive("rv32"))
+    if (ArchName.startswith_insensitive("rv32")) {
+      if (Target.isLittleEndian())
         Target.setArch(llvm::Triple::riscv32);
-    else if (ArchName.startswith_insensitive("rv64"))
+      else
+        Target.setArch(llvm::Triple::riscv32be);
+    } else if (ArchName.startswith_insensitive("rv64")) {
+      if (Target.isLittleEndian())
         Target.setArch(llvm::Triple::riscv64);
+      else
+        Target.setArch(llvm::Triple::riscv64be);
+    }
   }
 
   return Target;
 }
 
 // Parse the LTO options and record the type of LTO compilation
 // based on which -f(no-)?lto(=.*)? or -f(no-)?offload-lto(=.*)?
 // option occurs last.
default:
         TC = std::make_unique<toolchains::AVRToolChain>(*this, Target, Args);
         break;
       case llvm::Triple::msp430:
         TC =
             std::make_unique<toolchains::MSP430ToolChain>(*this, Target, Args);
         break;
       case llvm::Triple::riscv32:
       case llvm::Triple::riscv64:
+      case llvm::Triple::riscv32be:
+      case llvm::Triple::riscv64be:
         if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
           TC =
               std::make_unique<toolchains::RISCVToolChain>(*this, Target, Args);
         else
           TC = std::make_unique<toolchains::BareMetal>(*this, Target, Args);
         break;
       case llvm::Triple::ve:
         TC = std::make_unique<toolchains::VEToolChain>(*this, Target, Args);

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

static bool getArchFeatures(const Driver &D, StringRef Arch,
   return true;
 }
 
 // Get features except standard extension feature
 static void getRISCFeaturesFromMcpu(const Driver &D, const llvm::Triple &Triple,
                                     const llvm::opt::ArgList &Args,
                                     const llvm::opt::Arg *A, StringRef Mcpu,
                                     std::vector<StringRef> &Features) {
-  bool Is64Bit = (Triple.getArch() == llvm::Triple::riscv64);
+  bool Is64Bit = (Triple.getArch() == llvm::Triple::riscv64 ||
+                  Triple.getArch() == llvm::Triple::riscv64be);
   llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
   if (!llvm::RISCV::checkCPUKind(CPUKind, Is64Bit) ||
       !llvm::RISCV::getCPUFeaturesExceptStdExt(CPUKind, Features)) {
     D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
   }
 }
 
 void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group);
 }
 
 StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   assert((Triple.getArch() == llvm::Triple::riscv32 ||
-          Triple.getArch() == llvm::Triple::riscv64) &&
+          Triple.getArch() == llvm::Triple::riscv64 ||
+          Triple.getArch() == llvm::Triple::riscv32be ||
+          Triple.getArch() == llvm::Triple::riscv64be) &&
          "Unexpected triple");
 
   // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
   // configured using `--with-abi=`, then the logic for the default choice is
   // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
   //
   // The logic used in GCC 9.2.0 is the following, in order:
   // 1. Explicit choices using `--with-abi=`
StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   else
     return (*ParseResult)->computeDefaultABI();
 
   // 3. Choose a default based on the triple
   //
   // We deviate from GCC's defaults here:
   // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
   // - On all other OSs we use the double floating point calling convention.
-  if (Triple.getArch() == llvm::Triple::riscv32) {
+  if (Triple.getArch() == llvm::Triple::riscv32 ||
+      Triple.getArch() == llvm::Triple::riscv32be) {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
       return "ilp32";
     else
       return "ilp32d";
   } else {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
       return "lp64";
     else
       return "lp64d";
   }
 }
 
 StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
                               const llvm::Triple &Triple) {
   assert((Triple.getArch() == llvm::Triple::riscv32 ||
-          Triple.getArch() == llvm::Triple::riscv64) &&
+          Triple.getArch() == llvm::Triple::riscv64 ||
+          Triple.getArch() == llvm::Triple::riscv32be ||
+          Triple.getArch() == llvm::Triple::riscv64be) &&
          "Unexpected triple");
 
   // GCC's logic around choosing a default `-march=` is complex. If GCC is not
   // configured using `--with-arch=`, then the logic for the default choice is
   // defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
   // deviate from GCC's default on additional `-mcpu` option (GCC does not
   // support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
   // nor `-mabi` is specified.
else if (MABI.startswith_insensitive("lp64"))
       return "rv64imafdc";
   }
 
   // 4. Choose a default based on the triple
   //
   // We deviate from GCC's defaults here:
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
-  if (Triple.getArch() == llvm::Triple::riscv32) {
+  if (Triple.getArch() == llvm::Triple::riscv32 ||
+      Triple.getArch() == llvm::Triple::riscv32be) {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
       return "rv32imac";
     else
       return "rv32imafdc";
   } else {
     if (Triple.getOS() == llvm::Triple::UnknownOS)
       return "rv64imac";
     else
       return "rv64imafdc";
   }
 }

clang/lib/Driver/ToolChains/BareMetal.cpp

 
 static bool findRISCVMultilibs(const Driver &D,
                                const llvm::Triple &TargetTriple,
                                const ArgList &Args, DetectedMultilibs &Result) {
   Multilib::flags_list Flags;
   StringRef Arch = riscv::getRISCVArch(Args, TargetTriple);
   StringRef Abi = tools::riscv::getRISCVABI(Args, TargetTriple);
 
-  if (TargetTriple.getArch() == llvm::Triple::riscv64) {
+  if (TargetTriple.getArch() == llvm::Triple::riscv64 ||
+      TargetTriple.getArch() == llvm::Triple::riscv64be) {
     Multilib Imac = makeMultilib("").flag("+march=rv64imac").flag("+mabi=lp64");
     Multilib Imafdc = makeMultilib("/rv64imafdc/lp64d")
                           .flag("+march=rv64imafdc")
                           .flag("+mabi=lp64d");
 
     // Multilib reuse
     bool UseImafdc =
         (Arch == "rv64imafdc") || (Arch == "rv64gc"); // gc => imafdc
 
     addMultilibFlag((Arch == "rv64imac"), "march=rv64imac", Flags);
     addMultilibFlag(UseImafdc, "march=rv64imafdc", Flags);
     addMultilibFlag(Abi == "lp64", "mabi=lp64", Flags);
     addMultilibFlag(Abi == "lp64d", "mabi=lp64d", Flags);
 
     Result.Multilibs = MultilibSet().Either(Imac, Imafdc);
     return Result.Multilibs.select(Flags, Result.SelectedMultilib);
   }
-  if (TargetTriple.getArch() == llvm::Triple::riscv32) {
+  if (TargetTriple.getArch() == llvm::Triple::riscv32 ||
+      TargetTriple.getArch() == llvm::Triple::riscv32be) {
     Multilib Imac =
         makeMultilib("").flag("+march=rv32imac").flag("+mabi=ilp32");
     Multilib I =
         makeMultilib("/rv32i/ilp32").flag("+march=rv32i").flag("+mabi=ilp32");
     Multilib Im =
         makeMultilib("/rv32im/ilp32").flag("+march=rv32im").flag("+mabi=ilp32");
     Multilib Iac = makeMultilib("/rv32iac/ilp32")
                        .flag("+march=rv32iac")
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
   if (Triple.getOS() != llvm::Triple::UnknownOS)
     return false;
 
   return Triple.getEnvironmentName() == "elf";
 }
 
 static bool isRISCVBareMetal(const llvm::Triple &Triple) {
   if (Triple.getArch() != llvm::Triple::riscv32 &&
-      Triple.getArch() != llvm::Triple::riscv64)
+      Triple.getArch() != llvm::Triple::riscv64 &&
+      Triple.getArch() != llvm::Triple::riscv32be &&
+      Triple.getArch() != llvm::Triple::riscv64be)
     return false;
 
   if (Triple.getVendor() != llvm::Triple::UnknownVendor)
     return false;
 
   if (Triple.getOS() != llvm::Triple::UnknownOS)
     return false;
 

clang/lib/Driver/ToolChains/Clang.cpp

static void getTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   case llvm::Triple::ppc:
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
     ppc::getPPCTargetFeatures(D, Triple, Args, Features);
     break;
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     riscv::getRISCVTargetFeatures(D, Triple, Args, Features);
     break;
   case llvm::Triple::systemz:
     systemz::getSystemZTargetFeatures(D, Args, Features);
     break;
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
   case llvm::Triple::aarch64_be:
case llvm::Triple::msp430:
     // WebAssembly never wants frame pointers.
     return false;
   case llvm::Triple::ppc:
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
   case llvm::Triple::amdgcn:
   case llvm::Triple::r600:
   case llvm::Triple::csky:
     return !areOptimizationsEnabled(Args);
   default:
     break;
   }
 
if (Triple.isOSDarwin())
       return true;
     return false;
 
   case llvm::Triple::hexagon:
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
   case llvm::Triple::systemz:
   case llvm::Triple::xcore:
     return false;
   }
 }
 
 static bool hasMultipleInvocations(const llvm::Triple &Triple,
                                    const ArgList &Args) {
void Clang::RenderTargetOptions(const llvm::Triple &EffectiveTriple,
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
     AddPPCTargetArgs(Args, CmdArgs);
     break;
 
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     AddRISCVTargetArgs(Args, CmdArgs);
     break;
 
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
   case llvm::Triple::sparcv9:
     AddSparcTargetArgs(Args, CmdArgs);
     break;
if (Args.getLastArg(options::OPT_shared, options::OPT_fpic,
                       options::OPT_fPIC)) {
     // Not support linker relaxation for PIC.
     SmallDataLimit = "0";
     if (Args.hasArg(options::OPT_G)) {
       D.Diag(diag::warn_drv_unsupported_sdata);
     }
   } else if (Args.getLastArgValue(options::OPT_mcmodel_EQ)
                  .equals_insensitive("large") &&
-             (Triple.getArch() == llvm::Triple::riscv64)) {
+             (Triple.getArch() == llvm::Triple::riscv64 ||
+              Triple.getArch() == llvm::Triple::riscv64be)) {
     // Not support linker relaxation for RV64 with large code model.
     SmallDataLimit = "0";
     if (Args.hasArg(options::OPT_G)) {
       D.Diag(diag::warn_drv_unsupported_sdata);
     }
   } else if (Arg *A = Args.getLastArg(options::OPT_G)) {
     SmallDataLimit = A->getValue();
   }
case llvm::Triple::aarch64_be:
     if (Args.hasArg(options::OPT_mmark_bti_property)) {
       CmdArgs.push_back("-mllvm");
       CmdArgs.push_back("-aarch64-mark-bti-property");
     }
     break;
 
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     AddRISCVTargetArgs(Args, CmdArgs);
     break;
   }
 
   // Consume all the warning flags. Usually this would be handled more
   // gracefully by -cc1 (warning about unknown warning flags, etc) but -cc1as
   // doesn't handle that so rather than warning about unused flags that are
   // actually used, we'll lie by omission instead.

clang/lib/Driver/ToolChains/CommonArgs.cpp

case llvm::Triple::csky:
     if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
       return A->getValue();
     else if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
       return A->getValue();
     else
       return "ck810";
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
       return A->getValue();
     return "";
 
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:

clang/lib/Driver/ToolChains/FreeBSD.cpp

case llvm::Triple::riscv32:
     CmdArgs.push_back("elf32lriscv");
     CmdArgs.push_back("-X");
     break;
   case llvm::Triple::riscv64:
     CmdArgs.push_back("-m");
     CmdArgs.push_back("elf64lriscv");
     CmdArgs.push_back("-X");
     break;
+  case llvm::Triple::riscv32be:
+    CmdArgs.push_back("-m");
+    CmdArgs.push_back("elf32briscv");
+    CmdArgs.push_back("-X");
+    break;
+  case llvm::Triple::riscv64be:
+    CmdArgs.push_back("-m");
+    CmdArgs.push_back("elf64briscv");
+    CmdArgs.push_back("-X");
+    break;
   default:
     break;
   }
 
   if (Arg *A = Args.getLastArg(options::OPT_G)) {
     if (ToolChain.getTriple().isMIPS()) {
       StringRef v = A->getValue();
       CmdArgs.push_back(Args.MakeArgString("-G" + v));

clang/lib/Driver/ToolChains/Gnu.cpp

static const char *getLDMOption(const llvm::Triple &T, const ArgList &Args) {
   case llvm::Triple::ppc64:
     return "elf64ppc";
   case llvm::Triple::ppc64le:
     return "elf64lppc";
   case llvm::Triple::riscv32:
     return "elf32lriscv";
   case llvm::Triple::riscv64:
     return "elf64lriscv";
+  case llvm::Triple::riscv32be:
+    return "elf32briscv";
+  case llvm::Triple::riscv64be:
+    return "elf64briscv";
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
     return "elf32_sparc";
   case llvm::Triple::sparcv9:
     return "elf64_sparc";
   case llvm::Triple::mips:
     return "elf32btsmip";
   case llvm::Triple::mipsel:
case llvm::Triple::ppc64le: {
     CmdArgs.push_back("-a64");
     CmdArgs.push_back("-mppc64");
     CmdArgs.push_back("-mlittle-endian");
     CmdArgs.push_back(ppc::getPPCAsmModeForCPU(
         getCPUName(D, Args, getToolChain().getTriple())));
     break;
   }
   case llvm::Triple::riscv32:
-  case llvm::Triple::riscv64: {
+  case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be: {
     StringRef ABIName = riscv::getRISCVABI(Args, getToolChain().getTriple());
     CmdArgs.push_back("-mabi");
     CmdArgs.push_back(ABIName.data());
     StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
     CmdArgs.push_back("-march");
     CmdArgs.push_back(MArchName.data());
     if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
       Args.addOptOutFlag(CmdArgs, options::OPT_mrelax, options::OPT_mno_relax);
static void findRISCVBareMetalMultilibs(const Driver &D,
   std::vector<Multilib> Ms;
   for (auto Element : RISCVMultilibSet) {
     // multilib path rule is ${march}/${mabi}
     Ms.emplace_back(
         makeMultilib((Twine(Element.march) + "/" + Twine(Element.mabi)).str())
             .flag(Twine("+march=", Element.march).str())
             .flag(Twine("+mabi=", Element.mabi).str()));
   }
+
+  std::string EndiannessSuffix = TargetTriple.isLittleEndian() ? "" : "be";
   MultilibSet RISCVMultilibs =
       MultilibSet()
           .Either(ArrayRef<Multilib>(Ms))
           .FilterOut(NonExistent)
-          .setFilePathsCallback([](const Multilib &M) {
+          .setFilePathsCallback([EndiannessSuffix](const Multilib &M) {
             return std::vector<std::string>(
                 {M.gccSuffix(),
-                 "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix(),
-                 "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()});
+                 "/../../../../riscv64" + EndiannessSuffix +
+                   "-unknown-elf/lib" + M.gccSuffix(),
+                 "/../../../../riscv32" + EndiannessSuffix +
+                   "-unknown-elf/lib" + M.gccSuffix()});
           });
 
-
   Multilib::flags_list Flags;
   llvm::StringSet<> Added_ABIs;
   StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
   StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
   for (auto Element : RISCVMultilibSet) {
     addMultilibFlag(MArch == Element.march,
                     Twine("march=", Element.march).str().c_str(), Flags);
     if (!Added_ABIs.count(Element.mabi)) {
static void findRISCVMultilibs(const Driver &D,
   Multilib Lp64f = makeMultilib("lib64/lp64f").flag("+m64").flag("+mabi=lp64f");
   Multilib Lp64d = makeMultilib("lib64/lp64d").flag("+m64").flag("+mabi=lp64d");
   MultilibSet RISCVMultilibs =
       MultilibSet()
           .Either({Ilp32, Ilp32f, Ilp32d, Lp64, Lp64f, Lp64d})
           .FilterOut(NonExistent);
 
   Multilib::flags_list Flags;
-  bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64;
+  bool IsRV64 = (TargetTriple.getArch() == llvm::Triple::riscv64 ||
+                 TargetTriple.getArch() == llvm::Triple::riscv64be);
   StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
 
   addMultilibFlag(!IsRV64, "m32", Flags);
   addMultilibFlag(IsRV64, "m64", Flags);
   addMultilibFlag(ABIName == "ilp32", "mabi=ilp32", Flags);
   addMultilibFlag(ABIName == "ilp32f", "mabi=ilp32f", Flags);
   addMultilibFlag(ABIName == "ilp32d", "mabi=ilp32d", Flags);
   addMultilibFlag(ABIName == "lp64", "mabi=lp64", Flags);
/*static*/ void Generic_GCC::GCCInstallationDetector::CollectLibDirsAndTriples(
   static const char *const RISCV32LibDirs[] = {"/lib32", "/lib"};
   static const char *const RISCV32Triples[] = {"riscv32-unknown-linux-gnu",
                                                "riscv32-linux-gnu",
                                                "riscv32-unknown-elf"};
   static const char *const RISCV64LibDirs[] = {"/lib64", "/lib"};
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
                                                "riscv64-linux-gnu",
                                                "riscv64-unknown-elf"};
+  static const char *const RISCV32beLibDirs[] = {"/lib32", "/lib"};
+  static const char *const RISCV32beTriples[] = {"riscv32be-unknown-linux-gnu",
+                                                 "riscv32be-linux-gnu",
+                                                 "riscv32be-unknown-elf"};
+  static const char *const RISCV64beLibDirs[] = {"/lib64", "/lib"};
+  static const char *const RISCV64beTriples[] = {"riscv64be-unknown-linux-gnu",
+                                                 "riscv64be-linux-gnu",
+                                                 "riscv64be-unknown-elf"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};
   static const char *const SPARCv8Triples[] = {"sparc-linux-gnu",
                                                "sparcv8-linux-gnu"};
   static const char *const SPARCv9LibDirs[] = {"/lib64", "/lib"};
   static const char *const SPARCv9Triples[] = {"sparc64-linux-gnu",
                                                "sparcv9-linux-gnu"};
 
case llvm::Triple::riscv32:
     BiarchTripleAliases.append(begin(RISCV64Triples), end(RISCV64Triples));
     break;
   case llvm::Triple::riscv64:
     LibDirs.append(begin(RISCV64LibDirs), end(RISCV64LibDirs));
     TripleAliases.append(begin(RISCV64Triples), end(RISCV64Triples));
     BiarchLibDirs.append(begin(RISCV32LibDirs), end(RISCV32LibDirs));
     BiarchTripleAliases.append(begin(RISCV32Triples), end(RISCV32Triples));
     break;
+  case llvm::Triple::riscv32be:
+    LibDirs.append(begin(RISCV32beLibDirs), end(RISCV32beLibDirs));
+    TripleAliases.append(begin(RISCV32beTriples), end(RISCV32beTriples));
+    BiarchLibDirs.append(begin(RISCV64beLibDirs), end(RISCV64beLibDirs));
+    BiarchTripleAliases.append(begin(RISCV64beTriples), end(RISCV64beTriples));
+    break;
+  case llvm::Triple::riscv64be:
+    LibDirs.append(begin(RISCV64beLibDirs), end(RISCV64beLibDirs));
+    TripleAliases.append(begin(RISCV64beTriples), end(RISCV64beTriples));
+    BiarchLibDirs.append(begin(RISCV32beLibDirs), end(RISCV32beLibDirs));
+    BiarchTripleAliases.append(begin(RISCV32beTriples), end(RISCV32beTriples));
+    break;
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
     LibDirs.append(begin(SPARCv8LibDirs), end(SPARCv8LibDirs));
     TripleAliases.append(begin(SPARCv8Triples), end(SPARCv8Triples));
     BiarchLibDirs.append(begin(SPARCv9LibDirs), end(SPARCv9LibDirs));
     BiarchTripleAliases.append(begin(SPARCv9Triples), end(SPARCv9Triples));
     break;
   case llvm::Triple::sparcv9:
bool Generic_GCC::IsIntegratedAssemblerDefault() const {
   case llvm::Triple::mips64el:
   case llvm::Triple::msp430:
   case llvm::Triple::ppc:
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
   case llvm::Triple::sparcv9:
   case llvm::Triple::systemz:
   case llvm::Triple::thumb:
   case llvm::Triple::thumbeb:
   case llvm::Triple::ve:
   case llvm::Triple::x86:

clang/lib/Driver/ToolChains/Linux.cpp

static StringRef getOSLibDir(const llvm::Triple &Triple, const ArgList &Args) {
   // GCCInstallationDetector, but that is a more significant refactoring.
   if (Triple.getArch() == llvm::Triple::x86 || Triple.isPPC32() ||
       Triple.getArch() == llvm::Triple::sparc)
     return "lib32";
 
   if (Triple.getArch() == llvm::Triple::x86_64 && Triple.isX32())
     return "libx32";
 
-  if (Triple.getArch() == llvm::Triple::riscv32)
+  if (Triple.getArch() == llvm::Triple::riscv32 ||
+      Triple.getArch() == llvm::Triple::riscv32be)
     return "lib32";
 
   return Triple.isArch32Bit() ? "lib" : "lib64";
 }
 
 Linux::Linux(const Driver &D, const llvm::Triple &Triple, const ArgList &Args)
     : Generic_ELF(D, Triple, Args) {
   GCCInstallation.init(Triple, Args);
case llvm::Triple::riscv32: {
     break;
   }
   case llvm::Triple::riscv64: {
     StringRef ABIName = tools::riscv::getRISCVABI(Args, Triple);
     LibDir = "lib";
     Loader = ("ld-linux-riscv64-" + ABIName + ".so.1").str();
     break;
   }
+  case llvm::Triple::riscv32be: {
+    StringRef ABIName = tools::riscv::getRISCVABI(Args, Triple);
+    LibDir = "lib";
+    Loader = ("ld-linux-riscv32be-" + ABIName + ".so.1").str();
+    break;
+  }
+  case llvm::Triple::riscv64be: {
+    StringRef ABIName = tools::riscv::getRISCVABI(Args, Triple);
+    LibDir = "lib";
+    Loader = ("ld-linux-riscv64be-" + ABIName + ".so.1").str();
+    break;
+  }
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
     LibDir = "lib";
     Loader = "ld-linux.so.2";
     break;
   case llvm::Triple::sparcv9:
     LibDir = "lib64";
     Loader = "ld-linux.so.2";
SanitizerMask Linux::getSupportedSanitizers() const {
   const bool IsPowerPC64 = getTriple().getArch() == llvm::Triple::ppc64 ||
                            getTriple().getArch() == llvm::Triple::ppc64le;
   const bool IsAArch64 = getTriple().getArch() == llvm::Triple::aarch64 ||
                          getTriple().getArch() == llvm::Triple::aarch64_be;
   const bool IsArmArch = getTriple().getArch() == llvm::Triple::arm ||
                          getTriple().getArch() == llvm::Triple::thumb ||
                          getTriple().getArch() == llvm::Triple::armeb ||
                          getTriple().getArch() == llvm::Triple::thumbeb;
-  const bool IsRISCV64 = getTriple().getArch() == llvm::Triple::riscv64;
+  const bool IsRISCV64 = (getTriple().getArch() == llvm::Triple::riscv64 ||
+                          getTriple().getArch() == llvm::Triple::riscv64be);
   const bool IsSystemZ = getTriple().getArch() == llvm::Triple::systemz;
   const bool IsHexagon = getTriple().getArch() == llvm::Triple::hexagon;
   SanitizerMask Res = ToolChain::getSupportedSanitizers();
   Res |= SanitizerKind::Address;
   Res |= SanitizerKind::PointerCompare;
   Res |= SanitizerKind::PointerSubtract;
   Res |= SanitizerKind::Fuzzer;
   Res |= SanitizerKind::FuzzerNoLink;

clang/lib/Driver/ToolChains/RISCVToolchain.cpp

void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA,
                                  const char *LinkingOutput) const {
   const ToolChain &ToolChain = getToolChain();
   const Driver &D = ToolChain.getDriver();
   ArgStringList CmdArgs;
 
   if (!D.SysRoot.empty())
     CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
 
-  bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64;
   CmdArgs.push_back("-m");
-  if (IsRV64) {
+  if (ToolChain.getArch() == llvm::Triple::riscv64) {
     CmdArgs.push_back("elf64lriscv");
-  } else {
+  } else if (ToolChain.getArch() == llvm::Triple::riscv64be) {
+    CmdArgs.push_back("elf64briscv");
+  } else if (ToolChain.getArch() == llvm::Triple::riscv32) {
     CmdArgs.push_back("elf32lriscv");
+  } else { // llvm::Triple::riscv32be
+    CmdArgs.push_back("elf32briscv");
   }
   CmdArgs.push_back("-X");
 
   std::string Linker = getToolChain().GetLinkerPath();
 
   bool WantCRTs =
       !Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles);
 

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckTSBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
     return CheckPPCBuiltinFunctionCall(TI, BuiltinID, TheCall);
   case llvm::Triple::amdgcn:
     return CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall);
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     return CheckRISCVBuiltinFunctionCall(TI, BuiltinID, TheCall);
   }
 }
 
 ExprResult
 Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
                                CallExpr *TheCall) {
   ExprResult TheCallResult(TheCall);
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
   // message.
   bool FeatureMissing = false;
   SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
   Features.split(ReqFeatures, ',');
 
   // Check for 32-bit only builtins on a 64-bit target.
   const llvm::Triple &TT = TI.getTriple();
-  if (TT.getArch() != llvm::Triple::riscv32 && isRISCV32Builtin(BuiltinID))
+  if (TT.getArch() != llvm::Triple::riscv32 &&
+      TT.getArch() != llvm::Triple::riscv32be &&
+      isRISCV32Builtin(BuiltinID))
     return Diag(TheCall->getCallee()->getBeginLoc(),
                 diag::err_32_bit_builtin_64_bit_tgt);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
     SmallVector<StringRef> ReqOpFeatures;
     F.split(ReqOpFeatures, '|');
     bool HasFeature = false;

clang/lib/Sema/SemaDeclAttr.cpp

static void handleInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   case llvm::Triple::x86_64:
     handleAnyX86InterruptAttr(S, D, AL);
     break;
   case llvm::Triple::avr:
     handleAVRInterruptAttr(S, D, AL);
     break;
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv32be:
+  case llvm::Triple::riscv64be:
     handleRISCVInterruptAttr(S, D, AL);
     break;
   default:
     handleARMInterruptAttr(S, D, AL);
     break;
   }
 }
 

llvm/cmake/config.guess

EOF
   echo powerpc64le-unknown-linux-gnu
   exit ;;
     ppc:Linux:*:*)
   echo powerpc-unknown-linux-gnu
   exit ;;
     ppcle:Linux:*:*)
   echo powerpcle-unknown-linux-gnu
   exit ;;
-    riscv32:Linux:*:* | riscv64:Linux:*:*)
+    riscv32:Linux:*:* | riscv64:Linux:*:* | riscv32be:Linux:*:* | riscv64be:Linux:*:*)
   LIBC=gnu
   eval $set_cc_for_build
   # Do not check for __GLIBC__ because uclibc defines it too
   sed 's/^ //' << EOF >$dummy.c
   #include <features.h>
   #if defined(__UCLIBC__)
   LIBC=uclibc
   #elif defined(__dietlibc__)

llvm/include/llvm/ADT/Triple.h

enum ArchType {
     ppc,            // PPC: powerpc
     ppcle,          // PPCLE: powerpc (little endian)
     ppc64,          // PPC64: powerpc64, ppu
     ppc64le,        // PPC64LE: powerpc64le
     r600,           // R600: AMD GPUs HD2XXX - HD6XXX
     amdgcn,         // AMDGCN: AMD GCN GPUs
     riscv32,        // RISC-V (32-bit): riscv32
     riscv64,        // RISC-V (64-bit): riscv64
+    riscv32be,      // RISC-V (32-bit, big endian): riscv32be
+    riscv64be,      // RISC-V (64-bit, big endian): riscv64be
     sparc,          // Sparc: sparc
     sparcv9,        // Sparcv9: Sparcv9
     sparcel,        // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
     systemz,        // SystemZ: s390x
     tce,            // TCE (http://tce.cs.tut.fi/): tce
     tcele,          // TCE little endian (http://tce.cs.tut.fi/): tcele
     thumb,          // Thumb (little endian): thumb, thumbv.*
     thumbeb,        // Thumb (big endian): thumbeb
bool isPPC32() const {
     return getArch() == Triple::ppc || getArch() == Triple::ppcle;
   }
 
   /// Tests whether the target is 64-bit PowerPC (little and big endian).
   bool isPPC64() const {
     return getArch() == Triple::ppc64 || getArch() == Triple::ppc64le;
   }
 
-  /// Tests whether the target is RISC-V (32- and 64-bit).
+  /// Tests whether the target is RISC-V (32- and 64-bit LE or BE).
   bool isRISCV() const {
-    return getArch() == Triple::riscv32 || getArch() == Triple::riscv64;
+    return getArch() == Triple::riscv32 || getArch() == Triple::riscv64 ||
+           getArch() == Triple::riscv32be || getArch() == Triple::riscv64be;
+  }
+
+  /// Tests whether the target is a 32-bit RISC-V (LE or BE).
+  bool isRISCV32() const {
+    return getArch() == Triple::riscv32 || getArch() == Triple::riscv32be;
+  }
+
+  /// Tests whether the target is a 64-bit RISC-V (LE or BE).
+  bool isRISCV64() const {
+    return getArch() == Triple::riscv64 || getArch() == Triple::riscv64be;
   }
 
   /// Tests whether the target is 32-bit SPARC (little and big endian).
   bool isSPARC32() const {
     return getArch() == Triple::sparc || getArch() == Triple::sparcel;
   }
 
   /// Tests whether the target is 64-bit SPARC (big endian).

llvm/include/llvm/Object/ELFObjectFile.h

case ELF::EM_LANAI:
       return "elf32-lanai";
     case ELF::EM_MIPS:
       return "elf32-mips";
     case ELF::EM_MSP430:
       return "elf32-msp430";
     case ELF::EM_PPC:
       return (IsLittleEndian ? "elf32-powerpcle" : "elf32-powerpc");
     case ELF::EM_RISCV:
-      return "elf32-littleriscv";
+      return (IsLittleEndian ? "elf32-littleriscv" : "elf32-bigriscv");
     case ELF::EM_CSKY:
       return "elf32-csky";
     case ELF::EM_SPARC:
     case ELF::EM_SPARC32PLUS:
       return "elf32-sparc";
     case ELF::EM_AMDGPU:
       return "elf32-amdgpu";
     case ELF::EM_LOONGARCH:
       return "elf32-loongarch";
     default:
       return "elf32-unknown";
     }
   case ELF::ELFCLASS64:
     switch (EF.getHeader().e_machine) {
     case ELF::EM_386:
       return "elf64-i386";
     case ELF::EM_X86_64:
       return "elf64-x86-64";
     case ELF::EM_AARCH64:
       return (IsLittleEndian ? "elf64-littleaarch64" : "elf64-bigaarch64");
     case ELF::EM_PPC64:
       return (IsLittleEndian ? "elf64-powerpcle" : "elf64-powerpc");
     case ELF::EM_RISCV:
-      return "elf64-littleriscv";
+      return (IsLittleEndian ? "elf64-littleriscv" : "elf64-bigriscv");
     case ELF::EM_S390:
       return "elf64-s390";
     case ELF::EM_SPARCV9:
       return "elf64-sparc";
     case ELF::EM_MIPS:
       return "elf64-mips";
     case ELF::EM_AMDGPU:
       return "elf64-amdgpu";
case ELF::EM_MSP430:
     return Triple::msp430;
   case ELF::EM_PPC:
     return IsLittleEndian ? Triple::ppcle : Triple::ppc;
   case ELF::EM_PPC64:
     return IsLittleEndian ? Triple::ppc64le : Triple::ppc64;
   case ELF::EM_RISCV:
     switch (EF.getHeader().e_ident[ELF::EI_CLASS]) {
     case ELF::ELFCLASS32:
-      return Triple::riscv32;
+      return IsLittleEndian ? Triple::riscv32 : Triple::riscv32be;
     case ELF::ELFCLASS64:
-      return Triple::riscv64;
+      return IsLittleEndian ? Triple::riscv64 : Triple::riscv64be;
     default:
       report_fatal_error("Invalid ELFCLASS!");
     }
   case ELF::EM_S390:
     return Triple::systemz;
 
   case ELF::EM_SPARC:
   case ELF::EM_SPARC32PLUS:

llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

if (isPositionIndependent()) {
       LSDAEncoding = dwarf::DW_EH_PE_absptr;
       PersonalityEncoding = dwarf::DW_EH_PE_absptr;
       TTypeEncoding = dwarf::DW_EH_PE_absptr;
     }
     CallSiteEncoding = dwarf::DW_EH_PE_udata4;
     break;
   case Triple::riscv32:
   case Triple::riscv64:
+  case Triple::riscv32be:
+  case Triple::riscv64be:
     LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
     PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
                           dwarf::DW_EH_PE_sdata4;
     TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
                     dwarf::DW_EH_PE_sdata4;
     CallSiteEncoding = dwarf::DW_EH_PE_udata4;
     break;
   case Triple::sparcv9:

llvm/lib/Object/RelocationResolver.cpp

if (Obj.getBytesInAddress() == 8) {
         return {supportsPPC64, resolvePPC64};
       case Triple::systemz:
         return {supportsSystemZ, resolveSystemZ};
       case Triple::sparcv9:
         return {supportsSparc64, resolveSparc64};
       case Triple::amdgcn:
         return {supportsAmdgpu, resolveAmdgpu};
       case Triple::riscv64:
+      case Triple::riscv64be:
         return {supportsRISCV, resolveRISCV};
       default:
         return {nullptr, nullptr};
       }
     }
 
     // 32-bit object file
     assert(Obj.getBytesInAddress() == 4 &&
case Triple::mips:
       return {supportsMips32, resolveMips32};
     case Triple::msp430:
       return {supportsMSP430, resolveMSP430};
     case Triple::sparc:
       return {supportsSparc32, resolveSparc32};
     case Triple::hexagon:
       return {supportsHexagon, resolveHexagon};
     case Triple::riscv32:
+    case Triple::riscv32be:
       return {supportsRISCV, resolveRISCV};
     case Triple::csky:
       return {supportsCSKY, resolveCSKY};
     default:
       return {nullptr, nullptr};
     }
   } else if (Obj.isMachO()) {
     if (Obj.getArch() == Triple::x86_64)
if (Obj->isELF()) {
         auto *Elf64BEObj = cast<ELF64BEObjectFile>(Obj);
         return Elf64BEObj->getRelSection(R.getRawDataRefImpl())->sh_type;
       };
 
       if (GetRelSectionType() == ELF::SHT_RELA) {
         Addend = getELFAddend(R);
         // RISCV relocations use both LocData and Addend.
         if (Obj->getArch() != Triple::riscv32 &&
-            Obj->getArch() != Triple::riscv64)
+            Obj->getArch() != Triple::riscv64 &&
+            Obj->getArch() != Triple::riscv32be &&
+            Obj->getArch() != Triple::riscv64be)
           LocData = 0;
       }
     }
 
     return Resolver(R.getType(), R.getOffset(), S, LocData, Addend);
   }
 
   // Sometimes the caller might want to use its own specific implementation of

llvm/lib/Support/Triple.cpp

StringRef Triple::getArchTypeName(ArchType Kind) {
   case ppc64le:        return "powerpc64le";
   case ppc:            return "powerpc";
   case ppcle:          return "powerpcle";
   case r600:           return "r600";
   case renderscript32: return "renderscript32";
   case renderscript64: return "renderscript64";
   case riscv32:        return "riscv32";
   case riscv64:        return "riscv64";
+  case riscv32be:      return "riscv32be";
+  case riscv64be:      return "riscv64be";
   case shave:          return "shave";
   case sparc:          return "sparc";
   case sparcel:        return "sparcel";
   case sparcv9:        return "sparcv9";
   case spir64:         return "spir64";
   case spir:           return "spir";
   case spirv32:        return "spirv32";
   case spirv64:        return "spirv64";
StringRef Triple::getArchTypePrefix(ArchType Kind) {
 
   case kalimba:     return "kalimba";
   case lanai:       return "lanai";
   case shave:       return "shave";
   case wasm32:
   case wasm64:      return "wasm";
 
   case riscv32:
-  case riscv64:     return "riscv";
+  case riscv64:
+  case riscv32be:
+  case riscv64be:     return "riscv";
 
   case ve:          return "ve";
   case csky:        return "csky";
 
   case loongarch32:
   case loongarch64: return "loongarch";
   
   case dxil:        return "dx";
return StringSwitch<Triple::ArchType>(Name)
     .Case("ppc", ppc)
     .Case("ppc32le", ppcle)
     .Case("ppcle", ppcle)
     .Case("ppc64le", ppc64le)
     .Case("r600", r600)
     .Case("amdgcn", amdgcn)
     .Case("riscv32", riscv32)
     .Case("riscv64", riscv64)
+    .Case("riscv32be", riscv32be)
+    .Case("riscv64be", riscv64be)
     .Case("hexagon", hexagon)
     .Case("sparc", sparc)
     .Case("sparcel", sparcel)
     .Case("sparcv9", sparcv9)
     .Case("s390x", systemz)
     .Case("systemz", systemz)
     .Case("tce", tce)
     .Case("tcele", tcele)
auto AT = StringSwitch<Triple::ArchType>(ArchName)
     .Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6",
            "mips64r6", "mipsn32r6", Triple::mips64)
     .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
            "mipsn32r6el", Triple::mips64el)
     .Case("r600", Triple::r600)
     .Case("amdgcn", Triple::amdgcn)
     .Case("riscv32", Triple::riscv32)
     .Case("riscv64", Triple::riscv64)
+    .Case("riscv32be", Triple::riscv32be)
+    .Case("riscv64be", Triple::riscv64be)
     .Case("hexagon", Triple::hexagon)
     .Cases("s390x", "systemz", Triple::systemz)
     .Case("sparc", Triple::sparc)
     .Case("sparcel", Triple::sparcel)
     .Cases("sparcv9", "sparc64", Triple::sparcv9)
     .Case("tce", Triple::tce)
     .Case("tcele", Triple::tcele)
     .Case("xcore", Triple::xcore)
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::nvptx:
   case Triple::ppc64le:
   case Triple::ppcle:
   case Triple::r600:
   case Triple::renderscript32:
   case Triple::renderscript64:
   case Triple::riscv32:
   case Triple::riscv64:
+  case Triple::riscv32be:
+  case Triple::riscv64be:
   case Triple::shave:
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::sparcv9:
   case Triple::spir64:
   case Triple::spir:
   case Triple::tce:
   case Triple::tcele:
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::mips:
   case llvm::Triple::mipsel:
   case llvm::Triple::nvptx:
   case llvm::Triple::ppc:
   case llvm::Triple::ppcle:
   case llvm::Triple::r600:
   case llvm::Triple::renderscript32:
   case llvm::Triple::riscv32:
+  case llvm::Triple::riscv32be:
   case llvm::Triple::shave:
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
   case llvm::Triple::spir:
   case llvm::Triple::spirv32:
   case llvm::Triple::tce:
   case llvm::Triple::tcele:
   case llvm::Triple::thumb:
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::loongarch64:
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
   case llvm::Triple::nvptx64:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::renderscript64:
   case llvm::Triple::riscv64:
+  case llvm::Triple::riscv64be:
   case llvm::Triple::sparcv9:
   case llvm::Triple::spir64:
   case llvm::Triple::spirv64:
   case llvm::Triple::systemz:
   case llvm::Triple::ve:
   case llvm::Triple::wasm64:
   case llvm::Triple::x86_64:
     return 64;
Triple Triple::get32BitArchVariant() const {
   case Triple::mips:
   case Triple::mipsel:
   case Triple::nvptx:
   case Triple::ppc:
   case Triple::ppcle:
   case Triple::r600:
   case Triple::renderscript32:
   case Triple::riscv32:
+  case Triple::riscv32be:
   case Triple::shave:
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::spir:
   case Triple::spirv32:
   case Triple::tce:
   case Triple::tcele:
   case Triple::thumb:
Triple Triple::get32BitArchVariant() const {
   case Triple::mips64el:
     T.setArch(Triple::mipsel, getSubArch());
     break;
   case Triple::nvptx64:        T.setArch(Triple::nvptx);   break;
   case Triple::ppc64:          T.setArch(Triple::ppc);     break;
   case Triple::ppc64le:        T.setArch(Triple::ppcle);   break;
   case Triple::renderscript64: T.setArch(Triple::renderscript32); break;
   case Triple::riscv64:        T.setArch(Triple::riscv32); break;
+  case Triple::riscv64be:      T.setArch(Triple::riscv32be); break;
   case Triple::sparcv9:        T.setArch(Triple::sparc);   break;
   case Triple::spir64:         T.setArch(Triple::spir);    break;
   case Triple::spirv64:
     T.setArch(Triple::spirv32, getSubArch());
     break;
   case Triple::wasm64:         T.setArch(Triple::wasm32);  break;
   case Triple::x86_64:         T.setArch(Triple::x86);     break;
   }
Triple Triple::get64BitArchVariant() const {
   case Triple::loongarch64:
   case Triple::mips64:
   case Triple::mips64el:
   case Triple::nvptx64:
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::renderscript64:
   case Triple::riscv64:
+  case Triple::riscv64be:
   case Triple::sparcv9:
   case Triple::spir64:
   case Triple::spirv64:
   case Triple::systemz:
   case Triple::ve:
   case Triple::wasm64:
   case Triple::x86_64:
     // Already 64-bit.
Triple Triple::get64BitArchVariant() const {
   case Triple::mipsel:
     T.setArch(Triple::mips64el, getSubArch());
     break;
   case Triple::nvptx:           T.setArch(Triple::nvptx64);    break;
   case Triple::ppc:             T.setArch(Triple::ppc64);      break;
   case Triple::ppcle:           T.setArch(Triple::ppc64le);    break;
   case Triple::renderscript32:  T.setArch(Triple::renderscript64);     break;
   case Triple::riscv32:         T.setArch(Triple::riscv64);    break;
+  case Triple::riscv32be:       T.setArch(Triple::riscv64be);  break;
   case Triple::sparc:           T.setArch(Triple::sparcv9);    break;
   case Triple::spir:            T.setArch(Triple::spir64);     break;
   case Triple::spirv32:
     T.setArch(Triple::spirv64, getSubArch());
     break;
   case Triple::thumb:           T.setArch(Triple::aarch64);    break;
   case Triple::thumbeb:         T.setArch(Triple::aarch64_be); break;
   case Triple::wasm32:          T.setArch(Triple::wasm64);     break;
Triple Triple::getBigEndianArchVariant() const {
   case Triple::loongarch32:
   case Triple::loongarch64:
   case Triple::msp430:
   case Triple::nvptx64:
   case Triple::nvptx:
   case Triple::r600:
   case Triple::renderscript32:
   case Triple::renderscript64:
-  case Triple::riscv32:
-  case Triple::riscv64:
   case Triple::shave:
   case Triple::spir64:
   case Triple::spir:
   case Triple::spirv32:
   case Triple::spirv64:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
case Triple::mips64el:
     break;
   case Triple::mipsel:
     T.setArch(Triple::mips, getSubArch());
     break;
   case Triple::ppcle:   T.setArch(Triple::ppc);        break;
   case Triple::ppc64le: T.setArch(Triple::ppc64);      break;
   case Triple::sparcel: T.setArch(Triple::sparc);      break;
   case Triple::tcele:   T.setArch(Triple::tce);        break;
+  case Triple::riscv32: T.setArch(Triple::riscv32be);  break;
+  case Triple::riscv64: T.setArch(Triple::riscv64be);  break;
+
   default:
     llvm_unreachable("getBigEndianArchVariant: unknown triple.");
   }
   return T;
 }
 
 Triple Triple::getLittleEndianArchVariant() const {
   Triple T(*this);
case Triple::mips64:
     break;
   case Triple::mips:
     T.setArch(Triple::mipsel, getSubArch());
     break;
   case Triple::ppc:        T.setArch(Triple::ppcle);    break;
   case Triple::ppc64:      T.setArch(Triple::ppc64le);  break;
   case Triple::sparc:      T.setArch(Triple::sparcel);  break;
   case Triple::tce:        T.setArch(Triple::tcele);    break;
+  case Triple::riscv32be:  T.setArch(Triple::riscv32);  break;
+  case Triple::riscv64be:  T.setArch(Triple::riscv64);  break;
   default:
     llvm_unreachable("getLittleEndianArchVariant: unknown triple.");
   }
   return T;
 }
 
 bool Triple::isLittleEndian() const {
   switch (getArch()) {

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
 
   emitToStreamer(Out, Inst);
   return false;
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
   RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
+  RegisterMCAsmParser<RISCVAsmParser> A(getTheRISCV32beTarget());
+  RegisterMCAsmParser<RISCVAsmParser> B(getTheRISCV64beTarget());
 }

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
   // Register the disassembler for each target.
   TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
                                          createRISCVDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
                                          createRISCVDisassembler);
+  TargetRegistry::RegisterMCDisassembler(getTheRISCV32beTarget(),
+                                         createRISCVDisassembler);
+  TargetRegistry::RegisterMCDisassembler(getTheRISCV64beTarget(),
+                                         createRISCVDisassembler);
 }
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder) {
   const FeatureBitset &FeatureBits =
       Decoder->getSubtargetInfo().getFeatureBits();
   bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

 class RISCVAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo &STI;
   uint8_t OSABI;
   bool Is64Bit;
   bool ForceRelocs = false;
   const MCTargetOptions &TargetOptions;
 
 public:
   RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
-                  const MCTargetOptions &Options)
-      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
-        TargetOptions(Options) {
+                  bool IsLittleEndian, const MCTargetOptions &Options)
+      : MCAsmBackend(IsLittleEndian ? support::little : support::big),
+        STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
     RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
   }
   ~RISCVAsmBackend() override = default;
 
   void setForceRelocs() { ForceRelocs = true; }
 
   // Return Size with extra Nop Bytes for alignment directive in code section.
   bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Fixup = PtrSize == 4 ? std::make_pair(RISCV::fixup_riscv_add_32,
                                           RISCV::fixup_riscv_sub_32)
                          : std::make_pair(RISCV::fixup_riscv_add_64,
                                           RISCV::fixup_riscv_sub_64);
     OS.write_zeros(PtrSize);
   } else {
     OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
     Offset = OS.tell();
     Fixup = {RISCV::fixup_riscv_add_16, RISCV::fixup_riscv_sub_16};
-    support::endian::write<uint16_t>(OS, 0, support::little);
+    support::endian::write<uint16_t>(OS, 0, Endian);
   }
 
   const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
   Fixups.push_back(MCFixup::create(
       Offset, MBE.getLHS(), static_cast<MCFixupKind>(std::get<0>(Fixup))));
   Fixups.push_back(MCFixup::create(
       Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
 
Fixups.push_back(MCFixup::create(
         Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
   };
 
   if (isUIntN(6, Value)) {
     OS << uint8_t(dwarf::DW_CFA_advance_loc);
     AddFixups(0, {RISCV::fixup_riscv_set_6b, RISCV::fixup_riscv_sub_6b});
   } else if (isUInt<8>(Value)) {
     OS << uint8_t(dwarf::DW_CFA_advance_loc1);
-    support::endian::write<uint8_t>(OS, 0, support::little);
+    support::endian::write<uint8_t>(OS, 0, Endian);
     AddFixups(1, {RISCV::fixup_riscv_set_8, RISCV::fixup_riscv_sub_8});
   } else if (isUInt<16>(Value)) {
     OS << uint8_t(dwarf::DW_CFA_advance_loc2);
-    support::endian::write<uint16_t>(OS, 0, support::little);
+    support::endian::write<uint16_t>(OS, 0, Endian);
     AddFixups(1, {RISCV::fixup_riscv_set_16, RISCV::fixup_riscv_sub_16});
   } else if (isUInt<32>(Value)) {
     OS << uint8_t(dwarf::DW_CFA_advance_loc4);
-    support::endian::write<uint32_t>(OS, 0, support::little);
+    support::endian::write<uint32_t>(OS, 0, Endian);
     AddFixups(1, {RISCV::fixup_riscv_set_32, RISCV::fixup_riscv_sub_32});
   } else {
     llvm_unreachable("unsupported CFA encoding");
   }
 
   WasRelaxed = OldSize != Data.size();
   return true;
 }
bool RISCVAsmBackend::evaluateTargetFixup(
   if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
     WasForced = true;
     return false;
   }
 
   return true;
 }
 
+/// isDataFixup - Is this a data fixup kind? Data should
+/// be swapped for big endian cores.
+static bool isDataFixup(unsigned Kind) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("Unknown fixup kind!");
+
+  case FK_Data_1:
+  case FK_Data_6b:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_Data_8:
+  case RISCV::fixup_riscv_set_8:
+  case RISCV::fixup_riscv_add_8:
+  case RISCV::fixup_riscv_sub_8:
+  case RISCV::fixup_riscv_set_16:
+  case RISCV::fixup_riscv_add_16:
+  case RISCV::fixup_riscv_sub_16:
+  case RISCV::fixup_riscv_set_32:
+  case RISCV::fixup_riscv_add_32:
+  case RISCV::fixup_riscv_sub_32:
+  case RISCV::fixup_riscv_add_64:
+  case RISCV::fixup_riscv_sub_64:
+  case RISCV::fixup_riscv_set_6b:
+  case RISCV::fixup_riscv_sub_6b:
+    return true;
+
+  case RISCV::fixup_riscv_hi20:
+  case RISCV::fixup_riscv_lo12_i:
+  case RISCV::fixup_riscv_lo12_s:
+  case RISCV::fixup_riscv_pcrel_hi20:
+  case RISCV::fixup_riscv_pcrel_lo12_i:
+  case RISCV::fixup_riscv_pcrel_lo12_s:
+  case RISCV::fixup_riscv_got_hi20:
+  case RISCV::fixup_riscv_tprel_hi20:
+  case RISCV::fixup_riscv_tprel_lo12_i:
+  case RISCV::fixup_riscv_tprel_lo12_s:
+  case RISCV::fixup_riscv_tprel_add:
+  case RISCV::fixup_riscv_tls_got_hi20:
+  case RISCV::fixup_riscv_tls_gd_hi20:
+  case RISCV::fixup_riscv_jal:
+  case RISCV::fixup_riscv_branch:
+  case RISCV::fixup_riscv_call:
+  case RISCV::fixup_riscv_call_plt:
+  case RISCV::fixup_riscv_relax:
+  case RISCV::fixup_riscv_align:
+  case RISCV::fixup_riscv_rvc_jump:
+  case RISCV::fixup_riscv_rvc_branch:
+    return false;
+  }
+}
+
 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                                  const MCValue &Target,
                                  MutableArrayRef<char> Data, uint64_t Value,
                                  bool IsResolved,
                                  const MCSubtargetInfo *STI) const {
   MCFixupKind Kind = Fixup.getKind();
   if (Kind >= FirstLiteralRelocationKind)
     return;
void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
 
   unsigned Offset = Fixup.getOffset();
   unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
 
   assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
 
   // For each byte of the fragment that the fixup touches, mask in the
   // bits from the fixup value.
+
+  // For big endian cores, data fixup should be swapped.
+  bool SwapValue = (Endian == support::big) && isDataFixup(Kind);
   for (unsigned i = 0; i != NumBytes; ++i) {
-    Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
+    unsigned Idx = SwapValue ? (NumBytes - 1 - i) : i;
+    Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
   }
 }
 
 // Linker relaxation may change code size. We have to insert Nops
 // for .align directive when linker relaxation enabled. So then Linker
 // could satisfy alignment by removing Nops.
 // The function return the total Nops Size we need to insert.
 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(

 }
 
 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
                                           const MCSubtargetInfo &STI,
                                           const MCRegisterInfo &MRI,
                                           const MCTargetOptions &Options) {
   const Triple &TT = STI.getTargetTriple();
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
+  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), TT.isLittleEndian(), Options);
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp

 #include "llvm/ADT/Triple.h"
 #include "llvm/BinaryFormat/Dwarf.h"
 #include "llvm/MC/MCStreamer.h"
 using namespace llvm;
 
 void RISCVMCAsmInfo::anchor() {}
 
 RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) {
+  IsLittleEndian = TT.isLittleEndian();
   CodePointerSize = CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4;
   CommentString = "#";
   AlignmentIsInBytes = false;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
                                    std::unique_ptr<MCCodeEmitter> &&MCE,
                                    bool RelaxAll) {
   return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
                                 std::move(MCE), RelaxAll);
 }
 } // end anonymous namespace
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
-  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
+  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target(),
+                    &getTheRISCV32beTarget(), &getTheRISCV64beTarget()}) {
     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
     TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   RTS.setTargetABI(STI->getTargetABI());
 }
 
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
+  RegisterAsmPrinter<RISCVAsmPrinter> A(getTheRISCV32beTarget());
+  RegisterAsmPrinter<RISCVAsmPrinter> B(getTheRISCV64beTarget());
 }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 static cl::opt<bool> EnableRedundantCopyElimination(
     "riscv-enable-copyelim",
     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
     cl::Hidden);
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
+  RegisterTargetMachine<RISCVTargetMachine> A(getTheRISCV32beTarget());
+  RegisterTargetMachine<RISCVTargetMachine> B(getTheRISCV64beTarget());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVMakeCompressibleOptPass(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVSExtWRemovalPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
   initializeRISCVInsertVSETVLIPass(*PR);
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
-  if (TT.isArch64Bit())
-    return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
+  if (TT.isArch64Bit()) {
+    return (Twine(TT.isLittleEndian() ? "e" : "E") +
+      "-m:e-p:64:64-i64:64-i128:128-n64-S128").str();
+  }
   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
-  return "e-m:e-p:32:32-i64:64-n32-S128";
+  return (Twine(TT.isLittleEndian() ? "e" : "E") +
+    "-m:e-p:32:32-i64:64-n32-S128").str();
 }
 
 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
                                            Optional<Reloc::Model> RM) {
   return RM.value_or(Reloc::Static);
 }
 
 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
void RISCVPassConfig::addPreEmitPass2() {
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.
   addPass(createRISCVExpandAtomicPseudoPass());
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();
 
-  if (TM->getTargetTriple().getArch() == Triple::riscv64)
+  if (TM->getTargetTriple().getArch() == Triple::riscv64 ||
+      TM->getTargetTriple().getArch() == Triple::riscv64be)
     addPass(createRISCVSExtWRemovalPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());
 }

llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h

 #define LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H
 
 namespace llvm {
 
 class Target;
 
 Target &getTheRISCV32Target();
 Target &getTheRISCV64Target();
+Target &getTheRISCV32beTarget();
+Target &getTheRISCV64beTarget();
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H

llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

Target &llvm::getTheRISCV32Target() {
   return TheRISCV32Target;
 }
 
 Target &llvm::getTheRISCV64Target() {
   static Target TheRISCV64Target;
   return TheRISCV64Target;
 }
 
+Target &llvm::getTheRISCV32beTarget() {
+  static Target TheRISCV32beTarget;
+  return TheRISCV32beTarget;
+}
+
+Target &llvm::getTheRISCV64beTarget() {
+  static Target TheRISCV64beTarget;
+  return TheRISCV64beTarget;
+}
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() {
   RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
                                     "32-bit RISC-V", "RISCV");
   RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
                                     "64-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv32be> A(getTheRISCV32beTarget(), "riscv32be",
+                                    "32-bit big endian RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv64be> B(getTheRISCV64beTarget(), "riscv64be",
+                                    "64-bit big endian RISC-V", "RISCV");
 }

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

static ShadowMapping getShadowMapping(const Triple &TargetTriple, int LongSize,
   bool IsPPC64 = TargetTriple.getArch() == Triple::ppc64 ||
                  TargetTriple.getArch() == Triple::ppc64le;
   bool IsSystemZ = TargetTriple.getArch() == Triple::systemz;
   bool IsX86_64 = TargetTriple.getArch() == Triple::x86_64;
   bool IsMIPS32 = TargetTriple.isMIPS32();
   bool IsMIPS64 = TargetTriple.isMIPS64();
   bool IsArmOrThumb = TargetTriple.isARM() || TargetTriple.isThumb();
   bool IsAArch64 = TargetTriple.getArch() == Triple::aarch64;
-  bool IsRISCV64 = TargetTriple.getArch() == Triple::riscv64;
+  bool IsRISCV64 = TargetTriple.getArch() == Triple::riscv64 ||
+                   TargetTriple.getArch() == Triple::riscv64be;
   bool IsWindows = TargetTriple.isOSWindows();
   bool IsFuchsia = TargetTriple.isOSFuchsia();
   bool IsEmscripten = TargetTriple.isOSEmscripten();
   bool IsAMDGPU = TargetTriple.isAMDGPU();
 
   ShadowMapping Mapping;
 
   Mapping.Scale = kDefaultShadowScale;

llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test

 # RUN: llvm-readobj --file-headers %t.ppc64le.o | FileCheck %s --check-prefixes=CHECK,LE,PPC64,PPC64LE,64
 
 # RUN: llvm-objcopy -I binary -O elf32-littleriscv %t.txt %t.rv32.o
 # RUN: llvm-readobj --file-headers %t.rv32.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV32,32
 
 # RUN: llvm-objcopy -I binary -O elf64-littleriscv %t.txt %t.rv64.o
 # RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64
 
+# RUN: llvm-objcopy -I binary -O elf32-bigriscv %t.txt %t.rv32.o
+# RUN: llvm-readobj --file-headers %t.rv32.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV32,32
+
+# RUN: llvm-objcopy -I binary -O elf64-bigriscv %t.txt %t.rv64.o
+# RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV64,64
+
 # RUN: llvm-objcopy -I binary -O elf32-sparc %t.txt %t.sparc.o
 # RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,BE,SPARC,32
 
 # RUN: llvm-objcopy -I binary -O elf32-sparcel %t.txt %t.sparcel.o
 # RUN: llvm-readobj --file-headers %t.sparcel.o | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32
 
 # RUN: llvm-objcopy -I binary -O elf32-hexagon %t.txt %t.hexagon.o
 # RUN: llvm-readobj --file-headers %t.hexagon.o | FileCheck %s --check-prefixes=CHECK,LE,HEXAGON,32

llvm/tools/llvm-objcopy/ObjcopyOptions.cpp

static const StringMap<MachineInfo> TargetMap{
     // ARM
     {"elf32-littlearm", {ELF::EM_ARM, false, true}},
     // ARM AArch64
     {"elf64-aarch64", {ELF::EM_AARCH64, true, true}},
     {"elf64-littleaarch64", {ELF::EM_AARCH64, true, true}},
     // RISC-V
     {"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
     {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+    {"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+    {"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
     // PowerPC
     {"elf32-powerpc", {ELF::EM_PPC, false, false}},
     {"elf32-powerpcle", {ELF::EM_PPC, false, true}},
     {"elf64-powerpc", {ELF::EM_PPC64, true, false}},
     {"elf64-powerpcle", {ELF::EM_PPC64, true, true}},
     // MIPS
     {"elf32-bigmips", {ELF::EM_MIPS, false, false}},
     {"elf32-ntradbigmips", {ELF::EM_MIPS, false, false}},

llvm/unittests/Object/ELFObjectFileTest.cpp

TEST(ELFObjectFileTest, MachineTestForPPC) {
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_PPC)) {
     checkFormatAndArch(D, Formats[I], Archs[I]);
     ++I;
   }
 }
 
 TEST(ELFObjectFileTest, MachineTestForRISCV) {
-  std::array<StringRef, 4> Formats = {"elf32-littleriscv", "elf32-littleriscv",
-                                      "elf64-littleriscv", "elf64-littleriscv"};
-  std::array<Triple::ArchType, 4> Archs = {Triple::riscv32, Triple::riscv32,
-                                           Triple::riscv64, Triple::riscv64};
+  std::array<StringRef, 4> Formats = {"elf32-littleriscv", "elf32-bigriscv",
+                                      "elf64-littleriscv", "elf64-bigriscv"};
+  std::array<Triple::ArchType, 4> Archs = {Triple::riscv32, Triple::riscv32be,
+                                           Triple::riscv64, Triple::riscv64be};
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_RISCV)) {
     checkFormatAndArch(D, Formats[I], Archs[I]);
     ++I;
   }
 }
 
 TEST(ELFObjectFileTest, MachineTestForARM) {