nemanjai (Nemanja Ivanovic)
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Jan 23 2015, 9:38 AM (190 w, 6 d)

Recent Activity

Tue, Sep 18

nemanjai planned changes to D47332: [PowerPC] Exploit the vector min/max instructions.

@jedilyn Hi Ke Wen, thanks for your comments. This needs some cleanup with regard to which instructions match the semantics of F{MIN|MAX}NUM vs. F{MIN|MAX}NAN. I'll clean that up and re-post this for your review. Thanks.

Tue, Sep 18, 7:02 AM
nemanjai requested changes to D49507: [Power9] Add __float128 support in the backend for bitcast to a i128.

Since there are unaddressed comments, I'm moving this off of my Must Review queue until they are addressed.

Tue, Sep 18, 6:49 AM
nemanjai committed rL342478: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.
[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
Tue, Sep 18, 6:44 AM
nemanjai closed D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.
Tue, Sep 18, 6:44 AM
nemanjai committed rL342472: [PowerPC] Optimize compares fed by ANDISo.
[PowerPC] Optimize compares fed by ANDISo
Tue, Sep 18, 6:23 AM
nemanjai closed D51353: [PowerPC] Optimize compares fed by ANDISo.
Tue, Sep 18, 6:23 AM

Fri, Sep 14

nemanjai requested changes to D51988: [PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads..
Fri, Sep 14, 8:14 AM
nemanjai added a comment to D51988: [PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads..

Please add a test case that we used to transform to a D-Form and no longer do with your patch (preferably one for DS-Form and one for DQ-Form).

Fri, Sep 14, 8:14 AM
nemanjai added a comment to D52013: Add support for powerpc64-*-linux-musl targets.

Please provide the patch with full context as per http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface. Furthermore, if you would like to commit this, it'll have to go into trunk and then it can be merged into 7.0.1 (I'm not sure that we'd be able to merge it into any 6.0 release as there may not be a 6.0.2).
Finally, for the test case you can just compile anything with llc with the triple you are interested in and a CHECK directive can check for .abiversion 2 in the assembly.

Fri, Sep 14, 7:43 AM
nemanjai accepted D52040: [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8 .

LGTM.

Fri, Sep 14, 7:35 AM
nemanjai accepted D52074: [PowerPC] [Clang] Add vector int128 pack/unpack builtins.
Fri, Sep 14, 6:38 AM
nemanjai added a comment to D52074: [PowerPC] [Clang] Add vector int128 pack/unpack builtins.

LGTM.

Fri, Sep 14, 6:38 AM
nemanjai accepted D52039: [PowerPC][NFC] Add a mulld testcase for scheduling check..

LGTM. For a change such as this, I like the idea of committing a test case prior to the patch so the patch clearly shows the difference. Thank you.

Fri, Sep 14, 2:23 AM
nemanjai accepted D52072: [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1.

Minor nit, but LGTM.

Fri, Sep 14, 2:21 AM

Tue, Sep 11

nemanjai accepted D48185: [Power9] [LLVM] Add __float128 exponent GET and SET builtins.

LGTM.

Tue, Sep 11, 10:56 AM

Fri, Aug 31

nemanjai added a comment to rL341180: [XRay] FDR Record Producer/Consumer Implementation.

I think this patch caused failures (in addition to existing ones) on the PowerPC Big Endian buildbot (http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/23397). It fails unit tests in the file added in this patch, which is what makes me suspect that it is this patch that causes the failures. Can you please investigate or let me know if I need to do something on the buildbot (clean up directories, etc.)?

Fri, Aug 31, 6:29 AM
nemanjai added a comment to rL341032: [XRay] Move out template and use perfect forwarding.

Hi Dean, I think this patch may have caused failures on the PPC Big Endian build bot and the failures were hidden by other build breaks that happened near the same time. Initially this caused failures at compile time which you fixed in r341042. However after that was fixed, we are now getting failures that I don't understand but certainly seem related to this patch (please refer to: http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/23322).
The failures being:

FAIL: LLVM-Unit::FDRTraceWriterTest.WriteToStringBufferVersion3
FAIL: LLVM-Unit::FDRTraceWriterTest.WriteToStringBufferVersion2
FAIL: LLVM-Unit::FDRTraceWriterTest.WriteToStringBufferVersion1
Fri, Aug 31, 6:20 AM
nemanjai added a comment to D51353: [PowerPC] Optimize compares fed by ANDISo.

LGTM with nitpicking.

I feel that the current test case is somewhat fragile for minor change in inst. scheduling or register allocation.
Checking there is no cmpdi between andis. and isel may be enough.

Fri, Aug 31, 5:59 AM
nemanjai accepted D51403: [PowerPC] Combine ADD to ADDZE.

LGTM aside from a minor nit which you can fix on the commit.

Fri, Aug 31, 5:54 AM
nemanjai accepted D51506: [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 .

LGTM. Thanks on working on completing the set of itineraries.

Fri, Aug 31, 4:43 AM
nemanjai added a comment to D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.

@inouehrs I think I've addressed your comments adequately. Do you have any further comments or can you accept this revision?

Fri, Aug 31, 4:41 AM
nemanjai added a comment to D51353: [PowerPC] Optimize compares fed by ANDISo.

@inouehrs Can you please review/comment/approve this as I've separated this out per your request.

Fri, Aug 31, 4:41 AM

Tue, Aug 28

nemanjai added inline comments to D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.
Tue, Aug 28, 6:36 AM
nemanjai added a comment to D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.

This patch increases the number of record-form rotates we emit by more than 70%.

Do you mean reducing the record-form rotates by 70%? If so, it is great!

Oops! Yes this patch definitely causes a reduction in the number of record-form rotates :)
I updated the description (it was meant to say eliminate rather than emit).

Tue, Aug 28, 6:35 AM
nemanjai updated the diff for D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.

Remove the orthogonal change that allows us to optimize compares fed by record-form ANDIS.

Tue, Aug 28, 6:35 AM
nemanjai updated the summary of D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.
Tue, Aug 28, 6:35 AM
nemanjai created D51353: [PowerPC] Optimize compares fed by ANDISo.
Tue, Aug 28, 6:25 AM

Mon, Aug 27

nemanjai added a comment to D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices.

Ping. I'd like to get this committed. Can someone please review?

Mon, Aug 27, 2:01 PM
nemanjai added a reviewer for D44897: [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices: kbarton.
Mon, Aug 27, 2:01 PM
nemanjai added a comment to rL340729: [clangd] Use TRUE iterator instead of complete posting list.

It would appear that this patch caused buildbot failures. An example at: http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/19586

Mon, Aug 27, 9:13 AM
nemanjai accepted D50965: [PowerPC] Fix label address calculation for ppc64.

This seems to make sense to me and it resolves the kernel build issue. If @sfertile sees something wrong with the patch, he can chime in before or after the commit.

Mon, Aug 27, 7:57 AM
nemanjai accepted D51122: [PowerPC][MC] Support expressions in getMemRIX16Encoding.

Other than the minor nit about the test case, this LGTM.

Mon, Aug 27, 7:52 AM
nemanjai added inline comments to D49507: [Power9] Add __float128 support in the backend for bitcast to a i128.
Mon, Aug 27, 7:47 AM
nemanjai committed rL340740: [PowerPC] Revert commit r339779.
[PowerPC] Revert commit r339779
Mon, Aug 27, 6:21 AM
nemanjai committed rL340734: [PowerPC] Recommit r340016 after fixing the reported issue.
[PowerPC] Recommit r340016 after fixing the reported issue
Mon, Aug 27, 4:21 AM

Aug 17 2018

nemanjai accepted D49007: [PowerPC] Add a peephole post RA to transform the inst that fed by add.

I have done the following tests with this patch:

  1. LLVM check-all uniitests
  2. LLVM test-suites
  3. bootstrap build the clang with the clang including my fix, and then, run the llvm check-all and test-suites, and it passed.

    The patch passed all these tests.
Aug 17 2018, 5:46 AM
nemanjai committed rL340017: Revert extraneous directory added by accident in rL340016.
Revert extraneous directory added by accident in rL340016
Aug 17 2018, 5:42 AM
nemanjai committed rL340016: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction
Aug 17 2018, 5:36 AM
nemanjai closed D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
Aug 17 2018, 5:36 AM

Aug 15 2018

nemanjai committed rL339779: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
Aug 15 2018, 8:31 AM
nemanjai closed D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.
Aug 15 2018, 8:31 AM
nemanjai accepted D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.

LGTM aside from the minor nit.

Aug 15 2018, 6:18 AM
nemanjai committed rL339769: [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types.
[PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types
Aug 15 2018, 5:59 AM
nemanjai closed D49080: [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types.
Aug 15 2018, 5:58 AM
nemanjai added a comment to D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.

Could someone commit for me since I don't have svn access. Thank you very much.

Aug 15 2018, 5:41 AM

Aug 14 2018

nemanjai added a comment to rL339629: [analyzer] [NFC] Introduce separate targets for testing the analyzer: check….

For whatever reason, this does not seem to be NFC. It causes a number of failures on the PowerPC targets (including buildbots). For an example, please consider: http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/19269

Aug 14 2018, 12:11 PM
nemanjai added a comment to D38778: Implement rudimentary support for the PowerPC SPE APU.

Is this patch ready to be abandoned now that it has been broken up into smaller patches which were committed?

Aug 14 2018, 10:33 AM
nemanjai accepted D49698: [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loads.

LGTM.

Aug 14 2018, 10:31 AM
nemanjai accepted D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.

LGTM. Since we're all in agreement that we want to make this change for Power9, I think this is fine to go in.

Aug 14 2018, 10:25 AM
nemanjai added inline comments to D42590: [PowerPC] Try to move the stack pointer update instruction later in the prologue and earlier in the epilogue (Version 2).
Aug 14 2018, 10:23 AM

Aug 13 2018

nemanjai accepted D39386: [Power9] Allow gpr callee saved spills in prologue to vector registers rather than stack.

LGTM.
Perhaps @thegameg or @MatzeB want to look at it as well (particularly the target independent parts). And perhaps @hfinkel and @echristo are interested in having another look. Otherwise, I suppose this is ready to go.

Aug 13 2018, 11:58 AM
nemanjai requested changes to D48185: [Power9] [LLVM] Add __float128 exponent GET and SET builtins.
Aug 13 2018, 7:40 AM
nemanjai accepted D48184: [Power9] [CLANG] Add __float128 exponent GET and SET builtins.

LGTM

Aug 13 2018, 7:28 AM
nemanjai requested changes to D49507: [Power9] Add __float128 support in the backend for bitcast to a i128.

This is definitely going to need a test case.

Aug 13 2018, 7:27 AM
nemanjai accepted D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.

LGTM.

Aug 13 2018, 6:58 AM
nemanjai added inline comments to D49698: [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loads.
Aug 13 2018, 6:42 AM
nemanjai added inline comments to D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction.
Aug 13 2018, 6:29 AM
nemanjai added a comment to D49007: [PowerPC] Add a peephole post RA to transform the inst that fed by add.

I think that this is semantically correct now. There are just a few other stylistic comments.
Also, since this is a rather high-risk patch, can you describe on the patch the functional testing you have done with the patch (list of applications, bootstrap, etc.)?

Aug 13 2018, 5:31 AM
nemanjai added a comment to D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.
Aug 13 2018, 4:28 AM

Aug 10 2018

nemanjai added a comment to D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.

<snip>

diff of assembly before change and after change:

$ diff -Naur before.s after.s 
--- before.s    2018-08-09 13:52:24.785246846 -0400
+++ after.s     2018-08-09 13:59:38.815493708 -0400
@@ -9,7 +9,7 @@
 # %bb.0:                                # %entry
        lfd f0, 304(r1)
        lxsd v2, 312(r1)
-       xxlor v3, f1, f1
+      xscpsgndp v3, f1, f1
        xsmaddadp v3, v2, f0
        xsadddp f0, v3, f2
        xsmaddadp f0, v3, v2
Aug 10 2018, 5:57 AM
nemanjai added a comment to D49080: [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types.

This is a rather non-controversial change that resolves a release blocker bug. I'm going to commit this fix later today.

Aug 10 2018, 5:30 AM

Aug 8 2018

nemanjai added a comment to D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.

<snip>

No sure how much this will have impact, but maybe we need to consider still using xxlor for destructive instructions?

eg:
In Power ISA 3.0 B, 2.1.5 Destructive Operation Operand Preservation
"The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance."

Aug 8 2018, 8:02 AM
nemanjai added a reviewer for D49879: [PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction: hfinkel.
Aug 8 2018, 7:01 AM

Aug 2 2018

nemanjai added a comment to D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.

XSCPSGNDP has longer latency (6 cycles) than XXLOR (2 cycles) on POWER8 while it has higher throughput with the same latency on POWER9. So XXLOR is preferable for pre-P9.

Also, the two instructions have different behavior for a denormal input value in my understanding; XSCPSGNDP does normalization but XXLOR does not. Does this difference matter?

Aug 2 2018, 7:28 AM
nemanjai added a comment to D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9.

+1, even for Power9 XSCPSGNDP makes pipeline busy longer than XXLOR, XXLOR is still better.

Can you clarify this please? Where is this information coming from? According to the UM, XXLOR takes up a whole superslice whereas XSCPSGNDP takes up a single slice so we can dispatch 2 of the former per cycle and 4 of the latter. And the "Pipe Busy Cycles" field for both is 1.

Aug 2 2018, 7:25 AM

Aug 1 2018

nemanjai added a comment to D49080: [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types.

Ping. The bug this resolves (38087) is marked as a blocker for 7.0. @hfinkel Can you please have a look at this patch when you get the chance?

Aug 1 2018, 5:35 PM
nemanjai committed rL338658: [PowerPC] Do not round values prior to converting to integer.
[PowerPC] Do not round values prior to converting to integer
Aug 1 2018, 5:03 PM
nemanjai closed D50121: [PowerPC] Do not round values prior to converting to integer.
Aug 1 2018, 5:03 PM
nemanjai added a comment to D50121: [PowerPC] Do not round values prior to converting to integer.

One questions I had after looking into this bug was why does PPCTargetLowering::LowerFP_TO_INTForReuse() extend f32 values to f64 before creating the FCT* instructions?

Aug 1 2018, 5:47 AM
nemanjai updated the diff for D50121: [PowerPC] Do not round values prior to converting to integer.

Place comment into the respective if block.

Aug 1 2018, 5:25 AM

Jul 31 2018

nemanjai added a reviewer for D50121: [PowerPC] Do not round values prior to converting to integer: kbarton.
Jul 31 2018, 5:41 PM
nemanjai created D50121: [PowerPC] Do not round values prior to converting to integer.
Jul 31 2018, 5:40 PM

Jul 19 2018

nemanjai committed rC337451: NFC: Remove extraneous semicolons as pointed out in the differential review.
NFC: Remove extraneous semicolons as pointed out in the differential review
Jul 19 2018, 5:54 AM
nemanjai committed rL337451: NFC: Remove extraneous semicolons as pointed out in the differential review.
NFC: Remove extraneous semicolons as pointed out in the differential review
Jul 19 2018, 5:54 AM
nemanjai committed rL337449: [PowerPC] Handle __builtin_xxpermdi the same way as GCC does.
[PowerPC] Handle __builtin_xxpermdi the same way as GCC does
Jul 19 2018, 5:49 AM
nemanjai committed rC337449: [PowerPC] Handle __builtin_xxpermdi the same way as GCC does.
[PowerPC] Handle __builtin_xxpermdi the same way as GCC does
Jul 19 2018, 5:49 AM
nemanjai closed D49424: [PowerPC] Handle __builtin_xxpermdi the same way as GCC does.
Jul 19 2018, 5:49 AM

Jul 17 2018

nemanjai added inline comments to D49424: [PowerPC] Handle __builtin_xxpermdi the same way as GCC does.
Jul 17 2018, 4:27 PM
nemanjai created D49424: [PowerPC] Handle __builtin_xxpermdi the same way as GCC does.
Jul 17 2018, 6:30 AM
nemanjai accepted D48663: [Power9] Code Cleanup - Remove needsAggressiveScheduling().

LGTM.

Jul 17 2018, 6:00 AM
nemanjai added a comment to D48950: [PowerPC] Improve codegen for vector loads using scalar_to_vector .

There are a few minor nits, but aside from those this LGTM.
Also, please make note of the fact that we need to fix sequences such as xxsldwi -> xxspltw and xxpermdi -> xxspltw in PPCMIPeephole.cpp.

Jul 17 2018, 5:52 AM
nemanjai accepted D48950: [PowerPC] Improve codegen for vector loads using scalar_to_vector .

Forgot to approve the patch.

Jul 17 2018, 5:52 AM
nemanjai added a comment to D44830: Introduce codegen for the Signal Processing Engine.

I don't see anything in the update that would cause me to reverse the approval, so I'd say this is still fine.

Jul 17 2018, 4:50 AM

Jul 13 2018

nemanjai committed rL337008: [PowerPC] Materialize more constants with CR-field set in late peephole.
[PowerPC] Materialize more constants with CR-field set in late peephole
Jul 13 2018, 8:26 AM
nemanjai closed D42109: [PowerPC] Follow-up to r322373 for materializing constants that set the CR.
Jul 13 2018, 8:26 AM

Jul 11 2018

nemanjai requested changes to D49007: [PowerPC] Add a peephole post RA to transform the inst that fed by add.

This needs to be beefed up to account for the two unsafe situations I outlined in the comment.

Jul 11 2018, 11:54 AM

Jul 9 2018

nemanjai created D49080: [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types.
Jul 9 2018, 7:59 AM

Jul 6 2018

nemanjai accepted D48294: [Power9] Add __float128 support for compare operations.

LGTM.

Jul 6 2018, 4:37 AM

Jul 5 2018

nemanjai requested changes to D48950: [PowerPC] Improve codegen for vector loads using scalar_to_vector .

A number of the registers in the test cases you've added are mandated by the ABI. Rather than keeping track of which ones should be part of the test case, perhaps it's easiest to use utils/update_llc_test_checks.py to automatically generate the CHECK directives (if it works for all the RUN lines in your tests).

Jul 5 2018, 4:16 AM
nemanjai added a comment to D48950: [PowerPC] Improve codegen for vector loads using scalar_to_vector .

There's a notification from Phabricator that says:
This file was changed only by adding or removing whitespace. Show File Contents
for file lib/Target/PowerPC/PPCISelLowering.cpp. If this is a glitch with Phabricator, fine. Otherwise please remove any such unrelated changes.

Jul 5 2018, 2:53 AM
nemanjai added reviewers for D48950: [PowerPC] Improve codegen for vector loads using scalar_to_vector : echristo, hfinkel.
Jul 5 2018, 2:50 AM
nemanjai added inline comments to D48308: [Power9] Ensure float128 in non-homogenous aggregates are passed via VSX registers.
Jul 5 2018, 2:48 AM

Jul 4 2018

nemanjai added a comment to D39386: [Power9] Allow gpr callee saved spills in prologue to vector registers rather than stack.

Thank you for updating the code to get the CSR list from RegInfo. It looks much cleaner than having a static list of registers. I think the code can be cleaned up a bit further still, but overall this looks great.

Jul 4 2018, 10:44 AM
nemanjai accepted D46997: [Power9]Legalize and emit code for round & convert quad-precision values.

LGTM.

Jul 4 2018, 7:58 AM
nemanjai accepted D47550: [Power9] Add __float128 builtins for Round To Odd.

LGTM.

Jul 4 2018, 7:50 AM
nemanjai accepted D47548: [Power9] Add __float128 builtins for Round To Odd.

LGTM.

Jul 4 2018, 7:40 AM
nemanjai accepted D47552: [Power9] Implement float128 parameter passing and return values.

LGTM.

Jul 4 2018, 7:37 AM
nemanjai accepted D48044: [Power9] Update fp128 as a valid homogenous aggregate base type .

Other than a few style nits that can be fixed on the commit, this LGTM.

Jul 4 2018, 7:31 AM
nemanjai added a comment to D48184: [Power9] [CLANG] Add __float128 exponent GET and SET builtins.

Perhaps my comment about the GCC documentation really belongs in this patch rather than in D48185.

Jul 4 2018, 6:19 AM
nemanjai added a comment to D48185: [Power9] [LLVM] Add __float128 exponent GET and SET builtins.

Can you put a link in the description of the patch as to where the GCC builtins are documented (if such a document exists). The naming seems inconsistent and I don't see it at https://gcc.gnu.org/onlinedocs/gcc-8.1.0/gcc/PowerPC-Built-in-Functions.html.

Jul 4 2018, 5:01 AM