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nemanjai (Nemanja Ivanovic)
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Jan 23 2015, 9:38 AM (207 w, 4 d)

Recent Activity

Mon, Jan 14

nemanjai added inline comments to D56175: [PowerPC] Exploit store instructions that store a single vector element.
Mon, Jan 14, 2:10 PM
nemanjai added a comment to D54313: [compiler-rt][builtins][PowerPC] Add floattitf builtin compiler-rt method support for PowerPC .

Amy, can we get this committed?

Mon, Jan 14, 1:51 PM
nemanjai added inline comments to D56175: [PowerPC] Exploit store instructions that store a single vector element.
Mon, Jan 14, 1:50 PM

Fri, Jan 11

nemanjai updated the diff for D56175: [PowerPC] Exploit store instructions that store a single vector element.

Updated the wrong indices for big endian systems. Added comments for magic numbers for indices/shift amounts.

Fri, Jan 11, 7:44 AM
nemanjai added inline comments to D56175: [PowerPC] Exploit store instructions that store a single vector element.
Fri, Jan 11, 6:58 AM

Fri, Jan 4

nemanjai added a comment to D55503: Change llvm call once check for building Swift for PowerPC(ppc64le).

Sarvesh, I've tried this on a PPC64LE machine with one version of GLIBC and found no problems. However, I am reluctant to just go ahead with a change without testing with a few other versions of GLIBC.

Fri, Jan 4, 6:22 AM

Mon, Dec 31

nemanjai added inline comments to D56175: [PowerPC] Exploit store instructions that store a single vector element.
Mon, Dec 31, 12:09 PM
nemanjai updated the diff for D56175: [PowerPC] Exploit store instructions that store a single vector element.

Indentation was off in the td file.

Mon, Dec 31, 11:59 AM
nemanjai created D56175: [PowerPC] Exploit store instructions that store a single vector element.
Mon, Dec 31, 11:34 AM
nemanjai abandoned D44528: [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns.

Upon closer inspection, this actually almost never fires on PPC so spending any more time on it does not seem useful. Abandoning this patch.

Mon, Dec 31, 9:25 AM

Sun, Dec 30

nemanjai added inline comments to D42590: [PowerPC] Try to move the stack pointer update instruction later in the prologue and earlier in the epilogue (Version 2).
Sun, Dec 30, 2:53 PM
nemanjai updated the diff for D47332: [PowerPC] Exploit the vector min/max instructions.

Updated to remove the patterns for the Altivec versions of vector min/max as they have IEEE semantics wrt. handling NaN. A subsequent patch will legalize the _IEEE versions of the nodes for single precision and provide patterns to match them to vmaxfp/vminfp.

Sun, Dec 30, 5:25 AM
nemanjai added inline comments to D54583: PowerPC: Optimize SPE double parameter calling setup.
Sun, Dec 30, 5:13 AM
nemanjai accepted D56148: [PowerPC] Fix machine verify pass error for PATCHPOINT pseudo instruction that bad machine code.

LGTM.

Sun, Dec 30, 5:05 AM

Sat, Dec 29

nemanjai added a comment to D47332: [PowerPC] Exploit the vector min/max instructions.

This covers PR39130 right?

Maybe worth adding the new vec-min-max.ll test file to trunk with current codegen so this patch shows the improved codegen diff?

Sat, Dec 29, 4:37 PM
nemanjai added a comment to D20019: [PPC] exploitation of new xscmp*, as well as xsmaxcdp and xsmincdp.

We have neglected this for a very long time. Just adding a comment to trickle it up to the top of the review queue and I plan to review it very soon.

Sat, Dec 29, 3:28 PM
nemanjai requested changes to D42590: [PowerPC] Try to move the stack pointer update instruction later in the prologue and earlier in the epilogue (Version 2).

I think this is close to ready but there are a few comments that have to be addressed. Also, @hfinkel and @inouehrs do you see anything that needs to be handled in addition to what I commented on?

Sat, Dec 29, 3:17 PM
nemanjai requested changes to D55326: [Driver] Fix incorrect GNU triplet for PowerPC on SUSE Linux.

A couple of questions since I am not all that familiar with clang and am certainly not familiar with this unusual SUSE 32-bit situation:

  • We seem to be changing the set of aliases here, but what happens if someone actually explicitly specifies --target=powerpc-suse-linux?
  • Do we need to change anything about include paths?
  • Can you describe the default triple for clang on SUSE 32-bit PPC? Will it be powerpc-suse-linux? powerpc64-suse-linux?
  • Will this change not affect 64-bit PPC SUSE? Namely will the default libraries on actual 64-bit PPC SUSE big endian systems now be 32-bit libraries?
  • Can you please add a test case and a patch with full context before this patch can go any further?
Sat, Dec 29, 2:20 PM
nemanjai accepted D54409: PowerPC/SPE: Fix register spilling for SPE registers.

Other than the minor nit about the test case, LGTM.

Sat, Dec 29, 1:43 PM
nemanjai accepted D55810: [Power9] Enable the Out-of-Order scheduling model for P9 hw.

LGTM. We definitely want to go ahead with this.

Sat, Dec 29, 1:35 PM
nemanjai added inline comments to D54583: PowerPC: Optimize SPE double parameter calling setup.
Sat, Dec 29, 1:33 PM
nemanjai added a comment to D33499: [PPC] PPC32/Darwin ABI info.

@iains - I have interest in resolving this issue, and also a couple of other lingering bugs in the PPC32Darwin ABI realm. If you have your WIP available anywhere, I'd be happy to have a go at bringing it up to current.

Sat, Dec 29, 12:24 PM
nemanjai added a comment to D55686: [PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel.

I assume that we are fixing this specific instance because we have a test case that breaks if we turn on verification by default. However, I would assume that we actually have a lot of other failures hiding in here which would be uncovered by doing a bootstrap build with -O0. I am not suggesting that we put all the fixes in a single patch, just that we want to do more thorough testing before we turn on MachineFunction verification by default.

Sat, Dec 29, 12:20 PM
nemanjai added inline comments to D56148: [PowerPC] Fix machine verify pass error for PATCHPOINT pseudo instruction that bad machine code.
Sat, Dec 29, 8:30 AM
nemanjai committed rL350156: [PowerPC][NFC] Macro for register set defs for the Asm Parser.
[PowerPC][NFC] Macro for register set defs for the Asm Parser
Sat, Dec 29, 8:17 AM
nemanjai closed D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.
Sat, Dec 29, 8:17 AM
nemanjai committed rL350155: [PowerPC] Complete the custom legalization of vector int to fp conversion.
[PowerPC] Complete the custom legalization of vector int to fp conversion
Sat, Dec 29, 5:45 AM
nemanjai closed D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.
Sat, Dec 29, 5:44 AM
nemanjai committed rL350153: [PowerPC] Fix CR Bit spill pseudo expansion.
[PowerPC] Fix CR Bit spill pseudo expansion
Sat, Dec 29, 3:48 AM
nemanjai closed D55996: [PowerPC] Fix CR Bit spill pseudo expansion.
Sat, Dec 29, 3:48 AM

Mon, Dec 24

nemanjai updated subscribers of D55461: [PowerPC] Update Vector Costs for P9.

Also, I've thought a bit about what Jinsong mentioned and I am wondering if maybe we don't want to take a different approach. Namely, the cost model is meant to return the cost of individual instructions with a given type and this cost is the instructions latency relative to the latency of a simple scalar ALU instruction (I think a comment somewhere uses add as the basis for what 1 means). And the vectorizers use these values to essentially add up the costs of all the instructions in a loop/block and then compute what provides the lowest total cost assuming that the cost of an N-wide vectorization can be computed by simply dividing the total cost by N.

Mon, Dec 24, 3:05 PM
nemanjai added a comment to D55461: [PowerPC] Update Vector Costs for P9.

I think this code could be greatly simplified if we implement int PPCTTIImpl::vectorCostAdjustmentFactor(Type *Ty) which would return 1 by default and 2 if we are on a subtarget with vector operations that take up two execution units and Ty is a vector type.

Mon, Dec 24, 2:14 PM
nemanjai accepted D54313: [compiler-rt][builtins][PowerPC] Add floattitf builtin compiler-rt method support for PowerPC .

The remaining comments from me are minor. I am OK with this going in if Robert is.

Mon, Dec 24, 10:12 AM

Fri, Dec 21

nemanjai created D55996: [PowerPC] Fix CR Bit spill pseudo expansion.
Fri, Dec 21, 4:17 AM

Wed, Dec 19

nemanjai added a comment to D55503: Change llvm call once check for building Swift for PowerPC(ppc64le).

Hello @nemanjai @compnerd, please let me know how to proceed on this further.

Wed, Dec 19, 5:08 PM

Dec 13 2018

nemanjai added a comment to D55503: Change llvm call once check for building Swift for PowerPC(ppc64le).

The Swift 5.0 toolchain on PowerPC64LE also works fine if we remove the "defined(ppc)" check altogether in the original code i.e keep only "!(defined(NetBSD) || defined(OpenBSD)))".
Would that affect other PPC platforms (32/64 and BE/LE PPC other than PowerPC64LE)?

Dec 13 2018, 7:58 AM

Dec 12 2018

nemanjai added a comment to D55503: Change llvm call once check for building Swift for PowerPC(ppc64le).

Yeah, as we discussed over IRC, all I was suggesting is that there is a difference when we choose one over the other with this patch. But I don't think we really care about endianness here, so we might want to just change this to defined(__ppc__) || defined(__PPC__) so we always define LLVM_THREADING_USE_STD_CALL_ONCE the same way on all PPC platforms.

Dec 12 2018, 12:29 PM
nemanjai accepted D55499: [PowerPC] intrinsic llvm.eh.sjlj.setjmp should not have flag isBarrier..

Since we have discovered this in the PPC back end but the issue also exists in ARM and X86, it'd be nice to notify @t.p.northover (already a reviewer) and @craig.topper about this potentially needing to change in their back ends as well.

Dec 12 2018, 4:51 AM
nemanjai updated subscribers of D55503: Change llvm call once check for building Swift for PowerPC(ppc64le).

This code has been in place for quite a long time as there is some sort of bug in libstdc++. I don't remember what the problem was but I remember that this was required because of an issue with the GNU C++ runtime.
My concern is that the intent with defining LLVM_THREADING_USE_STD_CALL_ONCE to zero when __ppc__ is defined is that we would use the non GNU one on all PPC platforms.
However, gcc does not define __ppc__.
So the behaviour before this change is that anything built with clang on any PPC system will use the clang version of std::call_once and anything built with gcc will use the GNU version. This was the case on all little endian and big endian systems (both 32 and 64 bit). After this change, this is what the situation will be (compiler-rt == clang's libc++, GNU == GNU libstdc+++):

Dec 12 2018, 4:21 AM

Dec 10 2018

nemanjai accepted D55502: [NFC] [PPC] Store Instructions have a destination not a source.

:) It seems these have been around for a long time and nobody bothered to fix it. Thanks for fixing this.

Dec 10 2018, 4:44 PM
nemanjai added inline comments to rL348585: [Targets] Add errors for tiny and kernel codemodel on targets that don't….
Dec 10 2018, 11:08 AM

Dec 7 2018

nemanjai added a comment to D55143: [PowerPC][NFC] Sorting out Pseudo related classes to avoid confusion.

I am definitely on board with this refactoring since it makes the purpose of the various pseudo instructions more clear.
However, I really don't like the name PhonyInst. These will lead to real instructions being emitted during emit time. I think we should name these according to when we expect to expand these (similarly to what you did for the custom inserter ones).
The names should reflect the uses:

  • Custom inserter
  • Post-RA expansion
  • Emit-time expansion
  • Asm parser expansion (PPCAsmPseudo)
Dec 7 2018, 5:34 AM

Dec 6 2018

nemanjai added a comment to D55192: [PowerPC] VSX register support for inline assembly.

I suppose since it is in the ABI, it is fine to leave the magic numbers there. And thanks for adding the comment. However, please verify that this mapping applies for ELF v1 as well and if it doesn't please add an appropriate guard.

Dec 6 2018, 9:42 AM
nemanjai added inline comments to D55192: [PowerPC] VSX register support for inline assembly.
Dec 6 2018, 7:06 AM
nemanjai added inline comments to D54911: [compiler-rt][builtins][PowerPC] Add ___fixunstfti builtin compiler-rt method support for PowerPC .
Dec 6 2018, 6:04 AM

Nov 30 2018

nemanjai added a comment to D54313: [compiler-rt][builtins][PowerPC] Add floattitf builtin compiler-rt method support for PowerPC .

I'll let @renenkel approve or request changes to this as he understands the math much better than I do, but I do want an investigation into how the INFINITY/QNAN tests work along with a comment explaining that. Particularly since I would have expected that every __int128_t value is a number (i.e. not a NAN) and none of them produce an infinity.

Nov 30 2018, 9:12 AM
nemanjai accepted D54449: [compiler-rt][builtins][PowerPC] Enable builtins tests on PowerPC 64 bit LE .

Let's add the #include for the file that defines the pertinent macros and push this change so we start running the test cases on PPC64LE.

Nov 30 2018, 8:26 AM

Nov 26 2018

nemanjai added a comment to D54824: [PowerPC] [NFC] Add test cases to the ISD::BR_CC node in the instruction selection.

Personally, I don't like writing the test case using such script. Because, it will check all the instructions and make your test point unclear. And it hard code the register name, which make this test fragile。

Nov 26 2018, 10:50 AM
nemanjai added a comment to D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.

Please let me know if there are any further comments from anyone. Otherwise, we can probably proceed with this.

Nov 26 2018, 10:29 AM
nemanjai added a comment to D54906: [LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT..

The PPC changes seem to be neutral, so no objection from me. Would you mind adding a comment to https://reviews.llvm.org/D54663 if this gets committed before that one as I'll have to update the patch? I'll do the same if I commit mine first.

Nov 26 2018, 10:26 AM
nemanjai committed rC347556: [PowerPC] Vector load/store builtins overstate alignment of pointers.
[PowerPC] Vector load/store builtins overstate alignment of pointers
Nov 26 2018, 6:38 AM
nemanjai committed rL347556: [PowerPC] Vector load/store builtins overstate alignment of pointers.
[PowerPC] Vector load/store builtins overstate alignment of pointers
Nov 26 2018, 6:38 AM
nemanjai closed D54787: [PowerPC] Vector load/store builtins overstate alignment of pointers.
Nov 26 2018, 6:38 AM

Nov 21 2018

nemanjai created D54787: [PowerPC] Vector load/store builtins overstate alignment of pointers.
Nov 21 2018, 4:32 AM

Nov 20 2018

nemanjai committed rL347376: [PowerPC] Do not use vectors to codegen bswap with Altivec turned off.
[PowerPC] Do not use vectors to codegen bswap with Altivec turned off
Nov 20 2018, 6:56 PM
nemanjai added inline comments to D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.
Nov 20 2018, 6:35 PM
nemanjai accepted D54738: [PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction.

LGTM.

Nov 20 2018, 6:44 AM
nemanjai accepted D54700: [PowerPC] Add Itineraries for STWU/STWUX etc.

LGTM.

Nov 20 2018, 6:42 AM
nemanjai accepted D54699: [PowerPC][NFC]Add testcase for STWU scheduling check.

Feel free to just commit patches like this. It appears you're just adding a test case ahead of a patch to make the review easier as it shows only the diffs in code gen.

Nov 20 2018, 6:41 AM

Nov 19 2018

nemanjai committed rL347288: [PowerPC] Don't combine to bswap store on 1-byte truncating store.
[PowerPC] Don't combine to bswap store on 1-byte truncating store
Nov 19 2018, 8:45 PM
nemanjai added inline comments to rL347246: Fix build break from r347239.
Nov 19 2018, 11:14 AM
nemanjai added inline comments to rL347246: Fix build break from r347239.
Nov 19 2018, 11:08 AM

Nov 16 2018

nemanjai added a comment to D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.

The "recent patch" mentioned in the description is https://reviews.llvm.org/D53346.

Nov 16 2018, 10:39 PM
nemanjai updated the diff for D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.

Actually, the handling for v2i32 is already optimal due to the DAG combine that handles this. We'll leave it in the DAG combine since that handles extractions even if they didn't come from legalizing v2i32 types (i.e. it handles a superset of the legalization added here).

Nov 16 2018, 10:38 PM
nemanjai created D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.
Nov 16 2018, 9:51 PM
nemanjai updated the diff for D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.

Removed the actual definitions of the static arrays from the header. Simply provided the macro for the defs in the header and the macro is used in only the two CU's that need it.
This way if we need to add any new ones, they just need to be added to the macro.

Nov 16 2018, 1:01 PM
nemanjai committed rL347090: [PowerPC][NFC] Add tests for vector fp <-> int conversions.
[PowerPC][NFC] Add tests for vector fp <-> int conversions
Nov 16 2018, 12:26 PM

Nov 14 2018

nemanjai added inline comments to D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.
Nov 14 2018, 12:35 PM

Nov 13 2018

nemanjai accepted D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.

LGTM now that we don't bitcast types any longer.

Nov 13 2018, 8:22 AM
nemanjai added a comment to D54449: [compiler-rt][builtins][PowerPC] Enable builtins tests on PowerPC 64 bit LE .

Conceptually, COMPILER_RT_ABI is the calling convention used by all compiler-rt functions. It is explicitly named and used because it may be different from the default calling convention on some targets. In practice I believe it only affects ARM, where the calling convention uses ARM's soft-float ABI (where IIRC floats are passed in integer registers) even on targets that use the hard-float ABI by default. The compiler knows the calling conventions and emits the right code when it emits the libcalls, and the ABI declaration on the implementations causes the right calling convention to be used there. The unusual thing about the tests is that they locally declare the compiler-rt functions explicitly. So this declaration has to match the implementation. It may not matter for PPC but my recommendation would be "just use it everywhere in compiler-rt" for simplicity.

Nov 13 2018, 5:27 AM

Nov 12 2018

nemanjai added inline comments to D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.
Nov 12 2018, 8:22 PM
nemanjai added a reviewer for D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser: jsji.
Nov 12 2018, 8:22 PM
nemanjai updated the diff for D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.

This is how I meant to do it initially but was reluctant to introduce a new header dependency. However, I don't think it's an issue at all for PPCMCTargetDesc.h to have a dependency on MC/MCRegisterInfo.h.

Nov 12 2018, 8:21 PM
nemanjai updated the diff for D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.

Did the same for the disassembler.

Nov 12 2018, 10:31 AM
nemanjai created D54433: [PowerPC][NFC] Macro for register set defs for the Asm Parser.
Nov 12 2018, 9:50 AM

Nov 9 2018

nemanjai added inline comments to D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type.
Nov 9 2018, 1:24 PM

Nov 8 2018

nemanjai added a comment to D53417: [Clang][Sema]Choose a better candidate in overload function call if there is a compatible vector conversion instead of ambiguous call error.

@hubert.reinterpretcast Have your comments been addressed adequately in the latest version of the patch? Do you have an opinion on adding the test case I proposed?

Nov 8 2018, 8:33 AM
nemanjai accepted D54087: [PowerPC] [Clang] [AltiVec] The second parameter of vec_sr function should be modulo the number of bits in the element.

Just for clarification (and please add the text to the commit message), this is actually required by the ABI:

Each element of the result vector is the result of logically right shifting the corresponding
element of ARG1 by the number of bits specified by the value of the corresponding
element of ARG2, modulo the number of bits in the element. The bits that are shifted out
are replaced by zeros.
Nov 8 2018, 8:26 AM

Nov 2 2018

nemanjai accepted D53581: [Power9] Add support for stxvw4x.be and stxvd2x.be intrinsics.

The test case fix can be done on the commit. Approving this now.

Nov 2 2018, 11:52 AM
nemanjai added inline comments to D53384: [PowerPC] Make no-PIC default to match GCC - CLANG.
Nov 2 2018, 8:29 AM
nemanjai accepted D52900: [PowerPC]Disable randomized address space on Linux ppc64le.

Since this fixes the sanitizers on PPC for the newer kernels and the fix seems perfectly reasonable and there are no concerns brought up by anyone, let's go ahead with this fix.

Nov 2 2018, 7:58 AM

Oct 26 2018

nemanjai added inline comments to rL345330: Add MS ABI mangling for operator<=>..
Oct 26 2018, 2:21 AM

Oct 25 2018

nemanjai committed rL345363: [NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py.
[NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py
Oct 25 2018, 8:33 PM
nemanjai closed D53059: [NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py.
Oct 25 2018, 8:33 PM
nemanjai added a comment to rL345357: [PowerPC][NFC] Add tests for some missed optimization opportunities in….

Please revert this. The way this was committed is incorrect. You've created directories such as llvm/trunk/llvm/ which we do not want. I suppose this has something to do with the fact that the patch was created using the monorepo and committed in some different way.

Oct 25 2018, 8:25 PM
nemanjai committed rL345361: [PowerPC] Keep vector int to fp conversions in vector domain.
[PowerPC] Keep vector int to fp conversions in vector domain
Oct 25 2018, 8:21 PM
nemanjai closed D53346: [PowerPC] Keep vector int to fp conversions in vector domain.
Oct 25 2018, 8:21 PM
nemanjai added inline comments to rL345315: [AArch64] Create proper memoperand for multi-vector stores.
Oct 25 2018, 7:32 PM

Oct 23 2018

nemanjai accepted D53346: [PowerPC] Keep vector int to fp conversions in vector domain.

LGTM. Thanks.

Oct 23 2018, 10:27 AM
nemanjai added a comment to D53275: [PowerPC] Exploit power9 new instruction setb.

Since the logic in the switch statement is difficult to follow, I ended up having to test this patch with a script that tries all combinations of comparisons, results and operand order in order to convince myself that it doesn't emit a setb when it is not valid to do so. Everything checks out there, but I don't really have an easy way of testing whether any opportunities are missed.
I am really hoping that you can simplify the logic in that switch to make it easier to follow.

Oct 23 2018, 9:41 AM
nemanjai accepted D49507: [Power9] Add __float128 support in the backend for bitcast to a i128.

I think the changes that are needed are clear enough that this doesn't require another review cycle. Approving this with the assumption that the required change will be made on the commit.

Oct 23 2018, 2:54 AM

Oct 22 2018

nemanjai accepted D53494: [PowerPC] Improve BUILD_VECTOR of 4 i32s.

LGTM.

Oct 22 2018, 8:41 AM
nemanjai added inline comments to D49507: [Power9] Add __float128 support in the backend for bitcast to a i128.
Oct 22 2018, 8:01 AM
nemanjai updated the diff for D53059: [NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py.

Updated the regular expression to just eat any text that is not relevant between the function directive and its text. This seems to work for both ELFv1 and ELFv2 asm output.

Oct 22 2018, 7:41 AM
nemanjai retitled D44528: [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns from [PowerPC] Implement canCombineStoreAndExtract and provide the missing pattern for the combination to [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns.
Oct 22 2018, 5:15 AM
nemanjai updated the diff for D44528: [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns.

Implemented all the patterns for codegen of extract->store.

Oct 22 2018, 5:14 AM
nemanjai committed rL344894: [PowerPC][NFC] Fix bugs in r+r to r+i conversion.
[PowerPC][NFC] Fix bugs in r+r to r+i conversion
Oct 22 2018, 4:26 AM
nemanjai closed D53323: [PowerPC][NFC] Fix bugs in r+r to r+i conversion.
Oct 22 2018, 4:26 AM

Oct 19 2018

nemanjai updated the diff for D53323: [PowerPC][NFC] Fix bugs in r+r to r+i conversion.
Oct 19 2018, 6:27 AM
nemanjai updated the diff for D53323: [PowerPC][NFC] Fix bugs in r+r to r+i conversion.

Modified the changeset to not reduce the capabilities of the pass (select the correct opcode based on the register for post-ra).

Oct 19 2018, 6:19 AM