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nemanjai (Nemanja Ivanovic)
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User Since
Jan 23 2015, 9:38 AM (260 w, 20 h)

Recent Activity

Thu, Jan 16

nemanjai requested changes to D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.

Forgot to select request changes.

Thu, Jan 16, 6:28 AM · Restricted Project, Restricted Project
nemanjai added a comment to D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.

A few more comments need to be addressed for this to proceed.

Thu, Jan 16, 6:25 AM · Restricted Project, Restricted Project

Wed, Jan 15

nemanjai committed rG9c64f04df8ec: [PowerPC] Legalize saturating vector add/sub (authored by nemanjai).
[PowerPC] Legalize saturating vector add/sub
Wed, Jan 15, 5:07 AM
nemanjai closed D71940: [PowerPC] Legalize saturating vector add/sub.
Wed, Jan 15, 5:06 AM · Restricted Project

Mon, Jan 13

nemanjai added inline comments to D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.
Mon, Jan 13, 5:18 PM · Restricted Project, Restricted Project
nemanjai updated the diff for D72660: [PowerPC] Improve handling of some BUILD_VECTOR nodes.

The shift amount for one of the patterns was wrong for little endian.

Mon, Jan 13, 4:32 PM · Restricted Project
nemanjai created D72660: [PowerPC] Improve handling of some BUILD_VECTOR nodes.
Mon, Jan 13, 3:35 PM · Restricted Project
nemanjai added a comment to D72649: [PowerPC][NFC] Reclaim TSFlags bit 6.

This introduces a dependency for https://reviews.llvm.org/D72569.

Mon, Jan 13, 3:17 PM · Restricted Project, Restricted Project
nemanjai accepted D72577: [PowerPC][Future] Add prefixed loads and stores for future CPU.

LGTM.

Mon, Jan 13, 7:25 AM · Restricted Project, Restricted Project
nemanjai accepted D72572: [PowerPC][Future] Branch Distance Estimation For Prefixed Instructions.

Aside from a couple of minor nits, LGTM.

Mon, Jan 13, 7:16 AM · Restricted Project, Restricted Project
nemanjai added a comment to D72579: Evaluate __{c11_,}atomic_is_lock_free to 0 (avoid libcall) if larger than MaxAtomicPromoteWidth.

If I understand this correctly, this just evaluates the query for lock free atomics at compile time if the size is larger than the maximum possible size for an atomic on the target. If that's the case, this looks fine to me. But of course, some of the other target maintainers might feel otherwise.
The incompatibility with GCC might be an issue for some, but I don't expect this to be an issue at least on PPC.

Mon, Jan 13, 7:06 AM · Restricted Project

Sun, Jan 12

nemanjai added a comment to D72574: [PowerPC][Future] Add pld and pstd to future CPU.

Adding Florian, Daniel and Craig as reviewers since they were involved in the most recent change to this area of table gen.

Sun, Jan 12, 11:29 AM · Restricted Project, Restricted Project
nemanjai added reviewers for D72574: [PowerPC][Future] Add pld and pstd to future CPU: dsanders, craig.topper, fhahn.
Sun, Jan 12, 11:29 AM · Restricted Project, Restricted Project
nemanjai accepted D68411: Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp.

Forgot to accept.

Sun, Jan 12, 10:21 AM · Restricted Project
nemanjai added a comment to D68411: Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp.

LGTM other than a minor nit that can be addressed on the commit.

Sun, Jan 12, 10:15 AM · Restricted Project
nemanjai accepted D71600: PowerPC 32-bit - forces 8 byte lock/lock_free decisions at compiled time.

LGTM.

Sun, Jan 12, 10:15 AM · Restricted Project, Restricted Project, Restricted Project
nemanjai requested changes to D69066: Add support for intrinsic llvm.ppc.eieio.

The code looks fine to me, but where is the test case?

Sun, Jan 12, 10:06 AM · Restricted Project
nemanjai accepted D72063: [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin.

Thanks for removing this. LGTM.

Sun, Jan 12, 9:57 AM · Restricted Project
nemanjai added inline comments to D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.
Sun, Jan 12, 9:53 AM · Restricted Project, Restricted Project
nemanjai added a comment to D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.

Missing context on this review. Please produce the diff with -U99999 or arc to ensure full context is available.

Sun, Jan 12, 9:35 AM · Restricted Project, Restricted Project
nemanjai added a reviewer for D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU: Restricted Project.
Sun, Jan 12, 9:26 AM · Restricted Project, Restricted Project
nemanjai accepted D72570: [PowerPC][Future] Prefixed Instructions 64 Byte Boundary Support.

Other than a few minor nits, LGTM.

Sun, Jan 12, 9:26 AM · Restricted Project, Restricted Project

Fri, Jan 10

nemanjai committed rGd864d93496c5: [PowerPC] Handle constant zero bits in BitPermutationSelector (authored by nemanjai).
[PowerPC] Handle constant zero bits in BitPermutationSelector
Fri, Jan 10, 8:02 AM
nemanjai closed D72038: [PowerPC] Handle constant zero bits in BitPermutationSelector.
Fri, Jan 10, 8:02 AM · Restricted Project

Thu, Jan 9

nemanjai accepted D69835: Add options for PPC to enable/disable using non-volatile CR.

The remaining comments are stylistic nits that can be addressed on the commit. Assuming that those will be fixed, LGTM.

Thu, Jan 9, 4:14 AM · Restricted Project

Fri, Jan 3

nemanjai added a comment to D68411: Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp.
In D68411#1718116, @lei wrote:

Since these are just mnemonics for using dcbf, why not just add the tests to llvm/test/CodeGen/PowerPC/dcbf.ll instead of creating 2 small test files.

These are mnemonics true, but we have separate intrinsics for them as opposed to using one intrinsic with different constants and also the assembly code is different.
I think having multiple files gives more structure and in theory reduces chances of merge conflicts.

Fri, Jan 3, 5:38 AM · Restricted Project
nemanjai added inline comments to D71883: [PowerPC] Use PredictableSelectIsExpensive to enable select to branch in CGP.
Fri, Jan 3, 5:29 AM · Restricted Project
nemanjai added a comment to D70108: [TTI] Added TTI pass queries for max load/store-per-memory-intrinsic..

I realize that without any uses of these functions, we can't really add a test case. However, can we at least get a description of why this is useful in the middle end if this patch won't add any users of these functions?

Fri, Jan 3, 5:14 AM · Restricted Project

Thu, Jan 2

nemanjai committed rG781b78a36108: [PowerPC] Only legalize FNEARBYINT with unsafe fp math (authored by nemanjai).
[PowerPC] Only legalize FNEARBYINT with unsafe fp math
Thu, Jan 2, 11:54 AM
nemanjai added a comment to D71693: [NFC][PowerPC] Add a function tryAndWithMask.

I think this refactoring doesn't really do anything to simplify the code or make it more readable. It just takes fairly complex logic and moves it into a separate function. Then subsequent patches will add even further complexity to this function. Overall, there isn't much of a gain from the refactoring.
What I think would make sense is to simplify the tryAndWithMask() to something conceptually similar to the following:

tryAndWithMask(...) {
  if (canBeCodeGenedAsSingleRLWINM())
    return produceRLWINMSDNode();
  if (canBeCodeGenedAsSingleRLWIMI())
    return produceRLWIMISDNode();
  if (canBeCodeGenedAsSingleRLDICL())
    return produceRLDICLSDNode();
  if (canBeCodeGenedAsPairOfRLDICL())
    return produceRLDICLPairSDNode();
  ...
  return SDValue();
Thu, Jan 2, 9:40 AM · Restricted Project
nemanjai added a reviewer for D72067: [PowerPC] Delete PPCSubtarget::isDarwin and isDarwinABI: cebowleratibm.
Thu, Jan 2, 6:01 AM · Restricted Project
nemanjai updated subscribers of D72067: [PowerPC] Delete PPCSubtarget::isDarwin and isDarwinABI.

The code you are modifying should be unreachable and should be safe to remove. However, can you please provide a description with some rationale about why you are removing this now. Namely, is there a pressing concern to get this removed soon or is this just a regular cleanup?

Thu, Jan 2, 6:01 AM · Restricted Project

Wed, Jan 1

nemanjai accepted D71946: [PowerPC][LoopVectorize] Extend getRegisterClassForType to consider double and other floating point type.

LGTM but maybe give the original author a day or two to have a look as well before committing.

Wed, Jan 1, 7:24 PM · Restricted Project

Tue, Dec 31

nemanjai updated the diff for D72038: [PowerPC] Handle constant zero bits in BitPermutationSelector.

Run git-clang-format.
I don't want to address the clang-tidy check results as I don't really want to change the induction variable from i to I. The former is ubiquitous.

Tue, Dec 31, 12:15 PM · Restricted Project
nemanjai created D72038: [PowerPC] Handle constant zero bits in BitPermutationSelector.
Tue, Dec 31, 11:45 AM · Restricted Project

Mon, Dec 30

nemanjai accepted D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I would say that this is as close to a [perhaps begrudging] consensus as we'll get. Lets get this bike shed built. Please go ahead with the commit. LGTM.

Mon, Dec 30, 7:55 PM · Restricted Project
nemanjai added a comment to D71287: [PowerPC] Use fcti[dw] instructions in additional cases.

I have pushed the other patch now. Please rebase this patch against ToT.

Mon, Dec 30, 6:29 AM · Restricted Project
nemanjai updated the diff for D71940: [PowerPC] Legalize saturating vector add/sub.

Add a comment for the patterns.

Mon, Dec 30, 6:21 AM · Restricted Project
nemanjai added inline comments to D71940: [PowerPC] Legalize saturating vector add/sub.
Mon, Dec 30, 6:19 AM · Restricted Project
nemanjai committed rG0f0330a78709: [PowerPC] Legalize rounding nodes (authored by nemanjai).
[PowerPC] Legalize rounding nodes
Mon, Dec 30, 6:10 AM
nemanjai closed D69949: [PowerPC] Legalize rounding nodes.
Mon, Dec 30, 6:10 AM · Restricted Project

Sat, Dec 28

nemanjai committed rGb6cf400aaeae: Fix bots after a9ad65a2b34f (authored by nemanjai).
Fix bots after a9ad65a2b34f
Sat, Dec 28, 11:11 AM
nemanjai committed rGa9ad65a2b34f: [PowerPC] Change default for unaligned FP access for older subtargets (authored by nemanjai).
[PowerPC] Change default for unaligned FP access for older subtargets
Sat, Dec 28, 9:44 AM
nemanjai closed D71954: [PowerPC] Change default for unaligned FP access for older subtargets.
Sat, Dec 28, 9:43 AM · Restricted Project

Fri, Dec 27

nemanjai updated the diff for D71954: [PowerPC] Change default for unaligned FP access for older subtargets.

Add the feature to the BG cores as well.

Fri, Dec 27, 8:18 PM · Restricted Project
nemanjai created D71954: [PowerPC] Change default for unaligned FP access for older subtargets.
Fri, Dec 27, 8:18 PM · Restricted Project
nemanjai added a comment to D68237: [PowerPC] Handle f16 as a storage type only.

This should fix https://bugs.llvm.org/show_bug.cgi?id=39865

Fri, Dec 27, 6:33 PM · Restricted Project
nemanjai added inline comments to D71946: [PowerPC][LoopVectorize] Extend getRegisterClassForType to consider double and other floating point type.
Fri, Dec 27, 1:33 PM · Restricted Project
nemanjai added a comment to D71287: [PowerPC] Use fcti[dw] instructions in additional cases.

The conflict I see is the other patch uses VSX for the operations, but this uses instructions that have been around as far back as the PPC970.

Fri, Dec 27, 10:43 AM · Restricted Project
nemanjai created D71940: [PowerPC] Legalize saturating vector add/sub.
Fri, Dec 27, 9:37 AM · Restricted Project
nemanjai added a comment to D65967: [SeparateConstOffsetFromGEP][PowerPC] Fix: sext(a) + sext(b) -> sext(a + b) matches add and sub instructions with one another.

Sorry for the delay- I had to investigate some of the fragility so that my test case reduced to this pass would still trigger the issue. However, I did manage to get a test case that is only a few lines long that would trigger the issue without the update.

Fri, Dec 27, 7:59 AM · Restricted Project
nemanjai accepted D69982: PPC: Prepare tests for switch of default denormal-fp-math.

This seems straightforward to me - I assume the constant pool load in the test case is some value denoting the smallest normal value for the type. Then rather than comparing against zero do determine when to return zero, we compare against that value (after taking the absolute value).

Fri, Dec 27, 4:38 AM · Restricted Project
nemanjai added a comment to D71287: [PowerPC] Use fcti[dw] instructions in additional cases.

Please refer to https://reviews.llvm.org/D69949 that is about to be committed. I haven't looked at this patch but it seems related/overlapping. If there is an unforeseen issue with the other patch, please comment there.

Fri, Dec 27, 3:35 AM · Restricted Project

Dec 17 2019

nemanjai committed rGa5da8d90daa3: [PowerPC] Add missing legalization for vector BSWAP (authored by nemanjai).
[PowerPC] Add missing legalization for vector BSWAP
Dec 17 2019, 5:09 PM
nemanjai closed D70436: [PowerPC] Add missing legalization for vector BSWAP.
Dec 17 2019, 5:09 PM · Restricted Project
nemanjai added a comment to rGddd0bb8dba2a: [lit] Remove lit's REQUIRES-ANY directive.

I committed https://reviews.llvm.org/rGba5a00167bf30df5d544fdbe9fd28ce1a8341b89 to fix the bots. Please review that patch. If the fix is not quite as desired, please update it but I wanted to make sure to commit it to get the bots back to green.

Dec 17 2019, 2:20 PM
nemanjai committed rGba5a00167bf3: Fix buildbot failures after removing REQUIRES-ANY (authored by nemanjai).
Fix buildbot failures after removing REQUIRES-ANY
Dec 17 2019, 1:36 PM
nemanjai added a comment to rGddd0bb8dba2a: [lit] Remove lit's REQUIRES-ANY directive.

This commit (or one of the related ones in the series) has caused all the build bots to fail.

Dec 17 2019, 1:35 PM
nemanjai accepted D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.

LGTM.

Dec 17 2019, 11:07 AM · Restricted Project
nemanjai accepted D71346: [PowerPC] support loop ds form prep for lwa.

Other than the minor nit about readability, LGTM.

Dec 17 2019, 10:56 AM · Restricted Project
nemanjai added a comment to D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0.

Something doesn't match up here. The description/title say that you are changing the flag for both MFLR/MTLR. But in the code I only see the change for MTLR. Why is that?
Also, the context is missing from this patch so it cannot be reviewed properly, please fix that.

Dec 17 2019, 10:35 AM · Restricted Project

Dec 6 2019

nemanjai abandoned D71113: Recover shared libs build after 9e8c799e2b0dc3e3b20f5044309fa8e48e8e3e32.
In D71113#1772573, @avl wrote:

Hi @nemanjai I has recently integrated the fix for that problem https://reviews.llvm.org/rG8c714c93023d7d039a23fb47c8256570ba54b9c7 . I am sorry for inconvenience.

Dec 6 2019, 7:34 AM · Restricted Project
nemanjai created D71113: Recover shared libs build after 9e8c799e2b0dc3e3b20f5044309fa8e48e8e3e32.
Dec 6 2019, 5:25 AM · Restricted Project
nemanjai added a comment to rG9e8c799e2b0d: [Dsymutil][NFC] Move NonRelocatableStringpool into common CodeGen folder..

This breaks the shared libraries builds. An example on a build bot: http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/11299

Dec 6 2019, 5:16 AM

Dec 3 2019

nemanjai added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I was originally going to suggest a more verbose suffix much as Hal suggested, since any single letter is kind of meaningless. But to be honest, I hate the added verbosity and feel that instruction mnemonics are just an inherently tricky thing that requires experience with the ISA document.

Dec 3 2019, 4:32 AM · Restricted Project

Dec 2 2019

nemanjai added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

Yeah, I actually added my initial comment precisely because I thought the existing form is more familiar to those that do not have deep experience with the ISA. What I mean is that the r is fairly intuitive to those of us that are deeply familiar with the ISA - it means "record-form". But to those less familiar with the ISA, the phrase "record-form" may be completely foreign and the choice of r would then be quite confusing. Whereas looking at the mnemonics in the ISA:

Dec 2 2019, 2:56 PM · Restricted Project
nemanjai requested changes to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I am going to mark this as requiring changes until we can get more consensus on the direction. This is a very pervasive change that is completely subjective and as such should require agreement from more than two people that work on the target.

Dec 2 2019, 1:48 PM · Restricted Project
nemanjai committed rG241cbf201a6f: [PowerPC] Fix crash in peephole optimization (authored by nemanjai).
[PowerPC] Fix crash in peephole optimization
Dec 2 2019, 6:59 AM

Nov 28 2019

nemanjai added a comment to rG9d24933f79dd: Recommit f0c2a5a "[LV] Generalize conditions for sinking instrs for first order….

Hi Florian, this appears to break some of our downstream builds. Here's a minimal test case:

Nov 28 2019, 12:22 PM

Nov 27 2019

nemanjai added a comment to D70720: [llvm-objdump] Display locations of variables alongside disassembly.

This looked really cool so I thought I'd try it on PPC. I hit the unreachable for an unknown op: <unknown op DW_OP_regx (144)>unknown op.

Nov 27 2019, 4:11 AM · debug-info, Restricted Project

Nov 25 2019

nemanjai committed rG4d5c8caf9b4b: [LLD] Add a default copy constructor to avoid warnings (authored by nemanjai).
[LLD] Add a default copy constructor to avoid warnings
Nov 25 2019, 12:10 PM
nemanjai committed rG7fbaa8097ecc: [PowerPC] Fix VSX clobbers of CSR registers (authored by nemanjai).
[PowerPC] Fix VSX clobbers of CSR registers
Nov 25 2019, 9:47 AM
nemanjai closed D68576: [PowerPC] Fix VSX clobbers of CSR registers.
Nov 25 2019, 9:47 AM · Restricted Project
nemanjai accepted D70657: [Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics of ISD::BSWAP.

Thanks for cleaning this up. This seems completely obvious and non-controversial to me. Feel free to commit once the dependent patch lands.

Nov 25 2019, 4:14 AM · Restricted Project
nemanjai added inline comments to D70436: [PowerPC] Add missing legalization for vector BSWAP.
Nov 25 2019, 4:14 AM · Restricted Project

Nov 23 2019

nemanjai added a comment to rG9353c5dd0664: [Diagnostics] Put "deprecated copy" warnings into -Wdeprecated-copy.

Disabled -Werror on sanitizer bots.

Nov 23 2019, 8:50 AM

Nov 22 2019

nemanjai requested changes to D70223: [DAGCombine] Split vector load-update-store into single element stores.

This changeset is a rather complicated and hard-to-follow piece of code that appears to solve a problem in the motivating test case, but makes it rather unclear whether it is a good idea or a bad idea overall.
There are a number of things that need to be clarified for this patch to proceed:

  1. Needs empirical performance data. This is straightforward - see if it affects the performance of any benchmarks.
  2. Needs more thorough testing. We need to cover more types, more ways we may end up with these "merge-and-store" idioms, different numbers of elements changed, etc.
  3. An overview of the algorithm should be provided to aid readability. The code as written does not exactly aid readability so it would be good to provide an outline.
  4. I still think we should do this in InstCombine rather than on the SDAG. It seems like that would be a more natural place to do this.
  5. If we are doing it in InstCombine, why not simply produce a masked store? If we converted the IR for the test case in the description to this:
define dso_local void @foo(<4 x float>* nocapture %a, float %b) local_unnamed_addr #0 {
entry:
  call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> <float 1.000000e+00, float undef, float undef, float 2.000000e+00>, <4 x float>* %a, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 true>)
  ret void
}
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)

We will get the desired codegen:

lis 4, 16256
lis 5, 16384
stw 4, 0(3)
stw 5, 12(3)

And there is target-independent handling for masked stores, so it is not at all clear to me why we'd go through the trouble of implementing this complex handling in the SDAG.

Nov 22 2019, 6:14 AM · Restricted Project

Nov 21 2019

nemanjai added a comment to D70223: [DAGCombine] Split vector load-update-store into single element stores.

Added Eli and Justin in case they are interested in chiming in on at least the target-independent parts of this.

Nov 21 2019, 5:59 AM · Restricted Project
nemanjai added reviewers for D70223: [DAGCombine] Split vector load-update-store into single element stores: efriedma, bogner.
Nov 21 2019, 5:59 AM · Restricted Project
nemanjai accepted D70466: [PowerPC] Separate Features that are known to be Power9 specific from Future CPU.

LGTM with some clarification in a comment.

Nov 21 2019, 5:59 AM · Restricted Project
nemanjai accepted D70333: [PowerPC] Add new Future CPU for PowerPC in LLVM.

LGTM.

Nov 21 2019, 5:40 AM · Restricted Project
nemanjai accepted D70262: [PowerPC] Add new Future CPU for PowerPC.

LGTM.

Nov 21 2019, 4:42 AM · Restricted Project
nemanjai accepted D69730: [compiler-rt][builtins][PowerPC] Add __fixtfti builtin on PowerPC.

LGTM. Thank you.

Nov 21 2019, 4:12 AM · Restricted Project, Restricted Project
nemanjai requested changes to D69835: Add options for PPC to enable/disable using non-volatile CR.

This needs to be a property of PPCFunctionInfo and set when the option is provided.

Nov 21 2019, 4:01 AM · Restricted Project

Nov 20 2019

nemanjai added a comment to D70466: [PowerPC] Separate Features that are known to be Power9 specific from Future CPU.

The feature list here assume that, new processor will contain superset of features of those that came before it. And we are trying to break the assumption here. Can we do it another way. That is, keep the TD unchanged and check the CPU Directive in PPCSubtarget ? i.e.

PPCSubtarget::vectorsUseTwoUnits() const { return VectorsUseTwoUnits && DarwinDirective == PPC::DIR_PWR9; }
Nov 20 2019, 10:39 AM · Restricted Project

Nov 19 2019

nemanjai planned changes to D70015: [PowerPC] Improve vectorization of loops that operate on values that are extended in the body.

I need to add some additional pieces to this.

Nov 19 2019, 5:26 AM · Restricted Project
nemanjai created D70436: [PowerPC] Add missing legalization for vector BSWAP.
Nov 19 2019, 5:17 AM · Restricted Project
nemanjai accepted D55326: [Driver] Fix incorrect GNU triplet for PowerPC on SUSE Linux.

LGTM. Thanks for adding the test case.

Nov 19 2019, 4:51 AM · Restricted Project
nemanjai accepted D69168: [PowerPC] Fold redundant load immediates of zero and delete if possible.

LGTM except for formatting nits. Thanks for addressing the comments.

Nov 19 2019, 4:41 AM · Restricted Project

Nov 15 2019

nemanjai added a reviewer for D45267: [PowerPC] Combine BUILD_VECTOR of int to fp conversions: Restricted Project.
Nov 15 2019, 1:21 PM · Restricted Project
nemanjai updated the diff for D45267: [PowerPC] Combine BUILD_VECTOR of int to fp conversions.

Rebased with the current source tree.
Updated the new test cases.
Improved some of the handling for the target pattern.
Refactored some of the original combines as the new combine overrode what they do.
Fixed some issue in the combine for load/convert/splat which were exposed by the new combine.

Nov 15 2019, 1:21 PM · Restricted Project
nemanjai added a comment to D68576: [PowerPC] Fix VSX clobbers of CSR registers.

Thanks for your comments. I'll address them and commit this.

Nov 15 2019, 1:13 PM · Restricted Project
nemanjai added a comment to D69497: [PowerPC] Fix MI peephole optimization for splats.

Also, I noticed in the case PPC::XXPERMDI: block there are a couple of nested ifs without elses and checks on ifs that could simplified by converted to early breaks, albeit at the cost of polluting git blame with whitespace differences. Let me know if you are interested in a separate patch to clean some of that up.

Nov 15 2019, 1:04 PM · Restricted Project
nemanjai accepted D69497: [PowerPC] Fix MI peephole optimization for splats.

LGTM. Thank you for your patience.

Nov 15 2019, 1:04 PM · Restricted Project

Nov 11 2019

nemanjai committed rG70193b21d18b: [NFC] Fix test case after edab7dd426249bd40059b49b255ba9cc5b784753 (authored by nemanjai).
[NFC] Fix test case after edab7dd426249bd40059b49b255ba9cc5b784753
Nov 11 2019, 6:45 PM

Nov 9 2019

nemanjai added inline comments to D69601: [Power9] Implement the vector extend sign instruction pattern match.
Nov 9 2019, 8:07 AM · Restricted Project

Nov 8 2019

nemanjai created D70015: [PowerPC] Improve vectorization of loops that operate on values that are extended in the body.
Nov 8 2019, 10:17 AM · Restricted Project

Nov 7 2019

nemanjai committed rGe0407f549653: [PowerPC][Altivec] Fix offsets for vec_xl and vec_xst (authored by nemanjai).
[PowerPC][Altivec] Fix offsets for vec_xl and vec_xst
Nov 7 2019, 7:04 PM
nemanjai closed D63636: [PowerPC][Altivec] Fix offsets for vec_xl and vec_xst.
Nov 7 2019, 7:04 PM · Restricted Project
nemanjai committed rG070e4027b024: [PowerPC][Altivec] Emit correct builtin for single precision vec_all_ne (authored by nemanjai).
[PowerPC][Altivec] Emit correct builtin for single precision vec_all_ne
Nov 7 2019, 6:45 PM