[1/9] patch series to port HWASAN for riscv64
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LGTM. This makes sense. It may also simplify some of https://reviews.llvm.org/D128612
llvm/include/llvm/ADT/Triple.h | ||
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862 | The order "32-bit RISC-V" is more common. |
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Can we re-title this revision to something like [Triple] Add isRISCV32 and isRISCV64? First reading of the phrase "add explicit check" makes me think there's an if statement being added somewhere.
The order "32-bit RISC-V" is more common.