[Alignment][NFC] Remove unneeded llvm:: scoping on Align types

[courbet]

llvm/include/llvm/CodeGen/AsmPrinter.h

353

This works but is not ideal.

[gchatelet]

• Fix Align Align
• Also fix llvm::Align(<literal>)

[courbet]

llvm/include/llvm/CodeGen/CallingConvLower.h

428

Given that this is a public API it would be better to have a meaningful name - maybe use Alignment in the API and rename to CheckedAlignment in the implementation ?

llvm/include/llvm/Support/OnDiskHashTable.h

211 ↗

(On Diff #222106)

remve llvm::

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

509

Alignment ?

2937–2938

ditto

[gchatelet]

• Address comments

[gchatelet]

PTAL

[gchatelet]

thx!

[gchatelet]

Submitted as rL373081

llvm/include/llvm/Analysis/TargetTransformInfo.h

public:
   bool shouldFavorBackedgeIndex(const Loop *L) const;
 
   /// Return true if the target supports masked load.
   bool isLegalMaskedStore(Type *DataType) const;
   /// Return true if the target supports masked store.
   bool isLegalMaskedLoad(Type *DataType) const;
 
   /// Return true if the target supports nontemporal store.
-  bool isLegalNTStore(Type *DataType, llvm::Align Alignment) const;
+  bool isLegalNTStore(Type *DataType, Align Alignment) const;
   /// Return true if the target supports nontemporal load.
-  bool isLegalNTLoad(Type *DataType, llvm::Align Alignment) const;
+  bool isLegalNTLoad(Type *DataType, Align Alignment) const;
 
   /// Return true if the target supports masked scatter.
   bool isLegalMaskedScatter(Type *DataType) const;
   /// Return true if the target supports masked gather.
   bool isLegalMaskedGather(Type *DataType) const;
 
   /// Return true if the target supports masked compress store.
   bool isLegalMaskedCompressStore(Type *DataType) const;
public:
   virtual bool canMacroFuseCmp() = 0;
   virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
                           LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC,
                           TargetLibraryInfo *LibInfo) = 0;
   virtual bool shouldFavorPostInc() const = 0;
   virtual bool shouldFavorBackedgeIndex(const Loop *L) const = 0;
   virtual bool isLegalMaskedStore(Type *DataType) = 0;
   virtual bool isLegalMaskedLoad(Type *DataType) = 0;
-  virtual bool isLegalNTStore(Type *DataType, llvm::Align Alignment) = 0;
-  virtual bool isLegalNTLoad(Type *DataType, llvm::Align Alignment) = 0;
+  virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
+  virtual bool isLegalNTLoad(Type *DataType, Align Alignment) = 0;
   virtual bool isLegalMaskedScatter(Type *DataType) = 0;
   virtual bool isLegalMaskedGather(Type *DataType) = 0;
   virtual bool isLegalMaskedCompressStore(Type *DataType) = 0;
   virtual bool isLegalMaskedExpandLoad(Type *DataType) = 0;
   virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
   virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
   virtual bool prefersVectorizedAddressing() = 0;
   virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
bool shouldFavorBackedgeIndex(const Loop *L) const override {
     return Impl.shouldFavorBackedgeIndex(L);
   }
   bool isLegalMaskedStore(Type *DataType) override {
     return Impl.isLegalMaskedStore(DataType);
   }
   bool isLegalMaskedLoad(Type *DataType) override {
     return Impl.isLegalMaskedLoad(DataType);
   }
-  bool isLegalNTStore(Type *DataType, llvm::Align Alignment) override {
+  bool isLegalNTStore(Type *DataType, Align Alignment) override {
     return Impl.isLegalNTStore(DataType, Alignment);
   }
-  bool isLegalNTLoad(Type *DataType, llvm::Align Alignment) override {
+  bool isLegalNTLoad(Type *DataType, Align Alignment) override {
     return Impl.isLegalNTLoad(DataType, Alignment);
   }
   bool isLegalMaskedScatter(Type *DataType) override {
     return Impl.isLegalMaskedScatter(DataType);
   }
   bool isLegalMaskedGather(Type *DataType) override {
     return Impl.isLegalMaskedGather(DataType);
   }

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

public:
   bool shouldFavorPostInc() const { return false; }
 
   bool shouldFavorBackedgeIndex(const Loop *L) const { return false; }
 
   bool isLegalMaskedStore(Type *DataType) { return false; }
 
   bool isLegalMaskedLoad(Type *DataType) { return false; }
 
-  bool isLegalNTStore(Type *DataType, llvm::Align Alignment) {
+  bool isLegalNTStore(Type *DataType, Align Alignment) {
     // By default, assume nontemporal memory stores are available for stores
     // that are aligned and have a size that is a power of 2.
     unsigned DataSize = DL.getTypeStoreSize(DataType);
     return Alignment >= DataSize && isPowerOf2_32(DataSize);
   }
 
-  bool isLegalNTLoad(Type *DataType, llvm::Align Alignment) {
+  bool isLegalNTLoad(Type *DataType, Align Alignment) {
     // By default, assume nontemporal memory loads are available for loads that
     // are aligned and have a size that is a power of 2.
     unsigned DataSize = DL.getTypeStoreSize(DataType);
     return Alignment >= DataSize && isPowerOf2_32(DataSize);
   }
 
   bool isLegalMaskedScatter(Type *DataType) { return false; }
 

llvm/include/llvm/CodeGen/AsmPrinter.h

public:
   /// Check to see if the specified global is a special global used by LLVM. If
   /// so, emit it and return true, otherwise do nothing and return false.
   bool EmitSpecialLLVMGlobal(const GlobalVariable *GV);
 
   /// Emit an alignment directive to the specified power of two boundary. If a
   /// global value is specified, and if that global has an explicit alignment
   /// requested, it will override the alignment request if required for
   /// correctness.
-  void EmitAlignment(llvm::Align Align, const GlobalObject *GV = nullptr) const;
+  void EmitAlignment(Align Align, const GlobalObject *GV = nullptr) const;
 
   /// Lower the specified LLVM Constant to an MCExpr.
   virtual const MCExpr *lowerConstant(const Constant *CV);
 
   /// Print a general LLVM constant to the .s file.
   void EmitGlobalConstant(const DataLayout &DL, const Constant *CV);
 
   /// Unnamed constant global variables solely contaning a pointer to
public:
   void EmitVisibility(MCSymbol *Sym, unsigned Visibility,
                       bool IsDefinition = true) const;
 
   /// This emits linkage information about \p GVSym based on \p GV, if this is
   /// supported by the target.
   void EmitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const;
 
   /// Return the alignment for the specified \p GV.
-  static llvm::Align getGVAlignment(const GlobalValue *GV, const DataLayout &DL,
-                                    llvm::Align InAlign = llvm::Align::None());
+  static Align getGVAlignment(const GlobalValue *GV, const DataLayout &DL,
+                              Align InAlign = Align::None());
 
 private:
   /// Private state for PrintSpecial()
   // Assign a unique ID to this machine instruction.
   mutable const MachineInstr *LastMI = nullptr;
   mutable unsigned LastFn = 0;
   mutable unsigned Counter = ~0U;
 

llvm/include/llvm/CodeGen/CallingConvLower.h

unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
     MarkAllocated(Reg);
     MarkAllocated(ShadowReg);
     return Reg;
   }
 
   /// AllocateStack - Allocate a chunk of stack space with the specified size
   /// and alignment.
   unsigned AllocateStack(unsigned Size, unsigned Alignment) {
-    const llvm::Align Align(Alignment);
+    const Align Align(Alignment);
     StackOffset = alignTo(StackOffset, Align);
     unsigned Result = StackOffset;
     StackOffset += Size;
     MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
     ensureMaxAlignment(Align);
     return Result;
   }
 
-  void ensureMaxAlignment(llvm::Align Align) {
+  void ensureMaxAlignment(Align Align) {
     if (!AnalyzingMustTailForwardedRegs)
       MF.getFrameInfo().ensureMaxAlignment(Align.value());
   }
 
   /// Version of AllocateStack with extra register to be shadowed.
   unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
     MarkAllocated(ShadowReg);
     return AllocateStack(Size, Align);

llvm/include/llvm/CodeGen/MachineBasicBlock.h

private:
   Optional<uint64_t> IrrLoopHeaderWeight;
 
   /// Keep track of the physical registers that are livein of the basicblock.
   using LiveInVector = std::vector<RegisterMaskPair>;
   LiveInVector LiveIns;
 
   /// Alignment of the basic block. One if the basic block does not need to be
   /// aligned.
-  llvm::Align Alignment;
+  Align Alignment;
 
   /// Indicate that this basic block is entered via an exception handler.
   bool IsEHPad = false;
 
   /// Indicate that this basic block is potentially the target of an indirect
   /// branch.
   bool AddressTaken = false;
 
#endif
   /// to prevent register allocation across funclet transitions.
   const uint32_t *getBeginClobberMask(const TargetRegisterInfo *TRI) const;
 
   /// Get the clobber mask for the end of the basic block.
   /// \see getBeginClobberMask()
   const uint32_t *getEndClobberMask(const TargetRegisterInfo *TRI) const;
 
   /// Return alignment of the basic block.
-  llvm::Align getAlignment() const { return Alignment; }
+  Align getAlignment() const { return Alignment; }
 
   /// Set alignment of the basic block.
-  void setAlignment(llvm::Align A) { Alignment = A; }
+  void setAlignment(Align A) { Alignment = A; }
 
   /// Returns true if the block is a landing pad. That is this basic block is
   /// entered via an exception handler.
   bool isEHPad() const { return IsEHPad; }
 
   /// Indicates the block is a landing pad.  That is this basic block is entered
   /// via an exception handler.
   void setIsEHPad(bool V = true) { IsEHPad = V; }

llvm/include/llvm/CodeGen/MachineFrameInfo.h

struct StackObject {
     /// If true, the object has been zero-extended.
     bool isZExt = false;
 
     /// If true, the object has been zero-extended.
     bool isSExt = false;
 
     uint8_t SSPLayout;
 
-    StackObject(uint64_t Size, llvm::Align Alignment, int64_t SPOffset,
+    StackObject(uint64_t Size, Align Alignment, int64_t SPOffset,
                 bool IsImmutable, bool IsSpillSlot, const AllocaInst *Alloca,
                 bool IsAliased, uint8_t StackID = 0)
         : SPOffset(SPOffset), Size(Size), Alignment(Alignment),
           isImmutable(IsImmutable), isSpillSlot(IsSpillSlot), StackID(StackID),
           Alloca(Alloca), isAliased(IsAliased), SSPLayout(SSPLK_None) {}
   };
 
   /// The alignment of the stack.
public:
   /// Set the correction for frame offsets.
   void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; }
 
   /// Return the alignment in bytes that this function must be aligned to,
   /// which is greater than the default stack alignment provided by the target.
   unsigned getMaxAlignment() const { return MaxAlignment.value(); }
 
   /// Make sure the function is at least Align bytes aligned.
-  void ensureMaxAlignment(llvm::Align Align);
+  void ensureMaxAlignment(Align Align);
   /// FIXME: Remove this once transition to Align is over.
   inline void ensureMaxAlignment(unsigned Align) {
     ensureMaxAlignment(assumeAligned(Align));
   }
 
   /// Return true if this function adjusts the stack -- e.g.,
   /// when calling another function. This is only valid during and after
   /// prolog/epilog code insertion.
void markAsStatepointSpillSlotObjectIndex(int ObjectIdx) {
     assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
            "Invalid Object Idx!");
     Objects[ObjectIdx+NumFixedObjects].isStatepointSpillSlot = true;
     assert(isStatepointSpillSlotObjectIndex(ObjectIdx) && "inconsistent");
   }
 
   /// Create a new statically sized stack object, returning
   /// a nonnegative identifier to represent it.
-  int CreateStackObject(uint64_t Size, llvm::Align Alignment, bool isSpillSlot,
+  int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot,
                         const AllocaInst *Alloca = nullptr, uint8_t ID = 0);
-  /// FIXME: Remove this function when transition to llvm::Align is over.
+  /// FIXME: Remove this function when transition to Align is over.
   inline int CreateStackObject(uint64_t Size, unsigned Alignment,
                                bool isSpillSlot,
                                const AllocaInst *Alloca = nullptr,
                                uint8_t ID = 0) {
     return CreateStackObject(Size, assumeAligned(Alignment), isSpillSlot,
                              Alloca, ID);
   }
 
   /// Create a new statically sized stack object that represents a spill slot,
   /// returning a nonnegative identifier to represent it.
-  int CreateSpillStackObject(uint64_t Size, llvm::Align Alignment);
-  /// FIXME: Remove this function when transition to llvm::Align is over.
+  int CreateSpillStackObject(uint64_t Size, Align Alignment);
+  /// FIXME: Remove this function when transition to Align is over.
   inline int CreateSpillStackObject(uint64_t Size, unsigned Alignment) {
     return CreateSpillStackObject(Size, assumeAligned(Alignment));
   }
 
   /// Remove or mark dead a statically sized stack object.
   void RemoveStackObject(int ObjectIdx) {
     // Mark it dead.
     Objects[ObjectIdx+NumFixedObjects].Size = ~0ULL;
   }
 
   /// Notify the MachineFrameInfo object that a variable sized object has been
   /// created.  This must be created whenever a variable sized object is
   /// created, whether or not the index returned is actually used.
-  int CreateVariableSizedObject(llvm::Align Alignment,
-                                const AllocaInst *Alloca);
-  /// FIXME: Remove this function when transition to llvm::Align is over.
+  int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca);
+  /// FIXME: Remove this function when transition to Align is over.
   int CreateVariableSizedObject(unsigned Alignment, const AllocaInst *Alloca) {
     return CreateVariableSizedObject(assumeAligned(Alignment), Alloca);
   }
 
   /// Returns a reference to call saved info vector for the current function.
   const std::vector<CalleeSavedInfo> &getCalleeSavedInfo() const {
     return CSInfo;
   }

llvm/include/llvm/CodeGen/MachineFunction.h

class MachineFunction {
   BasicBlockListType BasicBlocks;
 
   /// FunctionNumber - This provides a unique ID for each function emitted in
   /// this translation unit.
   ///
   unsigned FunctionNumber;
 
   /// Alignment - The alignment of the function.
-  llvm::Align Alignment;
+  Align Alignment;
 
   /// ExposesReturnsTwice - True if the function calls setjmp or related
   /// functions with attribute "returns twice", but doesn't have
   /// the attribute itself.
   /// This is used to limit optimizations which cannot reason
   /// about the control flow of such functions.
   bool ExposesReturnsTwice = false;
 
public:
 
   /// getWinEHFuncInfo - Return information about how the current function uses
   /// Windows exception handling. Returns null for functions that don't use
   /// funclets for exception handling.
   const WinEHFuncInfo *getWinEHFuncInfo() const { return WinEHInfo; }
   WinEHFuncInfo *getWinEHFuncInfo() { return WinEHInfo; }
 
   /// getAlignment - Return the alignment of the function.
-  llvm::Align getAlignment() const { return Alignment; }
+  Align getAlignment() const { return Alignment; }
 
   /// setAlignment - Set the alignment of the function.
-  void setAlignment(llvm::Align A) { Alignment = A; }
+  void setAlignment(Align A) { Alignment = A; }
 
   /// ensureAlignment - Make sure the function is at least A bytes aligned.
-  void ensureAlignment(llvm::Align A) {
+  void ensureAlignment(Align A) {
     if (Alignment < A)
       Alignment = A;
   }
 
   /// exposesReturnsTwice - Returns true if the function calls setjmp or
   /// any other similar functions with attribute "returns twice" without
   /// having the attribute itself.
   bool exposesReturnsTwice() const {

llvm/include/llvm/CodeGen/TargetLowering.h

getExceptionSelectorRegister(const Constant *PersonalityFn) const {
     return 0;
   }
 
   virtual bool needsFixedCatchObjects() const {
     report_fatal_error("Funclet EH is not implemented for this target");
   }
 
   /// Return the minimum stack alignment of an argument.
-  llvm::Align getMinStackArgumentAlignment() const {
+  Align getMinStackArgumentAlignment() const {
     return MinStackArgumentAlignment;
   }
 
   /// Return the minimum function alignment.
-  llvm::Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
+  Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
 
   /// Return the preferred function alignment.
-  llvm::Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
+  Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
 
   /// Return the preferred loop alignment.
-  virtual llvm::Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
+  virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
     return PrefLoopAlignment;
   }
 
   /// Should loops be aligned even when the function is marked OptSize (but not
   /// MinSize).
   virtual bool alignLoopsWithOptSize() const {
     return false;
   }
protected:
   /// they want to provide a custom DAG combiner for by implementing the
   /// PerformDAGCombine virtual method.
   void setTargetDAGCombine(ISD::NodeType NT) {
     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
   }
 
   /// Set the target's minimum function alignment.
-  void setMinFunctionAlignment(llvm::Align Align) {
-    MinFunctionAlignment = Align;
-  }
+  void setMinFunctionAlignment(Align Align) { MinFunctionAlignment = Align; }
 
   /// Set the target's preferred function alignment.  This should be set if
   /// there is a performance benefit to higher-than-minimum alignment
-  void setPrefFunctionAlignment(llvm::Align Align) {
-    PrefFunctionAlignment = Align;
-  }
+  void setPrefFunctionAlignment(Align Align) { PrefFunctionAlignment = Align; }
 
   /// Set the target's preferred loop alignment. Default alignment is one, it
   /// means the target does not care about loop alignment. The target may also
   /// override getPrefLoopAlignment to provide per-loop values.
-  void setPrefLoopAlignment(llvm::Align Align) { PrefLoopAlignment = Align; }
+  void setPrefLoopAlignment(Align Align) { PrefLoopAlignment = Align; }
 
   /// Set the minimum stack alignment of an argument.
-  void setMinStackArgumentAlignment(llvm::Align Align) {
+  void setMinStackArgumentAlignment(Align Align) {
     MinStackArgumentAlignment = Align;
   }
 
   /// Set the maximum atomic operation size supported by the
   /// backend. Atomic operations greater than this size (as well as
   /// ones that are not naturally aligned), will be expanded by
   /// AtomicExpandPass into an __atomic_* library call.
   void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
private:
   /// when the element type is wider than i1. See getBooleanContents.
   BooleanContent BooleanVectorContents;
 
   /// The target scheduling preference: shortest possible total cycles or lowest
   /// register usage.
   Sched::Preference SchedPreferenceInfo;
 
   /// The minimum alignment that any argument on the stack needs to have.
-  llvm::Align MinStackArgumentAlignment;
+  Align MinStackArgumentAlignment;
 
   /// The minimum function alignment (used when optimizing for size, and to
   /// prevent explicitly provided alignment from leading to incorrect code).
-  llvm::Align MinFunctionAlignment;
+  Align MinFunctionAlignment;
 
   /// The preferred function alignment (used when alignment unspecified and
   /// optimizing for speed).
-  llvm::Align PrefFunctionAlignment;
+  Align PrefFunctionAlignment;
 
   /// The preferred loop alignment (in log2 bot in bytes).
-  llvm::Align PrefLoopAlignment;
+  Align PrefLoopAlignment;
 
   /// Size in bits of the maximum atomics size the backend supports.
   /// Accesses larger than this will be expanded by AtomicExpandPass.
   unsigned MaxAtomicSizeInBitsSupported;
 
   /// Size in bits of the minimum cmpxchg or ll/sc operation the
   /// backend supports.
   unsigned MinCmpXchgSizeInBits;

llvm/include/llvm/IR/DataLayout.h

 /// vector, float) and type bit width.
 ///
 /// \note The unusual order of elements in the structure attempts to reduce
 /// padding and make the structure slightly more cache friendly.
 struct LayoutAlignElem {
   /// Alignment type from \c AlignTypeEnum
   unsigned AlignType : 8;
   unsigned TypeBitWidth : 24;
-  llvm::Align ABIAlign;
-  llvm::Align PrefAlign;
+  Align ABIAlign;
+  Align PrefAlign;
 
-  static LayoutAlignElem get(AlignTypeEnum align_type, llvm::Align abi_align,
-                             llvm::Align pref_align, uint32_t bit_width);
+  static LayoutAlignElem get(AlignTypeEnum align_type, Align abi_align,
+                             Align pref_align, uint32_t bit_width);
 
   bool operator==(const LayoutAlignElem &rhs) const;
 };
 
 /// Layout pointer alignment element.
 ///
 /// Stores the alignment data associated with a given pointer and address space.
 ///
 /// \note The unusual order of elements in the structure attempts to reduce
 /// padding and make the structure slightly more cache friendly.
 struct PointerAlignElem {
-  llvm::Align ABIAlign;
-  llvm::Align PrefAlign;
+  Align ABIAlign;
+  Align PrefAlign;
   uint32_t TypeByteWidth;
   uint32_t AddressSpace;
   uint32_t IndexWidth;
 
   /// Initializer
-  static PointerAlignElem get(uint32_t AddressSpace, llvm::Align ABIAlign,
-                              llvm::Align PrefAlign, uint32_t TypeByteWidth,
+  static PointerAlignElem get(uint32_t AddressSpace, Align ABIAlign,
+                              Align PrefAlign, uint32_t TypeByteWidth,
                               uint32_t IndexWidth);
 
   bool operator==(const PointerAlignElem &rhs) const;
 };
 
 /// A parsed version of the target data layout string in and methods for
 /// querying it.
 ///
private:
 
   // The StructType -> StructLayout map.
   mutable void *LayoutMap = nullptr;
 
   /// Pointers in these address spaces are non-integral, and don't have a
   /// well-defined bitwise representation.
   SmallVector<unsigned, 8> NonIntegralAddressSpaces;
 
-  void setAlignment(AlignTypeEnum align_type, llvm::Align abi_align,
-                    llvm::Align pref_align, uint32_t bit_width);
-  llvm::Align getAlignmentInfo(AlignTypeEnum align_type, uint32_t bit_width,
-                               bool ABIAlign, Type *Ty) const;
-  void setPointerAlignment(uint32_t AddrSpace, llvm::Align ABIAlign,
-                           llvm::Align PrefAlign, uint32_t TypeByteWidth,
-                           uint32_t IndexWidth);
+  void setAlignment(AlignTypeEnum align_type, Align abi_align, Align pref_align,
+                    uint32_t bit_width);
+  Align getAlignmentInfo(AlignTypeEnum align_type, uint32_t bit_width,
+  void setPointerAlignment(uint32_t AddrSpace, Align ABIAlign, Align PrefAlign,
+                           uint32_t TypeByteWidth, uint32_t IndexWidth);
 
   /// Internal helper method that returns requested alignment for type.
-  llvm::Align getAlignment(Type *Ty, bool abi_or_pref) const;
+  Align getAlignment(Type *Ty, bool abi_or_pref) const;
 
   /// Parses a target data specification string. Assert if the string is
   /// malformed.
   void parseSpecifier(StringRef LayoutDescription);
 
   // Free all internal data structures.
   void clear();
 
for (unsigned LegalIntWidth : LegalIntWidths)
       if (LegalIntWidth == Width)
         return true;
     return false;
   }
 
   bool isIllegalInteger(uint64_t Width) const { return !isLegalInteger(Width); }
 
   /// Returns true if the given alignment exceeds the natural stack alignment.
-  bool exceedsNaturalStackAlignment(llvm::Align Align) const {
+  bool exceedsNaturalStackAlignment(Align Align) const {
     return StackNaturalAlign && (Align > StackNaturalAlign);
   }
 
-  llvm::Align getStackAlignment() const {
+  Align getStackAlignment() const {
     assert(StackNaturalAlign && "StackNaturalAlign must be defined");
     return *StackNaturalAlign;
   }
 
   unsigned getAllocaAddrSpace() const { return AllocaAddrSpace; }
 
   /// Returns the alignment of function pointers, which may or may not be
   /// related to the alignment of functions.
public:
   bool fitsInLegalInteger(unsigned Width) const {
     for (unsigned LegalIntWidth : LegalIntWidths)
       if (Width <= LegalIntWidth)
         return true;
     return false;
   }
 
   /// Layout pointer alignment
-  llvm::Align getPointerABIAlignment(unsigned AS) const;
+  Align getPointerABIAlignment(unsigned AS) const;
 
   /// Return target's alignment for stack-based pointers
   /// FIXME: The defaults need to be removed once all of
   /// the backends/clients are updated.
-  llvm::Align getPointerPrefAlignment(unsigned AS = 0) const;
+  Align getPointerPrefAlignment(unsigned AS = 0) const;
 
   /// Layout pointer size
   /// FIXME: The defaults need to be removed once all of
   /// the backends/clients are updated.
   unsigned getPointerSize(unsigned AS = 0) const;
 
   /// Returns the maximum pointer size over all address spaces.
   unsigned getMaxPointerSize() const;
uint64_t getTypeAllocSizeInBits(Type *Ty) const {
     return 8 * getTypeAllocSize(Ty);
   }
 
   /// Returns the minimum ABI-required alignment for the specified type.
   unsigned getABITypeAlignment(Type *Ty) const;
 
   /// Returns the minimum ABI-required alignment for an integer type of
   /// the specified bitwidth.
-  llvm::Align getABIIntegerTypeAlignment(unsigned BitWidth) const;
+  Align getABIIntegerTypeAlignment(unsigned BitWidth) const;
 
   /// Returns the preferred stack/global alignment for the specified
   /// type.
   ///
   /// This is always at least as good as the ABI alignment.
   unsigned getPrefTypeAlignment(Type *Ty) const;
 
   /// Returns an integer type with size at least as big as that of a

 inline LLVMTargetDataRef wrap(const DataLayout *P) {
   return reinterpret_cast<LLVMTargetDataRef>(const_cast<DataLayout *>(P));
 }
 
 /// Used to lazily calculate structure layout information for a target machine,
 /// based on the DataLayout structure.
 class StructLayout {
   uint64_t StructSize;
-  llvm::Align StructAlignment;
+  Align StructAlignment;
   unsigned IsPadded : 1;
   unsigned NumElements : 31;
   uint64_t MemberOffsets[1]; // variable sized array!
 
 public:
   uint64_t getSizeInBytes() const { return StructSize; }
 
   uint64_t getSizeInBits() const { return 8 * StructSize; }
 
-  llvm::Align getAlignment() const { return StructAlignment; }
+  Align getAlignment() const { return StructAlignment; }
 
   /// Returns whether the struct has padding or not between its fields.
   /// NB: Padding in nested element is not taken into account.
   bool hasPadding() const { return IsPadded; }
 
   /// Given a valid byte offset into the structure, returns the structure
   /// index that contains it.
   unsigned getElementContainingOffset(uint64_t Offset) const;

llvm/include/llvm/IR/Instructions.h

public:
 
   /// Return the alignment of the memory that is being allocated by the
   /// instruction.
   unsigned getAlignment() const {
     if (const auto MA = decodeMaybeAlign(getSubclassDataFromInstruction() & 31))
       return MA->value();
     return 0;
   }
-  // FIXME: Remove once migration to llvm::Align is over.
+  // FIXME: Remove once migration to Align is over.
   void setAlignment(unsigned Align);
-  void setAlignment(llvm::MaybeAlign Align);
+  void setAlignment(MaybeAlign Align);
 
   /// Return true if this alloca is in the entry block of the function and is a
   /// constant size. If so, the code generator will fold it into the
   /// prolog/epilog code, so it is basically free.
   bool isStaticAlloca() const;
 
   /// Return true if this alloca is used as an inalloca argument to a call. Such
   /// allocas are never considered static even if they are in the entry block.
public:
   /// Return the alignment of the access that is being performed.
   unsigned getAlignment() const {
     if (const auto MA =
             decodeMaybeAlign((getSubclassDataFromInstruction() >> 1) & 31))
       return MA->value();
     return 0;
   }
 
-  // FIXME: Remove once migration to llvm::Align is over.
+  // FIXME: Remove once migration to Align is over.
   void setAlignment(unsigned Align);
-  void setAlignment(llvm::MaybeAlign Align);
+  void setAlignment(MaybeAlign Align);
 
   /// Returns the ordering constraint of this load instruction.
   AtomicOrdering getOrdering() const {
     return AtomicOrdering((getSubclassDataFromInstruction() >> 7) & 7);
   }
 
   /// Sets the ordering constraint of this load instruction.  May not be Release
   /// or AcquireRelease.
public:
   /// Return the alignment of the access that is being performed
   unsigned getAlignment() const {
     if (const auto MA =
             decodeMaybeAlign((getSubclassDataFromInstruction() >> 1) & 31))
       return MA->value();
     return 0;
   }
 
-  // FIXME: Remove once migration to llvm::Align is over.
+  // FIXME: Remove once migration to Align is over.
   void setAlignment(unsigned Align);
-  void setAlignment(llvm::MaybeAlign Align);
+  void setAlignment(MaybeAlign Align);
 
   /// Returns the ordering constraint of this store instruction.
   AtomicOrdering getOrdering() const {
     return AtomicOrdering((getSubclassDataFromInstruction() >> 7) & 7);
   }
 
   /// Sets the ordering constraint of this store instruction.  May not be
   /// Acquire or AcquireRelease.

llvm/include/llvm/MC/MCSection.h

public:
 
   using const_reverse_iterator = FragmentListType::const_reverse_iterator;
   using reverse_iterator = FragmentListType::reverse_iterator;
 
 private:
   MCSymbol *Begin;
   MCSymbol *End = nullptr;
   /// The alignment requirement of this section.
-  llvm::Align Alignment;
+  Align Alignment;
   /// The section index in the assemblers section list.
   unsigned Ordinal = 0;
   /// The index of this section in the layout order.
   unsigned LayoutOrder;
 
   /// Keeping track of bundle-locked state.
   BundleLockStateType BundleLockState = NotBundleLocked;
 
public:
   void setBeginSymbol(MCSymbol *Sym) {
     assert(!Begin);
     Begin = Sym;
   }
   MCSymbol *getEndSymbol(MCContext &Ctx);
   bool hasEnded() const;
 
   unsigned getAlignment() const { return Alignment.value(); }
-  void setAlignment(llvm::Align Value) { Alignment = Value; }
+  void setAlignment(Align Value) { Alignment = Value; }
 
   unsigned getOrdinal() const { return Ordinal; }
   void setOrdinal(unsigned Value) { Ordinal = Value; }
 
   unsigned getLayoutOrder() const { return LayoutOrder; }
   void setLayoutOrder(unsigned Value) { LayoutOrder = Value; }
 
   BundleLockStateType getBundleLockState() const { return BundleLockState; }

llvm/include/llvm/Support/Alignment.h

public:
   }
 
   /// This is a hole in the type system and should not be abused.
   /// Needed to interact with C for instance.
   uint64_t value() const { return uint64_t(1) << ShiftValue; }
 
   /// Returns a default constructed Align which corresponds to no alignment.
   /// This is useful to test for unalignment as it conveys clear semantic.
-  /// `if (A != llvm::Align::None())`
+  /// `if (A != Align::None())`
   /// would be better than
   /// `if (A > llvm::Align(1))`
   constexpr static const Align None() { return llvm::Align(); }
 };
 
 /// Treats the value 0 as a 1, so Align is always at least 1.
 inline Align assumeAligned(uint64_t Value) {
   return Value ? Align(Value) : Align();

 /// Returns a multiple of A needed to store `Size` bytes.
 /// Returns `Size` if current alignment is undefined.
 inline uint64_t alignTo(uint64_t Size, MaybeAlign A) {
   return A ? alignTo(Size, A.getValue()) : Size;
 }
 
 /// Returns the offset to the next integer (mod 2**64) that is greater than
 /// or equal to \p Value and is a multiple of \p Align.
-inline uint64_t offsetToAlignment(uint64_t Value, llvm::Align Align) {
+inline uint64_t offsetToAlignment(uint64_t Value, Align Align) {
   return alignTo(Value, Align) - Value;
 }
 
 /// Returns the log2 of the alignment.
 inline unsigned Log2(Align A) { return A.ShiftValue; }
 
 /// Returns the log2 of the alignment.
 /// \pre A must be defined.

llvm/lib/Analysis/TargetTransformInfo.cpp

bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
   return TTIImpl->isLegalMaskedStore(DataType);
 }
 
 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
   return TTIImpl->isLegalMaskedLoad(DataType);
 }
 
 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
-                                         llvm::Align Alignment) const {
+                                         Align Alignment) const {
   return TTIImpl->isLegalNTStore(DataType, Alignment);
 }
 
-bool TargetTransformInfo::isLegalNTLoad(Type *DataType,
-                                        llvm::Align Alignment) const {
+bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
   return TTIImpl->isLegalNTLoad(DataType, Alignment);
 }
 
 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
   return TTIImpl->isLegalMaskedGather(DataType);
 }
 
 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

 static gcp_map_type &getGCMap(void *&P) {
   if (!P)
     P = new gcp_map_type();
   return *(gcp_map_type*)P;
 }
 
 /// getGVAlignment - Return the alignment to use for the specified global
 /// value.  This rounds up to the preferred alignment if possible and legal.
-llvm::Align AsmPrinter::getGVAlignment(const GlobalValue *GV,
-                                       const DataLayout &DL,
-                                       llvm::Align InAlign) {
-  llvm::Align Align;
+Align AsmPrinter::getGVAlignment(const GlobalValue *GV, const DataLayout &DL,
+                                 Align InAlign) {
+  Align Align;
   if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
     Align = llvm::Align(DL.getPreferredAlignment(GVar));
 
   // If InAlign is specified, round it to it.
   if (InAlign > Align)
     Align = InAlign;
 
   // If the GV has a specified alignment, take it into account.
-  const llvm::MaybeAlign GVAlign(GV->getAlignment());
+  const MaybeAlign GVAlign(GV->getAlignment());
   if (!GVAlign)
     return Align;
 
   assert(GVAlign && "GVAlign must be set");
 
   // If the GVAlign is larger than NumBits, or if we are required to obey
   // NumBits because the GV has an assigned section, obey it.
   if (*GVAlign > Align || GV->hasSection())
void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
   SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);
 
   const DataLayout &DL = GV->getParent()->getDataLayout();
   uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
 
   // If the alignment is specified, we *must* obey it.  Overaligning a global
   // with a specified alignment is a prompt way to break globals emitted to
   // sections and expected to be contiguous (e.g. ObjC metadata).
-  const llvm::Align Align = getGVAlignment(GV, DL);
+  const Align Align = getGVAlignment(GV, DL);
 
   for (const HandlerInfo &HI : Handlers) {
     NamedRegionTimer T(HI.TimerName, HI.TimerDescription,
                        HI.TimerGroupName, HI.TimerGroupDescription,
                        TimePassesIsEnabled);
     HI.Handler->setSymbolSize(GVSym, Size);
   }
 
if (!CS->getOperand(2)->isNullValue())
       S.ComdatKey =
           dyn_cast<GlobalValue>(CS->getOperand(2)->stripPointerCasts());
   }
 
   // Emit the function pointers in the target-specific order
   llvm::stable_sort(Structors, [](const Structor &L, const Structor &R) {
     return L.Priority < R.Priority;
   });
-  const llvm::Align Align = DL.getPointerPrefAlignment();
+  const Align Align = DL.getPointerPrefAlignment();
   for (Structor &S : Structors) {
     const TargetLoweringObjectFile &Obj = getObjFileLowering();
     const MCSymbol *KeySym = nullptr;
     if (GlobalValue *GV = S.ComdatKey) {
       if (GV->isDeclarationForLinker())
         // If the associated variable is not defined in this module
         // (it might be available_externally, or have been an
         // available_externally definition that was dropped by the

 }
 
 //===----------------------------------------------------------------------===//
 
 // EmitAlignment - Emit an alignment directive to the specified power of
 // two boundary.  If a global value is specified, and if that global has
 // an explicit alignment requested, it will override the alignment request
 // if required for correctness.
-void AsmPrinter::EmitAlignment(llvm::Align Align,
-                               const GlobalObject *GV) const {
+void AsmPrinter::EmitAlignment(Align Align, const GlobalObject *GV) const {
   if (GV)
     Align = getGVAlignment(GV, GV->getParent()->getDataLayout(), Align);
 
   if (Align == 1)
     return; // 1-byte aligned: no need to emit alignment.
 
   if (getCurrentSection()->getKind().isText())
     OutStreamer->EmitCodeAlignment(Align.value());
void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) {
   if (MBB.isEHFuncletEntry()) {
     for (const HandlerInfo &HI : Handlers) {
       HI.Handler->endFunclet();
       HI.Handler->beginFunclet(MBB);
     }
   }
 
   // Emit an alignment directive for this block, if needed.
-  const llvm::Align Align = MBB.getAlignment();
-  if (Align != llvm::Align::None())
+  const Align Align = MBB.getAlignment();
+  if (Align != Align::None())
     EmitAlignment(Align);
   MCCodePaddingContext Context;
   setupCodePaddingContext(MBB, Context);
   OutStreamer->EmitCodePaddingBasicBlockStart(Context);
 
   // If the block has its address taken, emit any labels that were used to
   // reference the block.  It is possible that there is more than one label
   // here, because multiple LLVM BB's may have been RAUW'd to this block after

llvm/lib/CodeGen/BranchRelaxation.cpp

struct BasicBlockInfo {
     unsigned Size = 0;
 
     BasicBlockInfo() = default;
 
     /// Compute the offset immediately following this block. \p MBB is the next
     /// block.
     unsigned postOffset(const MachineBasicBlock &MBB) const {
       const unsigned PO = Offset + Size;
-      const llvm::Align Align = MBB.getAlignment();
-      if (Align == 1)
+      const Align Alignment = MBB.getAlignment();
+      if (Alignment == 1)
         return PO;
 
-      const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
-      if (Align <= ParentAlign)
-        return PO + offsetToAlignment(PO, Align);
+      const Align ParentAlign = MBB.getParent()->getAlignment();
+      if (Alignment <= ParentAlign)
+        return PO + offsetToAlignment(PO, Alignment);
 
       // The alignment of this MBB is larger than the function's alignment, so we
       // can't tell whether or not it will insert nops. Assume that it will.
-      return PO + Align.value() + offsetToAlignment(PO, Align);
+      return PO + Alignment.value() + offsetToAlignment(PO, Alignment);
     }
   };
 
   SmallVector<BasicBlockInfo, 16> BlockInfo;
   std::unique_ptr<RegScavenger> RS;
   LivePhysRegs LiveRegs;
 
   MachineFunction *MF;

llvm/lib/CodeGen/CallingConvLower.cpp

 }
 
 /// Allocate space on the stack large enough to pass an argument by value.
 /// The size and alignment information of the argument is encoded in
 /// its parameter attribute.
 void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
                           CCValAssign::LocInfo LocInfo, int MinSize,
                           int MinAlignment, ISD::ArgFlagsTy ArgFlags) {
-  llvm::Align MinAlign(MinAlignment);
-  llvm::Align Align(ArgFlags.getByValAlign());
+  Align MinAlign(MinAlignment);
+  Align Align(ArgFlags.getByValAlign());
   unsigned Size  = ArgFlags.getByValSize();
   if (MinSize > (int)Size)
     Size = MinSize;
   if (MinAlign > Align)
     Align = MinAlign;
   ensureMaxAlignment(Align);
   MF.getSubtarget().getTargetLowering()->HandleByVal(this, Size, Align.value());
   Size = unsigned(alignTo(Size, MinAlign));
static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) {
   if (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall)
     return true;
   return false;
 }
 
 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
                                           MVT VT, CCAssignFn Fn) {
   unsigned SavedStackOffset = StackOffset;
-  llvm::Align SavedMaxStackArgAlign = MaxStackArgAlign;
+  Align SavedMaxStackArgAlign = MaxStackArgAlign;
   unsigned NumLocs = Locs.size();
 
   // Set the 'inreg' flag if it is used for this calling convention.
   ISD::ArgFlagsTy Flags;
   if (isValueTypeInRegForCC(CallingConv, VT))
     Flags.setInReg();
 
   // Allocate something of this value type repeatedly until we get assigned a

llvm/lib/CodeGen/MIRPrinter.cpp

if (MBB.hasAddressTaken()) {
     OS << "address-taken";
     HasAttributes = true;
   }
   if (MBB.isEHPad()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "landing-pad";
     HasAttributes = true;
   }
-  if (MBB.getAlignment() != llvm::Align::None()) {
+  if (MBB.getAlignment() != Align::None()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "align " << MBB.getAlignment().value();
     HasAttributes = true;
   }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
 

llvm/lib/CodeGen/MachineBasicBlock.cpp

if (hasAddressTaken()) {
     OS << "address-taken";
     HasAttributes = true;
   }
   if (isEHPad()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "landing-pad";
     HasAttributes = true;
   }
-  if (getAlignment() != llvm::Align::None()) {
+  if (getAlignment() != Align::None()) {
     OS << (HasAttributes ? ", " : " (");
     OS << "align " << Log2(getAlignment());
     HasAttributes = true;
   }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
 

llvm/lib/CodeGen/MachineBlockPlacement.cpp

for (MachineBasicBlock *ChainBB : FunctionChain) {
     // Don't align non-looping basic blocks. These are unlikely to execute
     // enough times to matter in practice. Note that we'll still handle
     // unnatural CFGs inside of a natural outer loop (the common case) and
     // rotated loops.
     MachineLoop *L = MLI->getLoopFor(ChainBB);
     if (!L)
       continue;
 
-    const llvm::Align Align = TLI->getPrefLoopAlignment(L);
+    const Align Align = TLI->getPrefLoopAlignment(L);
     if (Align == 1)
       continue; // Don't care about loop alignment.
 
     // If the block is cold relative to the function entry don't waste space
     // aligning it.
     BlockFrequency Freq = MBFI->getBlockFreq(ChainBB);
     if (Freq < WeightedEntryFreq)
       continue;

llvm/lib/CodeGen/MachineFrameInfo.cpp

 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 
 #define DEBUG_TYPE "codegen"
 
 using namespace llvm;
 
-void MachineFrameInfo::ensureMaxAlignment(llvm::Align Align) {
+void MachineFrameInfo::ensureMaxAlignment(Align Align) {
   if (!StackRealignable)
     assert(Align <= StackAlignment &&
            "For targets without stack realignment, Align is out of limit!");
   if (MaxAlignment < Align) MaxAlignment = Align;
 }
 
 /// Clamp the alignment if requested and emit a warning.
-static inline llvm::Align clampStackAlignment(bool ShouldClamp,
-                                              llvm::Align Align,
-                                              llvm::Align StackAlign) {
-  if (!ShouldClamp || Align <= StackAlign)
-    return Align;
-  LLVM_DEBUG(dbgs() << "Warning: requested alignment " << Align.value()
+static inline Align clampStackAlignment(bool ShouldClamp, Align Alignment,
+                                        Align StackAlign) {
+  if (!ShouldClamp || Alignment <= StackAlign)
+    return Alignment;
+  LLVM_DEBUG(dbgs() << "Warning: requested alignment " << Alignment.value()
                     << " exceeds the stack alignment " << StackAlign.value()
                     << " when stack realignment is off" << '\n');
   return StackAlign;
 }
 
-int MachineFrameInfo::CreateStackObject(uint64_t Size, llvm::Align Alignment,
+int MachineFrameInfo::CreateStackObject(uint64_t Size, Align Alignment,
                                         bool IsSpillSlot,
                                         const AllocaInst *Alloca,
                                         uint8_t StackID) {
   assert(Size != 0 && "Cannot allocate zero size stack objects!");
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   Objects.push_back(StackObject(Size, Alignment, 0, false, IsSpillSlot, Alloca,
                                 !IsSpillSlot, StackID));
   int Index = (int)Objects.size() - NumFixedObjects - 1;
   assert(Index >= 0 && "Bad frame index!");
   if (StackID == 0)
     ensureMaxAlignment(Alignment);
   return Index;
 }
 
-int MachineFrameInfo::CreateSpillStackObject(uint64_t Size,
-                                             llvm::Align Alignment) {
+int MachineFrameInfo::CreateSpillStackObject(uint64_t Size, Align Alignment) {
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   CreateStackObject(Size, Alignment, true);
   int Index = (int)Objects.size() - NumFixedObjects - 1;
   ensureMaxAlignment(Alignment);
   return Index;
 }
 
-int MachineFrameInfo::CreateVariableSizedObject(llvm::Align Alignment,
+int MachineFrameInfo::CreateVariableSizedObject(Align Alignment,
                                                 const AllocaInst *Alloca) {
   HasVarSizedObjects = true;
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   Objects.push_back(StackObject(0, Alignment, 0, false, false, Alloca, true));
   ensureMaxAlignment(Alignment);
   return (int)Objects.size()-NumFixedObjects-1;
 }
 
 int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
                                         bool IsImmutable, bool IsAliased) {
   assert(Size != 0 && "Cannot allocate zero size fixed stack objects!");
   // The alignment of the frame index can be determined from its offset from
   // the incoming frame position.  If the frame object is at offset 32 and
   // the stack is guaranteed to be 16-byte aligned, then we know that the
   // object is 16-byte aligned. Note that unlike the non-fixed case, if the
   // stack needs realignment, we can't assume that the stack will in fact be
   // aligned.
-  llvm::Align Alignment = commonAlignment(
-      ForcedRealign ? llvm::Align::None() : StackAlignment, SPOffset);
+  Align Alignment =
+      commonAlignment(ForcedRealign ? Align::None() : StackAlignment, SPOffset);
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   Objects.insert(Objects.begin(),
                  StackObject(Size, Alignment, SPOffset, IsImmutable,
                              /*IsSpillSlot=*/false, /*Alloca=*/nullptr,
                              IsAliased));
   return -++NumFixedObjects;
 }
 
 int MachineFrameInfo::CreateFixedSpillStackObject(uint64_t Size,
                                                   int64_t SPOffset,
                                                   bool IsImmutable) {
-  llvm::Align Alignment = commonAlignment(
-      ForcedRealign ? llvm::Align::None() : StackAlignment, SPOffset);
+  Align Alignment =
+      commonAlignment(ForcedRealign ? Align::None() : StackAlignment, SPOffset);
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   Objects.insert(Objects.begin(),
                  StackObject(Size, Alignment, SPOffset, IsImmutable,
                              /*IsSpillSlot=*/true, /*Alloca=*/nullptr,
                              /*IsAliased=*/false));
   return -++NumFixedObjects;
 }
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 
 SDValue SelectionDAG::expandVAArg(SDNode *Node) {
   SDLoc dl(Node);
   const TargetLowering &TLI = getTargetLoweringInfo();
   const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   EVT VT = Node->getValueType(0);
   SDValue Tmp1 = Node->getOperand(0);
   SDValue Tmp2 = Node->getOperand(1);
-  const llvm::MaybeAlign MA(Node->getConstantOperandVal(3));
+  const MaybeAlign MA(Node->getConstantOperandVal(3));
 
   SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1,
                                Tmp2, MachinePointerInfo(V));
   SDValue VAList = VAListLoad;
 
   if (MA && *MA > TLI.getMinStackArgumentAlignment()) {
     VAList = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
                      getConstant(MA->value() - 1, dl, VAList.getValueType()));

llvm/lib/IR/DataLayout.cpp

StructLayout::StructLayout(StructType *ST, const DataLayout &DL) {
   assert(!ST->isOpaque() && "Cannot get layout of opaque structs");
   StructSize = 0;
   IsPadded = false;
   NumElements = ST->getNumElements();
 
   // Loop over each of the elements, placing them in memory.
   for (unsigned i = 0, e = NumElements; i != e; ++i) {
     Type *Ty = ST->getElementType(i);
-    const llvm::Align TyAlign(ST->isPacked() ? 1 : DL.getABITypeAlignment(Ty));
+    const Align TyAlign(ST->isPacked() ? 1 : DL.getABITypeAlignment(Ty));
 
     // Add padding if necessary to align the data element properly.
     if (!isAligned(TyAlign, StructSize)) {
       IsPadded = true;
       StructSize = alignTo(StructSize, TyAlign);
     }
 
     // Keep track of maximum alignment constraint.
unsigned StructLayout::getElementContainingOffset(uint64_t Offset) const {
   // offset, implying that this element is non-empty.
   return SI-&MemberOffsets[0];
 }
 
 //===----------------------------------------------------------------------===//
 // LayoutAlignElem, LayoutAlign support
 //===----------------------------------------------------------------------===//
 
-LayoutAlignElem LayoutAlignElem::get(AlignTypeEnum align_type,
-                                     llvm::Align abi_align,
-                                     llvm::Align pref_align,
-                                     uint32_t bit_width) {
+LayoutAlignElem LayoutAlignElem::get(AlignTypeEnum align_type, Align abi_align,
+                                     Align pref_align, uint32_t bit_width) {
   assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
   LayoutAlignElem retval;
   retval.AlignType = align_type;
   retval.ABIAlign = abi_align;
   retval.PrefAlign = pref_align;
   retval.TypeBitWidth = bit_width;
   return retval;
 }
 
 bool
 LayoutAlignElem::operator==(const LayoutAlignElem &rhs) const {
   return (AlignType == rhs.AlignType
           && ABIAlign == rhs.ABIAlign
           && PrefAlign == rhs.PrefAlign
           && TypeBitWidth == rhs.TypeBitWidth);
 }
 
 //===----------------------------------------------------------------------===//
 // PointerAlignElem, PointerAlign support
 //===----------------------------------------------------------------------===//
 
-PointerAlignElem PointerAlignElem::get(uint32_t AddressSpace,
-                                       llvm::Align ABIAlign,
-                                       llvm::Align PrefAlign,
-                                       uint32_t TypeByteWidth,
+PointerAlignElem PointerAlignElem::get(uint32_t AddressSpace, Align ABIAlign,
+                                       Align PrefAlign, uint32_t TypeByteWidth,
                                        uint32_t IndexWidth) {
   assert(ABIAlign <= PrefAlign && "Preferred alignment worse than ABI!");
   PointerAlignElem retval;
   retval.AddressSpace = AddressSpace;
   retval.ABIAlign = ABIAlign;
   retval.PrefAlign = PrefAlign;
   retval.TypeByteWidth = TypeByteWidth;
   retval.IndexWidth = IndexWidth;

 DataLayout::findAlignmentLowerBound(AlignTypeEnum AlignType,
                                     uint32_t BitWidth) {
   auto Pair = std::make_pair((unsigned)AlignType, BitWidth);
   return partition_point(Alignments, [=](const LayoutAlignElem &E) {
     return std::make_pair(E.AlignType, E.TypeBitWidth) < Pair;
   });
 }
 
-void DataLayout::setAlignment(AlignTypeEnum align_type, llvm::Align abi_align,
-                              llvm::Align pref_align, uint32_t bit_width) {
+void DataLayout::setAlignment(AlignTypeEnum align_type, Align abi_align,
+                              Align pref_align, uint32_t bit_width) {
   // AlignmentsTy::ABIAlign and AlignmentsTy::PrefAlign were once stored as
   // uint16_t, it is unclear if there are requirements for alignment to be less
   // than 2^16 other than storage. In the meantime we leave the restriction as
   // an assert. See D67400 for context.
   assert(Log2(abi_align) < 16 && Log2(pref_align) < 16 && "Alignment too big");
   if (!isUInt<24>(bit_width))
     report_fatal_error("Invalid bit width, must be a 24bit integer");
   if (pref_align < abi_align)

 DataLayout::PointersTy::iterator
 DataLayout::findPointerLowerBound(uint32_t AddressSpace) {
   return std::lower_bound(Pointers.begin(), Pointers.end(), AddressSpace,
                           [](const PointerAlignElem &A, uint32_t AddressSpace) {
     return A.AddressSpace < AddressSpace;
   });
 }
 
-void DataLayout::setPointerAlignment(uint32_t AddrSpace, llvm::Align ABIAlign,
-                                     llvm::Align PrefAlign,
-                                     uint32_t TypeByteWidth,
+void DataLayout::setPointerAlignment(uint32_t AddrSpace, Align ABIAlign,
+                                     Align PrefAlign, uint32_t TypeByteWidth,
                                      uint32_t IndexWidth) {
   if (PrefAlign < ABIAlign)
     report_fatal_error(
         "Preferred alignment cannot be less than the ABI alignment");
 
   PointersTy::iterator I = findPointerLowerBound(AddrSpace);
   if (I == Pointers.end() || I->AddressSpace != AddrSpace) {
     Pointers.insert(I, PointerAlignElem::get(AddrSpace, ABIAlign, PrefAlign,
                                              TypeByteWidth, IndexWidth));
   } else {
     I->ABIAlign = ABIAlign;
     I->PrefAlign = PrefAlign;
     I->TypeByteWidth = TypeByteWidth;
     I->IndexWidth = IndexWidth;
   }
 }
 
 /// getAlignmentInfo - Return the alignment (either ABI if ABIInfo = true or
 /// preferred if ABIInfo = false) the layout wants for the specified datatype.
-llvm::Align DataLayout::getAlignmentInfo(AlignTypeEnum AlignType,
-                                         uint32_t BitWidth, bool ABIInfo,
-                                         Type *Ty) const {
+Align DataLayout::getAlignmentInfo(AlignTypeEnum AlignType, uint32_t BitWidth,
+                                   bool ABIInfo, Type *Ty) const {
   AlignmentsTy::const_iterator I = findAlignmentLowerBound(AlignType, BitWidth);
   // See if we found an exact match. Of if we are looking for an integer type,
   // but don't have an exact match take the next largest integer. This is where
   // the lower_bound will point to when it fails an exact match.
   if (I != Alignments.end() && I->AlignType == (unsigned)AlignType &&
       (I->TypeBitWidth == BitWidth || AlignType == INTEGER_ALIGN))
     return ABIInfo ? I->ABIAlign : I->PrefAlign;
 
const StructLayout *DataLayout::getStructLayout(StructType *Ty) const {
   // entries to be added to TheMap, invalidating our reference.
   SL = L;
 
   new (L) StructLayout(Ty, *this);
 
   return L;
 }
 
-llvm::Align DataLayout::getPointerABIAlignment(unsigned AS) const {
+Align DataLayout::getPointerABIAlignment(unsigned AS) const {
   PointersTy::const_iterator I = findPointerLowerBound(AS);
   if (I == Pointers.end() || I->AddressSpace != AS) {
     I = findPointerLowerBound(0);
     assert(I->AddressSpace == 0);
   }
   return I->ABIAlign;
 }
 
-llvm::Align DataLayout::getPointerPrefAlignment(unsigned AS) const {
+Align DataLayout::getPointerPrefAlignment(unsigned AS) const {
   PointersTy::const_iterator I = findPointerLowerBound(AS);
   if (I == Pointers.end() || I->AddressSpace != AS) {
     I = findPointerLowerBound(0);
     assert(I->AddressSpace == 0);
   }
   return I->PrefAlign;
 }
 

 /*!
   \param abi_or_pref Flag that determines which alignment is returned. true
   returns the ABI alignment, false returns the preferred alignment.
   \param Ty The underlying type for which alignment is determined.
 
   Get the ABI (\a abi_or_pref == true) or preferred alignment (\a abi_or_pref
   == false) for the requested type \a Ty.
  */
-llvm::Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const {
+Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const {
   AlignTypeEnum AlignType;
 
   assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
   switch (Ty->getTypeID()) {
   // Early escape for the non-numeric types.
   case Type::LabelTyID:
     return abi_or_pref ? getPointerABIAlignment(0) : getPointerPrefAlignment(0);
   case Type::PointerTyID: {
     unsigned AS = cast<PointerType>(Ty)->getAddressSpace();
     return abi_or_pref ? getPointerABIAlignment(AS)
                        : getPointerPrefAlignment(AS);
     }
   case Type::ArrayTyID:
     return getAlignment(cast<ArrayType>(Ty)->getElementType(), abi_or_pref);
 
   case Type::StructTyID: {
     // Packed structure types always have an ABI alignment of one.
     if (cast<StructType>(Ty)->isPacked() && abi_or_pref)
-      return llvm::Align::None();
+      return Align::None();
 
     // Get the layout annotation... which is lazily created on demand.
     const StructLayout *Layout = getStructLayout(cast<StructType>(Ty));
-    const llvm::Align Align =
-        getAlignmentInfo(AGGREGATE_ALIGN, 0, abi_or_pref, Ty);
+    const Align Align = getAlignmentInfo(AGGREGATE_ALIGN, 0, abi_or_pref, Ty);
     return std::max(Align, Layout->getAlignment());
   }
   case Type::IntegerTyID:
     AlignType = INTEGER_ALIGN;
     break;
   case Type::HalfTyID:
   case Type::FloatTyID:
   case Type::DoubleTyID:

 }
 
 unsigned DataLayout::getABITypeAlignment(Type *Ty) const {
   return getAlignment(Ty, true).value();
 }
 
 /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for
 /// an integer type of the specified bitwidth.
-llvm::Align DataLayout::getABIIntegerTypeAlignment(unsigned BitWidth) const {
+Align DataLayout::getABIIntegerTypeAlignment(unsigned BitWidth) const {
   return getAlignmentInfo(INTEGER_ALIGN, BitWidth, true, nullptr);
 }
 
 unsigned DataLayout::getPrefTypeAlignment(Type *Ty) const {
   return getAlignment(Ty, false).value();
 }
 
 IntegerType *DataLayout::getIntPtrType(LLVMContext &C,

llvm/lib/IR/Instructions.cpp

AllocaInst::AllocaInst(Type *Ty, unsigned AddrSpace, Value *ArraySize,
   assert(!Ty->isVoidTy() && "Cannot allocate void!");
   setName(Name);
 }
 
 void AllocaInst::setAlignment(unsigned Align) {
   setAlignment(llvm::MaybeAlign(Align));
 }
 
-void AllocaInst::setAlignment(llvm::MaybeAlign Align) {
+void AllocaInst::setAlignment(MaybeAlign Align) {
   assert((!Align || *Align <= MaximumAlignment) &&
          "Alignment is greater than MaximumAlignment!");
   setInstructionSubclassData((getSubclassDataFromInstruction() & ~31) |
                              encode(Align));
   if (Align)
     assert(getAlignment() == Align->value() &&
            "Alignment representation error!");
   else
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile,
   AssertOK();
   setName(Name);
 }
 
 void LoadInst::setAlignment(unsigned Align) {
   setAlignment(llvm::MaybeAlign(Align));
 }
 
-void LoadInst::setAlignment(llvm::MaybeAlign Align) {
+void LoadInst::setAlignment(MaybeAlign Align) {
   assert((!Align || *Align <= MaximumAlignment) &&
          "Alignment is greater than MaximumAlignment!");
   setInstructionSubclassData((getSubclassDataFromInstruction() & ~(31 << 1)) |
                              (encode(Align) << 1));
   if (Align)
     assert(getAlignment() == Align->value() &&
            "Alignment representation error!");
   else
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile,
   setAtomic(Order, SSID);
   AssertOK();
 }
 
 void StoreInst::setAlignment(unsigned Align) {
   setAlignment(llvm::MaybeAlign(Align));
 }
 
-void StoreInst::setAlignment(llvm::MaybeAlign Align) {
+void StoreInst::setAlignment(MaybeAlign Align) {
   assert((!Align || *Align <= MaximumAlignment) &&
          "Alignment is greater than MaximumAlignment!");
   setInstructionSubclassData((getSubclassDataFromInstruction() & ~(31 << 1)) |
                              (encode(Align) << 1));
   if (Align)
     assert(getAlignment() == Align->value() &&
            "Alignment representation error!");
   else

llvm/lib/IR/Value.cpp

uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL,
   }
   return DerefBytes;
 }
 
 unsigned Value::getPointerAlignment(const DataLayout &DL) const {
   assert(getType()->isPointerTy() && "must be pointer");
   if (auto *GO = dyn_cast<GlobalObject>(this)) {
     if (isa<Function>(GO)) {
-      const llvm::MaybeAlign FunctionPtrAlign = DL.getFunctionPtrAlign();
+      const MaybeAlign FunctionPtrAlign = DL.getFunctionPtrAlign();
       const unsigned Align = FunctionPtrAlign ? FunctionPtrAlign->value() : 0;
       switch (DL.getFunctionPtrAlignType()) {
       case DataLayout::FunctionPtrAlignType::Independent:
         return Align;
       case DataLayout::FunctionPtrAlignType::MultipleOfFunctionAlign:
         return std::max(Align, GO->getAlignment());
       }
       llvm_unreachable("Unhandled FunctionPtrAlignType");

llvm/lib/Object/ArchiveWriter.cpp

else
     Size += NumSyms * OffsetSize; // Table
   if (isBSDLike(Kind))
     Size += OffsetSize; // byte count
   Size += StringTable.size();
   // ld64 expects the members to be 8-byte aligned for 64-bit content and at
   // least 4-byte aligned for 32-bit content.  Opt for the larger encoding
   // uniformly.
   // We do this for all bsd formats because it simplifies aligning members.
-  const llvm::Align Alignment(isBSDLike(Kind) ? 8 : 2);
+  const Align Alignment(isBSDLike(Kind) ? 8 : 2);
   unsigned Pad = offsetToAlignment(Size, Alignment);
   Size += Pad;
 
   if (isBSDLike(Kind)) {
     const char *Name = is64BitKind(Kind) ? "__.SYMDEF_64" : "__.SYMDEF";
     printBSDMemberHeader(Out, Out.tell(), Name, now(Deterministic), 0, 0, 0,
                          Size);
   } else {

llvm/lib/Target/AArch64/AArch64CallingConvention.cpp

 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
                                      AArch64::Q3, AArch64::Q4, AArch64::Q5,
                                      AArch64::Q6, AArch64::Q7};
 
 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
                              MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
                              CCState &State, unsigned SlotAlign) {
   unsigned Size = LocVT.getSizeInBits() / 8;
-  const llvm::Align StackAlign =
+  const Align StackAlign =
       State.getMachineFunction().getDataLayout().getStackAlignment();
-  const llvm::Align OrigAlign(ArgFlags.getOrigAlign());
-  const llvm::Align Align = std::min(OrigAlign, StackAlign);
+  const Align OrigAlign(ArgFlags.getOrigAlign());
+  const Align Align = std::min(OrigAlign, StackAlign);
 
   for (auto &It : PendingMembers) {
     It.convertToMem(State.AllocateStack(
         Size, std::max((unsigned)Align.value(), SlotAlign)));
     State.addLoc(It);
     SlotAlign = 1;
   }
 

llvm/lib/Target/AMDGPU/SIISelLowering.h

public:
   bool denormalsEnabledForType(EVT VT) const;
 
   bool isKnownNeverNaNForTargetNode(SDValue Op,
                                     const SelectionDAG &DAG,
                                     bool SNaN = false,
                                     unsigned Depth = 0) const override;
   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 
-  llvm::Align getPrefLoopAlignment(MachineLoop *ML) const override;
+  Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
   void allocateHSAUserSGPRs(CCState &CCInfo,
                             MachineFunction &MF,
                             const SIRegisterInfo &TRI,
                             SIMachineFunctionInfo &Info) const;
 
   void allocateSystemSGPRs(CCState &CCInfo,
                            MachineFunction &MF,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

TargetLowering::computeKnownBitsForFrameIndex(Op, Known, DemandedElts,
                                                 DAG, Depth);
 
   // Set the high bits to zero based on the maximum allowed scratch size per
   // wave. We can't use vaddr in MUBUF instructions if we don't know the address
   // calculation won't overflow, so assume the sign bit is never set.
   Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
 }
 
-llvm::Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
-  const llvm::Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
-  const llvm::Align CacheLineAlign = llvm::Align(64);
+Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
+  const Align PrefAlign = TargetLowering::getPrefLoopAlignment(ML);
+  const Align CacheLineAlign = llvm::Align(64);
 
   // Pre-GFX10 target did not benefit from loop alignment
   if (!ML || DisableLoopAlignment ||
       (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
       getSubtarget()->hasInstFwdPrefetchBug())
     return PrefAlign;
 
   // On GFX10 I$ is 4 x 64 bytes cache lines.

llvm/lib/Target/ARM/ARMBasicBlockInfo.h

 using BBInfoVector = SmallVectorImpl<BasicBlockInfo>;
 
 /// UnknownPadding - Return the worst case padding that could result from
 /// unknown offset bits.  This does not include alignment padding caused by
 /// known offset bits.
 ///
 /// @param Align alignment
 /// @param KnownBits Number of known low offset bits.
-inline unsigned UnknownPadding(llvm::Align Align, unsigned KnownBits) {
+inline unsigned UnknownPadding(Align Align, unsigned KnownBits) {
   if (KnownBits < Log2(Align))
     return Align.value() - (1ull << KnownBits);
   return 0;
 }
 
 /// BasicBlockInfo - Information about the offset and size of a single
 /// basic block.
 struct BasicBlockInfo {
struct BasicBlockInfo {
 
   /// Unalign - When non-zero, the block contains instructions (inline asm)
   /// of unknown size.  The real size may be smaller than Size bytes by a
   /// multiple of 1 << Unalign.
   uint8_t Unalign = 0;
 
   /// PostAlign - When > 1, the block terminator contains a .align
   /// directive, so the end of the block is aligned to PostAlign bytes.
-  llvm::Align PostAlign;
+  Align PostAlign;
 
   BasicBlockInfo() = default;
 
   /// Compute the number of known offset bits internally to this block.
   /// This number should be used to predict worst case padding when
   /// splitting the block.
   unsigned internalKnownBits() const {
     unsigned Bits = Unalign ? Unalign : KnownBits;
     // If the block size isn't a multiple of the known bits, assume the
     // worst case padding.
     if (Size & ((1u << Bits) - 1))
       Bits = countTrailingZeros(Size);
     return Bits;
   }
 
   /// Compute the offset immediately following this block.  If Align is
   /// specified, return the offset the successor block will get if it has
   /// this alignment.
-  unsigned postOffset(llvm::Align Align = llvm::Align::None()) const {
+  unsigned postOffset(Align Alignment = Align::None()) const {
     unsigned PO = Offset + Size;
-    const llvm::Align PA = std::max(PostAlign, Align);
-    if (PA == llvm::Align::None())
+    const Align PA = std::max(PostAlign, Alignment);
+    if (PA == Align::None())
       return PO;
     // Add alignment padding from the terminator.
     return PO + UnknownPadding(PA, internalKnownBits());
   }
 
   /// Compute the number of known low bits of postOffset.  If this block
   /// contains inline asm, the number of known bits drops to the
   /// instruction alignment.  An aligned terminator may increase the number
   /// of know bits.
   /// If LogAlign is given, also consider the alignment of the next block.
-  unsigned postKnownBits(llvm::Align Align = llvm::Align::None()) const {
+  unsigned postKnownBits(Align Align = Align::None()) const {
     return std::max(Log2(std::max(PostAlign, Align)), internalKnownBits());
   }
 };
 
 class ARMBasicBlockUtils {
 
 private:
   MachineFunction &MF;

llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp

mayOptimizeThumb2Instruction(const MachineInstr *MI) {
   return false;
 }
 
 void ARMBasicBlockUtils::computeBlockSize(MachineBasicBlock *MBB) {
   LLVM_DEBUG(dbgs() << "computeBlockSize: " << MBB->getName() << "\n");
   BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
   BBI.Size = 0;
   BBI.Unalign = 0;
-  BBI.PostAlign = llvm::Align::None();
+  BBI.PostAlign = Align::None();
 
   for (MachineInstr &I : *MBB) {
     BBI.Size += TII->getInstSizeInBytes(I);
     // For inline asm, getInstSizeInBytes returns a conservative estimate.
     // The actual size may be smaller, but still a multiple of the instr size.
     if (I.isInlineAsm())
       BBI.Unalign = isThumb ? 1 : 2;
     // Also consider instructions that may be shrunk later.
LLVM_DEBUG(dbgs() << "Adjust block:\n"
              << " - name: " << BB->getName() << "\n"
              << " - number: " << BB->getNumber() << "\n"
              << " - function: " << MF.getName() << "\n"
              << "   - blocks: " << MF.getNumBlockIDs() << "\n");
 
   for(unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) {
     // Get the offset and known bits at the end of the layout predecessor.
     // Include the alignment of the current block.
-    const llvm::Align Align = MF.getBlockNumbered(i)->getAlignment();
+    const Align Align = MF.getBlockNumbered(i)->getAlignment();
     const unsigned Offset = BBInfo[i - 1].postOffset(Align);
     const unsigned KnownBits = BBInfo[i - 1].postKnownBits(Align);
 
     // This is where block i begins.  Stop if the offset is already correct,
     // and we have updated 2 blocks.  This is the maximum number of blocks
     // changed before calling this function.
     if (i > BBNum + 2 &&
         BBInfo[i].Offset == Offset &&

llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

StringRef getPassName() const override {
       return ARM_CP_ISLANDS_OPT_NAME;
     }
 
   private:
     void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
     void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
     bool BBHasFallthrough(MachineBasicBlock *MBB);
     CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
-    llvm::Align getCPEAlign(const MachineInstr *CPEMI);
+    Align getCPEAlign(const MachineInstr *CPEMI);
     void scanFunctionJumpTables();
     void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
     MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
     void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
     bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
     unsigned getCombinedIndex(const MachineInstr *CPEMI);
     int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
     bool findAvailableWater(CPUser&U, unsigned UserOffset,

 /// To start with, we put them all at the end of the function.
 void
 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
   MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes.
-  const llvm::Align MaxAlign(MCP->getConstantPoolAlignment());
+  const Align MaxAlign(MCP->getConstantPoolAlignment());
   const unsigned MaxLogAlign = Log2(MaxAlign);
 
   // Mark the basic block as required by the const-pool.
   BB->setAlignment(MaxAlign);
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
   MF->ensureAlignment(BB->getAlignment());
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
     if (CPEs[i].CPEMI == CPEMI)
       return &CPEs[i];
   }
   return nullptr;
 }
 
 /// getCPEAlign - Returns the required alignment of the constant pool entry
 /// represented by CPEMI.
-llvm::Align ARMConstantIslands::getCPEAlign(const MachineInstr *CPEMI) {
+Align ARMConstantIslands::getCPEAlign(const MachineInstr *CPEMI) {
   switch (CPEMI->getOpcode()) {
   case ARM::CONSTPOOL_ENTRY:
     break;
   case ARM::JUMPTABLE_TBB:
     return isThumb1 ? llvm::Align(4) : llvm::Align(1);
   case ARM::JUMPTABLE_TBH:
     return isThumb1 ? llvm::Align(4) : llvm::Align(2);
   case ARM::JUMPTABLE_INSTS:

 /// isWaterInRange - Returns true if a CPE placed after the specified
 /// Water (a basic block) will be in range for the specific MI.
 ///
 /// Compute how much the function will grow by inserting a CPE after Water.
 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
                                         MachineBasicBlock* Water, CPUser &U,
                                         unsigned &Growth) {
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
-  const llvm::Align CPEAlign = getCPEAlign(U.CPEMI);
+  const Align CPEAlign = getCPEAlign(U.CPEMI);
   const unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPEAlign);
   unsigned NextBlockOffset;
-  llvm::Align NextBlockAlignment;
+  Align NextBlockAlignment;
   MachineFunction::const_iterator NextBlock = Water->getIterator();
   if (++NextBlock == MF->end()) {
     NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
   } else {
     NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
     NextBlockAlignment = NextBlock->getAlignment();
   }
   unsigned Size = U.CPEMI->getOperand(2).getImm();
bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
   //   BB0:
   //      Big BB
   //   BB1:
   //      Constant Pool
   // When a CP access is out of range, BB0 may be used as water. However,
   // inserting islands between BB0 and BB1 makes other accesses out of range.
   MachineBasicBlock *UserBB = U.MI->getParent();
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
-  const llvm::Align CPEAlign = getCPEAlign(U.CPEMI);
+  const Align CPEAlign = getCPEAlign(U.CPEMI);
   unsigned MinNoSplitDisp = BBInfo[UserBB->getNumber()].postOffset(CPEAlign);
   if (CloserWater && MinNoSplitDisp > U.getMaxDisp() / 2)
     return false;
   for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
        --IP) {
     MachineBasicBlock* WaterBB = *IP;
     // Check if water is in range and is either at a lower address than the
     // current "high water mark" or a new water block that was created since

 /// block following which the new island can be inserted (the WaterList
 /// is not adjusted).
 void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
                                         unsigned UserOffset,
                                         MachineBasicBlock *&NewMBB) {
   CPUser &U = CPUsers[CPUserIndex];
   MachineInstr *UserMI = U.MI;
   MachineInstr *CPEMI  = U.CPEMI;
-  const llvm::Align CPEAlign = getCPEAlign(CPEMI);
+  const Align CPEAlign = getCPEAlign(CPEMI);
   MachineBasicBlock *UserMBB = UserMI->getParent();
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
 
   // If the block does not end in an unconditional branch already, and if the
   // end of the block is within range, make new water there.  (The addition
   // below is for the unconditional branch we will be adding: 4 bytes on ARM +
   // Thumb2, 2 on Thumb1.
void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
   // the instructions between the one currently being looked at and the
   // possible insertion point, and make sure any other instructions that
   // reference CPEs will be able to use the same island area; if not, we back
   // up the insertion point.
 
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // Align which is the largest possible alignment in the function.
-  const llvm::Align Align = MF->getAlignment();
+  const Align Align = MF->getAlignment();
   assert(Align >= CPEAlign && "Over-aligned constant pool entry");
   unsigned KnownBits = UserBBI.internalKnownBits();
   unsigned UPad = UnknownPadding(Align, KnownBits);
   unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
   LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
                               BaseInsertOffset));
 
   // The 4 in the following is for the unconditional branch we'll be inserting
if (IP != WaterList.end())
       NewWaterList.erase(WaterBB);
 
     // We are adding new water.  Update NewWaterList.
     NewWaterList.insert(NewIsland);
   }
   // Always align the new block because CP entries can be smaller than 4
   // bytes. Be careful not to decrease the existing alignment, e.g. NewMBB may
   // be an already aligned constant pool block.
-  const llvm::Align Align = isThumb ? llvm::Align(2) : llvm::Align(4);
+  const Align Align = isThumb ? llvm::Align(2) : llvm::Align(4);
   if (NewMBB->getAlignment() < Align)
     NewMBB->setAlignment(Align);
 
   // Remove the original WaterList entry; we want subsequent insertions in
   // this vicinity to go after the one we're about to insert.  This
   // considerably reduces the number of times we have to move the same CPE
   // more than once and is also important to ensure the algorithm terminates.
   if (IP != WaterList.end())
void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
   CPEMI->eraseFromParent();
   BBInfoVector &BBInfo = BBUtils->getBBInfo();
   BBUtils->adjustBBSize(CPEBB, -Size);
   // All succeeding offsets have the current size value added in, fix this.
   if (CPEBB->empty()) {
     BBInfo[CPEBB->getNumber()].Size = 0;
 
     // This block no longer needs to be aligned.
-    CPEBB->setAlignment(llvm::Align::None());
+    CPEBB->setAlignment(Align::None());
   } else {
     // Entries are sorted by descending alignment, so realign from the front.
     CPEBB->setAlignment(getCPEAlign(&*CPEBB->begin()));
   }
 
   BBUtils->adjustBBOffsetsAfter(CPEBB);
   // An island has only one predecessor BB and one successor BB. Check if
   // this BB's predecessor jumps directly to this BB's successor. This

llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp

bool HexagonBranchRelaxation::runOnMachineFunction(MachineFunction &MF) {
   return Changed;
 }
 
 void HexagonBranchRelaxation::computeOffset(MachineFunction &MF,
       DenseMap<MachineBasicBlock*, unsigned> &OffsetMap) {
   // offset of the current instruction from the start.
   unsigned InstOffset = 0;
   for (auto &B : MF) {
-    if (B.getAlignment() != llvm::Align::None()) {
+    if (B.getAlignment() != Align::None()) {
       // Although we don't know the exact layout of the final code, we need
       // to account for alignment padding somehow. This heuristic pads each
       // aligned basic block according to the alignment value.
       InstOffset = alignTo(InstOffset, B.getAlignment());
     }
     OffsetMap[&B] = InstOffset;
     for (auto &MI : B.instrs()) {
       InstOffset += HII->getSize(MI);

llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp

bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
   // Map for each basic block to it's first instruction.
   DenseMap<const MachineBasicBlock *, unsigned> BlockToInstOffset;
 
   const HexagonInstrInfo *HII =
       static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
 
   // First pass - compute the offset of each basic block.
   for (const MachineBasicBlock &MBB : MF) {
-    if (MBB.getAlignment() != llvm::Align::None()) {
+    if (MBB.getAlignment() != Align::None()) {
       // Although we don't know the exact layout of the final code, we need
       // to account for alignment padding somehow. This heuristic pads each
       // aligned basic block according to the alignment value.
       InstOffset = alignTo(InstOffset, MBB.getAlignment());
     }
 
     BlockToInstOffset[&MBB] = InstOffset;
     for (const MachineInstr &MI : MBB)

llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h

 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
 
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/Support/Alignment.h"
 
 namespace llvm {
 
 // NaCl MIPS sandbox's instruction bundle size.
-static const llvm::Align MIPS_NACL_BUNDLE_ALIGN = llvm::Align(16);
+static const Align MIPS_NACL_BUNDLE_ALIGN = llvm::Align(16);
 
 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
                                   bool *IsStore = nullptr);
 bool baseRegNeedsLoadStoreMask(unsigned Reg);
 
 // This function creates an MCELFStreamer for Mips NaCl.
 MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
                                          std::unique_ptr<MCAsmBackend> TAB,
                                          std::unique_ptr<MCObjectWriter> OW,
                                          std::unique_ptr<MCCodeEmitter> Emitter,
                                          bool RelaxAll);
 }
 
 #endif

llvm/lib/Target/Mips/MipsConstantIslandPass.cpp

public:
 
     MachineFunctionProperties getRequiredProperties() const override {
       return MachineFunctionProperties().set(
           MachineFunctionProperties::Property::NoVRegs);
     }
 
     void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
     CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
-    llvm::Align getCPEAlign(const MachineInstr &CPEMI);
+    Align getCPEAlign(const MachineInstr &CPEMI);
     void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
     unsigned getOffsetOf(MachineInstr *MI) const;
     unsigned getUserOffset(CPUser&) const;
     void dumpBBs();
 
     bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
                          unsigned Disp, bool NegativeOK);
     bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,

 /// entries.  To start with, we put them all at the end of the function.
 void
 MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
   // Create the basic block to hold the CPE's.
   MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
   MF->push_back(BB);
 
   // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
-  const llvm::Align MaxAlign(MCP->getConstantPoolAlignment());
+  const Align MaxAlign(MCP->getConstantPoolAlignment());
 
   // Mark the basic block as required by the const-pool.
   // If AlignConstantIslands isn't set, use 4-byte alignment for everything.
   BB->setAlignment(AlignConstantIslands ? MaxAlign : llvm::Align(4));
 
   // The function needs to be as aligned as the basic blocks. The linker may
   // move functions around based on their alignment.
   MF->ensureAlignment(BB->getAlignment());
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
     if (CPEs[i].CPEMI == CPEMI)
       return &CPEs[i];
   }
   return nullptr;
 }
 
 /// getCPEAlign - Returns the required alignment of the constant pool entry
 /// represented by CPEMI.  Alignment is measured in log2(bytes) units.
-llvm::Align MipsConstantIslands::getCPEAlign(const MachineInstr &CPEMI) {
+Align MipsConstantIslands::getCPEAlign(const MachineInstr &CPEMI) {
   assert(CPEMI.getOpcode() == Mips::CONSTPOOL_ENTRY);
 
   // Everything is 4-byte aligned unless AlignConstantIslands is set.
   if (!AlignConstantIslands)
     return llvm::Align(4);
 
   unsigned CPI = CPEMI.getOperand(1).getIndex();
   assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");

 /// Water (a basic block) will be in range for the specific MI.
 ///
 /// Compute how much the function will grow by inserting a CPE after Water.
 bool MipsConstantIslands::isWaterInRange(unsigned UserOffset,
                                         MachineBasicBlock* Water, CPUser &U,
                                         unsigned &Growth) {
   unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset();
   unsigned NextBlockOffset;
-  llvm::Align NextBlockAlignment;
+  Align NextBlockAlignment;
   MachineFunction::const_iterator NextBlock = ++Water->getIterator();
   if (NextBlock == MF->end()) {
     NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
-    NextBlockAlignment = llvm::Align::None();
+    NextBlockAlignment = Align::None();
   } else {
     NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
     NextBlockAlignment = NextBlock->getAlignment();
   }
   unsigned Size = U.CPEMI->getOperand(2).getImm();
   unsigned CPEEnd = CPEOffset + Size;
 
   // The CPE may be able to hide in the alignment padding before the next
if (BBHasFallthrough(UserMBB)) {
     }
   }
 
   // What a big block.  Find a place within the block to split it.
 
   // Try to split the block so it's fully aligned.  Compute the latest split
   // point where we can add a 4-byte branch instruction, and then align to
   // Align which is the largest possible alignment in the function.
-  const llvm::Align Align = MF->getAlignment();
+  const Align Align = MF->getAlignment();
   unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
   LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
                               BaseInsertOffset));
 
   // The 4 in the following is for the unconditional branch we'll be inserting
   // Alignment of the island is handled
   // inside isOffsetInRange.
   BaseInsertOffset -= 4;

llvm/lib/Target/Mips/MipsISelLowering.cpp

return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
                       MachinePointerInfo(SV));
 }
 
 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
   SDNode *Node = Op.getNode();
   EVT VT = Node->getValueType(0);
   SDValue Chain = Node->getOperand(0);
   SDValue VAListPtr = Node->getOperand(1);
-  const llvm::Align Align =
+  const Align Align =
       llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   SDLoc DL(Node);
   unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
 
   SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
                                    VAListPtr, MachinePointerInfo(SV));
   SDValue VAList = VAListLoad;

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
       // If the first operand is a FI, get the TargetFI Node
       if (FrameIndexSDNode *FIN =
               dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
       else {
         Base = Addr.getOperand(0);
         // If base is a FI, additional offset calculation is done in
         // eliminateFrameIndex, otherwise we need to check the alignment
-        const llvm::Align Align(1ULL << ShiftAmount);
+        const Align Align(1ULL << ShiftAmount);
         if (!isAligned(Align, CN->getZExtValue()))
           return false;
       }
 
       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
                                          ValTy);
       return true;
     }

llvm/lib/Target/Mips/MipsSERegisterInfo.cpp

LLVM_DEBUG(errs() << "Offset     : " << Offset << "\n"
                     << "<--------->\n");
 
   if (!MI.isDebugValue()) {
     // Make sure Offset fits within the field available.
     // For MSA instructions, this is a 10-bit signed immediate (scaled by
     // element size), otherwise it is a 16-bit signed immediate.
     unsigned OffsetBitSize =
         getLoadStoreOffsetSizeInBits(MI.getOpcode(), MI.getOperand(OpNo - 1));
-    const llvm::Align OffsetAlign(getLoadStoreOffsetAlign(MI.getOpcode()));
+    const Align OffsetAlign(getLoadStoreOffsetAlign(MI.getOpcode()));
     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
         (!isIntN(OffsetBitSize, Offset) || !isAligned(OffsetAlign, Offset))) {
       // If we have an offset that needs to fit into a signed n-bit immediate
       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
       MachineBasicBlock &MBB = *MI.getParent();
       DebugLoc DL = II->getDebugLoc();
       const TargetRegisterClass *PtrRC =
           ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

 FunctionPass *llvm::createPPCBranchSelectionPass() {
   return new PPCBSel();
 }
 
 /// In order to make MBB aligned, we need to add an adjustment value to the
 /// original Offset.
 unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB,
                                          unsigned Offset) {
-  const llvm::Align Align = MBB.getAlignment();
-  if (Align == 1)
+  const Align Alignment = MBB.getAlignment();
+  if (Alignment == Align::None())
     return 0;
 
-  const llvm::Align ParentAlign = MBB.getParent()->getAlignment();
+  const Align ParentAlign = MBB.getParent()->getAlignment();
 
-  if (Align <= ParentAlign)
-    return offsetToAlignment(Offset, Align);
+  if (Alignment <= ParentAlign)
+    return offsetToAlignment(Offset, Alignment);
 
   // The alignment of this MBB is larger than the function's alignment, so we
   // can't tell whether or not it will insert nops. Assume that it will.
   if (FirstImpreciseBlock < 0)
     FirstImpreciseBlock = MBB.getNumber();
-  return Align.value() + offsetToAlignment(Offset, Align);
+  return Alignment.value() + offsetToAlignment(Offset, Alignment);
 }
 
 /// We need to be careful about the offset of the first block in the function
 /// because it might not have the function's alignment. This happens because,
 /// under the ELFv2 ABI, for functions which require a TOC pointer, we add a
 /// two-instruction sequence to the start of the function.
 /// Note: This needs to be synchronized with the check in
 /// PPCLinuxAsmPrinter::EmitFunctionBodyStart.

 
 /// Determine the offset from the branch in Src block to the Dest block.
 /// BrOffset is the offset of the branch instruction inside Src block.
 int PPCBSel::computeBranchSize(MachineFunction &Fn,
                                const MachineBasicBlock *Src,
                                const MachineBasicBlock *Dest,
                                unsigned BrOffset) {
   int BranchSize;
-  llvm::Align MaxAlign = llvm::Align(4);
+  Align MaxAlign = llvm::Align(4);
   bool NeedExtraAdjustment = false;
   if (Dest->getNumber() <= Src->getNumber()) {
     // If this is a backwards branch, the delta is the offset from the
     // start of this block to this branch, plus the sizes of all blocks
     // from this block to the dest.
     BranchSize = BrOffset;
     MaxAlign = std::max(MaxAlign, Src->getAlignment());
 

llvm/lib/Target/PowerPC/PPCISelLowering.h

unsigned getRegisterByName(const char* RegName, EVT VT,
                                SelectionDAG &DAG) const override;
 
     void computeKnownBitsForTargetNode(const SDValue Op,
                                        KnownBits &Known,
                                        const APInt &DemandedElts,
                                        const SelectionDAG &DAG,
                                        unsigned Depth = 0) const override;
 
-    llvm::Align getPrefLoopAlignment(MachineLoop *ML) const override;
+    Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
       return true;
     }
 
     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
                                   AtomicOrdering Ord) const override;
     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case ISD::INTRINSIC_WO_CHAIN: {
     case Intrinsic::ppc_altivec_vcmpgtud_p:
       Known.Zero = ~1U;  // All bits but the low one are known to be zero.
       break;
     }
   }
   }
 }
 
-llvm::Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
+Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
   switch (Subtarget.getDarwinDirective()) {
   default: break;
   case PPC::DIR_970:
   case PPC::DIR_PWR4:
   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtA()) {
     setMinCmpXchgSizeInBits(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
   // Function alignments.
-  const llvm::Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
+  const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,

llvm/lib/Target/SystemZ/SystemZLongBranch.cpp

struct MBBInfo {
   uint64_t Address = 0;
 
   // The size of the block in bytes, excluding terminators.
   // This value never changes.
   uint64_t Size = 0;
 
   // The minimum alignment of the block.
   // This value never changes.
-  llvm::Align Alignment;
+  Align Alignment;
 
   // The number of terminators in this block.  This value never changes.
   unsigned NumTerminators = 0;
 
   MBBInfo() = default;
 };
 
 // Represents the state of a block terminator.

llvm/lib/Target/X86/X86TargetTransformInfo.h

public:
   int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
   int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                     Type *Ty);
   bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
                      TargetTransformInfo::LSRCost &C2);
   bool canMacroFuseCmp();
   bool isLegalMaskedLoad(Type *DataType);
   bool isLegalMaskedStore(Type *DataType);
-  bool isLegalNTLoad(Type *DataType, llvm::Align Alignment);
-  bool isLegalNTStore(Type *DataType, llvm::Align Alignment);
+  bool isLegalNTLoad(Type *DataType, Align Alignment);
+  bool isLegalNTStore(Type *DataType, Align Alignment);
   bool isLegalMaskedGather(Type *DataType);
   bool isLegalMaskedScatter(Type *DataType);
   bool isLegalMaskedExpandLoad(Type *DataType);
   bool isLegalMaskedCompressStore(Type *DataType);
   bool hasDivRemOp(Type *DataType, bool IsSigned);
   bool isFCmpOrdCheaperThanFCmpZero(Type *Ty);
   bool areInlineCompatible(const Function *Caller,
                            const Function *Callee) const;

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) {
   return IntWidth == 32 || IntWidth == 64 ||
          ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI());
 }
 
 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) {
   return isLegalMaskedLoad(DataType);
 }
 
-bool X86TTIImpl::isLegalNTLoad(Type *DataType, llvm::Align Alignment) {
+bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) {
   unsigned DataSize = DL.getTypeStoreSize(DataType);
   // The only supported nontemporal loads are for aligned vectors of 16 or 32
   // bytes.  Note that 32-byte nontemporal vector loads are supported by AVX2
   // (the equivalent stores only require AVX).
   if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32))
     return DataSize == 16 ?  ST->hasSSE1() : ST->hasAVX2();
 
   return false;
 }
 
-bool X86TTIImpl::isLegalNTStore(Type *DataType, llvm::Align Alignment) {
+bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) {
   unsigned DataSize = DL.getTypeStoreSize(DataType);
 
   // SSE4A supports nontemporal stores of float and double at arbitrary
   // alignment.
   if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy()))
     return true;
 
   // Besides the SSE4A subtarget exception above, only aligned stores are

llvm/lib/Target/XCore/XCoreAsmPrinter.cpp

if (!GV->hasInitializer() ||
       EmitSpecialLLVMGlobal(GV))
     return;
 
   const DataLayout &DL = getDataLayout();
   OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(GV, TM));
 
   MCSymbol *GVSym = getSymbol(GV);
   const Constant *C = GV->getInitializer();
-  const llvm::Align Align(DL.getPrefTypeAlignment(C->getType()));
+  const Align Align(DL.getPrefTypeAlignment(C->getType()));
 
   // Mark the start of the global
   getTargetStreamer().emitCCTopData(GVSym->getName());
 
   switch (GV->getLinkage()) {
   case GlobalValue::AppendingLinkage:
     report_fatal_error("AppendingLinkage is not supported by this target!");
   case GlobalValue::LinkOnceAnyLinkage: