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[llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets
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Authored by nickdesaulniers on Dec 19 2022, 6:53 PM.

Details

Summary

Follow up to the series:

  1. https://reviews.llvm.org/D140161
  2. https://reviews.llvm.org/D140349
  3. https://reviews.llvm.org/D140331
  4. https://reviews.llvm.org/D140323

Completes the work from the previous two for remaining targets.

This creates the following named passes that can be run via
llc -{start|stop}-{before|after}:

  • arc-isel
  • arm-isel
  • avr-isel
  • bpf-isel
  • csky-isel
  • hexagon-isel
  • lanai-isel
  • loongarch-isel
  • m68k-isel
  • msp430-isel
  • mips-isel
  • nvptx-isel
  • ppc-codegen
  • riscv-isel
  • sparc-isel
  • systemz-isel
  • ve-isel
  • wasm-isel
  • xcore-isel

A nice way to write tests for SelectionDAGISel might be to use a RUN:
line like:
llc -mtriple=<triple> -start-before=<arch>-isel -stop-after=finalize-isel -o -

Fixes: https://github.com/llvm/llvm-project/issues/59538

Diff Detail

Event Timeline

Herald added a project: Restricted Project. · View Herald TranscriptDec 19 2022, 6:53 PM
nickdesaulniers requested review of this revision.Dec 19 2022, 6:53 PM
asb accepted this revision.Dec 20 2022, 1:44 AM

LGTM - thanks for tackling this one!

The reordering of class Foo lines could have perhaps been done in a separate NFC commit, but it's not worth the hassle of splitting out at this point.

I note that git clang-format has a couple of suggestions (at least the NVTPX one matches the style of the surrounding lines, things are more inconsistent in HexagonTargetMachine.cpp):

$ git clang-format --diff
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 637d13221cca..b3865e861f2a 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -42,7 +42,6 @@ using namespace llvm;
 #define DEBUG_TYPE "arm-isel"
 #define PASS_NAME "ARM Instruction Selection"
 
-
 static cl::opt<bool>
 DisableShifterOp("disable-shifter-op", cl::Hidden,
   cl::desc("Disable isel of shifter-op"),
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index e5e0d517e69f..e275110bd7e6 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -155,7 +155,7 @@ namespace llvm {
   void initializeHexagonPacketizerPass(PassRegistry&);
   void initializeHexagonRDFOptPass(PassRegistry&);
   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
-  void initializeHexagonVExtractPass(PassRegistry&);
+  void initializeHexagonVExtractPass(PassRegistry &);
   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
   Pass *createHexagonLoopIdiomPass();
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index e51432b3f325..8cc0bccda8d9 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -71,8 +71,8 @@ void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
 void initializeNVPTXLowerAllocaPass(PassRegistry &);
 void initializeNVPTXLowerArgsPass(PassRegistry &);
 void initializeNVPTXProxyRegErasurePass(PassRegistry &);
-void initializeNVVMIntrRangePass(PassRegistry&);
-void initializeNVVMReflectPass(PassRegistry&);
+void initializeNVVMIntrRangePass(PassRegistry &);
+void initializeNVVMReflectPass(PassRegistry &);
 
 } // end namespace llvm
This revision is now accepted and ready to land.Dec 20 2022, 1:44 AM
  • git clang-format HEAD~
  • fix -Wextra-qualification in llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
zixuan-wu accepted this revision.Dec 20 2022, 8:00 PM
zixuan-wu edited reviewers, added: zixuan-wu; removed: Zeson.