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marksl (Mark Schimmel)
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User Since
Feb 4 2016, 9:07 AM (245 w, 4 d)

Recent Activity

Wed, Oct 14

marksl added inline comments to D88907: Polly - specify address space when creating a pointer to a vector type.
Wed, Oct 14, 7:44 AM · Restricted Project, Restricted Project

Wed, Oct 7

marksl updated the diff for D88907: Polly - specify address space when creating a pointer to a vector type.

Reduced the arguments to opt

Wed, Oct 7, 12:23 PM · Restricted Project, Restricted Project

Tue, Oct 6

marksl requested review of D88907: Polly - specify address space when creating a pointer to a vector type.
Tue, Oct 6, 8:53 AM · Restricted Project, Restricted Project

Mar 26 2020

marksl added a comment to D68510: [PATCH 16/27] [noalias] Clone scopes and llvm.noalias.decl when unrolling..

I assume that a similar fix would then be necessary for loop peeling (and any such loop optimization that clones blocks).

Mar 26 2020, 3:14 PM · Restricted Project

Feb 25 2019

marksl created D58629: Inlining Entry/Exit Instrumentation.
Feb 25 2019, 8:38 AM · Restricted Project

Apr 19 2017

marksl abandoned D32240: InstCombineCast AShr transformation.

This does not appear to be an issue on the trunk.

Apr 19 2017, 4:28 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.

Now with transform and test case.

Apr 19 2017, 3:09 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.

Added test case

Apr 19 2017, 3:06 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.
Apr 19 2017, 2:54 PM
marksl created D32240: InstCombineCast AShr transformation.
Apr 19 2017, 12:43 PM

Jun 16 2016

marksl added a comment to D16829: An implementation of Swing Modulo Scheduling.

After ISEL our compare instructions, multiply, and MAC instructions have real physical register side effects. I'm getting errors from SWP for loops containing these physical register dependencies. Are you aware of this? Is there a way to model physical register dependencies with loop carried dependencies such that we would generate correct code for them?

Jun 16 2016, 11:23 AM

Apr 22 2016

marksl updated the diff for D19239: Modified MachinePipeliner http://reviews.llvm.org/D16829.

This version of MachinePipeliner.cpp contains several fixes. Please search for SYNOPSYS for my changes to Brendon's original source.

Apr 22 2016, 4:08 PM · Restricted Project

Apr 18 2016

marksl retitled D19239: Modified MachinePipeliner http://reviews.llvm.org/D16829 from to Modified MachinePipeliner http://reviews.llvm.org/D16829.
Apr 18 2016, 2:38 PM · Restricted Project

Mar 9 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 9 2016, 1:43 PM

Mar 1 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 1 2016, 9:08 AM
marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 1 2016, 7:58 AM

Feb 12 2016

marksl accepted D16829: An implementation of Swing Modulo Scheduling.

Very nice work Brandon.

Feb 12 2016, 4:39 PM

Feb 11 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 11 2016, 4:59 PM
marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 11 2016, 9:59 AM

Feb 5 2016

marksl added a comment to D16829: An implementation of Swing Modulo Scheduling.

If you have a functional unit that issues in stages such that another instruction of needing the same FU can ussue the very next cycle, then isn't the sum of the cycles too great? Example:

Feb 5 2016, 2:24 PM