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myhsu (Min-Yih Hsu)
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Sep 1 2017, 5:24 AM (247 w, 1 d)

Recent Activity

Yesterday

myhsu added inline comments to D126349: [TableGen] Remove code beads.
Fri, May 27, 9:47 AM · Restricted Project, Restricted Project

Thu, May 26

myhsu committed rGad73ce318ef9: [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()) (authored by Ghost-LZW).
[Target] use getSubtarget<> instead of static_cast<>(getSubtarget())
Thu, May 26, 11:24 AM · Restricted Project, Restricted Project
myhsu closed D125391: [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()).
Thu, May 26, 11:24 AM · Restricted Project, Restricted Project
myhsu added a comment to D126349: [TableGen] Remove code beads.

Please implement M68kInstrInfo::isPCRelRegisterOperandLegal as suggested by the inline comment. Otherwise rest of the patch looks good :-)

Thu, May 26, 11:18 AM · Restricted Project, Restricted Project
myhsu added a comment to D125444: [M68k] Add MC support for link/unlk.

Thank you for working on these instructions. I will recommend to add codegen support in this patch as well.

Thu, May 26, 9:18 AM · Restricted Project, Restricted Project

Tue, May 24

myhsu added a comment to D125391: [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()).

Ping and Please note that I do not have commit rights.

Tue, May 24, 9:19 AM · Restricted Project, Restricted Project

Sat, May 21

myhsu accepted D125948: [M68k] Fix decoding conflict between move instructions and their tail call version.

LGTM. Thanks for fixing it.
Large portion of this patch seems to be additional tests for MOVE. Can you split them into a separate commit? (no need to create another Phab review, I've reviewed those test cases)

Sat, May 21, 6:04 PM · Restricted Project, Restricted Project
myhsu committed rG52d509f38b50: [M68k][Disassembler] Cleanup unused variables. NFC (authored by myhsu).
[M68k][Disassembler] Cleanup unused variables. NFC
Sat, May 21, 5:27 PM · Restricted Project, Restricted Project

Fri, May 20

myhsu committed rGf088b99eac74: [mlir][LLVMIR] Use the correct way to determine if it's a scalable vector (authored by myhsu).
[mlir][LLVMIR] Use the correct way to determine if it's a scalable vector
Fri, May 20, 9:48 PM · Restricted Project, Restricted Project
myhsu committed rG3b91657c7bc1: [mlir][LLVMIR] Add support for translating from some simple LLVM instructions (authored by myhsu).
[mlir][LLVMIR] Add support for translating from some simple LLVM instructions
Fri, May 20, 9:47 PM · Restricted Project, Restricted Project
myhsu closed D125818: [mlir][LLVMIR] Use the correct way to determine if it's a scalable vector.
Fri, May 20, 9:47 PM · Restricted Project, Restricted Project
myhsu closed D125817: [mlir][LLVMIR] Add support for translating from some simple LLVM instructions.
Fri, May 20, 9:47 PM · Restricted Project, Restricted Project

Thu, May 19

myhsu added a comment to D125817: [mlir][LLVMIR] Add support for translating from some simple LLVM instructions.

Just a FYI: the simple opcode map is sorted by instruction ordering listed in LangRef.

Thu, May 19, 10:41 AM · Restricted Project, Restricted Project
myhsu updated the diff for D125817: [mlir][LLVMIR] Add support for translating from some simple LLVM instructions.

Cleanup the opcode map for simple instructions and add // clang-format off/on comments on those lines (NFC).

Thu, May 19, 10:40 AM · Restricted Project, Restricted Project

Tue, May 17

myhsu requested review of D125818: [mlir][LLVMIR] Use the correct way to determine if it's a scalable vector.
Tue, May 17, 10:49 AM · Restricted Project, Restricted Project
myhsu requested review of D125817: [mlir][LLVMIR] Add support for translating from some simple LLVM instructions.
Tue, May 17, 10:43 AM · Restricted Project, Restricted Project
myhsu committed rG0b168a49bf58: [mlir][LLVMIR] Use a new way to verify GEPOp indices (authored by myhsu).
[mlir][LLVMIR] Use a new way to verify GEPOp indices
Tue, May 17, 10:30 AM · Restricted Project, Restricted Project
myhsu closed D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.
Tue, May 17, 10:30 AM · Restricted Project, Restricted Project
myhsu updated the diff for D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.
  • Prefix the name of our llvm::ErrorInfo classes with "GEP" and add some documentations (NFC).
  • Addressed minor issues.
Tue, May 17, 10:26 AM · Restricted Project, Restricted Project

Mon, May 16

myhsu accepted D125674: [mlir][LLVMIR] Add support for translating insertelement/extractelement..

LGTM. Thank you!

Mon, May 16, 9:33 AM · Restricted Project, Restricted Project

Sun, May 15

myhsu updated the diff for D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.

This is a major revision which verifies GEPOp indices using the index operand values rather than just the type. This can also solve multiple other problems on the way, for instance, refine/promote the struct index value into constant and check if the index is out of bound.

Sun, May 15, 3:32 PM · Restricted Project, Restricted Project

Sat, May 14

myhsu committed rG3da65c4c0b00: [mlir][LLVMIR] Add support for translating shufflevector (authored by myhsu).
[mlir][LLVMIR] Add support for translating shufflevector
Sat, May 14, 3:15 PM · Restricted Project, Restricted Project
myhsu committed rGb8f52c08f85a: [mlir][LLVMIR] Add support for translating insert/extractvalue (authored by myhsu).
[mlir][LLVMIR] Add support for translating insert/extractvalue
Sat, May 14, 3:15 PM · Restricted Project, Restricted Project
myhsu closed D125030: [mlir][LLVMIR] Add support for translating shufflevector.
Sat, May 14, 3:15 PM · Restricted Project, Restricted Project
myhsu closed D125028: [mlir][LLVMIR] Add support for translating insert/extractvalue.
Sat, May 14, 3:15 PM · Restricted Project, Restricted Project
myhsu accepted D120960: [M68k][Disassembler] Adopt the new variable length decoder.
Sat, May 14, 3:02 PM · Restricted Project, Restricted Project

Wed, May 11

myhsu accepted D125391: [Target] use getSubtarget<> instead of static_cast<>(getSubtarget()).

Looks good on m68k changes

Wed, May 11, 2:43 PM · Restricted Project, Restricted Project

Fri, May 6

myhsu updated the diff for D125030: [mlir][LLVMIR] Add support for translating shufflevector.

Removed (null) checks on ArrayAttr

Fri, May 6, 3:03 PM · Restricted Project, Restricted Project
myhsu updated the diff for D125028: [mlir][LLVMIR] Add support for translating insert/extractvalue.

Remove (null) checks on ArrayAttr values

Fri, May 6, 3:02 PM · Restricted Project, Restricted Project

Thu, May 5

myhsu requested review of D125030: [mlir][LLVMIR] Add support for translating shufflevector.
Thu, May 5, 11:39 AM · Restricted Project, Restricted Project
myhsu updated the diff for D125028: [mlir][LLVMIR] Add support for translating insert/extractvalue.

Spelling out auto variables.

Thu, May 5, 11:38 AM · Restricted Project, Restricted Project
myhsu requested review of D125028: [mlir][LLVMIR] Add support for translating insert/extractvalue.
Thu, May 5, 11:27 AM · Restricted Project, Restricted Project
myhsu accepted D124987: Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`.

LGTM. Please fix the include guard though

Thu, May 5, 11:20 AM · Restricted Project, Restricted Project
myhsu added a comment to D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.

It turns out this patch fails this test in test/Dialect/LLVMIR/invalid.mlir:

func.func @gep_struct_variable(%arg0: !llvm.ptr<struct<(i32)>>, %arg1: i32, %arg2: i32) {
  // expected-error @below {{op expected index 1 indexing a struct to be constant}}
  llvm.getelementptr %arg0[%arg1, %arg1] : (!llvm.ptr<struct<(i32)>>, i32, i32) -> !llvm.ptr<i32>
  return
}

Which does contain an invalid GEP index. That means, we're too permissive with the new changes.

Thu, May 5, 11:10 AM · Restricted Project, Restricted Project
myhsu updated the diff for D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.
  • Test GEP indices in the translation test
  • Add MLIR-only test to test GEPOp::build
Thu, May 5, 11:02 AM · Restricted Project, Restricted Project
myhsu added a comment to D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.

Thanks, something might be off with the check, but I'm not sure I agree with your current assessment. The verifier does recurse into structs - https://github.com/llvm/llvm-project/blob/ff8d0b338f48ab26919ac84aef2c79e1e1a20ef2/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp#L406-L429. My another suspicion is that build methods are not matching your expectation, it would be helpful to have a MLIR-only test that demonstrates the problem by parsing IR, rather than building it (use the generic form to bypass parser checks). If this proves impossible, the issue is in the build method.

Thu, May 5, 10:57 AM · Restricted Project, Restricted Project

Wed, May 4

myhsu committed rG794c4218a647: [mlir][LLVMIR] Do not update instMap via assignments to entry references (authored by myhsu).
[mlir][LLVMIR] Do not update instMap via assignments to entry references
Wed, May 4, 1:18 PM · Restricted Project, Restricted Project
myhsu closed D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.
Wed, May 4, 1:18 PM · Restricted Project, Restricted Project
myhsu requested review of D124935: [mlir][LLVMIR] Use a new way to verify GEPOp indices.
Wed, May 4, 9:24 AM · Restricted Project, Restricted Project

Tue, May 3

myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

Hello, We are maintaining a downstream version of the monorepo based on the LLVM main branch. In a recent attempt to merge the latest upstream commits
into our monorepo we came across the following test failures after your commit.
Any help would be greatly appreciated.
Thanks
Greg


`
FAIL: llvm_regressions :: LLVM/TableGen/VarLenDecoder.td
--------------------------------------------------------------------------------
Script:
--
: 'RUN: at line 1';   /scratch/gmiller/tools2/llvm_cgt/arm-llvm/RelWithAsserts/llvm/bin/llvm-tblgen -gen-disassembler -I /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/../../include /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td | /scratch/gmiller/tools2/llvm_cgt/arm-llvm/RelWithAsserts/llvm/bin/FileCheck /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td
--
Exit Code: 1

Command Output (stderr):
--
+ : 'RUN: at line 1'
+ /scratch/gmiller/tools2/llvm_cgt/arm-llvm/RelWithAsserts/llvm/bin/llvm-tblgen -gen-disassembler -I /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/../../include /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td
+ /scratch/gmiller/tools2/llvm_cgt/arm-llvm/RelWithAsserts/llvm/bin/FileCheck /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td
/scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td:50:16: error: CHECK-NEXT: expected string not found in input
// CHECK-NEXT: MCD::OPC_Decode, 244, 1, 0, // Opcode: FOO16
               ^
<stdin>:72:57: note: scanning from here
/* 3 */ MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12
                                                        ^
<stdin>:73:9: note: possible intended match here
/* 8 */ MCD::OPC_Decode, 245, 1, 0, // Opcode: FOO16
        ^

Input file: <stdin>
Check file: /scratch/gmiller/tools2/llvm_cgt/llvm-project/llvm/test/TableGen/VarLenDecoder.td

-dump-input=help explains the following input dump.

Input was:
<<<<<<
           .
           .
           .
          67:  field.insertBits(bits, startBit, numBits); 
          68: } 
          69:  
          70: static const uint8_t DecoderTable43[] = { 
          71: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ... 
          72: /* 3 */ MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12 
next:50'0                                                             X error: no match found
          73: /* 8 */ MCD::OPC_Decode, 245, 1, 0, // Opcode: FOO16 
next:50'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:50'1             ?                                             possible intended match
          74: /* 12 */ MCD::OPC_FilterValue, 9, 4, 0, 0, // Skip to: 21 
next:50'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          75: /* 17 */ MCD::OPC_Decode, 246, 1, 1, // Opcode: FOO32 
next:50'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          76: /* 21 */ MCD::OPC_Fail, 
next:50'0     ~~~~~~~~~~~~~~~~~~~~~~~~
          77:  0 
next:50'0     ~~~
          78: }; 
next:50'0     ~~~
           .
           .
           .
>>>>>>

--
`
Tue, May 3, 7:33 PM · Restricted Project, Restricted Project
myhsu updated the summary of D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.
Tue, May 3, 4:11 PM · Restricted Project, Restricted Project
myhsu added a comment to D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.

The complexity of the test is scary. Is it just a matter of having a sufficient amount of instructions and/or constants in a vector?

Tue, May 3, 4:09 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.

Update the test case.

Tue, May 3, 4:06 PM · Restricted Project, Restricted Project
myhsu committed rG857eb4a152cf: [mlir][LLVMIR] Add support for translating Switch instruction (authored by myhsu).
[mlir][LLVMIR] Add support for translating Switch instruction
Tue, May 3, 9:43 AM · Restricted Project, Restricted Project
myhsu closed D124628: [mlir][LLVMIR] Add support for translating Switch instruction.
Tue, May 3, 9:42 AM · Restricted Project, Restricted Project
myhsu added a comment to D120960: [M68k][Disassembler] Adopt the new variable length decoder.

just want to double check: all of the previously-XFAIL tests are now passing, right?

Yes. I don't see any 'unexpectedly passed' test.

Tue, May 3, 9:23 AM · Restricted Project, Restricted Project

Mon, May 2

myhsu committed rGe927a336a58b: [mlir][LLVMIR] Add support for translating FCmp & FP constants (authored by myhsu).
[mlir][LLVMIR] Add support for translating FCmp & FP constants
Mon, May 2, 4:24 PM · Restricted Project, Restricted Project
myhsu closed D124630: [mlir][LLVMIR] Add support for translating FCmp & more FP constants.
Mon, May 2, 4:23 PM · Restricted Project, Restricted Project
myhsu added a comment to D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.

The complexity of the test is scary. Is it just a matter of having a sufficient amount of instructions and/or constants in a vector?

Mon, May 2, 3:36 PM · Restricted Project, Restricted Project
myhsu added inline comments to D124628: [mlir][LLVMIR] Add support for translating Switch instruction.
Mon, May 2, 3:31 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124628: [mlir][LLVMIR] Add support for translating Switch instruction.
  • Integrate test cases into test/Target/LLVMIR/Import/basic.ll
  • Add a new test case to test llvm.switch with arguments
  • Remove error message printing while translating predicate values and block arguments to avoid showing (similar) error messages twice.
Mon, May 2, 3:30 PM · Restricted Project, Restricted Project

Sun, May 1

myhsu added a comment to D104439: [analyzer][NFC] Demonstrate a move from the analyzer-configs `.def` file to a TableGen file.

Just curious: Have you considered using llvm::opt or even llvm::cl infrastructure? What are the pros & cons?

Sun, May 1, 11:40 PM · Restricted Project, Restricted Project
myhsu added a comment to D120960: [M68k][Disassembler] Adopt the new variable length decoder.

just want to double check: all of the previously-XFAIL tests are now passing, right?

Sun, May 1, 12:44 PM · Restricted Project, Restricted Project
myhsu accepted D120958: [TableGen] Add support for variable length instruction in decoder generator.

lgtm. Thanks for the patch!

Sun, May 1, 12:33 PM · Restricted Project, Restricted Project

Thu, Apr 28

myhsu added inline comments to D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.
Thu, Apr 28, 2:16 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124628: [mlir][LLVMIR] Add support for translating Switch instruction.

Addressed coding style issues.

Thu, Apr 28, 2:16 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.

Remove unused variable v and update the assertion check.

Thu, Apr 28, 2:14 PM · Restricted Project, Restricted Project
myhsu requested review of D124630: [mlir][LLVMIR] Add support for translating FCmp & more FP constants.
Thu, Apr 28, 11:37 AM · Restricted Project, Restricted Project
myhsu requested review of D124628: [mlir][LLVMIR] Add support for translating Switch instruction.
Thu, Apr 28, 11:32 AM · Restricted Project, Restricted Project
myhsu requested review of D124627: [mlir][LLVMIR] Do not update instMap via assignments to map entry references.
Thu, Apr 28, 11:26 AM · Restricted Project, Restricted Project

Apr 27 2022

myhsu committed rGa75657d66a12: [mlir][LLVMIR] Do not cache llvm::Constant into instMap (authored by myhsu).
[mlir][LLVMIR] Do not cache llvm::Constant into instMap
Apr 27 2022, 9:47 AM · Restricted Project, Restricted Project
myhsu committed rGea9bcb8b274a: [mlir][LLVMIR] Do not cache Instruction generated on-the-fly (authored by myhsu).
[mlir][LLVMIR] Do not cache Instruction generated on-the-fly
Apr 27 2022, 9:47 AM · Restricted Project, Restricted Project
myhsu committed rG00fcf9e95a4a: [mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero) (authored by myhsu).
[mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero)
Apr 27 2022, 9:46 AM · Restricted Project, Restricted Project
myhsu closed D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.
Apr 27 2022, 9:46 AM · Restricted Project, Restricted Project
myhsu closed D124402: [mlir][LLVMIR] Do not cache Instruction generated on-the-fly.
Apr 27 2022, 9:46 AM · Restricted Project, Restricted Project
myhsu closed D124399: [mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero).
Apr 27 2022, 9:46 AM · Restricted Project, Restricted Project

Apr 26 2022

myhsu committed rGe1567e771b89: [docs] Fix typos in the 'CodeGenerator' doc (authored by JOE1994).
[docs] Fix typos in the 'CodeGenerator' doc
Apr 26 2022, 9:48 PM · Restricted Project, Restricted Project
myhsu closed D124305: [docs] Fix typo in 'CodeGenerator' docs.
Apr 26 2022, 9:48 PM · Restricted Project, Restricted Project
myhsu added inline comments to D124399: [mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero).
Apr 26 2022, 6:10 PM · Restricted Project, Restricted Project
myhsu added a comment to D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.

I edited the description a bit. Please also note that phabricator-style markup (e.g., using // for italic) looks weird in git commit messages (e.g., C-style comment).

even another llvm.func!

Isn't the cache cleared on entering a new function? The error is only manifest for globals.

Apr 26 2022, 5:58 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.

add bug descriptions into the test file.

Apr 26 2022, 5:57 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124399: [mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero).

minor fixes

Apr 26 2022, 5:56 PM · Restricted Project, Restricted Project

Apr 25 2022

myhsu updated the diff for D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.

Rebase

Apr 25 2022, 9:37 PM · Restricted Project, Restricted Project
myhsu updated the diff for D124402: [mlir][LLVMIR] Do not cache Instruction generated on-the-fly.

Taking @rriddle 's advice and simplify the patch

Apr 25 2022, 9:35 PM · Restricted Project, Restricted Project
myhsu accepted D124305: [docs] Fix typo in 'CodeGenerator' docs.

LGTM
I'll commit on your behalf

Apr 25 2022, 11:19 AM · Restricted Project, Restricted Project
myhsu updated the summary of D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.
Apr 25 2022, 10:02 AM · Restricted Project, Restricted Project
myhsu requested review of D124404: [mlir][LLVMIR] Do not cache llvm::Constant into instMap.
Apr 25 2022, 9:59 AM · Restricted Project, Restricted Project
myhsu requested review of D124402: [mlir][LLVMIR] Do not cache Instruction generated on-the-fly.
Apr 25 2022, 9:49 AM · Restricted Project, Restricted Project
myhsu requested review of D124399: [mlir][LLVMIR] Add support for importing struct-type ConstantAggregate(Zero).
Apr 25 2022, 9:42 AM · Restricted Project, Restricted Project

Apr 19 2022

myhsu added a comment to D123677: [PassManager] Implement DOTGraphTraitsViewer under NPM.

Thanks for the patch, lgtm for most of the parts. Please address my comment though (especially the static one)

Apr 19 2022, 9:09 PM · Restricted Project, Restricted Project

Apr 14 2022

myhsu added a reviewer for D123677: [PassManager] Implement DOTGraphTraitsViewer under NPM: myhsu.
Apr 14 2022, 10:43 AM · Restricted Project, Restricted Project

Apr 13 2022

myhsu added a comment to D123677: [PassManager] Implement DOTGraphTraitsViewer under NPM.

I understand that most of the code was copied from the original (LegacyPM) implementation, but I feel like it's also a good time to fix some of the minor issues as highlighted by my inline comments.

Apr 13 2022, 5:40 PM · Restricted Project, Restricted Project

Apr 10 2022

myhsu added inline comments to D122832: [TableGen] Add a backend to help with target enums.
Apr 10 2022, 11:45 AM · Restricted Project, Restricted Project
myhsu accepted D123451: [NFC] Rename `FixedLenDecoderEmitter` as `DecoderEmitter`.

LGTM, please resolve the formatting issues though

Apr 10 2022, 10:38 AM · Restricted Project, Restricted Project

Apr 5 2022

myhsu committed rGd68b4dc0a88e: [M68k] Adopt VarLenCodeEmitter for rest of the data instructions (authored by myhsu).
[M68k] Adopt VarLenCodeEmitter for rest of the data instructions
Apr 5 2022, 10:56 AM · Restricted Project, Restricted Project

Apr 4 2022

myhsu committed rG18b38ff6c7f1: [M68k] Adopt VarLenCodeEmitter for move instructions (authored by myhsu).
[M68k] Adopt VarLenCodeEmitter for move instructions
Apr 4 2022, 11:03 PM · Restricted Project, Restricted Project

Apr 3 2022

myhsu committed rGfccdc5618d97: [M68k] Adopt VarLenCodeEmitter for shift / rotate instructions (authored by myhsu).
[M68k] Adopt VarLenCodeEmitter for shift / rotate instructions
Apr 3 2022, 10:54 PM · Restricted Project, Restricted Project
myhsu committed rG22201f499da2: [M68k][test] Remove redundant CHECK-LABEL directive (authored by myhsu).
[M68k][test] Remove redundant CHECK-LABEL directive
Apr 3 2022, 10:54 PM · Restricted Project, Restricted Project

Mar 31 2022

myhsu added inline comments to D120958: [TableGen] Add support for variable length instruction in decoder generator.
Mar 31 2022, 10:05 AM · Restricted Project, Restricted Project
myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

Also, please make sure all existing disassembler tests, especially targets that use FixedLenDecoder, are passing.

Mar 31 2022, 10:00 AM · Restricted Project, Restricted Project
myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

The logics look cleaner now.
Now a bigger question is: Should we still calling it FixedLenDecoderEmitter?

What about DecoderEmitter.cpp ?

Mar 31 2022, 9:57 AM · Restricted Project, Restricted Project

Mar 29 2022

myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

The logics look cleaner now.
Now a bigger question is: Should we still calling it FixedLenDecoderEmitter?

Mar 29 2022, 9:45 PM · Restricted Project, Restricted Project

Mar 15 2022

myhsu added a reviewer for D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2: myhsu.
Mar 15 2022, 3:30 PM · Restricted Project, Restricted Project, Restricted Project
myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

We can traverse the Segments of VarLenInst and use CGIOperandList::OperandInfo::ParseOperandName to get the operand number, and then add that Segments into the correspoding OpInfo according to the operand number.

For example, if we find "dst.reg" and use CGIOperandList::OperandInfo::ParseOperandName and know "Oh, this is the third operand", then we can add this into the third OpInfo.

In this way we can avoid overload BitsInit completely.

Mar 15 2022, 1:15 PM · Restricted Project, Restricted Project

Mar 14 2022

myhsu added a comment to D120958: [TableGen] Add support for variable length instruction in decoder generator.

Thank you for the patch.
A high level question: It seems like generating a decoder requires two phases -- First, generates a list of OperandInfo, which is currently done by populateInstruction, then emit the real (C++) code according to these OperandInfo instances. My question is, can we use our own way -- possibly putting in a separate file -- to generate these OperandInfo before supplying them to the second phase, instead of trying to piggyback everything into the existing FixedLenDecoder framework?
Because, to be honest, I'm not a big fan of overloading the BitsInit (to carry operand info). Using a BitsInit might fit well for fixed-length instructions but I feel like there are more elegant ways to handle var-length instructions. For instance, using CGIOperandList::OperandInfo::ParseOperandName to parse suboperands rather than traversing every single in/out operands in the original instruction definition.

Mar 14 2022, 11:20 AM · Restricted Project, Restricted Project

Mar 9 2022

myhsu added a comment to D120993: [PassManager] Add pretty stack entries before P->run() call..

Yeah that's not great. I'll revert it in a bit and check if there's anything in particular that's very expensive.

Mar 9 2022, 9:31 AM · Restricted Project, Restricted Project

Mar 4 2022

myhsu added a comment to D120993: [PassManager] Add pretty stack entries before P->run() call..

I think this is a really neat feature :-)
Please remember to fix the clang-format errors.

Mar 4 2022, 10:30 AM · Restricted Project, Restricted Project

Mar 1 2022

myhsu added inline comments to D119876: [nfc][codegen] Move RegisterBank[Info].h under CodeGen.
Mar 1 2022, 9:28 AM · Restricted Project, Restricted Project, Restricted Project
myhsu accepted D119876: [nfc][codegen] Move RegisterBank[Info].h under CodeGen.

since D119053 was accepted, I don't see any reason why this patch shouldn't be :-)

Mar 1 2022, 9:25 AM · Restricted Project, Restricted Project, Restricted Project

Feb 28 2022

myhsu added a comment to D120477: [LoongArch] Add basic support to Disassembler.

Overall LGTM, only a few minor issues.

Feb 28 2022, 10:28 AM · Restricted Project, Restricted Project