[SelectionDAG] Give all the target specific subclasses of SelectionDAGISel their own pass ID.

[craig.topper]

Summary

Previously we had a shared ID in SelectionDAGISel. AMDGPU has an
initializePass function for its subclass of SelectionDAGISel. No
other target does.

This causes all target specific SelectionDAGISel passes to be known
as "amdgpu-isel".

I'm not sure what would happen if another target tried to implement
an initializePass function too since the ID is already claimed.

This patch gives all targets their own ID and passes it down to
SelectionDAGISel constructor to MachineFunctionPass's constructor.

Unfortunately, I think this causes most targets to lose
print-before/after-all support for their SelectionDAGISel pass.
And they probably no longer support start/stop-before/after. We
can add initializePass functions to fix this as a follow up. NOTE:
This was probably also broken if the AMDGPU target isn't compiled in.

Step 1 to fixing PR59538.

[nickdesaulniers]

Thanks for the (quick) patch!

Unfortunately, I think this causes most targets to lose
print-before/after-all support for their SelectionDAGISel pass.

I now see:

# *** IR Dump After Finalize ISel and expand pseudo-instructions (finalize-isel) ***:

for llc -mtriple=x86_64-linux-gnu /tmp/x.ll -stop-after=finalize-isel -o - -print-before-all
(good) and -mtriple=aarch64-linux-gnu (good). So perhaps that can perhaps be dropped from the commit message. Or was there another invocation of llc where you observed this?

And they probably no longer support start/stop-before/after.

Let's check that too!

When I apply this on top of my stack o' patches: https://reviews.llvm.org/D140160, my tests running -start-before=amdgpu-isel both fail.

LLVM ERROR: Cannot stop compilation after pass that is not run

This is expected (good).

Now let's see if I can change -start-before=amdgpu-isel to -start-before=finalize-isel...
and test's fail with no output. So indeed seems like we'll need that part 2.

[nickdesaulniers]

In D140161#3999328, @nickdesaulniers wrote:

Or was there another invocation of llc where you observed this?

Doesn't -print-after-all only print if changes were made (given for finalize-isel)? Rerunning my above tests with -print-after-all rather than -print-before-all I still see finalize-isel. I think this confirms that D140161 does not break -print-after-all/-print-before-all.

(Though one curiosity I do see for llc -mtriple=aarch64-linux-gnu /tmp/x.ll -stop-after=finalize-isel -o - -print-after-all is that MIR is printed after aarch64-local-dynamic-tls-cleanup which runs before finalize-isel; WAT?!)

[craig.topper]

Doesn't -print-after-all only print if changes were made (given for finalize-isel)?

I don't think it checks that.

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

24

Random observation. This is curiously in the llvm namespace instead of an anonymous namespace.

[jrtc27]

In D140161#3999380, @craig.topper wrote:

Doesn't -print-after-all only print if changes were made (given for finalize-isel)?

I don't think it checks that.

There's -print-changed and -print-before-changed.

[arsenm]

Not allowing -stop-before/-stop-after the actual isel pass is probably a feature, not a bug. We don't run the verifier between that and finalizeisel. You can see verifier failing MIR at that point which would confuse

[nickdesaulniers]

In D140161#3999433, @arsenm wrote:

Not allowing -stop-before/-stop-after the actual isel pass is probably a feature, not a bug. We don't run the verifier between that and finalizeisel. You can see verifier failing MIR at that point which would confuse

Without -stop-after, how are folks expected to test SelectionDAG in isolation?

(-stop-before is the other side of the same coin as -stop-after for whatever pass comes before finalize-isel. It's asymmetric to support one without the other, but if I can only have one, that's good enough to do my job).

[arsenm]

In D140161#3999437, @nickdesaulniers wrote:

In D140161#3999433, @arsenm wrote:

Not allowing -stop-before/-stop-after the actual isel pass is probably a feature, not a bug. We don't run the verifier between that and finalizeisel. You can see verifier failing MIR at that point which would confuse

Without -stop-after, how are folks expected to test SelectionDAG in isolation?

You kind of don't. That's one of the major issues with it. After finalizeisel is the first point where you're consistently guaranteed verifiable mir

[nickdesaulniers]

In D140161#3999447, @arsenm wrote:

In D140161#3999437, @nickdesaulniers wrote:

In D140161#3999433, @arsenm wrote:

Not allowing -stop-before/-stop-after the actual isel pass is probably a feature, not a bug. We don't run the verifier between that and finalizeisel. You can see verifier failing MIR at that point which would confuse

Without -stop-after, how are folks expected to test SelectionDAG in isolation?

You kind of don't. That's one of the major issues with it. After finalizeisel is the first point where you're consistently guaranteed verifiable mir

So why isn't -stop-after=finalizeisel working "not a bug?" (Perhaps I should have s/SelectionDAG/SelectionDAGISel/ above)

[arsenm]

In D140161#3999479, @nickdesaulniers wrote:

So why isn't -stop-after=finalizeisel working "not a bug?" (Perhaps I should have s/SelectionDAG/SelectionDAGISel/ above)

-stop-after=finalize-isel should work. That's what I always use

[arsenm]

In D140161#3999705, @arsenm wrote:

In D140161#3999479, @nickdesaulniers wrote:

So why isn't -stop-after=finalizeisel working "not a bug?" (Perhaps I should have s/SelectionDAG/SelectionDAGISel/ above)

-stop-after=finalize-isel should work. That's what I always use

Nothing also stops you from using -stop-before=finalize-isel, which is effectively the same thing

llvm/include/llvm/CodeGen/SelectionDAGISel.h

public:
   bool FastISelFailed;
   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
   bool UseInstrRefDebugInfo = false;
 
   /// Current optimization remark emitter.
   /// Used to report things like combines and FastISel failures.
   std::unique_ptr<OptimizationRemarkEmitter> ORE;
 
-  static char ID;
-
-  explicit SelectionDAGISel(TargetMachine &tm,
+  explicit SelectionDAGISel(char &ID, TargetMachine &tm,
                             CodeGenOpt::Level OL = CodeGenOpt::Default);
   ~SelectionDAGISel() override;
 
   const TargetLowering *getTargetLowering() const { return TLI; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction &MF) override;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

assert(!MI.hasPostISelHook() &&
          "If a target marks an instruction with 'hasPostISelHook', "
          "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
 }
 
 //===----------------------------------------------------------------------===//
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL)
+SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm,
+                                   CodeGenOpt::Level OL)
     : MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()),
       SwiftError(new SwiftErrorValueTracking()),
       CurDAG(new SelectionDAG(tm, OL)),
       SDB(std::make_unique<SelectionDAGBuilder>(*CurDAG, *FuncInfo, *SwiftError,
                                                 OL)),
       OptLevel(OL) {
   initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
   initializeBranchProbabilityInfoWrapperPassPass(
if (iid < Intrinsic::num_intrinsics)
       Msg << "intrinsic %" << Intrinsic::getBaseName((Intrinsic::ID)iid);
     else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
       Msg << "target intrinsic %" << TII->getName(iid);
     else
       Msg << "unknown intrinsic #" << iid;
   }
   report_fatal_error(Twine(Msg.str()));
 }
-
-char SelectionDAGISel::ID = 0;

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 
 class AArch64DAGToDAGISel : public SelectionDAGISel {
 
   /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const AArch64Subtarget *Subtarget;
 
 public:
+  static char ID;
+
   explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
                                CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
+      : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {}
 
   StringRef getPassName() const override {
     return "AArch64 Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<AArch64Subtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
bool SelectSVERegRegAddrMode(SDValue N, unsigned Scale, SDValue &Base,
                                SDValue &Offset);
   bool SelectSMETileSlice(SDValue N, unsigned Scale, SDValue &Vector,
                           SDValue &Offset);
 
   bool SelectAllActivePredicate(SDValue N);
 };
 } // end anonymous namespace
 
+char AArch64DAGToDAGISel::ID = 0;
+
 /// isIntImmediate - This method tests to see if the node is a constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
   if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
     Imm = C->getZExtValue();
     return true;
   }
   return false;

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h

class AMDGPUDAGToDAGISel : public SelectionDAGISel {
 
   bool EnableLateStructurizeCFG;
 
   // Instructions that will be lowered with a final instruction that zeros the
   // high result bits.
   bool fp16SrcZerosHighBits(unsigned Opc) const;
 
 public:
+  static char ID;
+
   explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
                               CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
   ~AMDGPUDAGToDAGISel() override = default;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool matchLoadD16FromBuildVector(SDNode *N) const;
 

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
                                         CodeGenOpt::Level OptLevel) {
   return new AMDGPUDAGToDAGISel(TM, OptLevel);
 }
 
 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(
     TargetMachine *TM /*= nullptr*/,
     CodeGenOpt::Level OptLevel /*= CodeGenOpt::Default*/)
-    : SelectionDAGISel(*TM, OptLevel) {
+    : SelectionDAGISel(ID, *TM, OptLevel) {
   EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
 }
 
 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
 #ifdef EXPENSIVE_CHECKS
   DominatorTree & DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
   LoopInfo * LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
   for (auto &L : LI->getLoopsInPreorder()) {
while (Position != CurDAG->allnodes_end()) {
         if (ResNode)
           ReplaceUses(Node, ResNode);
         IsModified = true;
       }
     }
     CurDAG->RemoveDeadNodes();
   } while (IsModified);
 }
+
+char AMDGPUDAGToDAGISel::ID = 0;

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

 namespace {
 
 class ARMDAGToDAGISel : public SelectionDAGISel {
   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
   /// make the right decision when generating code for different targets.
   const ARMSubtarget *Subtarget;
 
 public:
+  static char ID;
+
   explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(tm, OptLevel) {}
+      : SelectionDAGISel(ID, tm, OptLevel) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     Subtarget = &MF.getSubtarget<ARMSubtarget>();
     SelectionDAGISel::runOnMachineFunction(MF);
     return true;
   }
 
bool canExtractShiftFromMul(const SDValue &N, unsigned MaxShift,
                               unsigned &PowerOfTwo, SDValue &NewMulConst) const;
 
   /// Replace N with M in CurDAG, in a way that also ensures that M gets
   /// selected when N would have been selected.
   void replaceDAGValue(const SDValue &N, SDValue M);
 };
 }
 
+char ARMDAGToDAGISel::ID = 0;
+
 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
     Imm = cast<ConstantSDNode>(N)->getZExtValue();
     return true;
   }
   return false;

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

 
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "avr-isel"
 
 namespace llvm {
 
 /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
 class AVRDAGToDAGISel : public SelectionDAGISel {
 public:
+  static char ID;
+
   AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
+      : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
 
   StringRef getPassName() const override {
     return "AVR DAG->DAG Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
private:
   bool trySelect(SDNode *N);
 
   template <unsigned NodeType> bool select(SDNode *N);
   bool selectMultiplication(SDNode *N);
 
   const AVRSubtarget *Subtarget;
 };
 
+char AVRDAGToDAGISel::ID = 0;
+
 bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<AVRSubtarget>();
   return SelectionDAGISel::runOnMachineFunction(MF);
 }
 
 bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
                                  SDValue &Disp) {
   SDLoc dl(Op);

 }
 
 FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
                                CodeGenOpt::Level OptLevel) {
   return new AVRDAGToDAGISel(TM, OptLevel);
 }
 
 } // end of namespace llvm
+

llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp

 
 class BPFDAGToDAGISel : public SelectionDAGISel {
 
   /// Subtarget - Keep a pointer to the BPFSubtarget around so that we can
   /// make the right decision when generating code for different subtargets.
   const BPFSubtarget *Subtarget;
 
 public:
+  static char ID;
+
   explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
-      : SelectionDAGISel(TM), Subtarget(nullptr) {}
+      : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
 
   StringRef getPassName() const override {
     return "BPF DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     Subtarget = &MF.getSubtarget<BPFSubtarget>();
bool fillConstantStruct(const DataLayout &DL, const ConstantStruct *CS,
                           val_vec_type &Vals, int Offset);
   bool getConstantFieldValue(const GlobalAddressSDNode *Node, uint64_t Offset,
                              uint64_t Size, unsigned char *ByteSeq);
   // Mapping from ConstantStruct global value to corresponding byte-list values
   std::map<const void *, val_vec_type> cs_vals_;
 };
 } // namespace
 
+char BPFDAGToDAGISel::ID = 0;
+
 // ComplexPattern used on BPF Load/Store instructions
 bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
   // if Address is FI, get the TargetFrameIndex.
   SDLoc DL(Addr);
   if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
     Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
     return true;

llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h

 class HexagonInstrInfo;
 class HexagonRegisterInfo;
 
 class HexagonDAGToDAGISel : public SelectionDAGISel {
   const HexagonSubtarget *HST;
   const HexagonInstrInfo *HII;
   const HexagonRegisterInfo *HRI;
 public:
+  static char ID;
+
   explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
                                CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
+      : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
         HRI(nullptr) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     HST = &MF.getSubtarget<HexagonSubtarget>();
     HII = HST->getInstrInfo();
     HRI = HST->getRegisterInfo();
     SelectionDAGISel::runOnMachineFunction(MF);

llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

 /// createHexagonISelDag - This pass converts a legalized DAG into a
 /// Hexagon-specific DAG, ready for instruction scheduling.
 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
                                    CodeGenOpt::Level OptLevel) {
   return new HexagonDAGToDAGISel(TM, OptLevel);
 }
 }
 
+char HexagonDAGToDAGISel::ID = 0;
+
 void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
   SDValue Chain = LD->getChain();
   SDValue Base = LD->getBasePtr();
   SDValue Offset = LD->getOffset();
   int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
   EVT LoadedVT = LD->getMemoryVT();
   unsigned Opcode = 0;
 

llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp

 //===----------------------------------------------------------------------===//
 // LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
 // instructions for SelectionDAG operations.
 //===----------------------------------------------------------------------===//
 namespace {
 
 class LanaiDAGToDAGISel : public SelectionDAGISel {
 public:
+  static char ID;
+
   explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
-      : SelectionDAGISel(TargetMachine) {}
+      : SelectionDAGISel(ID, TargetMachine) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   // Pass Name
   StringRef getPassName() const override {
     return "Lanai DAG->DAG Pattern Instruction Selection";

 
 bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
   // Fits in 21-bit signed immediate and two low-order bits are zero.
   return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
 }
 
 } // namespace
 
+char LanaiDAGToDAGISel::ID = 0;
+
 // Helper functions for ComplexPattern used on LanaiInstrInfo
 // Used on Lanai Load/Store instructions.
 bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
     SDLoc DL(Addr);
     // Loading from a constant address.
     if (canBeRepresentedAsSls(*CN)) {
       int32_t Imm = CN->getSExtValue();

llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

 }
 
 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
   class MSP430DAGToDAGISel : public SelectionDAGISel {
   public:
+    static char ID;
+
     MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
-        : SelectionDAGISel(TM, OptLevel) {}
+        : SelectionDAGISel(ID, TM, OptLevel) {}
 
   private:
     StringRef getPassName() const override {
       return "MSP430 DAG->DAG Pattern Instruction Selection";
     }
 
     bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
#include "MSP430GenDAGISel.inc"
     bool tryIndexedLoad(SDNode *Op);
     bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
                          unsigned Opc16);
 
     bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
   };
 }  // end anonymous namespace
 
+char MSP430DAGToDAGISel::ID;
+
 /// createMSP430ISelDag - This pass converts a legalized DAG into a
 /// MSP430-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
                                         CodeGenOpt::Level OptLevel) {
   return new MSP430DAGToDAGISel(TM, OptLevel);
 }
 

llvm/lib/Target/Mips/MipsISelDAGToDAG.h

 //===----------------------------------------------------------------------===//
 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
 // instructions for SelectionDAG operations.
 //===----------------------------------------------------------------------===//
 namespace llvm {
 
 class MipsDAGToDAGISel : public SelectionDAGISel {
 public:
+  static char ID;
+
   explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
-      : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
+      : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
 
   // Pass Name
   StringRef getPassName() const override {
     return "MIPS DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 

llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp

SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
   case InlineAsm::Constraint_m:
   case InlineAsm::Constraint_R:
   case InlineAsm::Constraint_ZC:
     OutOps.push_back(Op);
     return false;
   }
   return true;
 }
+
+char MipsDAGToDAGISel::ID = 0;

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h

class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
   int getDivF32Level() const;
   bool usePrecSqrtF32() const;
   bool useF32FTZ() const;
   bool allowFMA() const;
   bool allowUnsafeFPMath() const;
   bool useShortPointers() const;
 
 public:
+  static char ID;
+
   explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
                              CodeGenOpt::Level   OptLevel);
 
   // Pass Name
   StringRef getPassName() const override {
     return "NVPTX DAG->DAG Pattern Instruction Selection";
   }
   bool runOnMachineFunction(MachineFunction &MF) override;

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

 
 /// createNVPTXISelDag - This pass converts a legalized DAG into a
 /// NVPTX-specific DAG, ready for instruction scheduling.
 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
                                        llvm::CodeGenOpt::Level OptLevel) {
   return new NVPTXDAGToDAGISel(TM, OptLevel);
 }
 
+char NVPTXDAGToDAGISel::ID = 0;
+
 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
                                      CodeGenOpt::Level OptLevel)
-    : SelectionDAGISel(tm, OptLevel), TM(tm) {
+    : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
   doMulWide = (OptLevel > 0);
 }
 
 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<NVPTXSubtarget>();
   return SelectionDAGISel::runOnMachineFunction(MF);
 }
 

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

namespace {
   ///
   class PPCDAGToDAGISel : public SelectionDAGISel {
     const PPCTargetMachine &TM;
     const PPCSubtarget *Subtarget = nullptr;
     const PPCTargetLowering *PPCLowering = nullptr;
     unsigned GlobalBaseReg = 0;
 
   public:
+    static char ID;
+
     explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
-        : SelectionDAGISel(tm, OptLevel), TM(tm) {}
+        : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       // Make sure we re-emit a set of the global base reg if necessary
       GlobalBaseReg = 0;
       Subtarget = &MF.getSubtarget<PPCSubtarget>();
       PPCLowering = Subtarget->getTargetLowering();
       if (Subtarget->hasROPProtect()) {
         // Create a place on the stack for the ROP Protection Hash.
private:
     void SwapAllSelectUsers(SDNode *N);
 
     bool isOffsetMultipleOf(SDNode *N, unsigned Val) const;
     void transferMemOperands(SDNode *N, SDNode *Result);
   };
 
 } // end anonymous namespace
 
+char PPCDAGToDAGISel::ID = 0;
+
 /// getGlobalBaseReg - Output the instructions required to put the
 /// base address to use for accessing globals into a register.
 ///
 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
   if (!GlobalBaseReg) {
     const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = MF->front();

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

 
 // RISCV-specific code to select RISCV machine instructions for
 // SelectionDAG operations.
 namespace llvm {
 class RISCVDAGToDAGISel : public SelectionDAGISel {
   const RISCVSubtarget *Subtarget = nullptr;
 
 public:
+  static char ID;
+
   explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
                              CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TargetMachine, OptLevel) {}
+      : SelectionDAGISel(ID, TargetMachine, OptLevel) {}
 
   StringRef getPassName() const override {
     return "RISCV DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<RISCVSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 }
 
 // This pass converts a legalized DAG into a RISCV-specific DAG, ready
 // for instruction scheduling.
 FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
                                        CodeGenOpt::Level OptLevel) {
   return new RISCVDAGToDAGISel(TM, OptLevel);
 }
+
+char RISCVDAGToDAGISel::ID = 0;

llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

 /// instructions for SelectionDAG operations.
 ///
 namespace {
 class SparcDAGToDAGISel : public SelectionDAGISel {
   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const SparcSubtarget *Subtarget = nullptr;
 public:
-  explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
+  static char ID;
+
+  explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<SparcSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   void Select(SDNode *N) override;
 

 #include "SparcGenDAGISel.inc"
 
 private:
   SDNode* getGlobalBaseReg();
   bool tryInlineAsm(SDNode *N);
 };
 }  // end anonymous namespace
 
+char SparcDAGToDAGISel::ID = 0;
+
 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
   Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
   return CurDAG->getRegister(GlobalBaseReg,
                              TLI->getPointerTy(CurDAG->getDataLayout()))
       .getNode();
 }
 
 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,

llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

class SystemZDAGToDAGISel : public SelectionDAGISel {
   // Return true if N (a load or a store) fullfills the alignment
   // requirements for a PC-relative access.
   bool storeLoadIsAligned(SDNode *N) const;
 
   // Try to expand a boolean SELECT_CCMASK using an IPM sequence.
   SDValue expandSelectBoolean(SDNode *Node);
 
 public:
+  static char ID;
+
   SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TM, OptLevel) {}
+      : SelectionDAGISel(ID, TM, OptLevel) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     const Function &F = MF.getFunction();
     if (F.getFnAttribute("fentry-call").getValueAsString() != "true") {
       if (F.hasFnAttribute("mnop-mcount"))
         report_fatal_error("mnop-mcount only supported with fentry-call");
       if (F.hasFnAttribute("mrecord-mcount"))
         report_fatal_error("mrecord-mcount only supported with fentry-call");
public:
   bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
   void PreprocessISelDAG() override;
 
   // Include the pieces autogenerated from the target description.
   #include "SystemZGenDAGISel.inc"
 };
 } // end anonymous namespace
 
+char SystemZDAGToDAGISel::ID = 0;
+
 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
                                          CodeGenOpt::Level OptLevel) {
   return new SystemZDAGToDAGISel(TM, OptLevel);
 }
 
 // Return true if Val should be selected as a displacement for an address
 // with range DR.  Here we're interested in the range of both the instruction
 // described by DR and of any pairing instruction.

llvm/lib/Target/VE/VEISelDAGToDAG.cpp

 ///
 namespace {
 class VEDAGToDAGISel : public SelectionDAGISel {
   /// Subtarget - Keep a pointer to the VE Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const VESubtarget *Subtarget;
 
 public:
-  explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {}
+  static char ID;
+
+  explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<VESubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   void Select(SDNode *N) override;
 

 private:
   SDNode *getGlobalBaseReg();
 
   bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index);
   bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset);
 };
 } // end anonymous namespace
 
+char VEDAGToDAGISel::ID = 0;
+
 bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
                                    SDValue &Offset) {
   if (Addr.getOpcode() == ISD::FrameIndex)
     return false;
   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
       Addr.getOpcode() == ISD::TargetGlobalAddress ||
       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
     return false; // direct calls.

llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp

 ///
 namespace {
 class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
   /// right decision when generating code for different targets.
   const WebAssemblySubtarget *Subtarget;
 
 public:
+  static char ID;
+
   WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
                           CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
+      : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
 
   StringRef getPassName() const override {
     return "WebAssembly Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n"
                          "********** Function: "
private:
 
   bool SelectAddrOperands(MVT AddrType, unsigned ConstOpc, SDValue Op,
                           SDValue &Offset, SDValue &Addr);
   bool SelectAddrAddOperands(MVT OffsetType, SDValue N, SDValue &Offset,
                              SDValue &Addr);
 };
 } // end anonymous namespace
 
+char WebAssemblyDAGToDAGISel::ID;
+
 void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
   // Stack objects that should be allocated to locals are hoisted to WebAssembly
   // locals when they are first used.  However for those without uses, we hoist
   // them here.  It would be nice if there were some hook to do this when they
   // are added to the MachineFrameInfo, but that's not the case right now.
   MachineFrameInfo &FrameInfo = MF->getFrameInfo();
   for (int Idx = 0; Idx < FrameInfo.getObjectIndexEnd(); Idx++)
     WebAssemblyFrameLowering::getLocalForStackObject(*MF, Idx);

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

class X86DAGToDAGISel final : public SelectionDAGISel {
 
     /// If true, selector should try to optimize for minimum code size.
     bool OptForMinSize;
 
     /// Disable direct TLS access through segment registers.
     bool IndirectTlsSegRefs;
 
   public:
+    static char ID;
+
     explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
-        : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
+        : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr),
           OptForMinSize(false), IndirectTlsSegRefs(false) {}
 
     StringRef getPassName() const override {
       return "X86 DAG->DAG Instruction Selection";
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       // Reset the subtarget each time through.
private:
     bool tryOptimizeRem8Extend(SDNode *N);
 
     bool onlyUsesZeroFlag(SDValue Flags) const;
     bool hasNoSignFlagUses(SDValue Flags) const;
     bool hasNoCarryFlagUses(SDValue Flags) const;
   };
 }
 
+char X86DAGToDAGISel::ID = 0;
 
 // Returns true if this masked compare can be implemented legally with this
 // type.
 static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {
   unsigned Opcode = N->getOpcode();
   if (Opcode == X86ISD::CMPM || Opcode == X86ISD::CMPMM ||
       Opcode == X86ISD::STRICT_CMPM || Opcode == ISD::SETCC ||
       Opcode == X86ISD::CMPMM_SAE || Opcode == X86ISD::VFPCLASS) {

llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp

 
 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
   class XCoreDAGToDAGISel : public SelectionDAGISel {
 
   public:
+    static char ID;
+
     XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TM, OptLevel) {}
+      : SelectionDAGISel(ID, TM, OptLevel) {}
 
     void Select(SDNode *N) override;
     bool tryBRIND(SDNode *N);
 
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
     inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
       return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
StringRef getPassName() const override {
       return "XCore DAG->DAG Pattern Instruction Selection";
     }
 
     // Include the pieces autogenerated from the target description.
   #include "XCoreGenDAGISel.inc"
   };
 }  // end anonymous namespace
 
+char XCoreDAGToDAGISel::ID = 0;
+
 /// createXCoreISelDag - This pass converts a legalized DAG into a
 /// XCore-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
                                        CodeGenOpt::Level OptLevel) {
   return new XCoreDAGToDAGISel(TM, OptLevel);
 }